Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a plurality of first wirings, a plurality of second wirings, a first insulating member and a second insulating member provided between them, a plurality of first semiconductor layers, a plurality of first gate electrodes electrically connected to the plurality of first wirings and facing the plurality of first semiconductor layers, a plurality of second semiconductor layers, a plurality of second gate electrodes electrically connected to the plurality of second wirings and facing the plurality of second semiconductor layers, a plurality of third semiconductor layers electrically connected to the plurality of second semiconductor layers, a plurality of third gate electrodes electrically connected to the plurality of first semiconductor layers and facing the plurality of third semiconductor layers, and via wiring electrically connected to the plurality of third semiconductor layers. In a predetermined cross-section, one end of the via wiring is provided between positions corresponding to the sides of the first insulating member and the second insulating member, and the other end is not provided between these positions.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] With the increasing integration of semiconductor memory devices, research into the three-dimensionalization of semiconductor memory devices is progressing. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0317132 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises: a plurality of first wirings aligned in a first direction and extending in a second direction intersecting the first direction; a plurality of second wirings aligned in a first direction and extending in a second direction, and aligned with the plurality of first wirings in a third direction intersecting the first and second directions; and a first insulating member and a second insulating member provided between the plurality of first wirings and the plurality of second wirings, aligned in a second direction and extending in the first and third directions.

[0006] Furthermore, this semiconductor memory device includes a plurality of first semiconductor layers provided between a first insulating member and a second insulating member, aligned in a first direction and extending in a third direction; a plurality of first gate electrodes, each electrically connected to a plurality of first wirings aligned in a first direction and facing the plurality of first semiconductor layers; and a first via wiring extending in a first direction and electrically connected to the plurality of first semiconductor layers.

[0007] The semiconductor memory device further comprises: a plurality of second semiconductor layers provided between the first insulating member and the second insulating member, arranged in the first direction and extending in the third direction; a plurality of second gate electrodes arranged in the first direction, each electrically connected to a plurality of second wirings, and opposed to the plurality of second semiconductor layers; and a second via wiring extending in the first direction and electrically connected to the plurality of second semiconductor layers.

[0008] The semiconductor memory device further comprises: a plurality of third semiconductor layers provided between the plurality of first semiconductor layers and the plurality of second semiconductor layers, arranged in the first direction, extending in the third direction, and each electrically connected to the plurality of second semiconductor layers; a plurality of third gate electrodes arranged in the first direction, each electrically connected to the plurality of first semiconductor layers, and opposed to the plurality of third semiconductor layers; and a third via wiring extending in the first direction and electrically connected to the plurality of third semiconductor layers.

[0009] Furthermore, in a predetermined cross-section extending in the second direction and the third direction, one end of the third via wiring in the second direction is provided between a first position in the second direction corresponding to the side surface of the first insulating member on the second insulating member side, and a second position in the second direction corresponding to the side surface of the second insulating member on the first insulating member side. The other end of the third via wiring in the second direction is not provided between the first position and the second position. [BRIEF DESCRIPTION OF THE DRAWINGS]

[0010] [Figure 1] FIG. 1 is a schematic circuit diagram showing a partial configuration of the semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a schematic perspective view showing a partial configuration of the same semiconductor memory device. [Figure 3] FIG. 3 is a schematic XY cross-sectional view showing a partial configuration of the same semiconductor memory device. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a partial configuration of the same semiconductor memory device. [Figure 5] FIG. 5 is a schematic cross-sectional view for explaining a method of manufacturing the same semiconductor memory device. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining the same manufacturing method. [Figure 7] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 8] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 9] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 10] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 11] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 26] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 27] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 34] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 35] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 37] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 39] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 41] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 43] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 44] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 45] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 46] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 47] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 48] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 49] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 50] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 51] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 52] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 53] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 54] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 55] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 56] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 57] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 58] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 59] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 60] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 61] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 62] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 63] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 64] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 65] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 66] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 67] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 68] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 69] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 70] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 71] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 72] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 73] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 74] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 75] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 76] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 77] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 78] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 79] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 80] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 81]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 82] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 83] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 84] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 85] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 86] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 87] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 88] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 89] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 90] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 91] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 92] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 93] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 94] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 95] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 96] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 97] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 98] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 99] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 100] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 101] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 102] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 103] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 104] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 105] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. [Figure 106] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Modes for carrying out the invention]

[0011] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0012] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0013] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor layer material, or transistors, etc. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0014] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0015] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0016] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0017] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0018] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0019] Furthermore, in this specification, when we refer to the "center position" of a certain configuration, it may mean, for example, the center of the circumscribed circle of the configuration, or it may mean the centroid of the configuration on the image.

[0020] [First Embodiment] [Circuit Configuration] Figure 1 is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML, a plurality of write bit lines WBL, a plurality of read bit lines RBL, and a plurality of source lines SL connected to these plurality of memory layers ML.

[0021] Each memory layer ML comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC connected to the write word line WWL and the read word line RWL. Each memory cell MC comprises a write transistor WTr, a storage node SN, a read transistor RTr, and a selection transistor Str.

[0022] The write transistor WTr is, for example, a field-effect NMOS transistor. One electrode of the write transistor WTr is connected to the write bit line WBL. The other electrode of the write transistor WTr is connected to the storage node SN. Both electrodes of the write transistor WTr function as source or drain electrodes depending on the voltage supplied to the write transistor WTr. The gate electrode of the write transistor WTr is connected to the write word line WWL.

[0023] The readout transistor RTr is, for example, a field-effect NMOS transistor. One electrode of the readout transistor RTr is connected to the source line SL. The source line SL is supplied with, for example, a ground voltage Vss. The other electrode of the readout transistor RTr is connected to the selection transistor Str. Both electrodes of the readout transistor RTr function as source electrodes or drain electrodes depending on the voltage supplied to the readout transistor RTr. The gate electrode of the readout transistor RTr is connected to the storage node SN.

[0024] The selection transistor STr is, for example, a field-effect NMOS transistor. One electrode of the selection transistor STr is connected to the readout bit line RBL. The other electrode of the selection transistor STr is connected to the readout transistor RTr. Both electrodes of the selection transistor STr function as source electrodes or drain electrodes depending on the voltage supplied to the selection transistor STr. The gate electrode of the selection transistor STr is connected to the readout word line RWL.

[0025] During a write operation, for example, a predetermined gate voltage is supplied to the word line WWL that is the target of the write operation, and a ground voltage Vss is supplied to the others. The predetermined gate voltage is, for example, a voltage whose magnitude is the sum of the power supply voltage Vdd and the threshold voltage of the write transistor WTr. In addition, the power supply voltage Vdd or the ground voltage Vss is supplied to the bit line WBL that is the target of the write operation, depending on the data to be written.

[0026] Furthermore, during a write operation, all write bit lines (WBLs) within the memory cell array (MCA) may be targeted for the write operation, or only some (for example, one) write bit lines (WBLs) may be targeted. In the latter case, any of the multiple write bit lines (WBLs) that are not targeted for the write operation may be left in a floating state, for example.

[0027] During a read operation, for example, the power supply voltage Vdd is supplied to the read word line RWL that is the target of the read operation, and the ground voltage Vss is supplied to the others. Here, if the storage node SN of the memory cell MC that is the target of the read operation (hereinafter sometimes referred to as the "selected memory cell MC") is charged by the power supply voltage Vdd, the read transistor RTr is turned ON, current flows through the read bit line RBL, or the charge in the read bit line RBL is discharged. On the other hand, if the storage node SN of the selected memory cell MC is discharged to the ground voltage Vss, the read transistor RTr is turned OFF. Therefore, no current flows through the read bit line RBL, or the charge in the read bit line RBL is not discharged.

[0028] Furthermore, during the read operation, all read bit lines RBL within the memory cell array MCA may be targeted for the read operation, or only some (for example, one) read bit lines RBL may be targeted for the read operation. In the latter case, for any of the multiple read bit lines RBL that are not targeted for the read operation, a ground voltage Vss may be supplied, for example.

[0029] [structure] Figure 2 is a schematic perspective view showing a part of the configuration of a semiconductor memory device according to the first embodiment. Figure 3 is a schematic XY cross-sectional view showing a part of the configuration of the same semiconductor memory device. Figure 4 is a schematic cross-sectional view showing a part of the configuration of the same semiconductor memory device, showing the structure shown in Figure 3 cut along line AA' and viewed along the direction of the arrow.

[0030] Figure 2 shows a portion of the semiconductor substrate Sub and a portion of the memory cell array MCA located above the semiconductor substrate Sub.

[0031] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer (not shown), and the electrode layer constitute a control circuit for controlling the semiconductor memory device. For example, a sense amplifier circuit is provided in the region directly beneath the memory cell array MCA. The sense amplifier circuit is electrically connected to the read bit line RBL. In a read operation, the sense amplifier circuit can read data stored in the selected memory cell MC by detecting the voltage or current of the read bit line RBL.

[0032] The memory cell array MCA comprises multiple memory layers ML arranged in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is provided between each of the multiple memory layers ML.

[0033] Furthermore, vias 102, 103, and 104 are provided in the memory cell array MCA. Via 102 functions as the write bit line WBL. Via 103 functions as the read bit line RBL. Via 104 functions as the source line SL. Vias 102, 103, and 104 are positioned differently from each other in the X direction and extend in the Z direction, penetrating multiple memory layers ML.

[0034] The via wiring 102 includes, for example, a conductive oxide film containing a conductive oxide, a barrier conductive film such as titanium nitride (TiN), and a conductive material such as tungsten (W). Alternatively, the via wiring 102 may contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film. Furthermore, the via wiring 102 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0035] In this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0036] The via wiring 103 includes, for example, a conductive oxide film containing a conductive oxide, a barrier conductive film such as titanium nitride (TiN), and a conductive material such as tungsten (W). Alternatively, the via wiring 103 may contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film. Furthermore, the via wiring 103 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0037] Furthermore, the memory cell array MCA is provided with an insulating member 105 made of silicon oxide (SiO2) or the like. The insulating member 105 extends in the Z direction, penetrating multiple memory layers ML. The insulating member 105 is aligned in the Y direction and extends in the X direction, electrically separating multiple memory cells MC aligned in the Y direction.

[0038] The memory layer ML comprises wirings 110 and 120 aligned in the X direction and extending in the Y direction. In the example shown in Figures 2 and 3, the region between the wirings 110 and 120 in the memory layer ML is divided into multiple substantially rectangular regions R by multiple insulating members 105 aligned in the Y direction. R It is divided as shown in (Figure 2). Furthermore, the memory layer ML is located in region R. R A transistor structure 130 is provided in the region on the wiring 110 side, and region R Ra transistor structure 140 provided in a region on the wiring 120 side in region R R and a transistor structure 150 provided in a region between the transistor structures 130 and 140 in .

[0039] Further, in the examples of FIGS. 2 and 3, a part of the via wiring 102, a part of the via wiring 103, and a part of the via wiring 104 are in the region R R and protrudes from , and digs into the insulating member 105.

[0040] Further, in the examples of FIGS. 2 and 3, the via wiring 104 is located in the region R R protrudes from to the positive side in the Y direction, and the via wirings 102 and 103 are located in the region R R protrudes from to the negative side in the Y direction. That is, the via wiring 104 is located in the region R R a portion provided inside , and a region R R and a portion provided on the positive side in the Y direction with respect to . On the other hand, the via wirings 102 and 103 are located in the region R R a portion provided inside , and a region R R and a portion provided on the negative side in the Y direction with respect to .

[0041] In FIG. 3, as two insulating members 105 adjacent to each other in the Y direction, insulating members 105a and 105b are illustrated. FIG. 3 also illustrates a position Y1 of a side surface in the Y direction on the 105b side of the insulating member 105a, and a position Y2 of a side surface in the Y direction on the 105a side of the insulating member 105b. For each of the via wirings 102, 103, and 104, one end in the Y direction is provided between the positions Y1 and Y2, and the other end in the Y direction is not provided between the positions Y1 and Y2.

[0042] In the example of FIG. 3, the via wiring 104 is located in the region R RIt protrudes in the positive direction in the Y direction, and a portion of the via wiring 104 is embedded in the insulating member 105a. Therefore, the negative side surface of the insulating member 105a in the Y direction comprises two linear portions provided at position Y1 and extending in the X direction, and a curved portion provided between these two portions. This curved portion is continuous with the two linear portions and is a portion of the outer surface of the via wiring 104 (region R R It is formed along the outer portion.

[0043] In addition, in the example in Figure 3, via connections 102 and 103 are in region R. R It protrudes to the negative side in the Y direction, and a portion of the via wirings 102 and 103 is embedded in the insulating member 105b. Therefore, the positive side surface of the insulating member 105b in the Y direction is provided at position Y2 and comprises three linear portions extending in the X direction, and two curved portions provided between two of these three portions. One of these two curved portions is provided between the first and second linear portions counting from the negative side in the X direction, and is continuous with these two portions, and is part of the outer surface of the via wiring 102 (region R R It is formed along the portion provided on the outside of the curved portion. The other of these two curved portions is provided between the second and third straight portions counting from the negative X direction, and is continuous with these two portions, and is part of the outer surface of the via wiring 103 (region R R It is formed along the outer portion.

[0044] The wiring 110 functions, for example, as a write word line WWL (Figure 1). The wiring 110 comprises, for example, a barrier conductive film 111 made of titanium nitride (TiN) and a conductive film 112 made of tungsten (W).

[0045] The wiring 120 functions, for example, as a read word line RWL (Figure 1). The wiring 120 comprises, for example, a barrier conductive film 121 made of titanium nitride (TiN) and a conductive film 122 made of tungsten (W).

[0046] The transistor structure 130 is connected to a portion of the outer surface of the via wiring 102, in the region R.R The device comprises a semiconductor layer 131 extending in the X direction, an insulating layer 132 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 110 side) of the semiconductor layer 131, a conductive layer 133 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 110 side) of the insulating layer 132, and an insulating layer 134 provided on the upper surface, lower surface, and both sides in the Y direction of the conductive layer 133.

[0047] In the XY cross-section illustrated in Figure 3, the other side of the semiconductor layer 131 in the X direction (the wiring 120 side) may be formed along a circle centered on the center position of via wiring 102 or via wiring 104. Furthermore, one side of the semiconductor layer 131, insulating layer 132, and conductive layer 133 in the X direction (the wiring 110 side) may be formed linearly along the side of wiring 110. Additionally, both sides of the semiconductor layer 131, insulating layer 132, conductive layer 133, and insulating layer 134 in the Y direction may be formed linearly along the side of insulating member 105.

[0048] The semiconductor layer 131 functions, for example, as the channel region of the writing transistor WTr (Figure 1). The semiconductor layer 131 may be a semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be another oxide semiconductor. Multiple semiconductor layers 131 aligned in the Z direction are commonly connected to via wiring 102 extending in the Z direction.

[0049] The insulating layer 132 functions, for example, as a gate insulating film of the writing transistor WTr (Figure 1). The insulating layer 132 includes, for example, silicon oxide (SiO2).

[0050] The conductive layer 133 functions, for example, as the gate electrode of the writing transistor WTr (Figure 1). The conductive layer 133 contains, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 faces the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (the side facing the wiring 110) of the semiconductor layer 131 via the insulating layer 132. In addition, one side of the conductive layer 133 in the X direction (the side facing the wiring 110) is connected to the wiring 110.

[0051] The insulating layer 134 includes, for example, silicon oxide (SiO2).

[0052] The transistor structure 140 is connected to a portion of the outer surface of the via wiring 103, in the region R. R The device comprises a semiconductor layer 141 extending in the X direction, an insulating layer 142 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the semiconductor layer 141, a conductive layer 143 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the insulating layer 142, and an insulating layer 144 provided on the upper surface, lower surface, and both sides in the Y direction of the conductive layer 143.

[0053] In the XY cross-section illustrated in Figure 3, the side surface of the semiconductor layer 141, insulating layer 142, and conductive layer 143 on one side in the X direction (the side with the wiring 120) may be formed linearly along the side surface of the wiring 120. Furthermore, the side surfaces of the semiconductor layer 141, insulating layer 142, conductive layer 143, and insulating layer 144 in the Y direction may be formed linearly along the side surface of the insulating member 105.

[0054] The semiconductor layer 141 functions, for example, as the channel region of a selection transistor STr (Figure 1). The semiconductor layer 141 may be a semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be another oxide semiconductor. Multiple semiconductor layers 141 aligned in the Z direction are commonly connected to via wiring 103 extending in the Z direction.

[0055] The insulating layer 142 functions, for example, as a gate insulating film of the selection transistor STr (Figure 1). The insulating layer 142 includes, for example, silicon oxide (SiO2).

[0056] The conductive layer 143 functions, for example, as the gate electrode of a selection transistor STr (Figure 1). The conductive layer 143 contains, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 143 faces the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (the side facing the wiring 120) of the semiconductor layer 141 via the insulating layer 142. In addition, one side of the conductive layer 143 in the X direction (the side facing the wiring 120) is connected to the wiring 120.

[0057] The insulating layer 144 includes, for example, silicon oxide (SiO2).

[0058] The transistor structure 150 is connected to one side of the semiconductor layer 131 in the X direction (the wiring 120 side), and the above region R R The device comprises a conductive layer 151 extending in the X direction, an insulating layer 152 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the wiring 120 side) of the conductive layer 151, a semiconductor layer 153 connected to a part of the outer surface of the via wiring 104 and provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the wiring 120 side) of the insulating layer 152, and an insulating layer 154 provided on the upper surface, lower surface, and both sides in the Y direction of the semiconductor layer 153.

[0059] In the XY cross-section illustrated in Figure 3, the side surface of the conductive layer 151 and the insulating layer 152 on one side in the X direction (the wiring 120 side) may be formed along a circle centered on the center position of the via wiring 104. The other side surface of the conductive layer 151 in the X direction (the wiring 110 side) may be formed along a circle centered on the center position of the via wiring 102 or via wiring 104. Furthermore, the side surfaces of the conductive layer 151, insulating layer 152, semiconductor layer 153, and insulating layer 154 on one side in the Y direction may be formed linearly along the side surface of the insulating member 105. The other side surface of the conductive layer 151 and insulating layer 152 in the Y direction may comprise two linear portions extending in the X direction along the side surface of the insulating member 105, and a curved portion provided between these two portions. This curved portion is continuous with the two linear portions and forms part of the outer circumferential surface (region R) of the via wiring 104. R It may also be formed along the portion located on the inside of it.

[0060] The conductive layer 151 functions, for example, as the gate electrode of the storage node SN (Figure 1) and the readout transistor RTr (Figure 1). The conductive layer 151 includes, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 151 is connected to one side of the semiconductor layer 131 in the X direction (the wiring 120 side).

[0061] The insulating layer 152 functions, for example, as a gate insulating film of the readout transistor RTr (Figure 1). The insulating layer 152 is continuous with the insulating layer 132 and contains the same material as the insulating layer 132. The insulating layer 152 is formed, for example, at the same time as the insulating layer 132 is formed.

[0062] The semiconductor layer 153 functions, for example, as the channel region of the readout transistor RTr (Figure 1). The semiconductor layer 153 is continuous with the semiconductor layer 141 and contains the same material as the semiconductor layer 141. The semiconductor layer 153 is formed, for example, simultaneously with the formation of the semiconductor layer 141. Multiple semiconductor layers 153 aligned in the Z direction are commonly connected to via wiring 104 extending in the Z direction. The semiconductor layer 153 faces the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (towards the wiring 120) of the conductive layer 151 via the insulating layer 152.

[0063] The insulating layer 154 includes, for example, silicon oxide (SiO2).

[0064] [Manufacturing method] Figures 5 to 98 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. Figures 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, and 97 show cross-sections corresponding to Figure 3. Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, and 98 show cross-sections corresponding to Figure 4.

[0065] In this manufacturing method, for example, as shown in Figure 6, multiple insulating layers 101 and multiple sacrificial layers MLA are formed alternately. The sacrificial layer MLA contains, for example, silicon nitride (Si3N4). This process is carried out by, for example, CVD (Chemical Vapor Deposition).

[0066] Next, an insulating member 105 is formed, for example, as shown in Figure 5. In this step, an opening is formed at a position corresponding to the insulating member 105. This opening extends in the Z direction and penetrates multiple insulating layers 101 and multiple sacrificial layers MLA that are aligned in the Z direction. This step is performed, for example, by RIE (Reactive Ion Etching). After the opening is formed, the insulating member 105 is formed. This step is performed, for example, by CVD.

[0067] Next, as shown in Figures 7 and 8, for example, openings 102A, 103A, and 104A are formed at positions corresponding to via wirings 102, 103, and 104. The openings 102A, 103A, and 104A extend in the Z direction. Each of the openings 102A, 103A, and 104A includes a portion that penetrates a plurality of insulating layers 101 and a plurality of sacrificial layers MLA arranged in the Z direction, and a portion that penetrates the insulating member 105. This process is carried out, for example, by RIE.

[0068] Next, as shown in Figures 9 and 10, for example, sacrificial layers 102B, 103B, and 104B made of silicon (Si) or the like are formed inside the openings 102A, 103A, and 104A. This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layers 102B, 103B, and 104B.

[0069] Next, as shown in Figures 11 and 12, for example, openings 110A and 120A are formed at positions corresponding to the wiring 110 and 120.

[0070] In this process, for example, grooves extending in the Y and Z directions are first formed near the locations corresponding to the wirings 110 and 120. These grooves penetrate multiple insulating layers 101 and multiple sacrificial layers MLA aligned in the Z direction, thereby dividing these structures in the X direction. This process is carried out, for example, by RIE.

[0071] Next, openings 110A and 120A are formed at positions corresponding to the wirings 110 and 120. Parts of the upper and lower surfaces of the insulating layer 101, a part of the Y-direction side surface of the insulating member 105, and a part of the X-direction side surface of the sacrificial layer MLA are exposed inside the openings 110A and 120A. In addition, a part of the outer circumferential surface of the sacrificial layer 102B is exposed inside opening 110A. In addition, a part of the outer circumferential surface of the sacrificial layer 103B is exposed inside opening 120A. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the grooves. This step is performed, for example, by wet etching.

[0072] Next, as shown in Figures 13 and 14, for example, sacrificial layers 110B and 120B made of carbon (C) or the like are embedded inside the openings 110A and 120A. This process is carried out by, for example, CVD.

[0073] Next, the sacrificial layer 102B is removed, for example, as shown in Figures 15 and 16. This step is performed, for example, by wet etching.

[0074] Next, as shown in Figures 17 and 18, for example, an opening 131A is formed at a position corresponding to the semiconductor layer 131. Inside the opening 131A, a portion of the upper and lower surfaces of the insulating layer 101, a portion of the X-direction side surface of the sacrificial layer MLA, a portion of the Y-direction side surface of the insulating member 105, a portion of the outer periphery of the sacrificial layer 104B, and a portion of the X-direction side surface of the sacrificial layer 110B are exposed. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A. This step is performed, for example, by wet etching.

[0075] Next, as shown in Figures 19 and 20, for example, an insulating layer 134 is formed inside the openings 131A and 102A. The insulating layer 134 is formed on a portion of the upper surface, a portion of the lower surface, and the surface exposed to the opening 102A of the insulating layer 101, a portion of the X-direction side surface of the sacrificial layer MLA, a portion of the Y-direction side surface of the insulating member 105, a portion of the outer circumferential surface of the sacrificial layer 104B, and a portion of the X-direction side surface of the sacrificial layer 110B. In addition, the opening 131A is filled with a sacrificial layer 131B made of silicon (Si), and the opening 102A is filled with a sacrificial layer 102B made of silicon (Si). This process is carried out by, for example, CVD. Although not shown in the figures, after the completion of this process, an insulating layer or the like is formed on top of the sacrificial layer 102B.

[0076] Next, the sacrificial layer 104B is removed, for example, as shown in Figures 21 and 22. This step is performed, for example, by wet etching.

[0077] Next, as shown in Figures 23 and 24, for example, an opening 151A is formed at a position corresponding to a part of the conductive layer 151. Inside the opening 151A, a part of the upper and lower surfaces of the insulating layer 101, a part of the X-direction side surface of the sacrificial layer MLA, a part of the Y-direction side surface of the insulating member 105, and a part of the X-direction side surface of the insulating layer 134 are exposed. In this step, for example, a part of the sacrificial layer MLA is selectively removed through the opening 104A. This step is performed, for example, by wet etching.

[0078] Next, as shown in Figures 25 and 26, for example, the opening 151A is filled with a sacrificial layer 151B made of silicon (Si), and the opening 104A is filled with a sacrificial layer 104B made of silicon (Si). This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layer 104B.

[0079] Next, the sacrificial layer 103B is removed, for example, as shown in Figures 27 and 28. This step is performed, for example, by wet etching.

[0080] Next, as shown in Figures 29 and 30, for example, an opening 141A is formed at a position corresponding to the semiconductor layer 141. Inside the opening 141A, a portion of the upper and lower surfaces of the insulating layer 101, the X-direction side surface of the sacrificial layer 151B, a portion of the Y-direction side surface of the insulating member 105, and a portion of the X-direction side surface of the sacrificial layer 120B are exposed. In this step, for example, the sacrificial layer MLA is selectively removed through the opening 103A. This step is performed, for example, by wet etching.

[0081] Next, as shown in Figures 31 and 32, for example, a portion of the sacrificial layer 151B is selectively removed through openings 141A and 103A. This step is performed, for example, by wet etching.

[0082] In the process described with reference to Figures 23 and 24, it is necessary to expose a portion of the sides of two adjacent insulating layers 105 in the Y direction inside the opening 151A. As a result, the opening 151A may become unnecessarily large, potentially causing the channel length of the read transistor RTr to become too long or the channel length of the selection transistor STr to become too short. Therefore, in this embodiment, a portion of the sacrificial layer 151B is selectively removed by the process described with reference to Figures 31 and 32, thereby adjusting the channel lengths of the read transistor RTr and the selection transistor STr.

[0083] Next, as shown in Figures 33 and 34, for example, an insulating layer 144 is formed inside the openings 141A and 103A. The insulating layer 144 is formed on a portion of the upper surface, a portion of the lower surface, and the surface exposed to the opening 103A of the insulating layer 101, the X-direction side surface of the sacrificial layer 151B, a portion of the Y-direction side surface of the insulating member 105, and a portion of the X-direction side surface of the sacrificial layer 120B. In addition, the opening 141A is filled with a sacrificial layer 141B made of silicon (Si), and the opening 103A is filled with a sacrificial layer 103B made of silicon (Si). This process is carried out by, for example, CVD. Although not shown in the figures, after the completion of this process, an insulating layer or the like is formed on top of the sacrificial layer 103B.

[0084] Next, as shown in Figures 35 and 36, for example, the sacrificial layers 102B, 103B, 131B, and 141B are removed. This step is performed, for example, by wet etching.

[0085] Next, as shown in Figures 37 and 38, for example, a conductive layer 133A and a sacrificial layer 131B are formed inside openings 131A and 102A. Similarly, a conductive layer 143A and a sacrificial layer 141B are formed inside openings 141A and 103A. Opening 131A is filled by the sacrificial layer 131B, while opening 102A is not. Similarly, opening 141A is filled by the sacrificial layer 141B, while opening 103A is not. This process is carried out by, for example, CVD.

[0086] Next, as shown in Figures 39 and 40, for example, a portion of the conductive layers 133A and 143A is removed. In this step, for example, the portion of the sacrificial layers 131B and 141B that is located on the inner circumferential surface of the openings 102A and 103A is removed to expose a portion of the conductive layers 133A and 143A. Next, the portion of the conductive layers 133A and 143A that is located on the inner circumferential surface of the openings 102A and 103A is removed, and the conductive layers 133A and 143A are divided in the Z direction. This step is performed, for example, by wet etching.

[0087] Next, as shown in Figures 41 and 42, for example, the openings 102A and 103A are filled with sacrificial layers 102B and 103B made of silicon (Si) or the like. This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layers 102B and 103B.

[0088] Next, the sacrificial layers 110B and 120B are removed, for example, as shown in Figures 43 and 44. This step is performed, for example, by wet etching.

[0089] Next, as shown in Figures 45 and 46, for example, a portion of the insulating layer 134 is removed through the opening 110A to expose one side surface of the conductive layer 133A in the X direction and a portion of the outer periphery of the sacrificial layer 102B. Similarly, a portion of the insulating layer 144 is removed through the opening 120A to expose one side surface of the conductive layer 143A in the X direction and a portion of the outer periphery of the sacrificial layer 103B. This process is carried out, for example, by wet etching.

[0090] Next, as shown in Figures 47 and 48, for example, wiring 110 is formed inside opening 110A and wiring 120 is formed inside opening 120A. Specifically, a barrier conductive film 111 is formed in opening 110A on a part of the upper and lower surfaces of the insulating layer 101, a part of the side surface in the Y direction and one side surface in the X direction of the insulating member 105, a part of the outer circumferential surface of the sacrificial layer 102B, and one side surface in the X direction of the conductive layer 133A. The interior of opening 110A is also filled with a conductive film 112. Similarly, a barrier conductive film 121 is formed in opening 120A on a part of the upper and lower surfaces of the insulating layer 101, a part of the side surface in the Y direction and the other side surface in the X direction of the insulating member 105, a part of the outer circumferential surface of the sacrificial layer 103B, and one side surface in the X direction of the conductive layer 143A. The interior of opening 120A is also filled with a conductive film 122. This process is carried out by, for example, CVD.

[0091] Next, the sacrificial layers 141B and 103B are removed, for example, as shown in Figures 49 and 50. This step is performed, for example, by wet etching.

[0092] Next, as shown in Figures 51 and 52, for example, the opening 141A is filled with a sacrificial layer 141C made of carbon (C), and the opening 103A is filled with a sacrificial layer 103C made of carbon (C). This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layer 103C.

[0093] Next, the sacrificial layers 151B and 104B are removed, for example, as shown in Figures 53 and 54. This step is performed, for example, by wet etching.

[0094] Next, as shown in Figures 55 and 56, for example, a portion of the insulating layers 134 and 144 and a portion of the conductive layers 133A and 143A are removed through openings 151A and 104A to expose a portion of the sacrificial layers 131B and 141C. This process is carried out, for example, by wet etching.

[0095] Next, the sacrificial layers 141C and 103C are removed, for example, as shown in Figures 57 and 58. This step is performed, for example, by wet etching.

[0096] Next, as shown in Figures 59 and 60, for example, an insulating layer 142 is formed inside the openings 141A and 103A. Similarly, an insulating layer 154 is formed inside the openings 151A and 104A. The insulating layer 142 is formed on the exposed surfaces of the wiring 120 and the insulating layer 144 to the opening 103A, as well as on the upper surface, lower surface, Y-direction side surface, and X-direction side surface of the conductive layer 143. The insulating layer 154 is formed on a portion of the upper surface, a portion of the lower surface, and the exposed surface to the opening 104A of the insulating layer 101, on the exposed surfaces of the conductive layer 133 and the sacrificial layer 131B to the opening 104A, and on the exposed surfaces of the insulating member 105 to the openings 151A and 104A. This process is carried out by, for example, CVD.

[0097] Next, as shown in Figures 61 and 62, for example, a sacrificial layer 141C of titanium nitride (TiN) or the like is formed inside the openings 141A, 103A, 151A, and 104A. Opening 141A is filled with the sacrificial layer 141C. Openings 103A, 151A, and 104A are not filled with the sacrificial layer 141C. This process is carried out, for example, by CVD.

[0098] Next, as shown in Figures 63 and 64, for example, the portion of the sacrificial layer 141C formed at the opening 103A is removed to expose the insulating layer 142. Also, the portions of the sacrificial layer 141C formed at the openings 151A and 104A are removed to expose the insulating layer 154. This step is performed, for example, by wet etching. After this step is completed, an insulating layer or the like is formed on top of the opening 103A.

[0099] Next, as shown in Figures 65 and 66, for example, sacrificial layers 151B and 104B made of silicon (Si) or the like are formed inside the openings 151A and 104A. This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layer 104B.

[0100] Next, as shown in Figures 67 and 68, for example, via wiring 103 is formed inside the opening 103A. This process is carried out by, for example, CVD.

[0101] Next, the sacrificial layers 131B and 102B are removed, for example, as shown in Figures 69 and 70. This step is performed, for example, by wet etching.

[0102] Next, as shown in Figures 71 and 72, for example, a portion of the insulating layer 154 is removed inside the opening 131A to expose a portion of the outer surface of the sacrificial layer 104B. Also, a portion of the insulating layer 134 is removed inside the opening 102A to expose a portion of the insulating layer 105. This process is carried out, for example, by wet etching.

[0103] Next, as shown in Figures 73 and 74, for example, sacrificial layers 131C and 102C of carbon (C) or the like are formed inside the openings 131A and 102A. This process is carried out by, for example, CVD. Although not shown in the figures, after this process is completed, an insulating layer or the like is formed on top of the sacrificial layer 102C.

[0104] Next, the sacrificial layers 151B and 104B are removed, for example, as shown in Figures 75 and 76. This step is performed, for example, by wet etching.

[0105] Next, the sacrificial layer 141C is removed, for example, as shown in Figures 77 and 78. This step is performed, for example, by wet etching.

[0106] Next, a portion of the sacrificial layer 131C is removed, for example, as shown in Figures 79 and 80. This step is performed, for example, by wet etching.

[0107] Next, as shown in Figures 81 and 82, for example, a semiconductor layer 141 is formed inside the opening 141A. The opening 141A is filled by the semiconductor layer 141. Also, a semiconductor layer 153A and a sacrificial layer 151C of carbon (C) or the like are formed inside the openings 151A and 104A. The opening 151A is filled by the semiconductor layer 153A and the sacrificial layer 151C. The opening 104A is not filled by the semiconductor layer 153A and the sacrificial layer 151C. This process is carried out by, for example, CVD.

[0108] Next, as shown in Figures 83 and 84, the sacrificial layer 151C is removed inside the opening 104A. This exposes a portion of the inner surface of the semiconductor layer 153A to the inner surface of the opening 104A. Next, a portion of the semiconductor layer 153A is removed, exposing a portion of the insulating layer 154 inside the opening 104A. In this step, the semiconductor layer 153A is divided in the Z direction, forming multiple semiconductor layers 153 aligned in the Z direction. This step is performed, for example, by wet etching.

[0109] Next, as shown in Figures 85 and 86, via wiring 104 is formed inside the opening 104A. This process is carried out, for example, by CVD.

[0110] Next, as shown in Figures 87 and 88, the sacrificial layers 131B and 102B are removed. This step is performed, for example, by wet etching.

[0111] Next, as shown in Figures 89 and 90, a portion of the semiconductor layer 153 is removed through openings 102A and 131A to expose one side of the sacrificial layer 151C in the X direction. This step is performed, for example, by wet etching.

[0112] Next, as shown in Figures 91 and 92, a portion of the semiconductor layer 153 is further removed through the openings 102A and 131A. This step is performed, for example, by wet etching.

[0113] Next, as shown in Figures 93 and 94, the sacrificial layer 151C is removed through openings 102A and 131A. This step is performed, for example, by wet etching.

[0114] Next, as shown in Figures 95 and 96, an insulating layer 152 is formed inside opening 151A, and an insulating layer 132 is formed inside openings 131A and 102A. A conductive layer 151D is also formed inside openings 151A, 131A, and 102A. Openings 151A and 131A are filled by the conductive layer 151D. Opening 102A is not filled by the conductive layer 151D. This process is carried out, for example, by CVD.

[0115] Next, as shown in Figures 97 and 98, the portion of the conductive layer 151D formed inside the openings 131A and 102A is removed. This forms the conductive layer 151. This step is performed, for example, by wet etching.

[0116] Subsequently, as shown in Figures 3 and 4, a semiconductor layer 131 is formed inside the opening 131A and via wiring 102 is formed inside the opening 102A, thereby forming a semiconductor memory device according to the first embodiment.

[0117] [effect] The semiconductor memory device according to this embodiment comprises a plurality of memory layers ML arranged in the Z direction and via connections 102, 103, and 104 extending in the Z direction. Each of the plurality of memory layers ML comprises a transistor structure 130, 140, and 150, respectively.

[0118] In this configuration, the number of memory layers ML included in the memory cell array MCA can be increased simply by increasing the number of insulating layers 101 and sacrificial layers MLA stacked in the stacking process (the process described with reference to Figure 6). Therefore, high integration can be achieved relatively easily.

[0119] However, in such a configuration, if the distance between memory layers ML becomes small, the capacitance between two adjacent conductive layers 151 in the Z direction becomes large, which can make it difficult to write and read data effectively, or may increase the time required for writing and reading data.

[0120] Therefore, in this embodiment, as described with reference to Figure 3, a portion of the via wiring 104 is located in a substantially rectangular region R between two adjacent insulating members 105 in the Y direction. R It's sticking out.

[0121] In such a structure, for example, via wiring 104 is in region R R Compared to a structure that does not extend beyond the area, it is possible to reduce the capacitance between two adjacent conductive layers 151 in the Z direction. via wiring 104 in region R R In a structure that does not extend beyond the boundaries, the conductive layer 151 will surround the via wiring 104 all around, and as a result, the area of ​​the conductive layer 151 in the XY plane will increase.

[0122] Furthermore, in this embodiment, as explained with reference to Figure 3, not only a portion of via wiring 104, but also a portion of via wirings 102 and 103 are included in region R. R It's sticking out.

[0123] In this structure, via connections 102 and 103 are in region R. R Compared to structures that do not extend beyond the region, it is possible to reduce the area of ​​transistor structures 130 and 140 in the XY plane. Via wiring 102 is in region R R In a structure that does not extend beyond the region, the semiconductor layer 131, insulating layer 132, and conductive layer 133 surround the via wiring 102 all around, and as a result, the area of ​​the transistor structure 130 in the XY plane increases. Similarly, if the via wiring 103 is within region R RIn a structure that does not extend beyond the boundaries, the semiconductor layer 141, the insulating layer 142, and the conductive layer 143 surround the via wiring 103 all around, which increases the area of ​​the transistor structure 140 in the XY plane.

[0124] Furthermore, in this embodiment, in each memory layer ML, the semiconductor layer 153 covers the upper and lower surfaces of the conductive layer 151 via the insulating layer 152. With such a structure, the electric field generated from the conductive layer 151 is shielded by the semiconductor layer 153, thereby making it possible to reduce the capacitance between two adjacent conductive layers 151 in the Z direction.

[0125] [Second Embodiment] In the first embodiment, as described with reference to Figure 3, via wiring 104 and via wirings 102 and 103 are located in region R in the Y direction. R It protrudes in the opposite direction. However, this configuration is merely an example, and the arrangement of vias 102, 103, and 104 can be adjusted as appropriate. For example, via 104 and vias 102 and 103 are located in region R in the Y direction. R Therefore, they may extend in the same direction. Also, via wiring 102 and via wiring 103 are in region R in the Y direction. R Therefore, it's okay if it extends in the opposite direction.

[0126] Also, two adjacent regions R in the Y direction R Between, region R R The relative positions of vias 102, 103, and 104 may differ. For example, two adjacent regions R in the Y direction. R During that time, one of the regions R R via wiring 104 corresponding to the other region R R It is also possible to place both via wiring 104 corresponding to and . Furthermore, in such cases, two adjacent regions R in the Y direction R In between, it is also possible to implement a configuration corresponding to the source line SL with a single via connection.

[0127] Hereinafter, the following configuration is given as an example of a semiconductor memory device according to the second embodiment. In the following description, the same reference numerals are used for parts that are the same as in the first embodiment, and their descriptions are omitted.

[0128] Figure 99 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the second embodiment. The semiconductor memory device according to the second embodiment is basically configured in the same way as the first embodiment.

[0129] However, in the semiconductor memory device according to the first embodiment, via wiring 104 corresponding to the source line SL is provided at positions in the Y direction corresponding to all insulating members 105. On the other hand, in the semiconductor memory device according to the second embodiment, via wiring 204 corresponding to the source line SL is provided only at positions in the Y direction corresponding to even-numbered insulating members 105 (insulating member 105e in Figure 99) counting from the negative side in the Y direction, and is not provided at positions in the Y direction corresponding to odd-numbered insulating members 105 (insulating member 105o in Figure 99) counting from the negative side in the Y direction.

[0130] The via wiring 204 is basically configured the same way as via wiring 104. However, one end of via wiring 204 in the Y direction is located in region R on one side in the Y direction relative to the corresponding insulating member 105e. R A region R is provided inside, and the other end in the Y direction is located on the other side in the Y direction relative to the corresponding insulating member 105e. R It is located inside. In addition, via wiring 204 is located between two adjacent regions R in the Y direction in each memory layer ML. R It is connected to two semiconductor layers 153 that correspond to it.

[0131] In the example shown in Figure 99, via wiring 204 is provided at a position in the Y direction corresponding to the insulating member 105e. Therefore, the insulating member 105e is divided in the X direction via wiring 204. The positive Y-side surfaces of these two portions each comprise two linear portions extending in the X direction and a curved portion provided between these two portions. This curved portion is continuous with the two linear portions and is part of the outer surface of via wirings 102 and 103 (region R). R It is formed along the outer portion of the structure. The negative Y-sides of these two portions are formed in a straight line and extend in the X-direction.

[0132] Furthermore, in the example shown in Figure 99, the via wiring 204 is not provided at a position in the Y direction corresponding to the insulating member 105o. Therefore, the insulating member 105o is not divided in the X direction. Also, the negative side surface in the Y direction of the insulating member 105o is formed in a straight line and extends in the X direction.

[0133] This configuration also makes it possible to achieve the same effects as the semiconductor memory device according to the first embodiment.

[0134] Furthermore, this configuration makes it possible to reduce the width of the insulating members 105e and 105o in the Y direction, thereby reducing the area of ​​the insulating member 105 in the XY plane.

[0135] It should be noted that the structure shown in Figure 99 is merely an example, and the specific structure can be adjusted as appropriate. For example, the via wiring 204 may be provided at a position in the Y direction corresponding to the insulating member 105o, rather than at a position in the Y direction corresponding to the insulating member 105e.

[0136] [Third Embodiment] Next, a semiconductor memory device according to the third embodiment will be described. In the following description, parts similar to those in the second embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0137] Figure 100 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. The semiconductor memory device according to the third embodiment is basically configured the same as the second embodiment. However, in the semiconductor memory device according to the third embodiment, via wiring 304 corresponding to the source line SL is provided at positions in the Y direction corresponding to all insulating members 105.

[0138] In the XY cross-section illustrated in Figure 100, both sides of the conductive layer 151 in the Y direction each comprise two linear portions extending in the X direction along the side surface of the insulating member 105, and a curved portion provided between these two portions. Furthermore, this curved portion is continuous with the two linear portions and forms part of the outer surface of the via wiring 304 (region R). R It is formed along the part located on the inside.

[0139] This configuration also makes it possible to achieve the same effects as the semiconductor memory device according to the second embodiment.

[0140] [Fourth Embodiment] Next, a semiconductor memory device according to the fourth embodiment will be described. In the fourth embodiment, the selection transistor STr (Figure 1) is equipped with a back gate electrode, and this back gate electrode is connected to the storage node SN. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0141] Figure 101 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. Figure 102 is a schematic cross-sectional view showing a part of the configuration of the same semiconductor memory device, showing the structure shown in Figure 101 cut along line AA' and viewed along the direction of the arrow.

[0142] The semiconductor memory device according to the fourth embodiment is basically configured in the same way as the first embodiment. However, the semiconductor memory device according to the fourth embodiment includes a transistor structure 440 instead of the transistor structure 140.

[0143] The transistor structure 440 is located in the above region R R The device comprises a conductive layer 441 extending in the X direction, an insulating layer 442 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the conductive layer 441, a semiconductor layer 443 connected to a part of the outer surface of the via wiring 103 and provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the insulating layer 442, an insulating layer 142 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the semiconductor layer 443, a conductive layer 143 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the insulating layer 142, and an insulating layer 144 provided on the upper surface, lower surface, and both sides in the Y direction of the conductive layer 143.

[0144] The conductive layer 441 functions, for example, as the back gate electrode of the selection transistor STr (Figure 1). The conductive layer 441 is continuous with the conductive layer 151 and contains the same material as the conductive layer 151. The conductive layer 441 is formed, for example, at the same time as the conductive layer 151 is formed.

[0145] The insulating layer 442 functions, for example, as a gate insulating film between the back gate electrode and the channel region of a selection transistor STr (Figure 1). The insulating layer 442 is continuous with the insulating layer 152 and contains the same material as the insulating layer 152. The insulating layer 442 is formed, for example, at the same time as the insulating layer 152 is formed.

[0146] The semiconductor layer 443 functions, for example, as the channel region of the selection transistor STr (Figure 1). The semiconductor layer 443 is formed similarly to the semiconductor layer 141, except for the points mentioned above.

[0147] This configuration also makes it possible to achieve the same effects as the semiconductor memory device according to the first embodiment.

[0148] Furthermore, in this embodiment, the threshold voltage of some of the multiple selection transistors STr (those in which the storage node SN is included in the memory cell MC charged by the power supply voltage Vdd) is smaller than the threshold voltage of other parts (those in which the storage node SN is included in the memory cell MC charged by the ground voltage Vss). Here, for example, in this embodiment, during a read operation, it is conceivable to supply a voltage between these two threshold voltages to the read word line RWL that is the target of the read operation. This makes it possible to turn off some of the other selection transistors STr and turn on only some of the selection transistors STr during a read operation. This makes it possible to suitably suppress the leakage current that may occur between the read bit line RBL and the source line SL during a read operation.

[0149] Furthermore, in the semiconductor memory device according to this embodiment, the conductive layer 441 is continuous with the conductive layer 151, and the semiconductor layer 443 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the conductive layer 441. Here, for example, in this embodiment, it is conceivable to supply a fixed voltage such as a ground voltage Vss to the read word line RWL during a write operation. With such a method, the conductive layer 441 and the conductive layer 143 act as capacitors, making it possible to stabilize the voltage of the storage node SN.

[0150] Furthermore, the semiconductor memory device according to the fourth embodiment may have via wirings 204 and 304 (Figures 99 and 100) instead of via wiring 104. In such a case, via wiring 204 may be provided only at positions in the Y direction corresponding to insulating member 105e, as in the second embodiment, or only at positions in the Y direction corresponding to insulating member 105o. Also, via wiring 304 may be provided at positions in the Y direction corresponding to all insulating members 105, as in the third embodiment.

[0151] [Fifth Embodiment] In the first embodiment, in the transistor structure 130 corresponding to the writing transistor WTr, the conductive layer 133, which functions as a gate electrode, faces the upper surface, lower surface, and both sides in the Y direction of the semiconductor layer 131, which functions as a channel region.

[0152] Similarly, in the transistor structure 140 corresponding to the selected transistor Str, the conductive layer 143, which functions as the gate electrode, faces the upper surface, lower surface, and both sides in the Y direction of the semiconductor layer 141, which functions as the channel region.

[0153] On the other hand, in the transistor structure 150 corresponding to the readout transistor RTr, the semiconductor layer 153, which functions as a channel region, faces the upper surface, lower surface, and both sides in the Y direction of the conductive layer 151, which functions as a gate electrode.

[0154] However, such configurations can be adjusted as appropriate. For example, in the transistor structure corresponding to at least one of the writing transistor WTr and the selection transistor Str, the semiconductor layer that functions as the channel region may face the top surface, bottom surface, and both sides in the Y direction of the conductive layer that functions as the gate electrode. Similarly, in the transistor structure corresponding to the readout transistor RTr, the conductive layer that functions as the gate electrode may face the top surface, bottom surface, and both sides in the Y direction of the semiconductor layer that functions as the channel region.

[0155] Hereinafter, as a semiconductor memory device according to the fifth embodiment, an example is shown in which, in the transistor structure corresponding to the read transistor RTr, the conductive layer functioning as the gate electrode faces the upper surface, lower surface, and both sides in the Y direction of the semiconductor layer functioning as the channel region. In the following description, the same reference numerals are used for parts similar to those in the first embodiment, and their descriptions are omitted.

[0156] Figure 103 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. Figure 104 is a schematic cross-sectional view showing a part of the configuration of the same semiconductor memory device, showing the structure shown in Figure 103 cut along line AA' and viewed along the direction of the arrow.

[0157] The semiconductor memory device according to the fifth embodiment is basically configured in the same way as the first embodiment. However, the semiconductor memory device according to the fifth embodiment includes a transistor structure 550 instead of the transistor structure 150.

[0158] The transistor structure 550 is connected to a portion of the outer surface of the via wiring 104, in region R R The device comprises a semiconductor layer 551 extending in the X direction, an insulating layer 552 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the wiring 110 side) of the semiconductor layer 551, and a conductive layer 553 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the wiring 110 side) of the insulating layer 552.

[0159] In the XY cross-section illustrated in Figure 103, the side surface of the semiconductor layer 551 on one side in the X direction (the wiring 110 side) may be formed along a circle centered on the center position of the via wiring 102. Furthermore, the side surfaces of the semiconductor layer 551, insulating layer 552, and conductive layer 553 on one side in the Y direction may be formed linearly along the side surface of the insulating member 105. Additionally, the other side surface of the semiconductor layer 551 in the Y direction may comprise two linear portions extending in the X direction and a curved portion provided between these two portions. This curved portion is continuous with the two linear portions and forms part of the outer surface of the via wiring 104 (region R). R It may also be formed along the portion located on the inside of it.

[0160] The semiconductor layer 551 functions, for example, as the channel region of the readout transistor RTr (Figure 1). The semiconductor layer 551 is continuous with the semiconductor layer 141 and contains the same material as the semiconductor layer 141. The semiconductor layer 551 is formed, for example, simultaneously with the formation of the semiconductor layer 141.

[0161] The insulating layer 552 functions, for example, as a gate insulating film of the readout transistor RTr (Figure 1). The insulating layer 552 is continuous with the insulating layer 142 and contains the same material as the insulating layer 142. The insulating layer 552 is formed, for example, at the same time as the insulating layer 142 is formed.

[0162] The conductive layer 553 functions, for example, as the gate electrode of the readout transistor RTr (Figure 1). The conductive layer 553 contains the same material as the conductive layer 143. The conductive layer 553 is formed, for example, at the same time as the conductive layer 143. One side of the conductive layer 553 in the X direction (the wiring 110 side) is connected to the semiconductor layer 131.

[0163] In this configuration as in the first embodiment, a portion of the via wiring 104 is located in a substantially rectangular region R between two adjacent insulating members 105 in the Y direction. R It extends beyond the region R. Therefore, via wiring 104 is in region R. R Compared to a structure that does not extend beyond the boundaries, it is possible to reduce the capacitance between two adjacent conductive layers 553 in the Z direction.

[0164] Furthermore, in this configuration as in the first embodiment, not only a portion of via wiring 104, but also a portion of via wirings 102 and 103 are in region R. R It extends beyond the region R. Therefore, via connections 102 and 103 are in region R. R Compared to structures that do not extend beyond the boundaries, it is possible to reduce the area of ​​transistor structures 130 and 140 in the XY plane.

[0165] Furthermore, the transistor structures 130 and 140 according to this embodiment may also include insulating layers 134 and 144, similar to the transistor structures 130 and 140 according to the first embodiment.

[0166] Furthermore, the semiconductor memory device according to the fifth embodiment may also be provided with vias 204 and 304 (Figures 99 and 100) instead of vias 104. In such a case, vias 204 may be provided only at positions in the Y direction corresponding to insulating member 105e, as in the second embodiment, or only at positions in the Y direction corresponding to insulating member 105o. Also, vias 304 may be provided at positions in the Y direction corresponding to all insulating members 105, as in the third embodiment.

[0167] [Sixth Embodiment] Next, a semiconductor memory device according to the sixth embodiment will be described. In the sixth embodiment, the selection transistor STr (Figure 1) is equipped with a floating gate electrode, and this floating gate electrode is connected to the storage node SN. In the following description, parts the same as those in the fifth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0168] Figure 105 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. Figure 106 is a schematic cross-sectional view showing a part of the configuration of the same semiconductor memory device, showing the structure shown in Figure 105 cut along line AA' and viewed along the direction of the arrow.

[0169] The semiconductor memory device according to the sixth embodiment is basically configured in the same way as the fifth embodiment. However, the semiconductor memory device according to the sixth embodiment includes a transistor structure 640 instead of the transistor structure 140.

[0170] The transistor structure 640 is connected to a portion of the outer surface of the via wiring 103, in the region R. RThe device comprises a semiconductor layer 641 extending in the X direction, an insulating layer 642 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the semiconductor layer 641, a conductive layer 643 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the insulating layer 642, an insulating layer 142 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the conductive layer 643, and a conductive layer 143 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (wiring 120 side) of the insulating layer 142.

[0171] The semiconductor layer 641 functions, for example, as the channel region of the selection transistor STr (Figure 1). The semiconductor layer 641 is continuous with the semiconductor layer 551 and contains the same material as the semiconductor layer 551. The semiconductor layer 641 is formed, for example, simultaneously with the formation of the semiconductor layer 551.

[0172] The insulating layer 642 functions, for example, as a gate insulating film between the floating gate electrode and the channel region of a selection transistor STr (Figure 1). The insulating layer 642 is continuous with the insulating layer 552 and contains the same material as the insulating layer 552. The insulating layer 642 is formed, for example, at the same time as the insulating layer 552 is formed.

[0173] The conductive layer 643 functions, for example, as the floating gate electrode of the selection transistor STr (Figure 1). The conductive layer 643 is continuous with the conductive layer 553 and contains the same material as the conductive layer 553. The conductive layer 643 is formed, for example, at the same time as the conductive layer 553 is formed.

[0174] This configuration also makes it possible to achieve the same effects as the semiconductor memory device according to the fifth embodiment.

[0175] Furthermore, in this embodiment as well, similar to the fourth embodiment, it is conceivable to supply a voltage between these two threshold voltages to the read word line RWL that is the target of the read operation during the read operation. This makes it possible to suitably suppress the leakage current that may occur between the read bit line RBL and the source line SL during the read operation, similar to the fourth embodiment.

[0176] Furthermore, in this embodiment, as in the fourth embodiment, it is conceivable to supply a fixed voltage such as the ground voltage Vss to the read word line RWL during the write operation. This makes it possible to stabilize the voltage of the storage node SN.

[0177] Furthermore, the transistor structure 130 according to this embodiment may also include an insulating layer 144, similar to the transistor structure 130 according to the first embodiment.

[0178] Furthermore, the semiconductor memory device according to the sixth embodiment may have via wirings 204 and 304 (Figures 99 and 100) instead of via wiring 104. In such a case, via wiring 204 may be provided only at positions in the Y direction corresponding to insulating member 105e, as in the second embodiment, or only at positions in the Y direction corresponding to insulating member 105o. Also, via wiring 304 may be provided at positions in the Y direction corresponding to all insulating members 105, as in the third embodiment.

[0179] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0180] Sub...semiconductor substrate, ML...memory layer, WBL...write bit line, WWL...write word line, WTr...write transistor, RBL...read bit line, RWL...read word line, RTr...write transistor, SN...storage node, 101...insulating layer, 102,103,104...via wiring, 105...insulating material, 110,120...wiring, 130,140,150...transistor structure, 131,141,153...semiconductor layer, 132,142,152...insulating layer, 133,143,151...conductive layer.

Claims

1. A plurality of first wirings are arranged in a first direction and extend in a second direction intersecting the first direction, Multiple second wirings are arranged in the first direction, extend in the second direction, and are arranged alongside the multiple first wirings in a third direction that intersects the first and second directions, A first insulating member and a second insulating member are provided between the plurality of first wirings and the plurality of second wirings, arranged in the second direction and extending in the first and third directions, A plurality of first semiconductor layers are provided between the first insulating member and the second insulating member, arranged in the first direction and extending in the third direction, A plurality of first gate electrodes are arranged in the first direction, electrically connected to each of the plurality of first wirings, and facing the plurality of first semiconductor layers, A first via wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers, A plurality of second semiconductor layers are provided between the first insulating member and the second insulating member, arranged in the first direction and extending in the third direction, A plurality of second gate electrodes are arranged in the first direction, electrically connected to each of the plurality of second wirings, and facing the plurality of second semiconductor layers, A second via wiring extending in the first direction and electrically connected to the plurality of second semiconductor layers, A plurality of third semiconductor layers are provided between the plurality of first semiconductor layers and the plurality of second semiconductor layers, arranged in the first direction, extending in the third direction, and electrically connected to each of the plurality of second semiconductor layers, A plurality of third gate electrodes are arranged in the first direction, electrically connected to each of the plurality of first semiconductor layers, and facing the plurality of third semiconductor layers, A third via wiring extending in the first direction and electrically connected to the plurality of third semiconductor layers and Equipped with, In a predetermined cross-section extending in the second and third directions, One end of the third via wiring in the second direction is provided between a first position in the second direction corresponding to the side surface of the first insulating member on the second insulating member side, and a second position in the second direction corresponding to the side surface of the second insulating member on the first insulating member side. The other end of the third via wiring in the second direction is not located between the first and second positions. Semiconductor memory device.

2. In the predetermined cross-section, one of the plurality of third gate electrodes has a curved portion formed along a part of the outer surface of the third via wiring on one side in the second direction. The semiconductor memory device according to claim 1.

3. In the predetermined cross-section, the other side of one of the plurality of third gate electrodes in the second direction includes a linear portion formed along the second insulating member. The semiconductor memory device according to claim 2.

4. In the predetermined cross-section, the side surface of the first insulating member on the side of the second insulating member is, A linear first portion provided at the first position and extending in the third direction, A curved second portion that is continuous with the first portion and is formed along a part of the outer surface of the third via wiring, A semiconductor memory device according to claim 1, comprising:

5. In the predetermined cross-section, the side surface of the second insulating member on the first insulating member side is provided at the second position and includes a linear third portion extending in the third direction. The semiconductor memory device according to claim 4.

6. In the predetermined cross-section, One end of the first via wiring in the second direction is provided between the first position and the second position. The other end of the first via wiring in the second direction is not located between the first and second positions. The semiconductor memory device according to claim 1.

7. In the predetermined cross-section, the side surface of the first insulating member or the second insulating member includes a curved portion formed along a part of the outer surface of the first via wiring. The semiconductor memory device according to claim 6.

8. In the predetermined cross-section, One end of the second via wiring in the second direction is provided between the first position and the second position. The other end of the second via wiring in the second direction is not located between the first and second positions. The semiconductor memory device according to claim 1.

9. In the predetermined cross-section, the side surface of the first insulating member or the second insulating member includes a curved portion formed along a part of the outer surface of the second via wiring. The semiconductor memory device according to claim 8.

10. In the predetermined cross-section, the first insulating member is divided in the third direction via the third via wiring. The semiconductor memory device according to claim 1.

11. In the second direction, a fourth via is provided on the opposite side of the third via to the plurality of third semiconductor layers, extends in the first direction, and is electrically connected to the plurality of third semiconductor layers. In the predetermined cross-section, One end of the fourth via wiring in the second direction is provided between the first position and the second position, The other end of the fourth via wiring in the second direction is not located between the first and second positions. The semiconductor memory device according to claim 1.

12. In the predetermined cross-section, One of the plurality of third gate electrodes has a side surface in the second direction that includes a curved portion formed along a part of the outer surface of the third via wiring. The other side of one of the plurality of third gate electrodes in the second direction comprises a curved portion formed along another part of the outer surface of the fourth via wiring. The semiconductor memory device according to claim 11.

13. Each of the plurality of third semiconductor layers faces one side and the other side of the plurality of third gate electrodes in the first direction. The semiconductor memory device according to claim 1.

14. The device comprises a plurality of fourth gate electrodes arranged in the first direction, each electrically connected to the plurality of third gate electrodes, and facing the plurality of second semiconductor layers, Each of the plurality of second semiconductor layers faces one side and the other side of the plurality of fourth gate electrodes in the first direction. Each of the plurality of second gate electrodes faces one side and the other side of the plurality of second semiconductor layers in the first direction. The semiconductor memory device according to claim 13.

15. Each of the plurality of third gate electrodes faces one side and the other side of the plurality of third semiconductor layers in the first direction. The semiconductor memory device according to claim 1.

16. The device comprises a plurality of fifth gate electrodes arranged in the first direction, each electrically connected to the plurality of third gate electrodes, and facing the plurality of second semiconductor layers, Each of the plurality of fifth gate electrodes faces one side and the other side of the plurality of second semiconductor layers in the first direction. Each of the plurality of second gate electrodes faces one side and the other side of the plurality of fifth gate electrodes in the first direction. The semiconductor memory device according to claim 15.

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