Wiring board and method for manufacturing a wiring board

Abstract

The present invention provides a wiring board and a method for manufacturing a wiring board that suppresses the occurrence of short circuits between adjacent connection terminals. [Solution] The wiring board includes a wiring layer 122, a solder resist layer 130 on which an opening 131 is formed, and a connection terminal 150 formed on the upper surface of the wiring layer. The connection terminal has a seed layer 151, a metal post 152, a protective metal layer 153, a solder layer 155, and an alloy layer 154. The seed layer is laminated on the upper surface of the wiring layer. The post is laminated on the upper surface of the seed layer. The protective metal layer is laminated on the upper surface of the post. The solder layer is formed on the upper surface of the protective metal layer. The alloy layer is formed at the interface between the protective metal layer and the solder layer and consists of at least a portion of an intermetallic compound. The solder layer covers the upper and side surfaces of the alloy layer. The side surfaces of the alloy layer are located closer to the center of the post than the side surfaces of the post.

Description

[[Technical Field]]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [[Background Art]]

[0002] Generally, connection terminals for connecting to a semiconductor chip are sometimes formed on a wiring board on which the semiconductor chip is mounted. The connection terminals are metal protrusions formed on the surface of the wiring board. Such connection terminals may have a multilayer structure in which a plurality of metal layers are stacked, for example.

[0003] Specifically, a seed layer made of a metal such as copper is formed on a surface of an insulating layer forming a wiring board, a post made of a metal such as copper is formed on an upper surface of the seed layer, and a protective metal layer made of a metal such as nickel is formed on an upper surface of the post. After a solder layer is stacked on the upper surface of the protective metal layer, only the solder layer is melted by a reflow process, thereby forming a connection terminal having a spherical surface. [[Prior Art Documents]] [[Patent Documents]]

[0004] [[Patent Document 1]] Japanese Unexamined Patent Publication No. 2022-189275 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] However, in the wiring board having the above-described connection terminals, there is a problem that a short circuit occurs between adjacent connection terminals. Specifically, when the reflow process is performed on the solder layer that is the top of the connection terminals, the solder layer melts and extends in the lateral direction, so that the solder layers of adjacent connection terminals come into contact with each other, and as a result, a short circuit may occur between adjacent connection terminals.

[0006] The disclosed technology was made in view of the above, and aims to provide a wiring board and a method for manufacturing a wiring board that can suppress the occurrence of short circuits between adjacent connection terminals. [Means for solving the problem]

[0007] In one embodiment, the wiring board disclosed herein has an insulating layer and a connection terminal formed on the upper surface of the insulating layer. The connection terminal has a seed layer, a metal post, a protective metal layer, a solder layer, and an alloy layer. The seed layer is laminated on the upper surface of the insulating layer. The post is laminated on the upper surface of the seed layer. The protective metal layer is laminated on the upper surface of the post. The solder layer is formed on the upper surface of the protective metal layer. The alloy layer is formed at the interface between the protective metal layer and the solder layer and consists of at least a portion of an intermetallic compound. The solder layer covers the upper and side surfaces of the alloy layer. The side surfaces of the alloy layer are located closer to the center of the post than the side surfaces of the post. [Effects of the Invention]

[0008] According to one embodiment of the wiring board disclosed in this application, the effect is to suppress the occurrence of short circuits between adjacent connection terminals. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows the configuration of a wiring board according to an embodiment. [Figure 2] Figure 2 is a magnified view of the connection terminals according to the embodiment. [Figure 3] Figure 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] Figure 4 shows a specific example of the core substrate formation process. [Figure 5] Figure 5 shows a specific example of the build-up process. [Figure 6] Figure 6 shows a specific example of the solder resist layer formation process. [Figure 7] Figure 7 shows a specific example of the connection terminal formation process. [Figure 8] FIG. 8 is a diagram illustrating a specific example of a semiconductor chip mounting step. [Figure 9] FIG. 9 is a flowchart illustrating a connection terminal forming step according to an embodiment. [Figure 10] FIG. 10 is a diagram illustrating an opening of a solder resist layer. [Figure 11] FIG. 11 is a diagram illustrating seed layer formation. [Figure 12] FIG. 12 is a diagram illustrating patterning. [Figure 13] FIG. 13 is a diagram illustrating post formation. [Figure 14] FIG. 14 is a diagram illustrating protective metal layer formation. [Figure 15] FIG. 15 is a diagram illustrating metal layer formation. [Figure 16] FIG. 16 is a diagram illustrating solder layer formation. [Figure 17] FIG. 17 is a diagram illustrating resist removal. [Figure 18] FIG. 18 is a diagram illustrating seed layer etching. [Figure 19] FIG. 19 is a diagram illustrating reflow. [Figure 20] FIG. 20 is a diagram illustrating a structure of a connection terminal according to Modification 1 of the embodiment. [Figure 21] FIG. 21 is a diagram illustrating a structure of a connection terminal according to Modification 2 of the embodiment. [Figure 22] FIG. 22 is a diagram illustrating a structure of a connection terminal according to Modification 3 of the embodiment. [Figure 23] FIG. 23 is a diagram illustrating post formation. [Figure 24] FIG. 24 is a diagram illustrating protective metal layer formation. [Figure 25] FIG. 25 is a diagram illustrating metal layer formation. [Figure 26] FIG. 26 is a diagram illustrating solder layer formation. DESCRIPTION OF EMBODIMENTS

[0010] The embodiments of the wiring board and the method for manufacturing the wiring board disclosed in this application will be described in detail below with reference to the drawings. However, the disclosed technology is not limited by these embodiments.

[0011] (Embodiment) Figure 1 is a diagram showing the configuration of a wiring board 100 according to an embodiment. In Figure 1, a schematic cross-section of the wiring board 100 is shown. The wiring board 100 shown in Figure 1 can be used, for example, as a substrate for a semiconductor device on which a semiconductor chip is mounted.

[0012] The wiring board 100 has a laminated structure and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. In the following description, as shown in Figure 1, the solder resist layer 140 is the bottom layer and the solder resist layer 130 is the top layer. However, the wiring board 100 may be used upside down, for example, or in any orientation.

[0013] The core substrate 110 is formed by plating metal on both sides of a base material 111, which is a plate-shaped insulator. The wiring layers 113 on both sides are connected by through-wiring 112 that penetrates the base material 111 as needed.

[0014] The multilayer wiring structure 120 is formed by laminating layers, each comprising an insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed using an insulating resin such as epoxy resin and polyimide resin. The wiring layer 122 is formed using a metal such as copper or a copper alloy. In Figure 1, two layers are laminated in the multilayer wiring structure 120 above the core substrate 110, and two layers are laminated in the multilayer wiring structure 120 below the core substrate 110, but the number of laminated layers may be one or three or more. Adjacent wiring layers 113 and 122 are connected via vias 123 that penetrate the insulating layer 121 as needed.

[0015] The solder resist layer 130 is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers. The solder resist layer 130 may also be formed using an insulating non-photosensitive resin such as epoxy resin.

[0016] The solder resist layer 130 side of the wiring board 100 is the side on which electronic components such as semiconductor chips are mounted. At the location where the semiconductor chip is mounted, an opening 131 is formed in the solder resist layer 130. That is, an opening 131 is formed in the solder resist layer 130 to connect the electrodes of the semiconductor chip to the wiring layers 122 of the multilayer wiring structure 120. If the solder resist layer 130 is formed using a photosensitive resin, the opening 131 can be formed by exposure and development. If the solder resist layer 130 is formed using a non-photosensitive resin, the opening 131 can be formed by laser processing. A connection terminal 150 is formed in the opening 131 to connect the wiring layers 122 of the multilayer wiring structure 120 to the electrodes of the semiconductor chip. The connection terminal 150 is a protruding electrode formed to protrude from the upper surface 130a of the solder resist layer 130.

[0017] The structure of the connection terminal 150 will now be described with reference to Figure 2. Figure 2 is an enlarged view of the connection terminal 150 according to this embodiment.

[0018] As shown in Figure 2, the connector 150 has a multilayer structure in which multiple metal layers are stacked. Specifically, the connector 150 has a seed layer 151, a post 152, a protective metal layer 153, an alloy layer 154, and a solder layer 155.

[0019] The seed layer 151 is a metal layer formed on the inner surface and upper surface 130a of the opening 131 of the solder resist layer 130, and on the upper surface of the wiring layer 122 exposed at the bottom of the opening 131. The seed layer 151 is provided in an annular shape on the upper surface 130a of the solder resist layer 130 around the periphery of the opening 131. The seed layer 151 is made of, for example, copper (Cu) and is laminated on the inner surface and upper surface 130a of the opening 131 of the solder resist layer 130 by electroless plating. The thickness of the seed layer 151 can be, for example, about 10 nm to 500 nm.

[0020] Post 152 is an electrode that forms the main body of the connection terminal 150 and is formed on the upper surface of the seed layer 151 by, for example, electroplating of copper (Cu). Post 152 can be formed by, for example, a semi-additive method. The thickness of post 152 (i.e., the thickness of only the portion above the upper surface of the seed layer 151, excluding the portion inside the opening 131) can be, for example, about 2 μm to 50 μm.

[0021] The protective metal layer 153 is a metal layer formed on the upper surface of the post 152. The protective metal layer 153 is made of, for example, nickel (Ni) and is laminated on the upper surface of the post 152 by electroplating. The thickness of the protective metal layer 153 can be, for example, about 0.01 μm to 3 μm.

[0022] The solder layer 155 is a metal layer formed on the upper surface of the protective metal layer 153. The solder layer 155 is made of, for example, tin (Sn) and is laminated on the upper surface of the protective metal layer 153 by electroplating. In addition to tin (Sn), the solder layer 155 may also be formed using various solder metals such as tin (Sn)-silver (Ag) alloys, tin (Sn)-silver (Ag)-copper (Cu) alloys, and tin (Sn)-bismuth (Bi) alloys. The upper surface of the solder layer 155 protrudes upward in a curved shape (for example, spherical). The solder layer 155 is, for example, hemispherical. A hemispherical solder layer 155 can be obtained, for example, by reflowing a solder layer 155 formed on the upper surface of the protective metal layer 153 by electroplating. A hemispherical solder layer 155 is also called a "solder bump".

[0023] The alloy layer 154 is formed at the interface (i.e., the joint surface) between the protective metal layer 153 and the solder layer 155. The alloy layer 154 is formed by the reaction of a layer of a different metal (e.g., copper (Cu)) from the protective metal layer 153, which is laminated on the upper surface of the protective metal layer 153, with the solder layer 155. The alloy layer 154 is a layer made of an intermetallic compound that contains at least a different metal (e.g., copper (Cu)) from the protective metal layer 153 and tin (Sn) that forms the solder layer 155. The intermetallic compound that forms the alloy layer 154 may also contain a different metal (e.g., copper (Cu)) from the protective metal layer 153, tin (Sn) that forms the solder layer 155, and nickel (Ni) that forms the protective metal layer 153. An example of the intermetallic compound that forms the alloy layer 154 is (Cu,Ni)6Sn5.

[0024] As shown in Figure 2, the solder layer 155 covers the top and sides of the alloy layer 154. The sides of the alloy layer 154 covered by the solder layer 155 are located closer to the center of the post 152 than the sides of the post 152. That is, the sides of the alloy layer 154 are set back closer to the center of the post 152 than the sides of the post 152 in the direction along the top surface of the protective metal layer 153. Here, the sides of the post 152 refer only to the sides above the top surface of the seed layer 151, excluding the portion inside the opening 131. Because the sides of the alloy layer 154 are located closer to the center of the post 152 than the sides of the post 152, a step is formed near the sides of the alloy layer 154, recessed towards the center of the post 152, between the sides of the alloy layer 154 and the sides of the protective metal layer 153.

[0025] Thus, in this embodiment, by positioning the side surface of the alloy layer 154 closer to the center of the post 152 than the side surface of the post 152, it is possible to suppress the solder layer 155 covering the side surface of the alloy layer 154 from extending laterally from the side surface of the alloy layer 154. That is, when the side surface of the alloy layer 154 is located further out than the side surface of the post 152, the step difference between the side surface of the alloy layer 154 and the side surface of the protective metal layer 153 is relatively small, and the solder layer 155 can easily extend laterally from the side surface of the alloy layer 154. In contrast, when the side surface of the alloy layer 154 is located closer to the center of the post 152 than the side surface of the post 152, the step difference between the side surface of the alloy layer 154 and the side surface of the protective metal layer 153 is relatively large. As a result, it is possible to suppress the solder layer 155 from extending laterally from the side surface of the alloy layer 154, and thus it is possible to suppress the solder layers 155 of adjacent connection terminals 150 from coming into contact with each other. As a result, it is possible to suppress the occurrence of short circuits between adjacent connection terminals 150.

[0026] Furthermore, in this embodiment, the alloy layer 154 is narrower than the post 152. This allows the side surface of the alloy layer 154 to be set further back toward the center of the post 152 than the side surface of the post 152, thereby further suppressing the lateral elongation of the solder layer 155.

[0027] Furthermore, in this embodiment, the alloy layer 154 is a layer made of an intermetallic compound containing at least a different metal from the protective metal layer 153 (for example, copper (Cu)) and tin (Sn) that forms the solder layer 155. By forming the alloy layer 154 from an intermetallic compound containing at least Cu and Sn, it is possible to suppress the diffusion of Sn from the solder layer 155 into the Ni of the protective metal layer 153 and the subsequent reaction of Ni in the protective metal layer 153. As a result, the depletion of Ni in the protective metal layer 153 can be suppressed, and the fracture of the connection terminal 150 at the location of the protective metal layer 153 can be suppressed.

[0028] Furthermore, in this embodiment, the side surface of the protective metal layer 153 is located outward from the side surface of the post 152. The side surface of the alloy layer 154 is located closer to the center of the post 152 than the side surface of the protective metal layer 153. The solder layer 155 extends from the side surface of the alloy layer 154 in a direction along the upper surface of the protective metal layer 153 to a position where it does not reach the side surface of the protective metal layer 153, exposing a region of the upper surface of the protective metal layer 153 that does not overlap with the solder layer 155 in a plan view. This region of the upper surface of the protective metal layer 153 that does not overlap with the solder layer 155 in a plan view is provided in an annular shape around the solder layer 155. By exposing the region of the upper surface of the protective metal layer 153 that does not overlap with the solder layer 155 in a plan view, the visibility of the upper surface of the protective metal layer 153 can be improved. As a result, the accuracy of inspections using reflected light from the upper surface of the protective metal layer 153 can be improved.

[0029] Furthermore, in this embodiment, the solder layer 155 is narrower than the protective metal layer 153. That is, the width of the solder layer 155 in the direction along the upper surface of the protective metal layer 153 is narrower than the width of the protective metal layer 153 in the direction along the upper surface of the protective metal layer 153. As a result, the exposed area of ​​the region of the upper surface of the protective metal layer 153 that does not overlap with the solder layer 155 in a plan view is increased, thereby improving the visibility of the upper surface of the protective metal layer 153. Consequently, the accuracy of inspections using reflected light from the upper surface of the protective metal layer 153 can be further improved. In this case, the solder layer 155 may be wider than the post 152. This ensures a sufficient volume of solder layer 155 for bonding the electrodes of the semiconductor chip.

[0030] Returning to the explanation of Figure 1, the solder resist layer 140, like the solder resist layer 130, is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of an insulating photosensitive resin such as acrylic resin and polyimide resin, and is one of the insulating layers. The solder resist layer 140 may also be formed using an insulating non-photosensitive resin such as epoxy resin.

[0031] The solder resist layer 140 side of the wiring board 100 is the side that connects to external components and equipment. At the locations where external connection terminals that electrically connect to external components and equipment are formed, an opening 141 is formed in the solder resist layer 140, and the wiring layer 122 of the multilayer wiring structure 120 is exposed through the opening 141. External connection terminals, such as solder balls, are formed in the opening 141. If the solder resist layer 140 is formed using a photosensitive resin, the opening 141 can be formed by exposure and development. If the solder resist layer 140 is formed using a non-photosensitive resin, the opening 141 can be formed by laser processing.

[0032] Next, a method for manufacturing a semiconductor device having the wiring board 100 configured as described above will be explained with reference to Figure 3, with specific examples. Figure 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.

[0033] First, a core substrate 110, which will serve as a support member for the wiring board 100, is formed (step S101). Specifically, as shown in Figure 4, for example, through-wiring 112 is formed on a base material 111, which is a plate-shaped insulator, and metal wiring layers 113, such as copper or a copper alloy, are formed on both sides of the base material 111, for example, by copper foil or copper plating. Figure 4 shows a specific example of the core substrate formation process. The wiring layers 113 on both sides of the base material 111 are connected by through-wiring 112 formed by metal plating, such as copper or a copper alloy, as needed. As the base material 111, for example, a reinforcing material such as glass woven fabric impregnated with an insulating resin such as epoxy resin can be used. As the reinforcing material, in addition to glass woven fabric, glass nonwoven fabric, aramid woven fabric, or aramid nonwoven fabric can be used. As the insulating resin, in addition to epoxy resin, polyimide resin or cyanate resin can be used.

[0034] Then, a multilayer wiring structure 120 is formed on the upper and lower surfaces of the core substrate 110 by a build-up method (step S102). Specifically, as shown in Figure 5, for example, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110, and a wiring layer 122 is formed on the surface of the insulating layer 121. Figure 5 is a diagram showing a specific example of the build-up process. The insulating layer 121 is formed using an insulating resin such as epoxy resin or polyimide resin. The wiring layer 122 is formed by plating a metal such as copper or a copper alloy. For example, the wiring layer 122 is formed by a semi-additive method.

[0035] The wiring layers 113 and 122 of the core substrate 110, or the wiring layers 122 of adjacent layers, are connected by vias 123 formed by metal plating, such as copper or a copper alloy, as needed. Multiple insulating layers 121 and wiring layers 122 may be laminated on the upper and lower surfaces of the core substrate 110, respectively.

[0036] Once the multilayer wiring structure 120 is formed, the wiring layers 122 on the surface of the multilayer wiring structure 120 are covered with solder resist layers 130 and 140 (step S103). Specifically, the wiring layers 122 on the surface of the multilayer wiring structure 120 laminated on the upper surface of the core substrate 110 are covered with solder resist layer 130, and the wiring layers 122 on the surface of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 are covered with solder resist layer 140.

[0037] Then, as shown in Figure 6, for example, an opening 131 is formed in the solder resist layer 130 on the side on which the semiconductor chip is mounted, at a position where connection terminals to the semiconductor chip are provided. Figure 6 is a diagram showing a specific example of the solder resist layer formation process. At the bottom of the opening 131, the wiring layer 122 on the surface of the multilayer wiring structure 120 is exposed. On the other hand, an opening 141 is formed in the solder resist layer 140 on the side that is connected to external components or equipment, at a position where external connection terminals are provided. At the bottom of the opening 141, the wiring layer 122 on the surface of the multilayer wiring structure 120 is exposed.

[0038] When photosensitive resins are used as solder resist layers 130 and 140, the openings 131 and 141 can be formed by exposure and development. When non-photosensitive resins are used as solder resist layers 130 and 140, the openings 131 and 141 can be formed by laser processing.

[0039] Then, a connection terminal for connecting a semiconductor chip is formed in the opening 131 of the solder resist layer 130 (step S104). That is, as shown in Figure 7, for example, a connection terminal 150 is formed in the opening 131. Figure 7 is a diagram showing a specific example of the connection terminal formation process. The connection terminal 150 has a multilayer structure and includes a seed layer 151 (see Figure 2), a post 152, a protective metal layer 153, an alloy layer 154, and a solder layer 155, with the solder layer 155, which is laminated on the upper surface of the protective metal layer 153, protruding upward in a curved shape (for example, spherical). The seed layer 151, post 152, protective metal layer 153, and solder layer 155 are all formed by plating.

[0040] The seed layer 151 is formed by electroless plating of, for example, copper (Cu) on the inner surface and upper surface 130a of the opening 131 of the solder resist layer 130. The post 152 is formed by electroplating of, for example, copper (Cu) on the upper surface of the seed layer 151 around the opening 131. The protective metal layer 153 is formed by electroplating of, for example, nickel (Ni) on the upper surface of the post 152. Then, a copper (Cu) metal layer is formed by electroplating of, for example, copper (Cu) on the upper surface of the protective metal layer 153, and the solder layer 155 is formed by electroplating of, for example, tin (Sn) on the upper surface of the protective metal layer 153 via this metal layer.

[0041] After the seed layer 151, post 152, protective metal layer 153, metal layer, and solder layer 155 are formed in sequence, the unnecessary portion of the seed layer 151 is removed by etching. When the seed layer 151 is removed, the post 152 and metal layer are thinned from the side by side etching. However, because the metal layer is thinner than the post 152, the metal layer is removed from the center of the post 152 beyond the side surface. After the metal layer is removed from the center of the post 152 beyond the side surface, the solder layer 155 is melted by a reflow process and protrudes upward and sideways in a curved shape (for example, spherical). At this time, the metal layer and the solder layer 155 react, and an alloy layer 154 made of an intermetallic compound is formed at the interface between the protective metal layer 153 and the solder layer 155.

[0042] Because the metal layer is removed from the post 152 to the center of the post 152 rather than the sides, when the metal layer and the solder layer 155 react during the reflow process, an alloy layer 154 is formed whose sides are located closer to the center of the post 152 than the sides of the post 152. The top and sides of the alloy layer 154 are then covered by the solder layer 155. This prevents the solder layer 155 covering the sides of the alloy layer 154 from extending laterally from the sides of the alloy layer 154. The process for forming the connection terminal 150 will be described in detail later.

[0043] When the connection terminal 150 is formed on the solder resist layer 130 side, an external connection terminal is formed on the solder resist layer 140 side (step S105). Then, a semiconductor chip is mounted on the solder resist layer 130 side (step S106), and the connection terminal 150 is connected to the electrodes of the semiconductor chip. Specifically, as shown in Figure 8 for example, an external connection terminal such as a solder ball 170 is formed in the opening 141 of the solder resist layer 140. The semiconductor chip 200 is then mounted above the connection terminal 150, and the electrodes 210 of the semiconductor chip 200 are joined to the connection terminal 150. At this time, the bumps 210a provided on the electrodes 210 of the semiconductor chip 200 and the connection terminal 150 are melted and integrated by reflow. Figure 8 shows a specific example of the semiconductor chip mounting process.

[0044] The joint between the electrode 210 and the connection terminal 150 is then sealed with underfill resin 220, resulting in a semiconductor device on which the semiconductor chip 200 is mounted on the wiring board 100. Note that the order of the process of forming the external connection terminals and the process of mounting the semiconductor chip may be reversed. That is, after the semiconductor chip 200 is mounted on the wiring board 100, external connection terminals such as solder balls 170 may be formed in the openings 141 of the solder resist layer 140.

[0045] Next, the process of forming connection terminals 150 for connecting semiconductor chips 200 will be described in more detail with reference to Figure 9. Figure 9 is a flowchart of the connection terminal formation process according to an embodiment.

[0046] When a multilayer wiring structure 120 is laminated on the upper surface of the core substrate 110, the wiring layers 122 of the multilayer wiring structure 120 are covered with a solder resist layer 130. An opening 131 is formed in the solder resist layer 130, for example, as shown in Figure 10. Figure 10 shows an opening 131 in the solder resist layer 130. The opening 131 is formed, for example, in a circular shape in a plan view. The wiring layers 122 are exposed at the bottom of the opening 131.

[0047] In this state, a seed layer is formed on the upper surface 130a of the solder resist layer 130 (step S201). That is, as shown in Figure 11, for example, a seed layer 151 is formed by electroless copper plating, for example, to continuously cover the upper surface 130a of the solder resist layer 130, the inner surface of the opening 131, and the upper surface of the wiring layer 122 exposed at the bottom of the opening 131. Figure 11 is a diagram illustrating the formation of the seed layer. The thickness of the seed layer 151 can be, for example, about 10 nm to 500 nm.

[0048] Next, patterning is performed to form a circuit pattern on the surface of the wiring board 100 (step S202). Specifically, as shown in Figure 12, for example, after the dry film resist (DFR) 302 is attached to the surface of the wiring board 100, exposure and development of the circuit pattern are performed, and the DFR 302 is removed from the wiring portion including the opening 131. Figure 12 is a diagram illustrating the patterning process.

[0049] Then, by supplying power from the seed layer 151 and performing electrolytic copper plating, a post 152 is formed on the upper surface of the seed layer 151 (step S203). Specifically, by performing electrolytic copper plating using, for example, a copper sulfate plating solution, copper (Cu) is deposited in the areas where DFR302 has not been formed, and a post 152 is formed on the upper surface of the seed layer 151, as shown in Figure 13. At this time, the inside of the opening 131 is filled by electrolytic plating. Figure 13 is a diagram illustrating the formation of the post. The thickness of the post 152 (i.e., the thickness of only the part above the upper surface of the seed layer 151, excluding the part inside the opening 131) can be, for example, about 2 μm to 50 μm.

[0050] After the post 152 is formed, electrolytic nickel plating is performed by supplying power from the seed layer 151, so that a protective metal layer 153 is formed on the upper surface of the post 152, for example, as shown in Figure 14 (step S204). Figure 14 is a diagram illustrating the formation of the protective metal layer. By forming the protective metal layer 153 on the upper surface of the post 152, a protective metal layer 153, which is a layer of a different metal from the post 152, is interposed between the post 152 and the solder layer 155. The presence of the protective metal layer 153 suppresses the diffusion of copper (Cu) from the post 152 to tin (Sn) in the solder layer 155. The thickness of the protective metal layer 153 can be, for example, about 0.01 μm to 3 μm.

[0051] After the protective metal layer 153 is formed, electrolytic copper plating is performed by supplying power from the seed layer 151, thereby forming a metal layer 156 on the upper surface of the protective metal layer 153, for example, as shown in Figure 15 (step S205). Figure 15 is a diagram illustrating the formation of the metal layer. The thickness of the metal layer 156 can be, for example, about 1 μm to 4 μm, and is smaller than the thickness of the post 152 (i.e., the thickness of only the part above the upper surface of the seed layer 151, excluding the part inside the opening 131). If the thickness of the metal layer 156 is less than 1 μm, an alloy layer 154 of sufficient thickness will not be formed when the reflow process described later is performed. If the thickness of the metal layer 156 is greater than 4 μm, copper (Cu) from the metal layer 156 will remain in the alloy layer 154 formed when the reflow process is performed.

[0052] After the metal layer 156 is formed, electrolytic tin plating is performed by supplying power from the seed layer 151, so that a solder layer 155 is formed on the upper surface of the protective metal layer 153 via the metal layer 156, for example as shown in Figure 16 (step S206). Figure 16 is a diagram illustrating the formation of the solder layer.

[0053] Once the solder layer 155 is formed, the DFR 302 is removed (step S207). For removing the DFR 302, for example, caustic soda or an amine-based alkaline stripping solution is used. After the removal of the DFR 302, as shown in Figure 17, for example, at the location of the opening 131, the seed layer 151, post 152, protective metal layer 153, metal layer 156 and solder layer 155 are stacked and protrude from the upper surface 130a of the solder resist layer 130. Figure 17 is a diagram illustrating the removal of the resist. At this stage, the seed layer 151 remains over the entire surface, and the post 152 is short-circuited with other posts, so it is necessary to remove the unnecessary portion of the seed layer 151 that does not overlap with the post 152.

[0054] Therefore, etching of the seed layer 151 is performed using post 152 as a mask (step S208). Specifically, the seed layer 151 formed on the upper surface 130a of the solder resist layer 130 is immersed in an etching solution that selectively dissolves, for example, copper, and the unnecessary portion of the seed layer 151 that does not overlap with post 152 is removed, for example, as shown in Figure 18. Figure 18 is a diagram illustrating seed layer etching.

[0055] During the etching of the seed layer 151, the unwanted portion of the seed layer 151 is dissolved, and at the same time, side etching proceeds, dissolving the post 152 and the metal layer 156 from the sides. As the post 152 and the metal layer 156 are dissolved from the sides by side etching, the sides of the post 152 and the sides of the metal layer 156 curve into a concave shape. Here, since the metal layer 156 is thinner than the post 152, the side etching of the metal layer 156 proceeds faster than the side etching of the post 152. In other words, the amount of side etching of the metal layer 156 is greater than the amount of side etching of the post 152. As a result, the metal layer 156 is removed up to the center of the post 152, beyond the sides of the post 152, and the sides of the metal layer 156 recede further towards the center of the post 152 than the sides of the post 152. In other words, the width of the metal layer 156 becomes smaller than the width of the post 152 (the maximum width of the post 152 at the periphery of the concave curved side).

[0056] By etching to remove the seed layer 151, the seed layer 151, post 152, protective metal layer 153, metal layer 156, and solder layer 155 are stacked at the location of the opening 131, forming a conductive portion that protrudes from the upper surface 130a of the solder resist layer 130.

[0057] Subsequently, a reflow process is performed at a reflow temperature that melts the solder layer 155 (step S209). That is, the solder layer 155 is melted under reflow conditions including predetermined reflow temperature and reflow time, and then solidified by cooling. This results in a hemispherical solder layer 155 (solder bump).

[0058] As a result, the upper surface of the solder layer 155 protrudes in a curved shape (for example, spherical shape), as shown in Figure 19, and a connection terminal 150 is formed. Figure 19 is a diagram illustrating reflow. In reflow, the metal layer 156 and the solder layer 155 react to form an alloy layer 154 made of an intermetallic compound at the interface between the protective metal layer 153 and the solder layer 155. For example, copper (Cu) diffused from the metal layer 156 reacts with the tin (Sn) in the solder layer 155 and the nickel (Ni) in the protective metal layer 153 to form an alloy layer 154 made of the intermetallic compound (Cu,Ni)6Sn5. The reflow conditions applied to reflow are set so that an alloy layer 154 made of an intermetallic compound is formed at the interface between the protective metal layer 153 and the solder layer 155. For example, reflow can be performed under reflow conditions where the reflow temperature is around 230°C to 280°C and the reflow time is around 10 to 200 seconds.

[0059] Here, since the metal layer 156 is removed from the post 152 to the center of the post 152 rather than the side surface, the metal layer 156 and the solder layer 155 react to form an alloy layer 154 whose side surface is located closer to the center of the post 152 than the side surface. In other words, the width W1 of the alloy layer 154 is smaller than the width W2 of the post 152 (the maximum width of the post 152 at the periphery of the concave curved side surface). Then, a solder layer 155 is formed that covers the top and side surfaces of the alloy layer 154. As a result, it is possible to suppress the solder layer 155 covering the side surface of the alloy layer 154 from extending laterally from the side surface of the alloy layer 154. As a result, it is possible to suppress the occurrence of short circuits between adjacent connection terminals 150.

[0060] In addition, at the connection terminal 150, the post 152, protective metal layer 153, alloy layer 154, and solder layer 155 may be circular in shape when viewed from above. In this case, the relative sizes of the diameters of the post 152, protective metal layer 153, alloy layer 154, and solder layer 155 may correspond to the relative sizes of the widths of the post 152, protective metal layer 153, alloy layer 154, and solder layer 155.

[0061] (modified version) Next, various modifications of the embodiment will be described with reference to Figures 20 to 26. In the modifications shown below, the same reference numerals are used for parts that are the same as in the embodiment, and redundant explanations may be omitted.

[0062] Figure 20 shows the structure of a connection terminal 150 according to a modified example 1 of the embodiment. In the above embodiment, the case in which the entire alloy layer 154 is made of an intermetallic compound was illustrated, but a part of the alloy layer 154 may be made of an intermetallic compound, and copper (Cu) that forms the metal layer 156 may remain in the other part of the alloy layer 154. That is, the alloy layer 154 may have a two-layer structure of copper (Cu) that forms the metal layer 156 and an intermetallic compound. For example, as shown in Figure 20, the alloy layer 154 may have a core layer 161 made of copper (Cu) that forms the metal layer 156, and an interface layer 162 made of an intermetallic compound that contains at least copper (Cu) that forms the core layer 161 and tin (Sn) that forms the solder layer 155. The core layer 161 is located on the upper surface of the protective metal layer 153, and the interface layer 162 is located at the interface between the core layer 161 and the solder layer 155.

[0063] Such a two-layer alloy layer 154 can be formed by making the reflow temperature and reflow time shorter than a predetermined time. Alternatively, the two-layer alloy layer 154 can also be formed by making the thickness of the metal layer 156 formed on the upper surface of the protective metal layer 153 greater than, for example, 4 μm.

[0064] In Modification 1, the alloy layer 154 has a two-layer structure of copper (Cu) and an intermetallic compound, which further suppresses the diffusion of Sn from the solder layer 155 into the Ni of the protective metal layer 153 and the subsequent reaction of Ni in the protective metal layer 153. As a result, the depletion of Ni in the protective metal layer 153 can be further suppressed, and thus the fracture of the connection terminal 150 at the location of the protective metal layer 153 can be further suppressed.

[0065] Figure 21 shows the structure of the connection terminal 150 according to the second modified embodiment. The wiring board 100 according to the second modified embodiment differs from the embodiment in the configuration of the solder layer 155 of the connection terminal 150.

[0066] In other words, as shown in Figure 21, the solder layer 155 may be narrower than the post 152. The width of the solder layer 155 can be adjusted by making the thickness of the solder layer 155 formed on the upper surface of the protective metal layer 153 less than a predetermined thickness.

[0067] In the modified example 2, the width of the solder layer 155 is smaller than the width of the post 152, which further suppresses the occurrence of short circuits between adjacent connection terminals 150.

[0068] Figure 22 shows the structure of the connection terminal 150 according to the third modified embodiment. In the above embodiment, the case in which the upper surface of the post 152, the upper surface of the protective metal layer 153, and the upper surface of the alloy layer 154 are flat surfaces was illustrated, but the shapes of the post 152, the protective metal layer 153, and the alloy layer 154 are not limited thereto. For example, as shown in Figure 22, the upper surface of the post 152 may protrude upward in a curved shape (e.g., spherical). The upper surfaces of the protective metal layer 153 and the upper surface of the alloy layer 154 may be curved in a curved shape (e.g., spherical) corresponding to the upper surface of the post 152.

[0069] When forming the connection terminal 150 shown in Figure 22, once the DFR 302 is removed from the wiring portion including the opening 131 by patterning, a post 152 is formed on the upper surface of the seed layer 151 by electrolytic copper plating at a predetermined current density. That is, by electrolytic copper plating at a current density greater than the current density required for the upper surface of the post 152 to be a flat surface, the upper surface of the post 152 formed on the upper surface of the seed layer 151 protrudes upward in a curved shape (for example, spherical shape), as shown in Figure 23. Figure 23 is a diagram illustrating the formation of the post.

[0070] After the post 152 is formed, a protective metal layer 153 is formed on the upper surface of the post 152 by electrolytic nickel plating. In the formation of the protective metal layer 153, a uniform thickness of plating is applied along the upper surface of the post 152. Therefore, as shown in Figure 24, for example, the upper surface of the protective metal layer 153 formed on the upper surface of the post 152 is curved in a curved shape (for example, spherical) corresponding to the upper surface of the post 152. Figure 24 is a diagram illustrating the formation of the protective metal layer.

[0071] After the protective metal layer 153 is formed, electrolytic copper plating is applied to form a metal layer 156 on the upper surface of the protective metal layer 153. In the formation of the metal layer 156, a uniform thickness of plating is applied along the upper surface of the protective metal layer 153. Therefore, as shown in Figure 25, for example, the upper surface of the metal layer 156 formed on the upper surface of the protective metal layer 153 is curved in a curved shape (for example, spherical) corresponding to the upper surface of the post 152 and the upper surface of the protective metal layer 153. Figure 25 is a diagram illustrating the formation of the metal layer.

[0072] After the metal layer 156 is formed, electrolytic tin plating is applied to form a solder layer 155 on the upper surface of the protective metal layer 153 via the metal layer 156. In the formation of the solder layer 155, a uniform thickness of plating is applied along the upper surface of the protective metal layer 153 via the metal layer 156. As a result, as shown in Figure 26, the upper surface of the solder layer 155 formed on the upper surface of the protective metal layer 153 via the metal layer 156 is curved in a curved shape (for example, spherical) corresponding to the upper surface of the post 152, the upper surface of the protective metal layer 153, and the upper surface of the metal layer 156. Figure 26 is a diagram illustrating the formation of the solder layer.

[0073] Subsequently, similar to the embodiment, the DFR302 is removed, the seed layer 151 is etched, and reflow is performed to form the connection terminal 150 shown in Figure 22.

[0074] Thus, in Modification 3, the upper surface of the post 152 protrudes upward in a curved shape (for example, spherical), and the upper surfaces of the protective metal layer 153 and the alloy layer 154 are curved in a curved shape (for example, spherical) corresponding to the upper surface of the post 152. As a result, the area of ​​the joint surface between the post 152 and the protective metal layer 153 and the interface (i.e., joint surface) between the protective metal layer 153 and the solder layer 155 increases compared to the case where the upper surfaces of the post 152, the protective metal layer 153 and the alloy layer 154 are flat surfaces. Consequently, the joint strength between the post 152 and the protective metal layer 153 and the joint strength between the protective metal layer 153 and the solder layer 155 can be improved.

[0075] As described above, the wiring board according to the embodiment (for example, wiring board 100) has an insulating layer (for example, a solder resist layer 130) and a connection terminal (for example, a connection terminal 150) formed on the upper surface (for example, the upper surface 130a) of the insulating layer. The connection terminal has a seed layer (for example, a seed layer 151), a metal post (for example, a post 152), a protective metal layer (for example, a protective metal layer 153), a solder layer (for example, a solder layer 155), and an alloy layer (for example, an alloy layer 154). The seed layer is laminated on the upper surface of the insulating layer. The post is laminated on the upper surface of the seed layer. The protective metal layer is laminated on the upper surface of the post. The solder layer is formed on the upper surface of the protective metal layer. The alloy layer is formed at the interface between the protective metal layer and the solder layer and consists of at least a portion of an intermetallic compound. The solder layer covers the upper and side surfaces of the alloy layer. The sides of the alloy layer are located closer to the center of the post than the sides of the post. This helps to suppress the occurrence of short circuits between adjacent connection terminals. [Explanation of symbols]

[0076] 100 Wiring boards 110 Core board 111 Base material 112 Through-wiring 113, 122 wiring layer 120 Multilayer wiring structure 121 Insulating layer 123 Beer 130, 140 solder resist layers 130a top surface 131, 141 openings 150 connection terminals 151 Seed Layer 152 posts 153 Protective metal layer 154 alloy layer 155 solder layers 156 Metal layer 161 core layers 162 Interface layer

Claims

1. Insulating layer and, A connection terminal formed on the upper surface of the insulating layer and It has, The aforementioned connection terminal is A seed layer laminated on the upper surface of the insulating layer, A metal post stacked on the upper surface of the seed layer, A protective metal layer is laminated on the upper surface of the post, A solder layer formed on the upper surface of the protective metal layer, An alloy layer formed at the interface between the protective metal layer and the solder layer, and at least a portion of which is composed of an intermetallic compound. It has, The solder layer covers the upper and side surfaces of the alloy layer. The side surface of the alloy layer is located closer to the center of the post than the side surface of the post. A wiring board characterized by the following features.

2. The alloy layer is narrower than the post. The wiring board according to feature 1.

3. The protective metal layer is a layer of a different metal from the post. The alloy layer is a layer made of the intermetallic compound which includes at least one metal different from the protective metal layer and the metal that forms the solder layer. The wiring board according to feature 1.

4. The protective metal layer is a layer of a different metal from the post. The aforementioned alloy layer is A core layer located on the upper surface of the protective metal layer and made of a different metal from the protective metal layer, An interface layer located at the interface between the core layer and the solder layer, comprising an intermetallic compound containing at least the metal forming the core layer and the metal forming the solder layer. has The wiring board according to feature 1.

5. The side surface of the protective metal layer is located outward from the side surface of the post. The side surface of the alloy layer is located closer to the center of the post than the side surface of the protective metal layer. The solder layer extends from the side surface of the alloy layer to a position where it does not reach the side surface of the protective metal layer, exposing a portion of the upper surface of the protective metal layer that does not overlap with the solder layer in a plan view. The wiring board according to feature 1.

6. The solder layer is narrower than the protective metal layer. The wiring board according to feature 1.

7. The aforementioned solder layer is narrower than the aforementioned post. The wiring board according to feature 1.

8. The solder layer is wider than the post. The wiring board according to feature 1.

9. The aforementioned solder layer is hemispherical. The wiring board according to feature 1.

10. The upper surface of the post protrudes in a curved shape, The upper surface of the protective metal layer and the upper surface of the alloy layer are curved in a curved shape corresponding to the upper surface of the post. The wiring board according to feature 1.

11. A seed layer lamination process in which a seed layer is laminated on the upper surface of the insulating layer, A post formation step in which a metal post is formed on the upper surface of the seed layer, A protective metal layer lamination step is performed to laminate a protective metal layer on the upper surface of the post, A metal layer lamination step of laminating a metal layer on the upper surface of the protective metal layer, A solder layer lamination step in which a solder layer is laminated on the upper surface of the protective metal layer via the metal layer, A removal step of removing the portion of the seed layer that does not overlap with the post by etching, A reflow step of melting the solder layer and reacting the metal layer with the solder layer to form an alloy layer at the interface between the protective metal layer and the solder layer, in which at least a portion is composed of an intermetallic compound. It has, The aforementioned removal process is, Simultaneously with the removal of the seed layer, the post and the metal layer are dissolved from the side, removing the metal layer from the side of the post up to the center of the post. The aforementioned reflow process is The metal layer after the removal process is reacted with the solder layer to form the alloy layer whose side surface is located closer to the center of the post than the side surface of the post, and the solder layer is formed to cover the top and side surfaces of the alloy layer. A method for manufacturing a wiring board, characterized by the following:

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