Drive circuit and electro-optical device

Abstract

To provide a drive circuit that enables highly accurate inspection. [Solution] The drive circuit comprises NODE1 electrically connected to pixel P, SW1 with one end electrically connected to NODE1, n C1 with one end electrically connected to the other end of SW1, a capacitor drive circuit 10 that drives the n C1 based on grayscale data D as a video signal representing image information and is electrically connected to the other end of each of the n C1, SW2 with one end electrically connected to the other end of SW1 and the other end electrically connected to the test node TEST_NODE1, SW3 with one end electrically connected to the output node NODE1, m SW4 with one end electrically connected to the other end of SW3, m C2 with one end electrically connected to the other end of each of the m SW4 and to which a constant potential is applied, and SW5 with one end electrically connected to the other end of SW3 and the other end electrically connected to TEST_NODE2.

Description

Technical Field

[0001] The present invention relates to a drive circuit and an electro-optical device including the drive circuit.

Background Art

[0002] Conventionally, there has been known a driver equipped with a drive circuit that supplies a data voltage corresponding to grayscale data to an electro-optical panel. For example, Patent Document 1 discloses a driver including: a voltage drive circuit that outputs a data voltage corresponding to grayscale data; and a capacitive drive circuit that includes first to n-th capacitors corresponding to grayscale data and first to n-th capacitor drive circuits, and outputs first to n-th capacitor drive voltages.

[0003] The driver of Patent Document 1 further includes a variable capacitance circuit composed of m capacitors and m switches. The variable capacitance circuit is used to bring a driven-side capacitance obtained by adding the capacitance of the variable capacitance circuit and the capacitance on the electro-optical panel side, and the capacitance of the first to n-th capacitors into a given capacitance ratio relationship.

Prior Art Literature

Patent Literature

[0004]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0005] In Patent Document 1, the first to nth capacitors are weighted by powers of 2 for their capacitance values. In other words, the first to nth capacitors have a capacitance ratio equal to or greater than the number of bits in the grayscale data. For example, if the grayscale data is 12 bits, the capacitance ratio between the capacitor for the most significant bit (MSB) and the capacitor for the least significant bit (LSB) is 2^12 or greater. Therefore, if each capacitor is driven at, for example, 15V, driving the capacitor corresponding to the most significant bit will result in a voltage change of 7.5V, while driving the capacitor corresponding to the least significant bit will result in a voltage change of only 3.7mV. In other words, the voltage change when driving the capacitor corresponding to the least significant bit is extremely small compared to the voltage change when driving the capacitor corresponding to the most significant bit. As a result, there was a problem in that it was difficult to ensure inspection accuracy when inspecting the first to nth capacitors based on this voltage change. Furthermore, the influence of the variable capacitance circuit was also a problem in the inspection of the first to nth capacitors. [Means for solving the problem]

[0006] A drive circuit according to one aspect of the present invention comprises: an output node electrically connected to a pixel; a first switch with one end electrically connected to the output node; n (n is an integer of 1 or more) first capacitors, one end of which is electrically connected to the other end of the first switch; a first capacitor drive circuit that drives the n first capacitors based on a video signal representing image information and is electrically connected to the other end of each of the n first capacitors; a second switch with one end electrically connected to the other end of the first switch and the other end of which is electrically connected to a first inspection node; a third switch with one end electrically connected to the output node; m (m is an integer of 1 or more) fourth switches, one end of which is electrically connected to the other end of the third switch; m second capacitors, each with one end electrically connected to the other end of each of the m fourth switches and to which a constant potential is applied to the other end; and a fifth switch with one end electrically connected to the other end of the third switch and the other end of which is electrically connected to a second inspection node.

[0007] A drive circuit according to one aspect of the present invention includes an output node electrically connected to a pixel, a seventh switch with one end electrically connected to the output node, s (where s is an integer greater than or equal to 1) third capacitors with one end electrically connected to the other end of the seventh switch, a second capacitor drive circuit that drives the s third capacitors based on the lower bits of the video signal representing image information and is electrically connected to the other end of each of the s third capacitors, an eighth switch with one end electrically connected to the other end of the seventh switch and the other end electrically connected to a third inspection node, a ninth switch with one end electrically connected to the output node, and ns (where n is an integer greater than s) fourth capacitors with one end electrically connected to the other end of the ninth switch, and the image The system includes: a third capacitor drive circuit that drives ns of fourth capacitors based on the video signal of the higher bits of the video signal representing information, and is electrically connected to the other ends of each of the ns of fourth capacitors; a tenth switch to which one end is electrically connected to the other end of the ninth switch, and the other end is electrically connected to the fourth inspection node; a third switch to which one end is electrically connected to the output node; m (m is an integer of 1 or more) fourth switches to which one end is electrically connected to the other end of the third switch; m second capacitors to which the other end of each of the m fourth switches is electrically connected to the other end, and a constant potential is applied to the other end; and a fifth switch to which one end is electrically connected to the other end of the third switch, and the other end is electrically connected to the second inspection node.

[0008] A drive circuit according to one aspect of the present invention includes an output node electrically connected to a pixel, a seventh switch with one end electrically connected to the output node, s (where s is an integer greater than or equal to 1) third capacitors with one end electrically connected to the other end of the seventh switch, a second capacitor drive circuit that drives the s third capacitors based on the lower bits of the video signal representing the image information and is electrically connected to the other end of each of the s third capacitors, an eighth switch with one end electrically connected to the other end of the seventh switch and the other end electrically connected to a third inspection node, a ninth switch with one end electrically connected to the output node, ns (where n is an integer greater than s) fourth capacitors with one end electrically connected to the other end of the ninth switch, a third capacitor drive circuit that drives the ns fourth capacitors based on the higher bits of the video signal representing the image information and is electrically connected to the other end of each of the ns fourth capacitors, and the other end of the ninth switch A 10th switch, one end of which is electrically connected and the other end of which is electrically connected to a 4th inspection node; an 11th switch, one end of which is electrically connected to the output node; p (p is an integer greater than or equal to 1) 12th switches, one end of which is electrically connected to the other end of the 11th switch; p 5th capacitors, each of which has one end of which is electrically connected to the other end and a constant potential applied to the other end; and a 12th switch, one end of which is electrically connected and the other end of which is electrically connected to a 5th inspection node. The system comprises a thirteenth switch that is electrically connected, a fourteenth switch whose one end is electrically connected to the output node, mp (where m is an integer greater than p) fifteenth switches whose other end is electrically connected to one end of the fourteenth switch, mp sixth capacitors whose other end is electrically connected to one end of each of the mp fifteenth switches and to which a constant potential is applied, and a sixteenth switch whose other end is electrically connected to one end of the fifteenth switch and to which the other end is electrically connected to the sixth test node.

[0009] An electro-optical device according to one aspect of the present invention comprises the drive circuit described above and an electro-optical panel having the pixels and electrically connected to the output node. [Brief explanation of the drawing]

[0010] [Figure 1] A perspective view showing the external appearance of an electro-optical device equipped with the drive circuit according to this embodiment. [Figure 2] A block diagram showing the general configuration of the drive circuit. [Figure 3] Circuit diagram of the drive circuit. [Figure 4] A timing chart showing the operation during testing in a proportional configuration. [Figure 5] A timing chart showing the operation during inspection in the configuration of this embodiment. [Figure 6] Circuit diagram of the drive circuit according to Embodiment 2. [Figure 7] A timing chart showing the operation of the drive circuit according to Embodiment 2 during inspection. [Figure 8] Circuit diagram of a drive circuit according to a modified example 1 of Embodiment 2. [Figure 9] Circuit diagram of a drive circuit according to a modified example 2 of Embodiment 2. [Figure 10] Circuit diagram of the drive circuit according to Embodiment 3. [Figure 11] A timing chart showing the operation of the drive circuit according to Embodiment 3 during inspection. [Figure 12] Circuit diagram of the drive circuit according to Embodiment 4. [Figure 13] A timing chart showing the operation of the drive circuit according to Embodiment 4. [Modes for carrying out the invention]

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0012] 1. Embodiment 1 1.1. Configuration of the electro-optical device 100 Figure 1 is a perspective view showing an example of the external appearance of the electro-optical apparatus 100 according to this embodiment. As shown in FIG. 1, the electro-optical device 100 includes a driver 1, an electro-optical panel 2, and a flexible substrate 3.

[0013] The electro-optical device 100 is preferably used as a display device for a projector. Note that the electro-optical device 100 may also be used as a display device for devices such as smartphones, cameras, televisions, car navigation systems, personal computers, displays, POS (Point of Sale) terminals, printers, scanners, copiers, video players, or devices equipped with a touch panel.

[0014] The electro-optical panel 2 is an active-driven transmissive liquid crystal display panel that includes pixels P in a display region TD and is provided with a TFT (Thin Film Transistor) as a switching element for each pixel P. Note that the electro-optical panel 2 may be a reflective liquid crystal display panel or a semi-transmissive liquid crystal display panel.

[0015] The pixels P are provided corresponding to intersections between scanning lines 2x and data lines 2y arranged in a matrix. The electro-optical panel 2 includes an element substrate 21 and a counter substrate 22, and the flexible substrate 3 is mounted on a protruding portion 21a of the element substrate 21.

[0016] The driver 1 outputs, to the electro-optical panel 2, a data voltage Vd for driving the electro-optical panel 2 based on a video signal representing image information. In the present embodiment, the driver 1 is configured by an integrated circuit device (IC). The integrated circuit device is, for example, an IC chip having a circuit formed on a silicon substrate, or a device in which an IC chip is housed in a package. In the present embodiment, the driver 1 is an example of a drive circuit.

[0017] In this embodiment, the driver 1 is mounted on the flexible substrate 3. That is, the data voltage Vd output from the driver 1 is supplied to the electro-optic panel 2 via the flexible substrate 3. The driver 1 may also be mounted on the protruding portion 21a of the electro-optic panel 2, or it may be mounted on a rigid substrate (not shown) and supplied with the data voltage Vd to the electro-optic panel 2 via the flexible substrate 3.

[0018] The electro-optical panel 2 is supplied with data voltage Vd, power supply voltage, timing signals, etc., via the flexible substrate 3, but some or all of the power supply voltage, timing signals, etc., may be output by the driver 1.

[0019] 1.2. Driver 1 Configuration Figure 2 is a block diagram showing the schematic configuration of driver 1. Figure 3 is a circuit diagram of driver 1. Figure 4 is a timing chart showing the operation of driver 1. Figure 5 is a timing chart showing the operation of driver 1.

[0020] Driver 1 includes a capacitive drive circuit 20, a balanced capacitive circuit 30, a voltage drive circuit 40, a test circuit 50, a control circuit 60, and an output node NODE1 which is an output terminal that outputs a data voltage Vd.

[0021] The capacitive drive circuit 20 outputs a data voltage Vd by redistributing the charge of the capacitor. The balancing capacitance circuit 30 is used to appropriately drive various electro-optic panels 2 with different electro-optic panel side capacitances CP. The voltage drive circuit 40 outputs a first voltage V1 based on a video signal representing image information as a data voltage Vd.

[0022] The capacitive drive circuit 20 is electrically connected to the output node NODE1 via switch SW1. The balanced capacitive circuit 30 is electrically connected to the output node NODE1 via switch SW3. The voltage drive circuit 40 is electrically connected to the output node NODE1 via switch SW6. In this embodiment, switch SW1 is an example of a first switch, switch SW3 is an example of a third switch, and switch SW6 is an example of a sixth switch.

[0023] When driver 1 drives the electro-optical panel 2, switches SW1 and SW3 are turned ON during the first period and OFF during the second period following the first period. Conversely, switch SW6 is turned OFF during the first period and ON during the second period following the first period. In other words, driver 1 outputs a data voltage Vd during the first period through capacitive drive by the capacitive drive circuit 20, and outputs a data voltage Vd during the second period following the first period through voltage drive by the voltage drive circuit 40. By controlling it in this way, driver 1 can be driven at high speed and with high precision.

[0024] The control terminal of switch SW1 is supplied with the control signal DENB from the control circuit 60, the control terminal of switch SW3 is supplied with the control signal LENB from the control circuit 60, and the control terminal of switch SW6 is supplied with the control signal AENB from the control circuit 60. In other words, the ON / OFF state of switches SW1, SW3, and SW6 is controlled by the control circuit 60.

[0025] The capacitive drive circuit 20 is electrically connected to the test node TEST_NODE1 via switch SW2. The balanced capacitive circuit 30 is electrically connected to the test node TEST_NODE2 via switch SW5. In other words, the capacitive drive circuit 20 and the balanced capacitive circuit 30 are connected to different test nodes. Therefore, the driver 1 can perform tests on the capacitive drive circuit 20 and the balanced capacitive circuit 30 in parallel, thereby improving the test speed. In this embodiment, switch SW2 is an example of a second switch, and switch SW5 is an example of a fifth switch. The balanced capacitive circuit 30 may also be electrically connected to the test node TEST_NODE1 via switch SW5. The circuit configuration, including wiring, can be made smaller, thus enabling miniaturization and cost reduction.

[0026] Test node TEST_NODE1 is electrically connected to test circuit 50 via test line TEST_LINE1. Test node TEST_NODE2 is electrically connected to test circuit 50 via test line TEST_LINE2.

[0027] The inspection circuit 50 is a circuit that inspects the accuracy of the capacitive drive circuit 20 and the balance capacitance circuit 30. The inspection results from the inspection circuit 50 are output to the inspection result output node NODE2 via the output line OUT_LINE. The inspection results from the inspection circuit 50 allow us to determine whether the capacitive drive circuit 20 and the balance capacitance circuit 30 are good or bad, and whether any defects have occurred.

[0028] The test circuit 50 is preferably formed on the same silicon substrate as the capacitive drive circuit 20 and the balance capacitive circuit 30. By forming it on the same silicon substrate, the test circuit 50 can be formed at a low cost. The driver 1 may also be configured without incorporating the test circuit 50.

[0029] When testing the capacitive drive circuit 20 using the test circuit 50, switch SW2 is turned ON and switch SW1 is turned OFF. In other words, the capacitive drive circuit 20 is disconnected from output node NODE1, so when testing the capacitive drive circuit 20, the influence of output node NODE1, such as voltage changes and parasitic capacitance, can be eliminated, thereby improving the accuracy of the test. Furthermore, switch SW3 is turned OFF. By turning off switch SW3, the influence of the balance capacitive circuit 30 can be eliminated, thus improving the accuracy of the test.

[0030] When testing the balance capacitance circuit 30 using the test circuit 50, switch SW5 is turned ON and switch SW3 is turned OFF. In other words, the balance capacitance circuit 30 is disconnected from output node NODE1, so when testing the balance capacitance circuit 30, the influence of output node NODE1, such as voltage changes and parasitic capacitance, can be eliminated. Furthermore, switch SW1 is turned OFF. By turning off switch SW2, the influence of the capacitance drive circuit 20 can be eliminated, thereby improving the accuracy of the test.

[0031] Thus, according to this embodiment, when inspecting the capacitive drive circuit 20, the influence of output node NODE1 and the balance capacitance circuit 30 can be eliminated, allowing the amplitude of the inspection voltage to be increased. Similarly, when inspecting the balance capacitance circuit 30, the influence of output node NODE1 and the capacitive drive circuit 20 can be eliminated, allowing the amplitude of the inspection voltage to be increased. Therefore, according to this embodiment, the accuracy of the inspection of the capacitive drive circuit 20 or the balance capacitance circuit 30 by the inspection circuit 50 can be improved.

[0032] The control terminal of switch SW2 receives the control signal TENB1 from the control circuit 60, and the control terminal of switch SW5 receives the control signal TENB2 from the control circuit 60. In other words, the ON / OFF state of switches SW2 and SW5 is controlled by the control circuit 60.

[0033] The control circuit 60 is connected to the input / output node NODE3. The control circuit 60 performs the various controls described above based on control information stored in a memory (not shown). The setting or modification of this control information can be performed externally via the input / output node NODE3.

[0034] 1.2.1. Configuration of the Capacitive Drive Circuit 20 The capacitive drive circuit 20 is a circuit that outputs a data voltage Vd by redistributing the charge of a capacitor. The capacitive drive circuit 20 outputs the data voltage Vd to the output node NODE1 via a switch SW1, one end of which is electrically connected to the output node NODE1.

[0035] As shown in Figure 3, the capacitive drive circuit 20 includes n capacitors C1 and a capacitor drive circuit 10 that drives the n capacitors C1 based on a video signal representing image information. Here, n is an integer of 1 or more, and for example, n can be set to the same number as the number of bits in the grayscale data D. In this embodiment, the n capacitors C1 are an example of n first capacitors, and the capacitor drive circuit 10 is an example of a first capacitor drive circuit.

[0036] n capacitors C1 include capacitors C10, C11, ..., C1n-1, and C1n. One end of each of the n capacitors C1 is electrically connected to the other end of switch SW1.

[0037] The capacitor drive circuit 10 includes n drive units B0, B1, ..., Bn-1, Bn. One end of each of the n drive units B0, B1, ..., Bn-1, Bn of the capacitor drive circuit 10 is electrically connected to the other end of each of the n capacitors C1.

[0038] The capacitance values ​​of capacitors C10, C11, ..., C1n-1, and C1n are weighted by powers of 2 corresponding to each digit of bits D0, D1, ..., Dn-1, and Dn of the grayscale data D. Then, the drive units B0, B1, ..., Bn-1, and Bn output low-level or high-level potentials according to bits D0, D1, ..., Dn-1, and Dn, and these potentials drive the capacitors C10, C11, ..., C1n-1, and C1n. A low-level potential is, for example, 0V, and a high-level potential is, for example, 15V. In this embodiment, grayscale data D is an example of a video signal representing image information.

[0039] This drive causes charge redistribution between capacitors C10, C11, ..., C1n-1, C1n and the electro-optic panel capacitance CP (see Figure 2), resulting in a data voltage Vd being output to output node NODE1. The electro-optic panel capacitance CP is determined by the substrate capacitance CP1 and the panel capacitance CP2.

[0040] The electro-optic panel capacitance CP is the sum of the capacitances visible from output node NODE1. For example, the electro-optic panel capacitance CP is the sum of the substrate capacitance CP1, which is the parasitic capacitance of the flexible substrate 3, and the panel capacitance CP2, which is the parasitic capacitance and pixel capacitance within the electro-optic panel 2. The TFTs within the electro-optic panel 2 have parasitic capacitance between the source and gate. Since many TFTs are connected to the data line 2y (see Figure 1), the data line 2y has parasitic capacitance from many TFTs. In addition, there is parasitic capacitance between the data line 2y and the scan line 2x. Furthermore, in a liquid crystal display panel, there is capacitance in the pixel P. The sum of these is the panel capacitance CP2.

[0041] 1.2.2. Configuration of the Balance Capacitance Circuit 30 In this embodiment, the driver 1 has a balance capacitance circuit 30. The balanced capacitance circuit 30 is a capacitance connected to the output node NODE1 via the switch SW3, and is a circuit whose capacitance value can be set variably. It is a circuit that corresponds to the variable capacitance circuit described in Patent Document 1.

[0042] The balancing capacitance circuit 30 includes m switches SW4 and m capacitors C2 for capacitance adjustment, where m is an integer greater than or equal to 1. Each of the m switches SW4 has one end electrically connected to the other end of switch SW3. Control signals EN0, EN1, ..., ENm-1, ENm are supplied to each of the control terminals of the m switches SW4 from the control circuit 60. In this embodiment, the m switches SW4 are an example of m fourth switches.

[0043] The m capacitors C2 include capacitors C20, C21, ..., C2m-1, and C2m. Each capacitor C20, C21, ..., C2m-1, and C2m has a capacitance value weighted by a power of 2. One end of each of the m capacitors C2 is electrically connected to the other end of each of the m switches SW4, and the other end of each of the m capacitors C2 is connected to a node of reference potential, to which a constant potential, which is the reference potential, is applied. In this embodiment, the m capacitors C2 are an example of m second capacitors.

[0044] The balancing capacitance circuit 30 is used to set the capacitance ratio between the capacitance of n capacitors C1 (the sum of the capacitances of capacitors C10, C11, ..., C1n-1, and C1n) and the capacitance CP on the electro-optic panel side to a predetermined value. By having the balancing capacitance circuit 30, the driver 1 can appropriately drive various electro-optic panels 2 with different electro-optic panel side capacitances CP, thereby increasing the versatility of the driver 1.

[0045] In this embodiment, capacitors C10, C11, ..., C1n-1, C1n and capacitors C20, C21, ..., C2m-1, C2m are capacitances built into the integrated circuit device and can be composed of, for example, MIM (Metal Insulation Metal) capacitors.

[0046] 1.2.3. Configuration of the voltage drive circuit 40 The voltage drive circuit 40 includes a DAC (Digital to Analog Converter) 41 and an amplifier 42. The DAC41 generates and outputs a reference voltage (gradation voltage) corresponding to each value of the gradation data D. If the gradation data D is, for example, 12 bits, it generates and outputs a reference voltage for 4096 gradations.

[0047] Amplifier 42 amplifies the reference voltage output from DAC 41 and outputs a first voltage V1. The first voltage V1 is output as a data voltage Vd from output node NODE1 via switch SW6.

[0048] 1.3. Operational description during inspection based on timing chart Next, the operation of the capacitive drive circuit 20 during inspection will be explained based on the timing charts in Figures 4 and 5.

[0049] Figure 4 is a timing chart showing the operation during testing in a proportional configuration. Here, a proportional configuration is a configuration used to explain the influence of output node NODE1 during testing, and is a configuration in which switches SW1 and SW3 are in the ON state. Figure 5 is a timing chart showing the operation during testing in the configuration of this embodiment.

[0050] As shown in Figure 4, when testing the capacitive drive circuit 20 in a proportional configuration, switches SW1, SW3, and SW2 are ON, and switch SW5 is OFF from the start to the end of the test. Therefore, control signals DENB, LENB, and TENB1 are set to a high level, and control signal TENB2 is set to a low level. The control signals EN0, EN1, ..., ENm-1, and ENm of the m switches SW4 of the balanced capacitance circuit 30 are each set to a low level. In this proportional configuration, when testing the capacitive drive circuit 20, the balanced capacitance circuit 30 is electrically connected to the output node NODE1.

[0051] As shown in Figure 5, in this embodiment, when testing the capacitive drive circuit 20, switch SW2 is ON, and switches SW1, SW3, and SW5 are OFF from the start to the end of the test. Therefore, control signal TENB1 is set to a high level, and control signals DENB, LENB, and TENB2 are set to a low level. Thus, in this embodiment, when testing the capacitive drive circuit 20, the balanced capacitance circuit 30 is electrically isolated from the output node NODE1. Note that the balanced capacitance circuit 30 may be tested simultaneously with the capacitive drive circuit 20. In that case, switch SW3 is OFF, switch SW5 is ON, control signal TENB2 is set to a high level, and control signal LENB is set to a low level. Furthermore, when testing the capacitive drive circuit 20 and the balanced capacitance circuit 30 simultaneously with the test circuit 50, the test circuit 50 may include a first test circuit for testing the capacitive drive circuit 20 and a second test circuit for testing the balanced capacitance circuit 30.

[0052] When the test of the capacitive drive circuit 20 is started, the capacitive drive circuit 20 is driven sequentially based on the grayscale data D. The drive units B0, B1, ..., Bn-1, Bn sequentially output low-level or high-level potentials based on bits D0, D1, ..., Dn-1, Dn of the grayscale data D, and the capacitors C10, C11, ..., C1n-1, C1n are driven sequentially by these potentials, and the capacitive drive circuit 20 outputs a test voltage that increases in a stepwise manner to the test node TEST_NODE1 via switch SW2.

[0053] Comparing Figure 4 and Figure 5, the amplitude of the test voltage at the test node TEST_NODE1 is larger in Figure 5 than in Figure 4. In other words, by using the configuration of this embodiment, the amplitude of the test voltage output to the test node TEST_NODE1 can be increased, thereby improving the accuracy of the test.

[0054] As described above, the driver 1 of this embodiment provides the following benefits. The driver 1 in this embodiment, as a drive circuit, comprises an output node NODE1 electrically connected to a pixel P, a switch SW1 as a first switch with one end electrically connected to the output node NODE1, n capacitors C1 as n (n is an integer of 1 or more) as first capacitors with one end electrically connected to the other end of the switch SW1, a capacitor drive circuit 10 as a first capacitor drive circuit that drives the n capacitors C1 based on grayscale data D as a video signal representing image information and is electrically connected to the other end of each of the n capacitors C1, and a test node TEST with one end electrically connected to the other end of the switch SW1, the other end of which is a first test node. The system comprises: a switch SW2 as a second switch electrically connected to NODE1; a switch SW3 as a third switch with one end electrically connected to output node NODE1; m switches SW4 as m fourth switches (m is an integer greater than or equal to 1), with one end electrically connected to the other end of switch SW3; m capacitors C2 as m second capacitors, with one end electrically connected to the other end of each of the m switches SW4 and a constant potential applied to the other end; and a switch SW5 as a fifth switch, with one end electrically connected to the other end of switch SW3 and the other end electrically connected to test node TEST_NODE2 as a second test node.

[0055] Thus, n capacitors C1 are electrically connected between switch SW1 and switch SW2, and m capacitors C2 are electrically connected between switch SW3 and switch SW5.

[0056] Therefore, according to this embodiment, when inspecting n capacitors C1, the influence of output node NODE1 and m capacitors C2 can be eliminated, thereby increasing the amplitude of the inspection voltage output to inspection node TEST_NODE1. Thus, according to this embodiment, the accuracy of the inspection can be improved. Similarly, when inspecting m capacitors C2, the influence of output node NODE1 and n capacitors C1 can be eliminated, thereby increasing the amplitude of the inspection voltage output to inspection node TEST_NODE1. Thus, according to this embodiment, the accuracy of the inspection can be improved.

[0057] The driver 1 in this embodiment, as a drive circuit, further comprises a switch SW6, which is a sixth switch with one end electrically connected to an output node NODE1, and a voltage drive circuit 40, which is electrically connected to the other end of the switch SW6 and outputs a first voltage V1 based on a video signal representing image information. Therefore, a driver 1 capable of high-precision driving can be realized.

[0058] The electro-optical device 100 of this embodiment comprises a driver 1 as a drive circuit as described above, and an electro-optical panel 2 having pixels P and electrically connected to an output node NODE 1. Thus, the electro-optical device 100 of this embodiment is equipped with a driver 1 capable of high-precision inspection, and therefore, a highly reliable electro-optical device 100 can be realized.

[0059] 2. Embodiment 2 Next, the driver 1 according to Embodiment 2 will be described based on Figures 6 to 9. Figure 6 is a circuit diagram of the driver 1 according to Embodiment 2. Figure 7 is a timing chart showing the operation of the driver 1 according to Embodiment 2 during inspection. Figure 8 is a circuit diagram of the driver 1 according to Modification 1 of Embodiment 2. Figure 9 is a circuit diagram of the driver 1 according to Modification 2 of Embodiment 2.

[0060] The driver 1 according to Embodiment 2 differs from the driver 1 according to Embodiment 1 in that it has a configuration that outputs a test voltage from the test node TEST_NODE2 when testing the balance capacitance circuit 30. Note that components identical to those in Embodiment 1 may be given the same reference numerals and their descriptions may be omitted.

[0061] As shown in Figure 6, the driver 1 according to Embodiment 2 has a buffer 71 in the balance capacitance circuit 30. One end of the buffer 71 is connected to the capacitor C2m, and the other end of the buffer 71 is supplied with a drive signal T0.

[0062] As shown in Figure 7, in the configuration of Embodiment 2, when testing the balance capacitance circuit 30, switch SW5 is ON, and switches SW1, SW3, and SW2 are OFF from the start to the end of the test. Therefore, control signal TENB2 is set to a high level, and control signals DENB, LENB, and TENB1 are set to a low level. The capacitance drive circuit 20 may also be tested simultaneously with the balance capacitance circuit 30. In that case, switch SW1 is OFF, switch SW2 is ON, control signal TENB1 is set to a high level, and control signal DENB is set to a low level. Furthermore, when the capacitance drive circuit 20 and the balance capacitance circuit 30 are tested simultaneously by the test circuit 50, the test circuit 50 may include a first test circuit for testing the capacitance drive circuit 20 and a second test circuit for testing the balance capacitance circuit 30.

[0063] When the test of the balance capacitance circuit 30 is started, the buffer 71 is supplied with a drive signal T0 from the control circuit 60 that alternates between high and low levels. The control signals EN0, EN1, ..., ENm-1, and ENm are all set to high levels at the start of the test, and thereafter, the control signals EN0, EN1, ..., ENm-1 alternate between high and low levels at predetermined intervals. This operation causes the capacitance electrically connected to the test node TEST_NODE2 to decrease in steps, and the amplitude of the test voltage output to the test node TEST_NODE2 increases in steps each time the drive signal T0 reaches a high level. The balance capacitance circuit 30 can be tested by comparing this test voltage with a reference voltage in the test circuit 50.

[0064] 2.1. Variation 1 As shown in Figure 8, the driver 1 according to the modified example 1 has a clocked gate 72 instead of a buffer 71. The clocked gate 72 is supplied with a control signal ENm. The driver 1 according to the modified example 1 can be operated in the same way as the driver 1 according to embodiment 2, and the balance capacitance circuit 30 can be inspected.

[0065] 2.2. Variation Example 2 As shown in Figure 9, in the modified version 2 of the driver 1, a part of the capacitive drive circuit 20 is electrically connected between switch SW3 and switch SW5, similar to the balance capacitive circuit 30. Specifically, a capacitor C1n and a drive unit Bn, which output a low-level or high-level potential based on the most significant bit Dn of the grayscale data D, are electrically connected between switch SW3 and switch SW5. The driver 1 according to the modified example 2 can be operated in the same way as the driver 1 according to embodiment 2 and modified example 1, and the balance capacitance circuit 30 can be inspected.

[0066] As described above, the driver 1 of Embodiment 2 provides the following effects in addition to the effects of Embodiment 1. The driver 1, which serves as the drive circuit in Embodiment 2, further includes a buffer 71 or a clocked gate 72, one end of which is electrically connected to the other end of the switch SW3.

[0067] Therefore, the driver 1 as the drive circuit in Embodiment 2 can output a test voltage from the test node TEST_NODE2, and thus can test m capacitors C2.

[0068] 3. Embodiment 3 Next, the driver 1 according to Embodiment 3 will be described based on Figures 10 and 11. Figure 10 is a circuit diagram of the driver 1 according to Embodiment 3. Figure 11 is a timing chart showing the operation of the driver 1 according to Embodiment 3 during inspection.

[0069] The driver 1 according to Embodiment 3 differs from the driver 1 according to Embodiments 1 and 2 in that the capacitive drive circuit 20 is divided into two capacitive drive circuit 20a and capacitive drive circuit 20b. Note that components identical to those in Embodiments 1 and 2 are denoted by the same reference numerals, and their descriptions may be omitted.

[0070] Capacitive drive circuit 20a is responsible for the least significant bit of the grayscale data D, and capacitive drive circuit 20b is responsible for the most significant bit of the grayscale data D. In other words, capacitive drive circuit 20a is composed of the part of the capacitive drive circuit 20 of Embodiment 1 that corresponds to the lower bits D0, D1, ..., Ds-1, Ds of the grayscale data D, and capacitive drive circuit 20b is composed of the part of the capacitive drive circuit 20 of Embodiment 1 that corresponds to the upper bits Ds+1, Ds+2, ..., Dn-1, Dn of the grayscale data D. Here, s is an integer less than n.

[0071] Thus, in Embodiment 3, the capacitive drive circuit 20 is divided into two capacitive drive circuit 20a and capacitive drive circuit 20b, which are the least significant bit and most significant bit sides of the grayscale data D. As a result, the difference between the capacitance that drives a large voltage and the capacitance that drives a small voltage is smaller in the capacitive drive circuit 20a and capacitive drive circuit 20b than in the capacitive drive circuit 20 of Embodiment 1, thus reducing the voltage difference. Therefore, inspection accuracy can be improved. Note that the number of divisions of the capacitive drive circuit 20 is not limited to two; it may be divided into three or more divisions.

[0072] Furthermore, in Embodiment 3, when inspecting the capacitive drive circuit 20a, the capacitive drive circuit 20b is electrically disconnected from the capacitive drive circuit 20a. Therefore, the capacitance ratio between the total capacitance of the capacitive drive circuit 20a, i.e., the total capacitance of s capacitors C1a, and the capacitance corresponding to the smallest bit D0 of the capacitive drive circuit 20a, i.e., capacitor C10, can be made closer to 1 than in the capacitive drive circuit 20 of Embodiment 1. Specifically, when the grayscale data D is 12 bits, the ratio was 1 / 4096 in the capacitive drive circuit 20 of Embodiment 1, whereas in the capacitive drive circuit 20a it becomes 1 / 64, thus approaching 1. Therefore, the amplitude of the voltage when driving the drive unit B0 electrically connected to capacitor C10 can be increased, and the inspection accuracy can be improved.

[0073] Similarly, during the inspection of the capacitive drive circuit 20b, the capacitive drive circuit 20a is electrically disconnected from the capacitive drive circuit 20b. Therefore, the capacitance ratio between the total capacitance of the capacitive drive circuit 20b, i.e., the total capacitance of ns capacitors C1b, and the capacitance corresponding to the smallest bit Ds+1 of the capacitive drive circuit 20b, i.e., capacitor C1s+1, can be brought closer to 1. Thus, the amplitude of the voltage when driving the drive unit Bs+1 electrically connected to capacitor C1s+1 can be increased, and the inspection accuracy can be improved.

[0074] As shown in Figure 10, the capacitive drive circuit 20a is electrically connected to the output node NODE1 via switch SW1a. The capacitive drive circuit 20b is electrically connected to the output node NODE1 via switch SW1b. In this embodiment, switch SW1a is an example of a seventh switch, and switch SW1b is an example of a ninth switch.

[0075] When driver 1 drives the electro-optical panel 2, switches SW1a, SW1b, and SW3 are turned ON during the first period and OFF during the second period following the first period. Conversely, switch SW6 is turned OFF during the first period and ON during the second period following the first period. In other words, driver 1 outputs the data voltage Vd during the first period through capacitive drive by capacitive drive circuits 20a and 20b, and outputs the data voltage Vd during the second period following the first period through voltage drive by voltage drive circuit 40. By controlling it in this way, driver 1 can be driven at high speed and with high precision.

[0076] Control signals DENB are supplied from the control circuit 60 to the control terminals of switches SW1a and SW1b. In other words, capacitive drive circuits 20a and 20b are electrically connected to output node NODE1 during the first period.

[0077] Capacitive drive circuit 20a is electrically connected to test node TEST_NODE1a via switch SW2a. Capacitive drive circuit 20b is electrically connected to test node TEST_NODE1b via switch SW2b. In other words, capacitive drive circuits 20a and 20b are connected to different test nodes. Therefore, driver 1 can perform tests on capacitive drive circuits 20a and 20b in parallel, thereby improving the test speed. In this embodiment, switch SW2a is an example of an eighth switch, and switch SW2b is an example of a tenth switch. Capacitive drive circuit 20b may also be electrically connected to test node TEST_NODE1a via switch SW2b. Since the circuit configuration, such as wiring, can be reduced, miniaturization and cost reduction can be achieved.

[0078] Test node TEST_NODE1a is electrically connected to test circuit 50 via test line TEST_LINE1a. Test node TEST_NODE1b is electrically connected to test circuit 50 via test line TEST_LINE1b.

[0079] When testing the capacitive drive circuit 20a using the test circuit 50, switch SW2a is turned ON and switch SW1a is turned OFF. In other words, the capacitive drive circuit 20a is disconnected from output node NODE1, so when testing the capacitive drive circuit 20a, the influence of output node NODE1, such as voltage changes and parasitic capacitance, can be eliminated, thereby improving the accuracy of the test. Furthermore, switch SW5 is turned OFF. By turning off switch SW5, the influence of the balance capacitance circuit 30 can be eliminated, thus improving the accuracy of the test.

[0080] The control terminal of switch SW2a is supplied with the control signal TENB1a from the control circuit 60, and the control terminal of switch SW2b is supplied with the control signal TENB1b from the control circuit 60. In other words, the ON / OFF state of switches SW2a and SW2b is controlled by the control circuit 60.

[0081] The capacitive drive circuit 20a includes s capacitors C1a and a capacitor drive circuit 10a that drives the s capacitors C1a based on the lower bits of the video signal representing image information. In this embodiment, the s capacitors C1a are an example of s third capacitors, and the capacitor drive circuit 10a is an example of a second capacitor drive circuit.

[0082] The capacitance drive circuit 20b includes ns capacitors C1b and a capacitor drive circuit 10b that drives the ns capacitors C1b based on the video signal of the higher bits of the video signal representing image information. In this embodiment, the ns capacitors C1b are an example of ns fourth capacitors, and the capacitor drive circuit 10b is an example of a third capacitor drive circuit.

[0083] The s capacitors C1a include capacitors C10, C11, ..., C1s-1, and C1s. One end of each of the s capacitors C1a is electrically connected to the other end of the switch SW1a.

[0084] The capacitor drive circuit 10a includes s drive units B0, B1, ..., Bs-1, Bs. One end of each of the s drive units B0, B1, ..., Bs-1, Bs of the capacitor drive circuit 10a is electrically connected to the other end of each of the s capacitors C1a.

[0085] The ns capacitors C1b include capacitors C1s+1, C1s+2, ..., C1n-1, and C1n. One end of the ns capacitors C1b is electrically connected to the other end of switch SW1b.

[0086] The capacitor drive circuit 10b includes ns drive units Bs+1, Bs+2, ..., Bn-1, Bn. One end of each of the ns drive units Bs+1, Bs+2, ..., Bn-1, Bn of the capacitor drive circuit 10b is electrically connected to the other end of each of the ns capacitors C1b.

[0087] During testing, switch SW2a is ON and switch SW1a is OFF in the capacitive drive circuit 20a. Similarly, during testing, switch SW2b is ON and switch SW1b is OFF in the capacitive drive circuit 20b. In other words, during testing, capacitive drive circuits 20a and 20b are electrically disconnected.

[0088] Therefore, when inspecting the capacitive drive circuits 20a and 20b, the capacitance ratios of capacitors C10, C11, ..., C1s-1, and C1s in s capacitors C1a are the same as the capacitance ratios of capacitors C1s+1, C1s+2, ..., C1n-1, and C1n in ns capacitors C1b. Thus, as shown in the timing chart of Figure 11, inspection voltages with similar waveforms are detected from inspection nodes TEST_NODE1a and TEST_NODE1b. Furthermore, similar to the driver 1 according to the first embodiment and the driver 1 according to the second embodiment, if the inspection circuit 50 has a first inspection circuit, a second inspection circuit, and a third inspection circuit that inspect the capacitive drive circuits 20a, 20b, and 30 respectively, they may be inspected simultaneously.

[0089] As described above, the driver 1 of Embodiment 3 provides the following effects in addition to the effects of Embodiments 1 and 2. The driver 1 as a drive circuit in Embodiment 3 includes an output node NODE1 electrically connected to a pixel P, a switch SW1a as a seventh switch with one end electrically connected to the output node NODE1, s capacitors C1a as third capacitors (s is an integer greater than or equal to 1) with one end electrically connected to the other end of switch SW1a, a capacitor drive circuit 10a as a second capacitor drive circuit that drives the s capacitors C1a based on the lower bits of the video signal of the grayscale data D which is a video signal representing image information, and is electrically connected to the other end of each of the s capacitors C1a, a switch SW2a as an eighth switch with one end electrically connected to the other end of switch SW1a and the other end electrically connected to the inspection node TEST_NODE1a as a third inspection node, a switch SW1b as a ninth switch with one end electrically connected to the output node NODE1, and ns capacitors C1b as fourth capacitors (n is an integer greater than s) with one end electrically connected to the other end of switch SW1b. The system includes: a capacitor drive circuit 10b as a third capacitor drive circuit that drives ns capacitors C1b based on the video signal of the higher bits of the grayscale data D which is a video signal representing image information, and is electrically connected to the other ends of each of the ns capacitors C1b; a switch SW2b as a tenth switch, to which one end is electrically connected to the other end of switch SW1b, and the other end is electrically connected to the inspection node TEST_NODE1b as a fourth inspection node; a switch SW3 as a third switch, to which one end is electrically connected to the output node NODE1; m switches SW4 as m (m is an integer of 1 or more) as fourth switches, to which one end is electrically connected to the other end of switch SW3; m capacitors C2 as m second capacitors, to which one end is electrically connected to the other end of each of the m switches SW4, and to which a constant potential is applied; and a switch SW5 as a fifth switch, to which one end is electrically connected to the other end of switch SW3, and the other end is electrically connected to the inspection node TEST_NODE2 as a second inspection node.

[0090] Thus, s capacitors C1a are electrically connected between switch SW1a and switch SW2a, ns capacitors C1b are electrically connected between switch SW1b and switch SW2b, and m capacitors C2 are electrically connected between switch SW3 and switch SW5.

[0091] Therefore, according to Embodiment 3, when inspecting s capacitors C1a, the influence of output node NODE1, the influence of ns capacitors C1b, and the influence of m capacitors C2 can be eliminated, thus increasing the amplitude of the inspection voltage output to inspection node TEST_NODE1a. Thus, according to Embodiment 3, the accuracy of the inspection can be improved.

[0092] Similarly, when inspecting ns capacitors C1b, the influence of output node NODE1, s capacitors C1a, and m capacitors C2 can be eliminated, allowing the amplitude of the inspection voltage output to inspection node TEST_NODE1b to be increased. Therefore, according to Embodiment 3, the accuracy of the inspection can be improved.

[0093] Similarly, when inspecting m capacitors C2, the influence of output node NODE1, s capacitors C1a, and ns capacitors C1b can be eliminated, allowing the amplitude of the inspection voltage output to inspection node TEST_NODE2 to be increased. Therefore, according to Embodiment 3, the accuracy of the inspection can be improved.

[0094] Furthermore, in Embodiment 3, since s capacitors C1a correspond to the least significant bit of the grayscale data D, and ns capacitors C1b correspond to the most significant bit of the grayscale data D, the difference in capacitance between the s capacitors C1a and the ns capacitors C1b becomes smaller, thus reducing the voltage difference. Therefore, inspection accuracy can be improved.

[0095] 4. Embodiment 4 Next, the driver 1 according to Embodiment 4 will be described based on Figures 12 and 13. Figure 12 is a circuit diagram of the driver 1 according to Embodiment 4. Figure 13 is a timing chart showing the operation of the driver 1 according to Embodiment 4 during inspection.

[0096] As shown in Figure 12, the driver 1 according to Embodiment 4 differs from the driver 1 according to Embodiment 3 in that the balance capacitance circuit 30 is divided into two parts: balance capacitance circuit 30a and balance capacitance circuit 30b. Note that components identical to those in Embodiments 1, 2, and 3 are denoted by the same reference numerals, and their descriptions may be omitted.

[0097] In Embodiment 4, the balance capacitance circuit 30 is divided into two balance capacitance circuits 30a and 30b. As a result, the ratio of large capacitance to small capacitance in balance capacitance circuits 30a and 30b is closer to 1 than in the balance capacitance circuit 30 of Embodiment 1, thus reducing the difference in test voltage. Therefore, the test accuracy can be improved.

[0098] Furthermore, in Embodiment 4, similar to the driver 1 in Modification 2 of Embodiment 2 described above, a part of the capacitive drive circuit 20b is electrically connected between switch SW3a and switch SW5a, and between switch SW3b and switch SW5b. Specifically, the capacitor Cm-1 and drive unit Bm-1 corresponding to the upper bit Dm-1 of the gradation data D are electrically connected between switch SW3a and switch SW5a, and the capacitor Cm and drive unit Bm corresponding to the upper bit Dm of the gradation data D are electrically connected between switch SW3b and switch SW5b.

[0099] The driver 1 according to Embodiment 4 can be operated in the same way as the driver 1 according to Modification 2 of Embodiment 2, and the balance capacitance circuit 30a and the balance capacitance circuit 30b can be tested separately.

[0100] As shown in Figure 13, when the test of the balance capacitor circuit 30a is started, the control signals LENB and DENB are set to a low level, and the control signal TENB2a is set to a high level. As a result, the balance capacitor circuit 30a is electrically disconnected from the output node NODE1 and electrically connected to the test node TEST_NODE2a.

[0101] The drive unit Bm-1 is supplied with bit Dm-1 from the control circuit 60, which alternates between high and low levels. At the start of the test, all control signals EN0, EN1, ..., ENp-1, and ENp are set to high levels, and thereafter, control signals EN0, EN1, ..., ENp-1 alternate between high and low levels at predetermined intervals. This operation gradually decreases the capacitance electrically connected to the test node TEST_NODE2a, and each time bit Dm-1 reaches a high level, the amplitude of the test voltage output to the test node TEST_NODE2a gradually increases. The balance capacitance circuit 30a can be tested by comparing this test voltage with a reference voltage in the test circuit 50.

[0102] Similarly, when testing of the balance capacitor circuit 30b is initiated, the control signals LENB and DENB are set to a low level, and the control signal TENB2b is set to a high level. As a result, the balance capacitor circuit 30b is electrically disconnected from the output node NODE1 and electrically connected to the test node TEST_NODE2b.

[0103] The drive unit Bm is supplied with bit Dm from the control circuit 60, which alternates between high and low levels. At the start of the test, the control signals ENp+1, ENp+2, ..., ENm-1, and ENm are all set to high levels, and thereafter, the control signals ENp+1, ENp+2, ..., ENm-1 alternate between high and low levels at predetermined intervals. This operation causes the capacitance electrically connected to the test node TEST_NODE2b to decrease in steps, and each time bit Dm reaches a high level, the amplitude of the test voltage output to the test node TEST_NODE2b increases in steps. The balance capacitance circuit 30b can be tested by comparing this test voltage with a reference voltage in the test circuit 50.

[0104] The test node TEST_NODE2a is electrically connected to the test circuit 50 via the test line TEST_LINE2a. The test node TEST_NODE2b is electrically connected to the test circuit 50 via the test line TEST_LINE2b. The balance capacitor circuit 30a may also be electrically connected to the test node TEST_NODE1b via the switch SW5a. Since the circuit configuration, such as wiring, can be made smaller, miniaturization and cost reduction can be achieved. Furthermore, similar to the driver 1 according to the first embodiment, the driver 1 according to the second embodiment, and the driver 1 according to the third embodiment, if the test circuit 50 has a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit that test the capacitive drive circuit 20a and the capacitive drive circuit 20b and the balance capacitor circuit 30a and the balance capacitor circuit 30b respectively, they may be tested simultaneously.

[0105] As described above, the driver 1 of Embodiment 4 provides the following effects in addition to those of Embodiments 1, 2, and 3. The driver 1 as a drive circuit in Embodiment 4 includes an output node NODE1 electrically connected to a pixel P, a switch SW1a as a seventh switch with one end electrically connected to the output node NODE1, s capacitors C1a as third capacitors (s being an integer of 1 or more) with one end electrically connected to the other end of the switch SW1a, and a second capacitor that drives the s capacitors C1a based on the video signal of the lower bits of the grayscale data D which is a video signal representing image information, and is electrically connected to the other end of each of the s capacitors C1a. The circuit includes a capacitor drive circuit 10a as a shutter drive circuit, a switch SW2a as an eighth switch to which one end is electrically connected to the other end of switch SW1a and the other end is electrically connected to the test node TEST_NODE1a as a third test node, a switch SW1b as a ninth switch to which one end is electrically connected to the output node NODE1, and ns (where n is an integer greater than s) capacitors C1b as fourth capacitors to which one end is electrically connected to the other end of switch SW1b, and grayscale data D as a video signal representing image information. A capacitor drive circuit 10b, which drives ns capacitors C1b based on the video signal of the higher bits and is electrically connected to the other ends of each of the ns capacitors C1b; a switch SW2b, which is a 10th switch, with one end electrically connected to the other end of switch SW1b and the other end electrically connected to the test node TEST_NODE1b, which is a 4th test node; a switch SW3a, which is an 11th switch, with one end electrically connected to the output node NODE1; and a switch SW3a, which is electrically connected to the other end. The system comprises p (where p is an integer greater than or equal to 1) switches SW4a as 12th switches, p capacitors C2a as 5th capacitors, each of which has one end electrically connected to the other end of each of the p switches SW4a and to which a constant potential is applied to the other end, switch SW5a as 13th switches, each of which has one end electrically connected to the other end of switch SW4a and to which the other end is electrically connected to the test node TEST_NODE2a as the 5th test node, and switch SW3b as 14th switches, one end of which is electrically connected to the output node NODE1.The system comprises mp (where m is an integer greater than p) switches SW4b, which are mp (m is an integer greater than p) of the 15th switches, with one end of switch SW3b electrically connected to the other end of each of the mp switches SW4b, and mp capacitors C2b, which are mp of the 6th capacitors, with one end of each of the mp switches SW4b electrically connected and a constant potential applied to the other end of each capacitor, and switch SW5b, which is the 16th switch, with one end of each of the mp switches SW4b electrically connected and the other end of which is electrically connected to the test node TEST_NODE2b, which is the 6th test node.

[0106] Thus, s capacitors C1a are electrically connected between switches SW1a and SW2a, ns capacitors C1b are electrically connected between switches SW1b and SW2b, p capacitors C2a are electrically connected between switches SW3a and SW5a, and mp capacitors C2b are electrically connected between switches SW3b and SW5b.

[0107] Therefore, according to Embodiment 4, when inspecting s capacitors C1a, the influence of output node NODE1, ns capacitors C1b, p capacitors C2a, and mp capacitors C2b can be eliminated, thus increasing the amplitude of the inspection voltage output to inspection node TEST_NODE1a. Thus, according to Embodiment 4, the accuracy of the inspection can be improved.

[0108] Similarly, when inspecting ns capacitors C1b, the influence of output node NODE1, s capacitors C1a, p capacitors C2a, and mp capacitors C2b can be eliminated, thus increasing the amplitude of the inspection voltage output to inspection node TEST_NODE1b. Therefore, according to Embodiment 4, the accuracy of the inspection can be improved.

[0109] Similarly, when inspecting p capacitors C2a, the influence of output node NODE1, s capacitors C1a, ns capacitors C1b, and mp capacitors C2b can be eliminated, thus increasing the amplitude of the inspection voltage output to inspection node TEST_NODE2a. Therefore, according to Embodiment 4, the accuracy of the inspection can be improved.

[0110] Similarly, when inspecting mp capacitors C2b, the influence of output node NODE1, s capacitors C1a, ns capacitors C1b, and p capacitors C2a can be eliminated, thus increasing the amplitude of the inspection voltage output to inspection node TEST_NODE2b. Therefore, according to Embodiment 4, the accuracy of the inspection can be improved.

[0111] Furthermore, in Embodiment 4, since s capacitors C1a correspond to the least significant bit of the grayscale data D, and ns capacitors C1b correspond to the most significant bit of the grayscale data D, the difference in capacitance between the s capacitors C1a and the ns capacitors C1b becomes smaller, thus reducing the voltage difference. Therefore, inspection accuracy can be improved.

[0112] Furthermore, in Embodiment 4, since the capacitors are divided into p capacitors C2a and mp capacitors C2b, the difference in capacitance between the p capacitors C2a and the mp capacitors C2b becomes smaller, thus reducing the voltage difference. Therefore, the inspection accuracy can be improved.

[0113] The driver 1 as a drive circuit in Embodiment 4 further comprises a drive unit Bm-1, one end of which is electrically connected to the other end of switch SW5a, which is a 13th switch, and a drive unit Bm, one end of which is electrically connected to the other end of switch SW5b, which is a 16th switch.

[0114] Therefore, the driver 1 as a drive circuit in Embodiment 4 can output a test voltage from the test node TEST_NODE2a, thus enabling the testing of p capacitors C2a, and can also output a test voltage from the test node TEST_NODE2b, thus enabling the testing of mp capacitors C2b.

[0115] Although preferred embodiments have been described above, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added. For example, in each of the embodiments described above, the switch was set to the ON state when the control signal was at a high level, but the switch may be set to the ON state when the control signal is at a low level. If the switch is set to the ON state when the control signal is at a low level, the descriptions of high level and low level of the control signal in each of the embodiments described above will be reversed. [Explanation of symbols]

[0116] 1…Driver, 2…Electro-optical panel, 2x…Scan line, 2y…Data line, 3…Flexible substrate, 10, 10a, 10b…Capacitor drive circuit, 20, 20a, 20b…Capacitor drive circuit, 21…Element substrate, 21a…Protruding part, 22…Opposite substrate, 30…Balanced capacitance circuit, 30a…Balanced capacitance circuit, 30b…Balanced capacitance circuit, 40…Voltage drive circuit, 41…DAC, 42…Amplifier, 50…Test circuit, 60…Control circuit, 71…Buffer 72...Clocked gate, 100...Electro-optical device, C1...n capacitors, C10...Capacitor, C1a...s capacitors, C1b...ns capacitors, C1n, C1s...Capacitors, C2...m capacitors, C20...Capacitor, C2a...p capacitors, C2b...mp capacitors, C2m...Capacitor, CP1...Substrate capacitance, CP2...Panel capacitance, CP...Electro-optical panel capacitance, SW1, SW2, SW3...Switches, SW4...m switches, SW5...Switch, SW6...Switch, V1...First voltage, TEST_LINE1, TEST_LINE1a, TEST_LINE1b...Test lines, TEST_LINE2, TEST_LINE2a, TEST_LINE2b...Test lines, NODE1...Output node, NODE2...Test result output node, NODE3...Input / output node, TEST_NODE1, TEST_NODE1 a, TEST_NODE1b… Inspection node, TEST_NODE2, TEST_NODE2a, TEST_NODE2b… Inspection node, SW1a, SW1b, SW2a, SW2b, SW3a, SW3b… Switch, SW4a… p switches, SW4b… mp switches, SW5a, SW5b… Switch, TENB1, TENB1a, TENB1b, TENB2… Control signal, Bm, Bm-1… Drive unit, P… Pixel, D… Grayscale data.

Claims

1. A pixel and an output node electrically connected, A first switch, one end of which is electrically connected to the output node, The other end and one end of the first switch are electrically connected to n (n is an integer of 1 or more) first capacitors, A first capacitor drive circuit drives the n first capacitors based on a video signal representing image information, and is electrically connected to the other end of each of the n first capacitors. A second switch is electrically connected to one end of the first switch and to the other end of the first switch, and the other end of the second switch is electrically connected to the first test node, A third switch, one end of which is electrically connected to the output node, The other end and one end of the third switch are electrically connected to m (m is an integer of 1 or more) fourth switches, Each of the m fourth switches has one end electrically connected to the other end of each second capacitor, and a constant potential is applied to the other end of each second capacitor. The system comprises a fifth switch, the other end of which is electrically connected to one end of the third switch, and the other end of which is electrically connected to the second inspection node. Drive circuit.

2. A sixth switch, one end of which is electrically connected to the output node, The system further comprises a voltage drive circuit electrically connected to the other end of the sixth switch, which outputs a first voltage based on the video signal representing the image information. The drive circuit according to claim 1.

3. The third switch further comprises a buffer or clocked gate, one end of which is electrically connected to the other end. The drive circuit according to claim 1.

4. A pixel and an output node electrically connected, A seventh switch, one end of which is electrically connected to the output node, The other end and one end of the seventh switch are electrically connected to s (where s is an integer of 1 or more) third capacitors, A second capacitor drive circuit drives the s third capacitors based on the lower bits of the video signal representing image information, and is electrically connected to the other ends of each of the s third capacitors. An eighth switch, to which one end is electrically connected to the other end of the seventh switch and the other end is electrically connected to the third inspection node, A ninth switch, one end of which is electrically connected to the output node, The other end and one end of the ninth switch are electrically connected to n-s (where n is an integer greater than s) fourth capacitors, A third capacitor drive circuit drives the n-s fourth capacitors based on the video signal of the higher bits of the video signal representing the image information, and is electrically connected to the other ends of each of the n-s fourth capacitors. A 10th switch is electrically connected to one end of the 9th switch and to the other end of the 10th switch which is electrically connected to the 4th test node, A third switch, one end of which is electrically connected to the output node, The other end and one end of the third switch are electrically connected to m (m is an integer of 1 or more) fourth switches, Each of the m fourth switches has one end electrically connected to the other end of each second capacitor, and a constant potential is applied to the other end of each second capacitor. The system comprises a fifth switch, the other end of which is electrically connected to one end of the third switch, and the other end of which is electrically connected to the second inspection node. Drive circuit.

5. A pixel and an output node electrically connected, A seventh switch, one end of which is electrically connected to the output node, The other end and one end of the seventh switch are electrically connected to s (where s is an integer of 1 or more) third capacitors, A second capacitor drive circuit drives the s third capacitors based on the lower bits of the video signal representing image information, and is electrically connected to the other ends of each of the s third capacitors. An eighth switch, to which one end is electrically connected to the other end of the seventh switch and the other end is electrically connected to the third inspection node, A ninth switch, one end of which is electrically connected to the output node, The other end and one end of the ninth switch are electrically connected to n-s (where n is an integer greater than s) fourth capacitors, A third capacitor drive circuit drives the n-s fourth capacitors based on the video signal of the higher bits of the video signal representing the image information, and is electrically connected to the other ends of each of the n-s fourth capacitors. A 10th switch is electrically connected to one end of the 9th switch and to the other end of the 10th switch which is electrically connected to the 4th test node, An 11th switch, one end of which is electrically connected to the output node, The other end and one end of the 11th switch are electrically connected to p (where p is an integer of 1 or more) 12th switches, Each of the p 12 switches has one end electrically connected to the other end of each of the p 5th capacitors to which a constant potential is applied. A 13th switch is electrically connected to one end of the 12th switch and to the other end of the 13th switch which is electrically connected to the 5th inspection node, A 14th switch, one end of which is electrically connected to the output node, The other end and one end of the 14th switch are electrically connected to m-p (where m is an integer greater than p) 15th switches, Each of the m-p 15 switches has one end electrically connected to the other end of each of the m-p 6th capacitors, to which a constant potential is applied. The system comprises a 16th switch, the other end of which is electrically connected to one end of the 15th switch and the other end of which is electrically connected to the 6th inspection node. Drive circuit.

6. A drive unit, one end of which is electrically connected to the other end of the 13th switch, The device further comprises a drive unit, one end of which is electrically connected to the other end of the 16th switch. The drive circuit according to claim 5.

7. A drive circuit according to any one of claims 1 to 6, The system comprises an electro-optic panel having the aforementioned pixels and electrically connected to the output node. Electro-optical device.

Images