Calibration circuits and electro-optical devices

Abstract

To provide a high-speed and high-precision verification circuit. [Solution] The test circuit 70 comprises an amplifier 53 having input node NODE_V, input node NODE_R and output node TEST_OUT; a first circuit 51 having a switch SW4 connected to input node NODE_V to which an initial potential VREF2 is applied and a switch SW5 connected to input node NODE_R to which a reference potential VREF1 is applied; a second circuit 52 provided between the node under test TEST_NODE1 and input node NODE_V and having a capacitive element C1 and switch SW1 connected to input node NODE_V and a capacitive element C2 and switch SW2; and a control circuit 60 that controls the first circuit 51 and the second circuit 52, wherein the withstand voltage of the amplifier 53 is lower than the voltage applied to the node under test TEST_NODE1, and the capacitance of the capacitive element C2 is smaller than the capacitance of the capacitive element C1.

Description

Technical Field

[0001] The present invention relates to a test circuit and an electro-optical device.

Background Art

[0002] Patent Document 1 describes a measurement circuit for a driver circuit that outputs a data signal to a liquid crystal panel. The measurement circuit measures a voltage change amount of the data signal output from the driver circuit. The measurement circuit includes a first capacitive element, a second capacitive element, a switch, a comparison circuit, and a control circuit. A voltage of a data signal to be measured is applied to one end of the first capacitive element, and the other end of the first capacitive element is electrically connected to a comparison node of the comparison circuit.

[0003] A first voltage is applied to the comparison node of the comparison circuit in a first period, and in a second period, a second voltage obtained by adding a divided voltage amount corresponding to a capacitance ratio between the first capacitive element and the second capacitive element to a voltage change of the data signal is applied. Therefore, according to Patent Document 1, a low-voltage-withstand transistor can be used in the comparison circuit.

Prior Art Literature

Patent Literature

[0004]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0005] In the measurement circuit described in Patent Document 1, when the voltage change amount of the data signal is large, it is difficult to ensure sufficient sensitivity for all magnitudes of the voltage change amount, which poses a problem that high-precision measurement is difficult.

Means for Solving the Problem

[0006] A verification circuit according to one aspect of the present invention comprises: an amplifier having a first input node, a second input node, and an output node; a first circuit having a first switch with one end electrically connected to the first input node and a first potential applied to the other end; a second switch with one end electrically connected to the second input node and a second potential applied to the other end; a second circuit having a first capacitive element provided between the node to be verified and the first input node, with one end electrically connected to the first input node; a third switch with one end electrically connected to the other end of the first capacitive element and the other end electrically connected to the node to be verified; a second capacitive element with one end electrically connected to the first input node; a fourth switch with one end electrically connected to the other end of the second capacitive element and the other end electrically connected to the node to be verified; and a control circuit for controlling the first circuit and the second circuit, wherein the withstand voltage of the amplifier is lower than the voltage applied to the node to be verified, and the capacitance of the second capacitive element is smaller than the capacitance of the first capacitive element.

[0007] An electro-optical apparatus according to one aspect of the present invention comprises an electro-optical panel, a drive circuit for driving the electro-optical panel, and the above-mentioned calibration circuit. [Brief explanation of the drawing]

[0008] [Figure 1] A perspective view showing the external appearance of a driver equipped with a calibration circuit according to this embodiment and an electro-optical device equipped with the driver. [Figure 2A] A block diagram showing the general configuration of the driver. [Figure 2B] A block diagram showing the general configuration of a modified driver. [Figure 3] Circuit diagram of the verification circuit. [Figure 4] A timing chart showing the operation of the test circuit. [Figure 5] Circuit diagram of the verification circuit according to Embodiment 2. [Figure 6] A timing chart showing the operation of the verification circuit according to Embodiment 2. [Figure 7] Circuit diagram of the verification circuit according to Embodiment 3. [Figure 8A] Timing chart showing operations according to a verification circuit of a comparative example for the verification circuit of Embodiment 3. [Figure 8B] Timing chart showing operations of the verification circuit according to Embodiment 3. [Figure 9A] Circuit diagram of the verification circuit according to Embodiment 4. [Figure 9B] Circuit diagram of a verification circuit according to a modification of Embodiment 4. [Figure 10] Timing chart showing operations of the verification circuit according to Embodiment 4. [Figure 11] Circuit diagram of the verification circuit according to Embodiment 5. [Figure 12A] Circuit diagram of the verification circuit according to Embodiment 6. [Figure 12B] Circuit diagram of a verification circuit according to a modification of Embodiment 6. [Figure 13A] Timing chart showing operations of the verification circuit according to Embodiment 6. [Figure 13B] Timing chart showing operations of the verification circuit according to Embodiment 6. [Figure 13C] Timing chart showing operations of the verification circuit according to Embodiment 6. [Figure 14] Circuit diagram of the verification circuit according to Embodiment 7. DESCRIPTION OF EMBODIMENTS

[0009] 1. Embodiment 1 1.1. Configuration of electro-optical device 100 FIG. 1 is a perspective view illustrating an example of the appearance of electro-optical device 100 according to the present embodiment. As shown in FIG. 1, electro-optical device 100 includes driver 1, electro-optical panel 2, and flexible substrate 3. Driver 1 includes verification circuit 70 (see FIG. 2A) which will be described later.

[0010] The electro-optical device 100 is preferably used as a display device for a projector. The electro-optical device 100 may also be used as a display device for devices including smartphones, cameras, televisions, car navigation systems, personal computers, displays, POS (Point of Sale) terminals, printers, scanners, copiers, video players, or devices equipped with touch panels.

[0011] The electro-optical panel 2 is an active-drive transmissive liquid crystal display panel that includes pixels P in a display area TD and is provided with a TFT (Thin Film Transistor) as a switching element for each pixel P. The electro-optical panel 2 may be a reflective liquid crystal display panel or a semi-transmissive liquid crystal display panel. Furthermore, the electro-optical panel 2 may be a display device other than a liquid crystal display panel, for example, an organic EL display.

[0012] The pixels P are provided corresponding to intersections between scanning lines 2x and data lines 2y arranged in a matrix. The electro-optical panel 2 includes an element substrate 21 and a counter substrate 22, and the flexible substrate 3 is mounted on an overhang portion 21a of the element substrate 21.

[0013] The driver 1 outputs a data voltage Vd for driving the electro-optical panel 2 to the electro-optical panel 2 based on a video signal representing image information. In the present embodiment, the driver 1 is configured by an integrated circuit device (IC). The integrated circuit device is, for example, an IC chip having a circuit formed on a silicon substrate, or a device in which an IC chip is housed in a package.

[0014] In the present embodiment, the driver 1 is mounted on the flexible substrate 3. That is, the data voltage Vd output from the driver 1 is supplied to the electro-optical panel 2 via the flexible substrate 3. Note that the driver 1 may be mounted on the overhang portion 21a of the electro-optical panel 2, or may be mounted on a rigid substrate (not shown) and configured to supply the data voltage Vd to the electro-optical panel 2 via the flexible substrate 3.

[0015] The electro-optical panel 2 is supplied with data voltage Vd, power supply voltage, timing signals, etc., via the flexible substrate 3, but some or all of the power supply voltage, timing signals, etc., may be output by the driver 1.

[0016] 1.2. Driver 1 Configuration Figure 2A is a block diagram showing a schematic configuration of driver 1 with a calibration circuit 70. Figure 2B is a block diagram showing another schematic configuration of driver 1 with a calibration circuit 70.

[0017] As shown in Figure 2A, the driver 1 includes a capacitive drive circuit 20, a balanced capacitive circuit 30, a voltage drive circuit 40, a test circuit 50, a control circuit 60, and an output node NODE1 which is an output terminal that outputs a data voltage Vd. The output node NODE1 is electrically connected to the input node NODE4 of the electro-optical panel 2 via a flexible substrate 3. In this embodiment, the verification circuit 70 consists of the test circuit 50 and the control circuit 60.

[0018] The capacitive drive circuit 20 outputs a data voltage Vd by redistributing the charge of the capacitor. The balancing capacitive circuit 30 is used to appropriately drive various electro-optical panels 2 with different electro-optical panel side capacitive elements CP. The voltage drive circuit 40 outputs a voltage V40 based on a video signal representing image information as the data voltage Vd. In this embodiment, the capacitive drive circuit 20 is an example of a drive circuit.

[0019] The capacitive drive circuit 20 is electrically connected to output node NODE1 via switch SW101. The balanced capacitive circuit 30 is electrically connected to output node NODE1 via switch SW103. The voltage drive circuit 40 is electrically connected to output node NODE1 via switch SW106.

[0020] When driver 1 drives the electro-optical panel 2, switches SW101 and SW103 are turned ON during the first period and OFF during the second period following the first period. Conversely, switch SW106 is turned OFF during the first period and ON during the second period following the first period. In other words, driver 1 outputs a data voltage Vd during the first period driven by the capacitive drive circuit 20, and outputs a data voltage Vd during the second period following the first period driven by the voltage drive circuit 40. By controlling it in this way, driver 1 can be driven at high speed and with high precision.

[0021] The control terminal of switch SW101 is supplied with the control signal DENB from the control circuit 60, the control terminal of switch SW103 is supplied with the control signal LENB from the control circuit 60, and the control terminal of switch SW106 is supplied with the control signal AENB from the control circuit 60. In other words, the ON / OFF state of switches SW101, SW103, and SW106 is controlled by the control circuit 60.

[0022] The capacitive drive circuit 20 is electrically connected to the node under test TEST_NODE1 via switch SW102. The balanced capacitive circuit 30 is electrically connected to the node under test TEST_NODE2 via switch SW105. In other words, the capacitive drive circuit 20 and the balanced capacitive circuit 30 are connected to different nodes under test. Therefore, the driver 1 can perform the testing of the capacitive drive circuit 20 and the balanced capacitive circuit 30 in parallel, thereby improving the testing speed.

[0023] The node under test, TEST_NODE1, is electrically connected to the test circuit 50 via the test line, TEST_LINE1. The node under test, TEST_NODE2, is electrically connected to the test circuit 50 via the test line, TEST_LINE2.

[0024] The inspection circuit 50 is a circuit that inspects the accuracy of the capacitive drive circuit 20 and the balance capacitance circuit 30. The inspection results from the inspection circuit 50 are output to node NODE2 via the output line OUT_LINE. The inspection results from the inspection circuit 50 allow us to determine whether the capacitive drive circuit 20 and the balance capacitance circuit 30 are good or bad, and whether any defects have occurred. Specifically, the inspection results from the inspection circuit 50 allow us to determine whether each of the n capacitors C201 and m capacitors C302 are good or bad.

[0025] The test circuit 50 is preferably formed on the same silicon substrate as the capacitive drive circuit 20 and the balance capacitive circuit 30. By forming it on the same silicon substrate, the test circuit 50 can be formed at a low cost.

[0026] When testing the capacitive drive circuit 20 using the test circuit 50, switch SW102 is turned ON and switch SW101 is turned OFF. As a result, the voltage under test V20 is output to the test circuit 50 via switch SW102 through the node under test TEST_NODE1 and the test line TEST_LINE1.

[0027] Thus, since the capacitive drive circuit 20 is disconnected from the output node NODE1 during testing, the influence of the output node NODE1 and the balance capacitance circuit 30 can be eliminated, and the amplitude of the test voltage can be increased. Therefore, according to this embodiment, the accuracy of the test of the capacitive drive circuit 20 by the test circuit 50 can be improved.

[0028] When testing the balance capacitance circuit 30 using the test circuit 50, switch SW105 is turned ON and switch SW103 is turned OFF. As a result, the voltage under test V30 is output to the test circuit 50 via switch SW105, through the node under test TEST_NODE2 and the test line TEST_LINE2.

[0029] Thus, since the balance capacitance circuit 30 is disconnected from the output node NODE1 during testing, the influence of the output node NODE1 and the capacitance drive circuit 20 can be eliminated, and the amplitude of the test voltage can be increased. Therefore, according to this embodiment, the accuracy of testing the balance capacitance circuit 30 by the test circuit 50 can be improved.

[0030] The control terminal of switch SW102 receives control signal TENB1 from the control circuit 60, and the control terminal of switch SW105 receives control signal TENB2 from the control circuit 60. In other words, the ON / OFF state of switches SW102 and SW105 is controlled by the control circuit 60.

[0031] The control circuit 60 is connected to the input / output node NODE3. The control circuit 60 performs the various controls described above based on control information stored in a memory (not shown). The setting or modification of this control information can be performed externally via the input / output node NODE3.

[0032] As described above, in this embodiment, the verification circuit 70 consists of a test circuit 50 and a control circuit 60. As described above, it is preferable that the test circuit 50 be formed on the same silicon substrate as the capacitive drive circuit 20 and the balance capacitance circuit 30, but all or part of the verification circuit 70 may be formed on a different silicon substrate from the capacitive drive circuit 20 and the balance capacitance circuit 30. In other words, the verification circuit 70 may be provided on an IC chip separate from the driver 1.

[0033] 1.2.1. Configuration of the Capacitive Drive Circuit 20 The capacitive drive circuit 20 is a circuit that outputs a data voltage Vd by redistributing the charge of a capacitor. The capacitive drive circuit 20 outputs the data voltage Vd to the output node NODE1 via a switch SW101, one end of which is electrically connected to the output node NODE1.

[0034] The capacitive drive circuit 20 includes n capacitors C201 and a capacitor drive circuit 210 that drives the n capacitors C201 based on a video signal representing image information. Here, n is an integer of 1 or more, and for example, n can be set to the same number as the number of bits in the grayscale data D.

[0035] The capacitance values ​​of the n capacitors C201 are weighted by powers of 2 corresponding to the bits D0, D1, ..., Dn-1, and Dn of the grayscale data D. Then, each drive unit of the capacitance drive circuit 20 outputs a low-level or high-level potential according to the bits D0, D1, ..., Dn-1, and Dn, and the n capacitors C201 are driven by that potential. The low-level potential is, for example, 0V, and the high-level potential is, for example, 15V.

[0036] This drive causes charge redistribution between the n capacitors C201 and the electro-optic panel side capacitance element CP, resulting in a data voltage Vd being output to the output node NODE1. The electro-optic panel side capacitance element CP is determined by the substrate capacitance element CP1 and the panel capacitance element CP2.

[0037] The electro-optic panel side capacitance element CP is the sum of the capacitances visible from the output node NODE1. For example, the electro-optic panel side capacitance element CP is the sum of the substrate capacitance element CP1, which is the parasitic capacitance of the flexible substrate 3, and the panel capacitance element CP2, which is the parasitic capacitance and pixel capacitance within the electro-optic panel 2. The TFTs within the electro-optic panel 2 have parasitic capacitance between the source and gate. Since many TFTs are connected to the data line 2y (see Figure 1), the data line 2y has parasitic capacitance from many TFTs. In addition, there is parasitic capacitance between the data line 2y and the scan line 2x. Furthermore, in a liquid crystal display panel, there is capacitance in the pixels P. The sum of these is the panel capacitance element CP2.

[0038] 1.2.2. Configuration of the Balance Capacitance Circuit 30 The balanced capacitance circuit 30 is a capacitance connected to the output node NODE1 via the switch SW103, and its capacitance value can be set to a variable value.

[0039] The balancing capacitance circuit 30 includes m switches SW104 and m capacitors C302 for capacitance adjustment, where m is an integer greater than or equal to 1. Each of the m switches SW104 has one end electrically connected to the other end of switch SW103. Control signals EN0, EN1, ..., ENm-1, ENm are supplied to each of the m control terminals of the switches SW104 from the control circuit 60.

[0040] The balancing capacitance circuit 30 is used to set the capacitance ratio between the n capacitors C201 and the electro-optic panel side capacitance element CP to a predetermined value. The driver 1 having the balancing capacitance circuit 30 enables it to appropriately drive various electro-optic panels 2 with different electro-optic panel side capacitance elements CP, thereby increasing the versatility of the driver 1.

[0041] The balance capacitance circuit 30 has a buffer 303. The buffer 303 is used to output the voltage V30 under test when the balance capacitance circuit 30 is being tested. One end of the buffer 303 is connected to one of the m capacitors C302, and the other end of the buffer 303 is supplied with a drive signal T0.

[0042] 1.2.3. Configuration of the voltage drive circuit 40 The voltage drive circuit 40 includes a DAC (Digital to Analog Converter) 41 and an amplifier 42. The DAC41 generates and outputs gradation voltages corresponding to each value of the gradation data D. If the gradation data D is, for example, 12 bits, it generates and outputs 4096 gradation voltages.

[0043] Amplifier 42 amplifies, inverts, inverts, and performs impedance conversion on the gradation voltage output from DAC 41 to output voltage V40. Voltage V40 is output as data voltage Vd from output node NODE1 via switch SW106.

[0044] 1.2.4. Configuration of a modified example of Driver 1 Figure 2B shows a schematic configuration of a modified version of driver 1. The driver 1 shown in Figure 2B differs from the driver 1 shown in Figure 2A in that the capacitive drive circuit 20 is divided into three parts: capacitive drive circuit 20a, capacitive drive circuit 20b, and capacitive drive circuit 20c. Note that components identical to those in the driver 1 shown in Figure 2A are given the same reference numerals, and their explanation may be omitted.

[0045] Capacitive drive circuit 20a is responsible for bits D0, D1, ..., Dp-2, Dp-1 of the least significant bit (LSB) of the grayscale data Da, which is divided into three parts from the grayscale data D. Capacitive drive circuit 20b is responsible for bits Dp, Dp+1, ..., Dq-2, Dq-1 of the middle grayscale data Db, which is divided into three parts from the grayscale data D. Capacitive drive circuit 20c is responsible for bits Dq, Dq+1, ..., Dn-1, Dn of the most significant bit (MSB) of the grayscale data Dc, which is divided into three parts from the grayscale data D. Here, q is an integer less than n, and p is an integer less than q.

[0046] When the test circuit 50 tests the capacitive drive circuit 20a, the control circuit 60 outputs control signals TENB1a and DENB to turn switch SW102a ON and switch SW101a OFF. As a result, the voltage under test V20a is output to the test circuit 50 via switch SW102a, through the node under test TEST_NODE1a and the test line TEST_LINE_L. In this embodiment, the node under test TEST_NODE1a is an example of a first node under test.

[0047] When the test circuit 50 tests the capacitive drive circuit 20b, the control circuit 60 outputs control signals TENB1b and DENB to turn switch SW102b ON and switch SW101b OFF. As a result, the voltage under test V20b is output to the test circuit 50 via switch SW102b, through the node under test TEST_NODE1b and the test line TEST_LINE_M. In this embodiment, the node under test TEST_NODE1b is an example of a second node under test.

[0048] When the test circuit 50 tests the capacitive drive circuit 20c, the control circuit 60 outputs control signals TENB1c and DENB to turn switch SW102c ON and switch SW101c OFF. As a result, the voltage under test V20c is output to the test circuit 50 via switch SW102c, through the node under test TEST_NODE1c and the test line TEST_LINE_H.

[0049] Here, the voltage under test V20a is lower than the voltage under test V20b, and the voltage under test V20c is higher than the voltage under test V20b.

[0050] 1.3. Configuration of the verification circuit 70 Figure 3 is the circuit diagram of the verification circuit 70. As shown in Figure 3, the verification circuit 70 consists of a test circuit 50 and a control circuit 60. The test circuit 50 includes a first circuit 51 which includes an amplifier 53, and a second circuit 52 which includes capacitive elements C1, C2, C3 and switches SW1, SW2, SW3.

[0051] Amplifier 53 compares the potential of input node NODE_V with the potential of input node NODE_R and outputs the comparison result to output node TEST_OUT. In other words, in this embodiment, amplifier 53 is a comparator and outputs a binary logic level signal of either a high level or a low level based on the comparison result. The comparison result output from output node TEST_OUT is output to node NODE2 via buffer 54 and output line OUT_LINE.

[0052] A reference potential VREF1 is supplied to the input node NODE_R of amplifier 53 via switch SW5. The reference potential VREF1 can be, for example, the ground potential.

[0053] The input node NODE_V of amplifier 53 is supplied with an initial potential VREF2 via switch SW4, and the node under test TEST_NODE1 is electrically connected via the second circuit 52.

[0054] In this embodiment, the input node NODE_V of amplifier 53 is an example of a first input node, the input node NODE_R is an example of a second input node, and the output node TEST_OUT is an example of an output node. Also, the initial potential VREF2 is an example of a first potential, and the reference potential VREF1 is an example of a second potential. Furthermore, the switch SW4 is an example of a first switch, and the switch SW5 is an example of a second switch.

[0055] The second circuit 52 is provided between the node under test TEST_NODE1 and the input node NODE_V of the amplifier 53. It changes the amplitude of the voltage under test V20 (see Figure 2A) applied via the node under test TEST_NODE1 and the test line TEST_LINE1 to a desired amplitude smaller than the amplitude of the voltage under test V20, and outputs it to the input node NODE_V.

[0056] The second circuit 52 is a variable capacitance circuit and includes capacitive elements C1, C2, and C3 arranged in parallel, and switches SW1, SW2, and SW3 arranged in series with each of the capacitive elements C1, C2, and C3. In the second circuit 52 of this embodiment, the capacitance of capacitive element C1 is the largest, the capacitance of capacitive element C3 is the smallest, and the capacitance of capacitive element C2 is intermediate in size between that of capacitive elements C1 and C3. Note that the number of capacitive elements C1, C2, and C3 in the second circuit 52 is not limited to three, but may be two or four or more. In this embodiment, capacitive element C1 is an example of a first capacitive element, and switch SW1 is an example of a third switch. Also, capacitive element C2 is an example of a second capacitive element, and switch SW2 is an example of a fourth switch.

[0057] The second circuit 52 receives the voltage under test V20 from the capacitance drive circuit 20 (see Figure 2A) via the node under test TEST_NODE1 and the test line TEST_LINE1. The input node NODE_V of the amplifier 53 receives a voltage that is divided from the voltage under test V20 according to the capacitance ratio of the second circuit 52 and the first circuit 51, specifically the parasitic capacitance of switch SW4. Therefore, the second circuit 52 can lower the voltage applied to the input node NODE_V of the amplifier 53 to a level lower than the voltage under test V20.

[0058] Thus, the voltage applied to the input node NODE_V of amplifier 53 is lower than the voltage V20 under test applied to the second circuit 52 via the node under test TEST_NODE1 and the test line TEST_LINE1.

[0059] Therefore, the breakdown voltage of amplifier 53 can be lower than the test voltage V20. Similarly, the breakdown voltages of switches SW4 and SW5 can be lower than the test voltage V20. In other words, the first circuit 51 can be a lower breakdown voltage circuit than the second circuit 52. Note that the second circuit 52 is a higher breakdown voltage circuit than the first circuit 51, and the breakdown voltage of the transistors used in switches SW1, SW2, and SW3 is set to be equal to or greater than the test voltage V20.

[0060] In this embodiment, by making the first circuit 51 a circuit with a lower voltage than the voltage under test V20, the circuit area required to form the first circuit 51 can be reduced, contributing to the miniaturization of the IC chip. Furthermore, by making the first circuit 51 a circuit with a lower voltage than the voltage under test V20, the first circuit 51 can be operated at high speed, thereby shortening the verification time.

[0061] In this embodiment, the voltage of the voltage under test V20 applied to the second circuit 52 via the test line TEST_LINE1 can be changed so that the voltage output from the second circuit 52 to the input node NODE_V of the amplifier 53 falls within the withstand voltage range of the first circuit 51 by appropriately selecting the capacitive elements C1, C2, and C3 of the second circuit 52 using switches SW1, SW2, and SW3. Furthermore, by appropriately selecting the capacitive elements C1, C2, and C3 of the second circuit 52 according to the voltage of the voltage under test V20, the voltage output from the second circuit 52 to the input node NODE_V of the amplifier 53 can be made suitable for testing, thereby improving the accuracy of the testing.

[0062] 1.4. Operation of the verification circuit 70 Figure 4 is a timing chart showing the operation of the calibration circuit 70. In Figure 4, the waveform shown by TEST_LINE1 is the waveform of the voltage V20 under test applied to the second circuit 52 via the node under test TEST_NODE1 and the test line TEST_LINE1.

[0063] The waveforms shown by SW1, SW2, SW3, and SW4 are the waveforms of the control signals output from the control circuit 60 and input to the control terminals of switches SW1, SW2, SW3, and SW4. Switches SW1, SW2, SW3, and SW4 turn ON when the control signal is at a high level and OFF when the control signal is at a low level.

[0064] The waveform shown by NODE_V is the waveform of the voltage applied to the input node NODE_V of amplifier 53.

[0065] The waveforms shown for NODE_R(High) and NODE_R(Low) are the waveforms of the reference potential VREF1 voltage applied to the input node NODE_R of amplifier 53, where NODE_R(Low) has a lower reference potential VREF1 voltage than NODE_R(High). By changing the voltage of the reference potential VREF1, the sensitivity of amplifier 53 can be changed. For example, by reducing the potential difference between the reference potential VREF1 and the initial potential VREF2, amplifier 53 can capture small amplitudes and output a verification result.

[0066] The waveform shown by TEST_OUT is the voltage waveform output from the output node TEST_OUT of amplifier 53. The potential of input node NODE_V is compared with the potential of input node NODE_R. When the potential of input node NODE_V is higher, a high-level signal is output, and when the potential of input node NODE_V is lower, a low-level signal is output.

[0067] When the calibration circuit 70 is activated, the control signal shown on SW5 is set to a high level for the entire period, and switch SW5 is turned ON. In the example shown in Figure 4, the control signals SW1, SW2, and SW3 are set to high levels in sequence, and the capacitive elements C1, C2, and C3 are electrically connected in sequence between the test line TEST_LINE1 and the input node NODE_V of amplifier 53. Note that all or any two of the capacitive elements C1, C2, and C3 may be electrically connected simultaneously between the test line TEST_LINE1 and the input node NODE_V of amplifier 53. The ON or OFF state of switches SW1, SW2, and SW3 is controlled so that the necessary capacitive elements C1, C2, and C3 are selected for accurate testing.

[0068] During periods when the control signals indicated by SW1, SW2, or SW3 are at a high level, i.e., when capacitive element C1, capacitive element C2, or capacitive element C3 is selected, a high-amplitude test voltage V20 and a low-amplitude test voltage V20 are sequentially input to the test line TEST_LINE1.

[0069] As shown in Figure 4, a voltage divided by the capacitance ratio between the capacitive element C1, C2, or C3 and the parasitic capacitance of the second circuit 52 is applied to the input node NODE_V of amplifier 53.

[0070] In this embodiment, since the capacitance of capacitive element C1 is the largest and the capacitance of capacitive element C3 is the smallest, the voltage applied to the input node NODE_V is highest when capacitive element C1 is selected and lowest when capacitive element C3 is selected.

[0071] Therefore, depending on the voltage of the reference potential VREF1 indicated by NODE_R(high) and NODE_R(low), a high-level or low-level signal is output from the output node TEST_OUT. Therefore, by setting the reference potential VREF1 to an appropriate voltage, the accuracy of the voltage under test V20 output from the capacitive drive circuit 20, or in other words, whether or not there is a fault in the capacitive drive circuit 20, can be determined by the signal output from the output node TEST_OUT.

[0072] As described above, the following effects can be obtained with the verification circuit 70 of this embodiment. The verification circuit 70 of this embodiment includes an amplifier 53 having an input node NODE_V as a first input node, an input node NODE_R as a second input node, and an output node TEST_OUT; a first circuit 51 having a switch SW4 as a first switch with one end electrically connected to the input node NODE_V and an initial potential VREF2 as a first potential applied to the other end; and a switch SW5 as a second switch with one end electrically connected to the input node NODE_R and a reference potential VREF1 as a second potential applied to the other end; and a first capacitive element provided between the node under verification TEST_NODE1 and the input node NODE_V, with one end electrically connected to the input node NODE_V. The amplifier 53 comprises a capacitive element C1, a switch SW1 as a third switch with one end electrically connected to the other end of the capacitive element C1 and the other end electrically connected to the node under test TEST_NODE1, a capacitive element C2 as a second capacitive element with one end electrically connected to the input node NODE_V, and a switch SW2 as a fourth switch with one end electrically connected to the other end of the capacitive element C2 and the other end electrically connected to the node under test TEST_NODE1, and a control circuit 60 that controls the first circuit 51 and the second circuit 52, wherein the withstand voltage of the amplifier 53 is lower than the voltage applied to the node under test TEST_NODE1, and the capacitance of the capacitive element C2 is smaller than the capacitance of the capacitive element C1.

[0073] As described above, the verification circuit 70 of this embodiment includes capacitive elements C1 and C2 arranged in parallel between the node under test TEST_NODE1 and the input node NODE_V, and switches SW1 and SW2 connected to capacitive elements C1 and C2. Therefore, the withstand voltage of the amplifier 53 can be made lower than the voltage applied to the node under test TEST_NODE1. Furthermore, since capacitive elements C1 and C2 have different capacitances, by appropriately selecting between capacitive elements C1 and C2 using switches SW1 and SW2, the voltage applied to the input node NODE_V can be made lower than the voltage under test V20 applied to the node under test TEST_NODE1, and also a desired voltage.

[0074] Therefore, according to the calibration circuit 70 of this embodiment, the amplifier 53 can be made low-voltage, which reduces the circuit area of ​​the calibration circuit 70 and enables the realization of a high-speed and high-precision calibration circuit 70. Furthermore, even when the amplitude of the voltage V20 under test changes significantly, sufficient sensitivity can be ensured, and high-precision measurements can be performed.

[0075] In the verification circuit 70 of this embodiment, the control circuit 60 controls the conduction state of switch SW1 and switch SW2 according to the voltage applied to the node under verification TEST_NODE1.

[0076] Therefore, the verification circuit 70 of this embodiment is controlled by the control circuit 60, realizing a high-speed and high-precision verification circuit 70.

[0077] In the calibration circuit 70 of this embodiment, the reference potential VREF1 is the ground potential. Therefore, the calibration circuit 70 can be operated stably.

[0078] The electro-optical apparatus 100 of this embodiment includes an electro-optical panel 2, a capacitive drive circuit 20 as a drive circuit for driving the electro-optical panel 2, and the above-described calibration circuit 70. Therefore, in this embodiment, the electro-optical device 100 can be inspected by the calibration circuit 70, thereby enabling the realization of an electro-optical device 100 of excellent quality.

[0079] In this embodiment of the electro-optical device 100, when the electro-optical panel 2 is driven by the capacitive drive circuit 20, the switch SW5 is OFF. Therefore, in this embodiment, when the electro-optical panel 2 is driven by the capacitive drive circuit 20, the calibration circuit 70 is in the off state, thus enabling the realization of an electro-optical device 100 with low power consumption.

[0080] 2. Embodiment 2 Next, the verification circuit 70 according to Embodiment 2 will be described based on Figures 5 and 6. Figure 5 is a circuit diagram of the verification circuit 70 according to Embodiment 2. Figure 6 is a timing chart showing the operation of the verification circuit 70 according to Embodiment 2.

[0081] The verification circuit 70 according to Embodiment 2 is used in the driver 1 shown in Figure 2B and differs from the verification circuit 70 according to Embodiment 1 in that switches SW1, SW2, and SW3 are electrically connected to different nodes under verification TEST_NODE1a, TEST_NODE1b, TEST_NODE1c and verification lines TEST_LINE_L, TEST_LINE_M, and TEST_LINE_H, respectively. Note that components identical to those in Embodiment 1 may be given the same reference numerals and their descriptions may be omitted.

[0082] Switch SW1 is electrically connected to the node under test TEST_NODE1a and the test line TEST_LINE_L. The voltage under test V20a is applied to the test line TEST_LINE_L from the capacitive drive circuit 20a, which is responsible for the least significant bit of the three-part division of the grayscale data D.

[0083] Switch SW2 is electrically connected to the node under test TEST_NODE1b and the test line TEST_LINE_M. The voltage under test V20b is applied to the test line TEST_LINE_M from the capacitive drive circuit 20b, which is responsible for the middle bit of the three-part division of the grayscale data D.

[0084] Switch SW3 is electrically connected to the node under test TEST_NODE1c and the test line TEST_LINE_H. The voltage under test V20c is applied to the test line TEST_LINE_H from the capacitive drive circuit 20c, which is responsible for the most significant bit of the three-part division of the grayscale data D.

[0085] As shown in Figure 6, the highest amplitude test voltage V20c is applied to the test line TEST_LINE_H, and the lowest amplitude test voltage V20a is applied to the test line TEST_LINE_L. However, by appropriately selecting the capacitances of capacitive elements C1, C2, and C3, the amplitude of the voltage applied to the input node NODE_V of amplifier 53 can be made uniform. Therefore, according to the test circuit 70 of Embodiment 2, proper testing can be performed for each of the test voltages V20a, V20b, and V20c with different amplitudes.

[0086] As described above, the verification circuit 70 of Embodiment 2 provides the following additional effects in addition to those of the verification circuit 70 of Embodiment 1. In the second embodiment, the test circuit 70 has a node under test TEST_NODE1 which includes a node under test TEST_NODE1a as the first node under test and a node under test TEST_NODE1b as the second node under test, with node under test TEST_NODE1a being electrically connected to the other end of switch SW1 and node under test TEST_NODE1b being electrically connected to the other end of switch SW2.

[0087] Thus, the calibration circuit 70 of this embodiment can electrically connect an appropriate capacitive element C1 or C2 to each of the voltages under test V20a and V20b. Therefore, a high-speed and high-precision calibration circuit 70 can be realized. Furthermore, even when the amplitude of the voltage under test V20 changes significantly, sufficient sensitivity can be ensured, and high-precision measurements can be performed.

[0088] 3. Embodiment 3 Next, the verification circuit 70 according to Embodiment 3 will be described based on Figures 7, 8A, and 8B. Figure 7 is a circuit diagram of the verification circuit 70 according to Embodiment 3. Figure 8A is a timing chart showing the operation of a comparative example verification circuit of the verification circuit 70 of Embodiment 3. Figure 8B is a timing chart showing the operation of the verification circuit 70 according to Embodiment 3.

[0089] The verification circuit 70 according to Embodiment 3 is used in the driver 1 shown in Figure 2B and differs from the verification circuit 70 according to Embodiment 1 in that switches SW1, SW2, and SW3 are electrically connected to different nodes under verification TEST_NODE1a, TEST_NODE1b, TEST_NODE1c and verification lines TEST_LINE_L, TEST_LINE_M, and TEST_LINE_H, respectively, and also differs from the verification circuit 70 according to Embodiment 2 in that a capacitive element C4 is electrically connected to the input node NODE_V of the amplifier 53. Note that components identical to those in Embodiment 1 and Embodiment 2 are denoted by the same reference numerals and their descriptions may be omitted.

[0090] Capacitive element C4 is composed of a MIM (Metal Insulation Metal) capacitor. One end of capacitive element C4 is electrically connected to the input node NODE_V of amplifier 53, and the other end is electrically connected to a fixed potential VREF3. The fixed potential VREF3 is, for example, VSS. In this embodiment, the fixed potential VREF3 is an example of a third potential, and capacitive element C4 is an example of a third capacitive element.

[0091] When the capacitance ratio between the second circuit 52 and the first circuit 51, that is, the input capacitance of the input node NODE_V of amplifier 53, is large, the voltage of the input node NODE_V of amplifier 53 fluctuates greatly due to the influence of noise, as shown in ranges N1 and N2 in Figure 8A. In the example shown in Figure 8A, the portion shown in range N2 overlaps with the input node NODE_R, so the output of the output node TEST_OUT of amplifier 53 is also not determined. Note that the example shown in Figure 8A does not include the capacitive element C4, and the capacitance ratio between the capacitance of the second circuit 52 and the capacitance of the first circuit 51 is larger than in Embodiment 3.

[0092] In contrast, in Embodiment 3, a capacitive element C4 is provided electrically connected to the input node NODE_V, which allows the capacitance ratio between the capacitance of the second circuit 52 and the capacitance of the first circuit 51 to be reduced. Therefore, as shown in the ranges N1 and N2 in Figure 8B, the voltage fluctuation at the input node NODE_V of the amplifier 53 can be reduced. Thus, the calibration by the amplifier 53 can be performed with high accuracy.

[0093] As described above, the verification circuit 70 of Embodiment 3 provides the following additional effects in addition to the effects of the verification circuits 70 of Embodiments 1 and 2. The verification circuit 70 of Embodiment 3 further includes a capacitive element C4 as a third capacitive element, one end of which is electrically connected to the input node NODE_V, and to which a fixed potential VREF3 as a third potential is applied as a third potential at the other end. According to the calibration circuit 70 of Embodiment 3, the influence of noise can be suppressed, thus enabling the realization of a highly accurate calibration circuit 70.

[0094] 4. Embodiment 4 Next, the verification circuit 70 according to Embodiment 4 will be described based on Figures 9A, 9B, and 10. Figure 9A is a circuit diagram of the verification circuit 70 according to Embodiment 4. Figure 9B is a circuit diagram of the verification circuit 70 according to a modified example of Embodiment 4. Figure 10 is a timing chart showing the operation of the verification circuit 70 according to Embodiment 4.

[0095] The verification circuit 70 according to Embodiment 4 differs from the verification circuit 70 according to Embodiments 1 to 3 in that the input node NODE_V of amplifier 53 is electrically connected to the same power supply as the input node NODE_R of amplifier 53, specifically to the reference potential VREF1. Note that components identical to those in Embodiments 1 to 3 are denoted by the same reference numerals, and their descriptions may be omitted.

[0096] As shown in Figure 9A, the input node NODE_V of amplifier 53 is electrically connected to the same reference potential VREF1 as the input node NODE_R of amplifier 53 via switch SW4. Switch SW6 is connected in parallel to switch SW4. Switch SW6 is a transistor and is used to create a potential difference between the potential of input node NODE_V and input node NODE_R of amplifier 53. Specifically, when switch SW6 is turned OFF, the pushdown caused by the drain capacitance of switch SW6 lowers the potential of input node NODE_V, thereby creating a potential difference between the potential of input node NODE_V and input node NODE_R of amplifier 53.

[0097] The switch SW6 can be replaced with a capacitor. Figure 9B shows the circuit configuration of a modified example of Embodiment 4, in which a capacitive element C5 is provided instead of the switch SW6. The capacitive element C5 is electrically connected to the input node NODE_V of the amplifier 53.

[0098] In Embodiment 4, two configurations were described for creating a potential difference between the potential of input node NODE_V and input node NODE_R of amplifier 53: one using a switch SW6 and the other using a capacitive element C5. However, the configuration using the switch SW6 is preferable. Since the potential difference between the potential of input node NODE_V and input node NODE_R of amplifier 53 can be small, the capacitance required to create this potential difference can also be small. Furthermore, when forming such a small capacitance in an integrated circuit device, the drain capacitance of the switch SW6 is easier to make smaller than that of the capacitive element C5.

[0099] When the verification circuit 70 of Embodiment 4 is operated, as shown in Figure 10, the control signals shown for SW4, SW5, and SW6 are initially set to a high level, turning on switches SW4, SW5, and SW6. A reference potential VREF1 is supplied to the input node NODE_V of amplifier 53 via switch SW4, and input nodes NODE_V and NODE_R of amplifier 53 become at the same potential. Because input nodes NODE_V and NODE_R of amplifier 53 are at the same potential, the output of the output node TEST_OUT of amplifier 53 is not determined.

[0100] Subsequently, the control signals shown for SW4 and SW6 are set to a low level, turning switches SW4 and SW6 OFF. When switch SW6 is turned OFF, the potential of input node NODE_V drops due to the pushdown caused by the drain capacitance, as shown in Figure 10. This creates a potential difference between the potential of input node NODE_V and input node NODE_R of amplifier 53, allowing amplifier 53 to output a stable signal from output node TEST_OUT.

[0101] As described above, the verification circuit 70 of Embodiment 4 provides the following additional effects in addition to the effects of the verification circuits 70 of Embodiments 1 to 3. In the verification circuit 70 of Embodiment 4, the other end of switch SW4 and the other end of switch SW5 are electrically connected to a reference potential VREF1 which is the same power source. Therefore, since the verification circuit 70 can be constructed with a simple circuit, the circuit area of ​​the verification circuit 70 can be reduced.

[0102] 5. Embodiment 5 Next, the verification circuit 70 according to Embodiment 5 will be described based on Figure 11. Figure 11 is a circuit diagram of the verification circuit 70 according to Embodiment 5.

[0103] The verification circuit 70 according to Embodiment 5 differs from the verification circuit 70 according to Embodiments 1 to 4 in that the amplifier 53 has a feedback circuit and constitutes a differential amplifier circuit. Note that components identical to those in Embodiments 1 to 4 are denoted by the same reference numerals, and their descriptions may be omitted.

[0104] As shown in Figure 11, the test circuit 70 according to Embodiment 5 has an amplifier 53 with a feedback circuit. The feedback circuit consists of a capacitive element C6, one end of which is electrically connected to the output node TEST_OUT of the amplifier 53 and the other end of which is electrically connected to the input node NODE_R, and a capacitive element C7, one end of which is electrically connected to the input node NODE_R and to which a fixed potential VREF4 is applied. In Embodiment 5, the capacitive element C6 is an example of a fourth capacitive element, the capacitive element C7 is an example of a fifth capacitive element, and the fixed potential VREF4 is an example of a fourth potential.

[0105] Amplifier 53 amplifies the potential difference between input node NODE_V and input node NODE_R according to the capacitances of capacitive elements C6 and C7, and outputs it. Therefore, by adjusting the voltage of the reference potential VREF1 to the predetermined voltage it should be, it becomes possible to determine how much deviation there is in the voltage under test V20 output from the capacitive drive circuit 20. Capacitive elements C6 and C7 may be composed of resistors.

[0106] As described above, the verification circuit 70 of Embodiment 5 provides the following additional effects in addition to the effects of the verification circuits 70 of Embodiments 1 to 4. The verification circuit 70 of Embodiment 5 further comprises a capacitive element C6 as a fourth capacitive element, one end of which is electrically connected to the output node TEST_OUT and the other end of which is electrically connected to the input node NODE_R, and a capacitive element C7 as a fifth capacitive element, one end of which is electrically connected to the input node NODE_R and to which a fixed potential VREF4 as a fourth potential is applied.

[0107] As described above, the verification circuit 70 of Embodiment 5 amplifies and outputs the potential difference between input node NODE_V and input node NODE_R with an amplification factor corresponding to the capacitances of capacitive elements C6 and C7. Therefore, by adjusting the voltage of the reference potential VREF1 to a predetermined voltage, it becomes possible to determine how much deviation there is in the voltage under test V20 output from the capacitance drive circuit 20.

[0108] 6. Embodiment 6 Next, the verification circuit 70 according to Embodiment 6 will be described based on Figures 12A to 13C. Figure 12A is a circuit diagram of the verification circuit 70 according to Embodiment 6. Figure 12B is a circuit diagram of the verification circuit 70 according to a modified example of Embodiment 6. Figure 13A is a timing chart showing the operation of the verification circuit 70 according to Embodiment 6. Figure 13B is a timing chart showing the operation of the verification circuit 70 according to Embodiment 6. Figure 13C is a timing chart showing the operation of the verification circuit 70 according to Embodiment 6.

[0109] The verification circuit 70 according to Embodiment 6 is similar to the verification circuit 70 according to Embodiment 5 in that the amplifier 53 has a feedback circuit, but differs from the verification circuit 70 according to Embodiment 5 in that the feedback circuit has a configuration that changes the amplification factor. Note that components identical to those in Embodiments 1 to 5 are denoted by the same reference numerals, and their descriptions may be omitted.

[0110] As shown in Figure 12A, the verification circuit 70 according to Embodiment 6 includes a capacitive element C8, one end of which is electrically connected to a capacitive element C6 and the other end of which is electrically connected to an input node NODE_R; a switch SW7, one end of which is electrically connected and the other end of which is electrically connected to an input node NODE_R, between the other end of capacitive element C6 and one end of capacitive element C8; a capacitive element C9, one end of which is electrically connected to an input node NODE_R via switch SW8 and the other end of which is electrically connected to a fixed potential VREF5; and a switch SW9, one end of which is electrically connected to an input node NODE_R and the other end of which is electrically connected to a capacitive element C7. In Embodiment 6, capacitive element C8 is an example of a sixth capacitive element, capacitive element C9 is an example of a seventh capacitive element, switch SW7 is an example of a fifth switch, and fixed potential VREF5 is an example of a fifth potential.

[0111] The verification circuit 70 of Embodiment 6 shown in Figure 12A may be modified as shown in Figure 12B. The verification circuit 70 according to the modified embodiment of Embodiment 6 in Figure 12B includes a capacitive element C10, one end of which is electrically connected to the output node TEST_OUT of the amplifier 53, and the other end of which is electrically connected to the input node NODE_R via a switch SW10.

[0112] When operating the verification circuit 70 according to Embodiment 6, the amplification factor of the amplifier 53 is set by turning switches SW7, SW8, and SW9 ON or OFF. In the timing chart shown in Figure 13A, all of switches SW7, SW8, and SW9 are ON. In the timing chart shown in Figure 13B, switches SW7 and SW9 are ON, and switch SW8 is OFF. In the timing chart shown in Figure 13C, switch SW7 is OFF, and switches SW8 and SW9 are ON.

[0113] As is evident from the signal amplitude of the output node TEST_OUT shown in Figures 13A, 13B, and 13C, the amplification factor of amplifier 53 is highest in the example in Figure 13B, and decreases in the order of Figures 13A and 13C.

[0114] As described above, the verification circuit 70 of Embodiment 6 provides the following additional effects in addition to the effects of the verification circuits 70 of Embodiments 1 to 5. The verification circuit 70 of Embodiment 6 further comprises a capacitor element C8 as a sixth capacitor element, one end of which is electrically connected to a capacitor element C6 as a fourth capacitor element and the other end of which is electrically connected to an input node NODE_R; a switch SW7 as a fifth switch, one end of which is electrically connected to an input node NODE_R and the other end of which is electrically connected to an input node NODE_R, between the other end of the capacitor element C6 and one end of the capacitor element C8; and a capacitor element C9 as a seventh capacitor element, one end of which is electrically connected to an input node NODE_R and to which a fixed potential VREF5 as a fifth potential is applied.

[0115] As described above, the calibration circuit 70 of Embodiment 6 amplifies the potential difference between input node NODE_V and input node NODE_R according to the capacitance of capacitive elements C6 to C9, and outputs it. Therefore, the voltage of the reference potential VREF1 can be adjusted to the predetermined voltage that it should originally be. Thus, a highly accurate calibration circuit 70 can be realized.

[0116] 7. Embodiment 7 Next, the verification circuit 70 according to Embodiment 7 will be described based on Figure 14. Figure 14 is a circuit diagram of the verification circuit 70 according to Embodiment 7.

[0117] The verification circuit 70 according to Embodiment 7 differs from the verification circuit 70 according to Embodiments 1 to 6 in that it has a discharge circuit. Note that components identical to those in Embodiments 1 to 6 are denoted by the same reference numerals, and their descriptions may be omitted.

[0118] The discharge circuit consists of a switch SW11, one end of which is electrically connected to the input node NODE_V of amplifier 53, and the other end of which is electrically connected to a common potential. In this embodiment, switch SW11 is an example of a sixth switch, and the common potential is an example of ground potential.

[0119] In the verification circuit 70 according to Embodiment 7, switch SW11 is controlled to turn ON before at least one of switches SW1, SW2, and SW3 is turned ON, and discharges the input node NODE_V of amplifier 53 to a common potential. This prevents overvoltage exceeding the breakdown voltage range of the first circuit 51 from being applied to the low-voltage first circuit 51, thereby suppressing malfunctions in the first circuit 51.

[0120] As described above, the verification circuit 70 of Embodiment 7 provides the following additional effects in addition to the effects of the verification circuits 70 of Embodiments 1 to 6. The verification circuit 70 of Embodiment 7 further includes a switch SW11 as a sixth switch, one end of which is electrically connected to the input node NODE_V and the other end of which is electrically connected to ground potential.

[0121] Therefore, according to the verification circuit 70 of Embodiment 7, the input node NODE_V of the amplifier 53 can be discharged to ground potential, thus realizing a highly reliable verification circuit 70.

[0122] Although preferred embodiments have been described above, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs similar functions to those of the embodiments described above, and any configuration can be added. [Explanation of Symbols]

[0123] 1…Driver, 2…Electro-optical panel, 2x…Scanning line, 2y…Data line, 3…Flexible substrate, 20, 20a, 20b, 20c…Capacitor drive circuit, 21…Element substrate, 21a…Protruding part, 22…Opposite substrate, 30…Balanced capacitance circuit, 40…Voltage drive circuit, 41…DAC, 42…Amplifier, 50…Test circuit, 51…First circuit, 52…Second circuit, 53…Amplifier, 54…Buffer, 60…Control circuit, 70…Verification circuit, 100…Electro-optical device, 210…Capacitor - Drive circuit, 303... Buffer, C201, C302... Capacitors, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10... Capacitive elements, CP... Electro-optical panel side capacitive element, CP1... Substrate capacitive element, CP2... Panel capacitive element, N1, N2... Range, SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11... Switches, SW101, SW101a, SW101b, SW101c, SW102, S W102a, SW102b, SW102c, SW103, SW104, SW105, SW106… Switch, Vd… Data voltage, V20, V20a, V20b, V20c… Tested voltage, V30… Tested voltage, V40… Voltage, TEST_LINE1, TEST_LINE2, TEST_LINE_L, TEST_LINE_M, TEST_LINE_H… Verification line, TEST_NODE1, TEST_NODE1a, TEST_NODE1b, TES T_NODE1c, TEST_NODE2… Tested node, TEST_OUT… Output node, NODE1… Output node, NODE2… Node, NODE3… Input / Output node, NODE4… Input node, NODE_V, NODE_R… Input node, TENB1, TENB2, DENB, LENB, AENB, EN0… Control signals, VREF1… Reference potential, VREF2… Initial potential, VREF3, VREF4, VREF5… Fixed potential, P… Pixel, TD… Display area.

Claims

1. A first circuit comprising: an amplifier having a first input node, a second input node, and an output node; a first switch having one end electrically connected to the first input node and the other end to which a first potential is applied; and a second switch having one end electrically connected to the second input node and the other end to which a second potential is applied; A second circuit comprising: a first capacitive element provided between the node under test and the first input node, with one end electrically connected to the first input node; a third switch with one end electrically connected to the other end of the first capacitive element and the other end electrically connected to the node under test; a second capacitive element with one end electrically connected to the first input node; and a fourth switch with one end electrically connected to the other end of the second capacitive element and the other end electrically connected to the node under test; The system includes a control circuit that controls the first circuit and the second circuit, The breakdown voltage of the amplifier is lower than the voltage applied to the node under test. The capacitance of the second capacitance element is smaller than the capacitance of the first capacitance element. Test circuit.

2. The control circuit controls the conduction state of the third switch and the fourth switch in accordance with the voltage applied to the node under test. The verification circuit according to claim 1.

3. The second potential is the ground potential. The verification circuit according to claim 1.

4. The node under test comprises a first node under test and a second node under test. The first node under inspection is electrically connected to the other end of the third switch. The second node under inspection is electrically connected to the other end of the fourth switch. The verification circuit according to claim 1.

5. The device further comprises a third capacitive element, one end of which is electrically connected to the first input node and the other end to which a third potential is applied. The verification circuit according to claim 1.

6. The other end of the first switch and the other end of the second switch are electrically connected to the same power source. The verification circuit according to claim 1.

7. A fourth capacitive element, one end of which is electrically connected to the output node and the other end of which is electrically connected to the second input node, The system further comprises a fifth capacitive element, one end of which is electrically connected to the second input node and the other end to which a fourth potential is applied. The verification circuit according to claim 1.

8. A sixth capacitor element, one end of which is electrically connected to the fourth capacitor element and the other end of which is electrically connected to the second input node, Between the other end of the fourth capacitance element and one end of the sixth capacitance element, there is a fifth switch, one end of which is electrically connected and the other end of which is electrically connected to the second input node. The system further comprises a seventh capacitive element, one end of which is electrically connected to the second input node and the other end to which a fifth potential is applied. The verification circuit according to claim 7.

9. The system further comprises a sixth switch, one end of which is electrically connected to the first input node and the other end of which is electrically connected to ground potential. The verification circuit according to claim 1.

10. Electro-optical panel and The system includes a drive circuit for driving the electro-optical panel, A verification circuit according to any one of claims 1 to 9, comprising Electro-optical device.

11. When the electro-optical panel is being driven by the drive circuit, the second switch is in the off position. The electro-optical apparatus according to claim 10.

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