Semiconductor equipment

Abstract

This increases the overvoltage withstand capability between the power terminal and the ground terminal, and between a specified terminal and the power terminal. [Solution] The semiconductor device 1 comprises a terminal section 1a including terminals T1, T2, and T3, and a clamp circuit 1b. Terminal T1 corresponds to a power terminal, terminal T2 to a signal terminal, and terminal T3 to a ground terminal. When an overvoltage Vsg1 is applied externally between terminals T1 and T3, the clamp circuit 1b clamps the overvoltage Vsg1 by allowing an overcurrent Isg1 to flow from terminal T1 to terminal T3. Furthermore, when an overvoltage Vsg2 is applied externally between terminals T2 and T1, the clamp circuit 1b clamps the overvoltage Vsg2 by allowing an overcurrent Isg2 to flow from terminal T2 to terminal T1.

Description

[[Technical Field]]

[0001] The present invention relates to a semiconductor device. [[Background Art]]

[0002] In an electronic device including a semiconductor device or the like, occurrence of an overvoltage such as ESD (Electro-Static Discharge) may cause malfunction or failure. For this reason, measures are taken to protect the device while satisfying the overvoltage resistance requirement.

[0003] As a related technology, for example, there has been proposed a circuit including a plurality of diodes, the number of which is determined according to a potential difference between a first power supply voltage and a second power supply voltage, between an output terminal of an open drain output circuit and an internal power supply line (Patent Document 1). There has also been proposed a circuit that performs switching to turn on so as to short-circuit the terminal to ground potential when an overvoltage occurs, thereby clamping the overvoltage at the terminal to protect the terminal (Patent Document 2). [[Prior Art Literature]] [[Patent Literature]]

[0004] [[Patent Document 1]] Japanese Patent Laid-Open No. 2004-222119 [[Patent Document 2]] Japanese Patent Laid-Open No. 2006-333595 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] An object of the present invention is to provide a semiconductor device with improved overvoltage resistance between a power supply terminal and a ground terminal and improved overvoltage resistance between a predetermined terminal and the power supply terminal. [[Means for Solving the Problem]]

[0006] To solve the above problems, a semiconductor device is provided. The semiconductor device includes a terminal section including a first terminal, a second terminal, and a third terminal, and a clamping circuit that, when a first overvoltage is applied externally between the first terminal and the third terminal, allows a first overcurrent to flow from the first terminal to the third terminal to clamp the first overvoltage, and when a second overvoltage is applied externally between the second terminal and the first terminal, allows a second overcurrent to flow from the second terminal to the first terminal to clamp the second overvoltage. [Effects of the Invention]

[0007] One aspect of this design makes it possible to increase the overvoltage withstand capability between the power terminal and the ground terminal, and between a predetermined terminal and the power terminal. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram illustrating an example of a semiconductor device. [Figure 2] This is a diagram showing the configuration of a semiconductor device in the reference example. [Figure 3] This diagram illustrates an example of ESD protection when an ESD surge voltage is applied to a signal terminal with respect to GND. [Figure 4] This diagram illustrates the state when an ESD surge voltage is applied to a signal terminal relative to the power supply voltage. [Figure 5] This figure shows an example of a cross-sectional structure of an NPN transistor. [Figure 6] This figure shows an example of the configuration of the semiconductor device in this embodiment. [Figure 7] This is a diagram illustrating an example of the operation of the first ESD protection. [Figure 8] This is a diagram illustrating an example of the operation of the second ESD protection. [Modes for carrying out the invention]

[0009] This embodiment will now be described with reference to the drawings. Note that elements having substantially the same configuration in this specification and the drawings may be denoted by the same reference numerals, thus omitting redundant explanations.

[0010] Figure 1 is a diagram illustrating an example of a semiconductor device. The semiconductor device 1 comprises a terminal section 1a and a clamp circuit 1b. The terminal section 1a includes terminals T1 (first terminal), T2 (second terminal), and T3 (third terminal). A first circuit 1c1 is connected to terminals T1 and T3, and a second circuit 1c2 is connected to terminals T1 and T2.

[0011] [Step S1] An overvoltage Vsg1 (first overvoltage) is applied externally between terminals T1 and T3. The overvoltage Vsg1 is an ESD surge voltage that occurs, for example, when a human body touches a metal terminal.

[0012] [Step S2] When an overvoltage Vsg1 is applied, the clamp circuit 1b clamps the overvoltage Vsg1 by allowing an overcurrent Isg1 (first overcurrent) associated with the application of the overvoltage Vsg1 to flow from terminal T1 to terminal T3, thereby protecting the first circuit 1c1 from the overvoltage Vsg1.

[0013] [Step S3] An overvoltage Vsg2 (second overvoltage) is applied externally between terminals T2 and T1. The overvoltage Vsg2 is an ESD surge voltage that occurs, for example, when a human body touches a metal terminal.

[0014] [Step S4] When an overvoltage Vsg2 is applied, the clamp circuit 1b clamps the overvoltage Vsg2 by allowing an overcurrent Isg2 (second overcurrent) associated with the application of the overvoltage Vsg2 to flow from terminal T2 to terminal T1, thereby protecting the second circuit 1c2 from the overvoltage Vsg2.

[0015] As described above, the semiconductor device 1 is configured such that one clamp circuit 1b performs overvoltage protection control in response to both the overvoltage Vsg1 applied between the terminal T1 and the terminal T3 and the overvoltage Vsg2 applied between the terminal T2 and the terminal T1.

[0016] Accordingly, for example, when the terminal T1 is a power supply terminal, the terminal T2 is a signal terminal, and the terminal T3 is a ground terminal, it is possible to improve the overvoltage withstand capability not only for an overvoltage applied to the power supply terminal with reference to GND of the ground terminal, but also for an overvoltage applied to the signal terminal with reference to VCC of the power supply terminal.

[0017] Next, overvoltage protection of the semiconductor device according to a reference example will be described with reference to FIGS. 2 to 5. Hereinafter, it is assumed that ESD occurs at a terminal, and the overvoltage is referred to as an ESD surge voltage, and the overcurrent is referred to as an ESD surge current. Further, the terminal T1 is a power supply terminal T1 to which a power supply voltage is supplied, the terminal T2 is a signal terminal T2 through which signal communication is performed, and the terminal T3 is a ground terminal T3 connected to GND.

[0018] FIG. 2 is a diagram showing the configuration of the semiconductor device according to the reference example. The semiconductor device 100 of the reference example includes a power supply terminal T1, a signal terminal T2, and a ground terminal T3. The semiconductor device 100 further includes an internal power supply circuit 10, an element circuit 20, a PMOS transistor m1 that is a P-type Metal-Oxide-Semiconductor (MOS) transistor, an NMOS transistor m2 that is an N-type MOS transistor, resistors R11 and R12, and a Zener diode Z0.

[0019] The internal power supply circuit 10 includes transistors Tr1 and Tr2. NPN transistors are used as the transistors Tr1 and Tr2. The transistors Tr1 and Tr2 are Darlington-connected by connecting their collectors to each other and connecting the emitter of the transistor Tr2 to the base of the transistor Tr1. The Darlington-connected transistors Tr1 and Tr2 operate as a single transistor with a high current amplification factor.

[0020] The collectors of transistors Tr1 and Tr2 are connected to the power supply terminal T1. When a predetermined base current is input to the base of transistor Tr2, transistors Tr1 and Tr2 turn on, and the internal power supply voltage VDD is output from the emitter of transistor Tr1.

[0021] The power supply terminal of the element circuit 20 is connected to the emitter of transistor Tr1, and the internal power supply voltage VDD generated by the internal power supply circuit 10 is supplied to the element circuit 20. The ground terminal of the element circuit 20 is connected to the ground terminal T3.

[0022] Furthermore, the emitter of transistor Tr1 is connected to the source of PMOS transistor m1, the back gate of PMOS transistor m1, and the cathode of body diode D0, which is connected in antiparallel to PMOS transistor m1.

[0023] The drain of PMOS transistor m1 is connected to one end of resistor R11 and the anode of body diode D0. The other end of resistor R11 is connected to one end of resistor R12, the cathode of Zener diode Z0, and the signal terminal T2.

[0024] The other end of resistor R12 is connected to the drain of NMOS transistor m2. The source of NMOS transistor m2 is connected to the back gate of NMOS transistor m2, the anode of Zener diode Z0, and the ground terminal T3. The gate of PMOS transistor m1 is connected to the first output terminal of element circuit 20, and the gate of NMOS transistor m2 is connected to the second output terminal of element circuit 20.

[0025] The element circuit 20 includes a circuit for detecting the operating state of the semiconductor device 100. The element circuit 20 outputs a first detection signal from its first output terminal in the first operating state to switch-control the PMOS transistor m1 and output a voltage level indicating the first operating state from the signal terminal T2. The element circuit 20 also outputs a second detection signal from its second output terminal in the second operating state to switch-control the NMOS transistor m2 and output a voltage level indicating the second operating state from the signal terminal T2.

[0026] On the other hand, the Zener diode Z0 functions as an ESD protection diode that ensures ESD withstand capability between the signal terminal T2 and the ground terminal T3 when an ESD surge voltage is applied to the signal terminal T2 with respect to GND, thereby providing ESD protection. The clamp voltage of the Zener diode Z0 is denoted as the clamp voltage Vc.

[0027] Figure 3 illustrates an example of ESD protection when an ESD surge voltage is applied to a signal terminal with respect to GND. When the semiconductor device 100 is operating normally, the Zener diode Z0 is in the off state.

[0028] On the other hand, suppose an ESD surge voltage greater than or equal to the clamp voltage Vc is applied to the signal terminal T2 with respect to GND (in Figure 3, this state is shown by connecting the positive side of the ESD source 4 to the signal terminal T2 and the negative side of the ESD source 4 to the ground terminal T3).

[0029] In this case, the Zener diode Z0 breaks down and turns on, allowing the ESD surge current Isg11 to flow to the GND side of the ground terminal T3, clamping the ESD surge voltage. This prevents the ESD surge voltage from being applied to the circuit connected to the signal terminal T2 and the ground terminal T3 (the NMOS transistor m2 in the example in Figure 3), thus providing protection from the ESD surge voltage.

[0030] Figure 4 illustrates the state when an ESD surge voltage is applied to a signal terminal with respect to the power supply voltage. Assume that the ESD surge voltage is applied to signal terminal T2 with respect to VCC (in Figure 4, this state is shown by connecting the positive side of ESD source 4 to signal terminal T2 and the negative side of ESD source 4 to power supply terminal T1).

[0031] In this case, the ESD surge current Isg12 generated by the ESD surge voltage flows from the anode of the body diode D0 through the cathode to the emitter of transistor Tr1. If the ESD surge current Isg12 flows to the emitter of transistor Tr1, the base-emitter junction of transistor Tr1 may be destroyed.

[0032] Figure 5 shows an example of the cross-sectional structure of an NPN transistor. In an NPN transistor, a P-type base layer 202 is formed on the surface layer of an N-type substrate 201, and a P+-type base layer 204 and an N+-type emitter layer 205 are formed on the surface layer of the P-type base layer 202. An N+-type collector layer 203 is also formed on the surface layer of the N-type substrate 201. An oxide film 208 is formed on the surface of the N-type substrate 201. An emitter electrode E is formed on the surface of the N+-type emitter layer 205, a base electrode B is formed on the surface of the P+-type base layer 204, and a collector electrode C is formed on the surface of the N+-type collector layer 203.

[0033] In such an NPN transistor structure, when an ESD surge current Isg12 flows toward the emitter electrode E of transistor Tr1, pulses of abnormal ESD energy penetrate from the emitter electrode E of transistor Tr1 through the N+-type emitter layer 205, the P-type base layer 202, and the P+-type base layer 204 toward the base electrode B. This can potentially cause degradation or destruction of the base-emitter junction of transistor Tr1.

[0034] In previous ESD countermeasures, ESD resistance was only guaranteed against GND. Therefore, at the external terminals of semiconductor devices where ESD may occur, measures are taken to meet ESD resistance requirements, such as incorporating protective elements into the ground terminal or increasing the resistance of the semiconductor device itself (e.g., by increasing the wafer size).

[0035] For example, in the reference semiconductor device 100, as shown in Figure 3, a Zener diode Z0 is inserted between the signal terminal T2 and the ground terminal T3. This protects the circuit placed between the signal terminal T2 and the ground terminal T3 from the ESD surge voltage when the ESD surge voltage is applied to the signal terminal T2 with respect to GND.

[0036] However, while such a semiconductor device 100 has a configuration for ESD protection based on GND, it does not have a configuration for ESD protection based on VCC. Therefore, when an ESD surge voltage is applied to the signal terminal T2 based on VCC, it is difficult to protect the circuit placed between the power supply terminal T1 and the signal terminal T2 (transistor Tr1 in the example of Figure 4) from the ESD surge voltage.

[0037] This embodiment was made in view of these points, and enables not only ESD protection that enhances the ESD withstand capability between the signal terminal and the ground terminal, but also ESD protection that further enhances the ESD withstand capability between the signal terminal and the power terminal.

[0038] Next, the semiconductor device of this embodiment will be described in detail. The explanation will use the case where it is applied to an LVIC (Low Voltage IC) of an IPM (Intelligent Power Module) as an example.

[0039] Figure 6 shows an example of the configuration of the semiconductor device of this embodiment. The semiconductor device 1-1 has a power terminal T1 to which the power supply voltage VCCL is applied, a signal terminal T2 to which a signal indicating the device status is output, and a ground terminal T3 connected to GND. The ground terminal T3 corresponds to terminal COM which is connected to a common GND for the upper arm control circuit and the lower arm control circuit of the IPM.

[0040] The semiconductor device 1-1 includes an internal power supply circuit 10a, an element circuit 20a, a PMOS transistor m1, an NMOS transistor m2, resistors R11 and R12, a Zener diode Z0, and a clamp circuit 30.

[0041] The internal power supply circuit 10a includes a constant current circuit 11 and a transistor circuit 12, the transistor circuit 12 including the transistors Tr1 and Tr2 described above. Transistors Tr1 and Tr2 are connected in a Darlington configuration as shown in Figure 2, and the output terminal of the constant current circuit 11 is connected to the base of transistor Tr2.

[0042] The constant current output from the output terminal of the constant current circuit 11 is input to the base of transistor Tr2, which turns on transistors Tr1 and Tr2, and the internal power supply voltage VDD1 is output from the emitter of transistor Tr1.

[0043] The internal power supply terminal Tv is connected to the emitter of transistor Tr1, to which the internal power supply voltage VDD1 is applied (the internal power supply terminal Tv and the wiring connected to it correspond to a predetermined wiring section that conducts to the signal terminal T2 when the ESD surge voltage Vsg2 occurs).

[0044] The element circuit 20a includes a temperature detection circuit 21 and an undervoltage protection circuit 22, both of which are driven by an internal power supply voltage VDD1. The temperature detection circuit 21 detects the temperature of a switching element (not shown) provided in the semiconductor device 1-1 during operation and outputs a temperature detection signal with a voltage corresponding to the temperature to the gate of a PMOS transistor m1. The PMOS transistor m1 supplies a current corresponding to the voltage of the temperature detection signal output from the temperature detection circuit 21 and outputs a voltage corresponding to the temperature from the signal terminal T2.

[0045] The undervoltage protection circuit 22 detects the voltage level of the power supply voltage VCCL or the internal power supply voltage VDD1, and outputs an H-level undervoltage detection signal to the gate of the NMOS transistor m2 when the power supply voltage VCCL or the internal power supply voltage VDD1 falls below a predetermined voltage.

[0046] The NMOS transistor m2 turns on when a high-level low-voltage detection signal is output from the low-voltage protection circuit 22, and cuts off the output voltage from the signal terminal T2 (when a low-voltage abnormality occurs, the signal terminal T2 becomes low).

[0047] The clamp circuit 30 has the same function as the clamp circuit 1b shown in Figure 1 and includes Zener diodes Z1 to Z5 and a switch circuit 31. The switch circuit 31 includes a transistor Tr10, resistors R1 and R2. An NPN transistor is used for transistor Tr10.

[0048] Transistor Tr10 turns on when an ESD surge voltage (first overvoltage) is applied to the power supply terminal T1 with respect to GND. The series-stage Zener diodes Z1 to Z5 are connected in parallel to transistor Tr10. Note that multiple Zener diodes can be connected in series in n stages, and in the example in Figure 6, there are 5 stages. n is a natural number (usually n is a natural number of 3 or greater). Resistor R1 is the base resistor of transistor Tr10, and resistor R2 is a pull-down resistor that pulls down the base potential of transistor Tr10 to the ground voltage.

[0049] In the connection of the components of the clamp circuit 30, the collector (high potential terminal) of transistor Tr10 is connected to the cathode of Zener diode Z1 (the first Zener diode) and the power supply terminal T1. The base (control terminal) of transistor Tr10 is electrically connected to the cathode of Zener diode Z5. The base of transistor Tr10 is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of resistor R2, the anode of Zener diode Z4, and the cathode of Zener diode Z5. The emitter (low potential terminal) of transistor Tr10 is connected to the other end of resistor R2, the anode of Zener diode Z5 (the nth Zener diode), and the ground terminal T3.

[0050] The anode of Zener diode Z1 is connected to the cathode of Zener diode Z2, and the anode of Zener diode Z2 is connected to the cathode of Zener diode Z3. The anode of Zener diode Z3 is connected to the cathode of Zener diode Z4, the internal power supply terminal Tv, the emitter of transistor Tr1, the power supply terminal of element circuit 20a, the source of PMOS transistor m1, and the cathode of body diode D0.

[0051] Here, the predetermined connection position a (first connection position) of the series connection of multiple Zener diodes is, under normal operation of the device, pulled down to the ground terminal T3, and when a first overvoltage is applied, it is the position having a first potential (potential relative to GND of the ground terminal T3) determined by the Zener voltage (breakdown voltage) of a predetermined number of Zener diodes and the resistance value of resistor R2.

[0052] In the example shown in Figure 6, the Zener voltages in a predetermined number of Zener diodes when the first overvoltage is applied correspond to the Zener voltage of Zener diode Z5. When the first overvoltage is applied, the first potential, determined by the Zener voltage of Zener diode Z5 and the resistance value of resistor R2, becomes the potential at connection position a. At this time, by adjusting the resistance value of resistor R2, the first potential can be set to the Zener voltage value of Zener diode Z5. For example, the resistance value of resistor R2 is set to 100kΩ.

[0053] Furthermore, during normal operation of the device, the potential of the internal power terminal Tv is assumed to be the second potential, relative to the GND of the grounding terminal T3. During normal operation of the device, a position that is higher than the second potential is designated as connection position b (second connection position), and the internal power terminal Tv is set to be connected to this connection position b. Therefore, if an ESD surge voltage (second overvoltage) occurs at the signal terminal T2 relative to the power terminal T1, the signal terminal T2 is connected to connection position b via the body diode D0 and the internal power wiring section.

[0054] For example, suppose that during normal operation of the device, the second potential at connection point b is 7.4V, and the second potential at the internal power terminal Tv is 5V relative to the GND of the grounding terminal T3. In this case, since the potential at connection point b is greater than that of the internal power terminal Tv, connecting the internal power terminal Tv to connection point b will maintain the potential of the internal power terminal Tv at 5V during normal operation of the device.

[0055] On the other hand, if connection position b is placed between the anode of Zener diode Z4 and the cathode of Zener diode Z5 (the same position as connection position a), then during normal operation of the device, connection position a is pulled down to the ground terminal T3, and the 5V potential of the internal power supply terminal Tv will no longer be maintained.

[0056] Therefore, any position other than connection position a is designated as connection position b. That is, if connection position b is set to be the space between the anode of Zener diode Z1 and the cathode of Zener diode Z2, the space between the anode of Zener diode Z2 and the cathode of Zener diode Z3, or the space between the anode of Zener diode Z3 and the cathode of Zener diode Z4, then the potential of 5V at the internal power supply terminal Tv will be maintained during normal operation of the device. Furthermore, connection position b is determined according to the ESD withstand capability to be guaranteed between the power supply terminal T1 and the signal terminal T2. In Figure 6, as an example, connection position b is set to be the space between the anode of Zener diode Z3 and the cathode of Zener diode Z4.

[0057] Based on the above, when a first overvoltage occurs, the Zener diodes Z1 to Z5 of clamp circuit 1b conduct in the reverse direction to the n-stage Zener diodes, and when a second overvoltage occurs, they conduct in the forward direction to the m-stage (where m is a natural number smaller than n) Zener diodes.

[0058] Next, the ESD protection operation of the clamp circuit 30 provided in semiconductor device 1-1 will be explained using Figures 7 and 8. Note that the ESD withstand voltage is guaranteed to be 2000V or higher using the HBM (Human Body Model), and the clamp circuit 30 provides ESD protection that meets this requirement.

[0059] The clamp circuit 30 has both functions: a first ESD protection operation when an ESD surge voltage Vsg1 occurs at the power supply terminal T1 with respect to GND, and a second ESD protection operation when an ESD surge voltage Vsg2 occurs at the signal terminal T2 with respect to the power supply voltage.

[0060] Figure 7 is a diagram illustrating an example of the operation of the first ESD protection. When an ESD surge voltage Vsg1 is generated at the power terminal T1 with respect to GND (in Figure 7, this state is shown by the positive side of the ESD source 4 being connected to the power terminal T1 and the negative side of the ESD source 4 being connected to the ground terminal T3), the clamp circuit 30 performs the first ESD protection for the circuit placed between the ground terminal T3 and the power terminal T1.

[0061] In the first ESD protection operation, when an ESD surge voltage Vsg1 occurs at the power supply terminal T1 with respect to the GND of the ground terminal T3, the Zener diodes Z1 to Z5 break down and conduct in the reverse direction.

[0062] At this time, the voltage (on-level) applied to the connection point between the anode of Zener diode Z4 and the cathode of Zener diode Z5 is applied to one end of the base resistor R1, causing a base current to flow through transistor Tr10 and turning it on.

[0063] When transistor Tr10 is turned on, a collector current corresponding to the ESD surge current Isg1 flows from the collector to the emitter. Furthermore, if the DC current amplification factor of transistor Tr10 is hfe, the collector current will be tens to hundreds of times the base current, depending on the DC current amplification factor hfe. Therefore, when an ESD surge voltage Vsg1 is generated at the power supply terminal T1, transistor Tr10 turns on, and the ESD surge current Isg1 associated with the generation of the ESD surge voltage Vsg1 is drawn out from the power supply terminal T1.

[0064] This configuration clamps the ESD surge voltage Vsg1 applied to the power terminal T1, relative to GND, to a predetermined voltage. This clamping protects the circuit connected to the power terminal T1 and the ground terminal T3 from the ESD surge voltage Vsg1. In the example in Figure 7, the constant current circuit 11 (corresponding to the first circuit 1c1 in Figure 1) connected to the power terminal T1 and the ground terminal T3 is protected from the ESD surge voltage Vsg1.

[0065] Transistor Tr10 functions as a switch that diverts the ESD surge voltage Vsg1 to the power supply terminal T1 to GND. However, until the Zener diodes Z1 to Z5 exceed the clamp voltage, it remains in the off state due to resistor R2, which has a predetermined resistance value. Therefore, no current flows from the power supply terminal T1 to GND through transistor Tr10. Resistor R2 also has the role of removing any residual charge from the base of transistor Tr10, for example, immediately after restarting the device, as residual charge in the base of transistor Tr10 can cause it to malfunction.

[0066] Figure 8 is a diagram illustrating an example of the operation of the second ESD protection. The clamp circuit 30 performs a second ESD protection for the circuit placed between the power supply terminal T1 and the signal terminal T2 when an ESD surge voltage Vsg2 occurs at the signal terminal T2 with respect to the power supply voltage VCCL (in Figure 8, this state is shown by the positive side of the ESD source 4 being connected to the signal terminal T2 and the negative side of the ESD source 4 being connected to the power supply terminal T1).

[0067] In the operation of the second ESD protection, when an ESD surge voltage Vsg2 is generated at the signal terminal T2 with reference to the power supply voltage VCCL at the power supply terminal T1, the ESD surge current Isg2 flowing from the signal terminal T2 through the body diode D0 flows in the forward direction through the Zener diodes Z3, Z2, and Z1 located between the power supply terminal T1 and connection point b. In other words, the ESD surge current Isg2 associated with the generation of the ESD surge voltage Vsg2 flows from the signal terminal T2 towards the power supply terminal T1.

[0068] This configuration clamps the ESD surge voltage Vsg2 applied to the signal terminal T2 to a predetermined voltage, relative to VCCL. This clamping protects the circuit connected to the power terminal T1 and the signal terminal T2 from the ESD surge voltage Vsg2. In the example in Figure 8, transistor Tr1 (corresponding to the second circuit 1c2 in Figure 1), which is connected to the power terminal T1 and the signal terminal T2, is protected from the ESD surge voltage Vsg2.

[0069] Although embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Furthermore, various modifications or improvements can be made to the above embodiments. Moreover, the technical scope of the present invention may also include modified or improved forms and their equivalents without departing from the spirit of the invention. [Explanation of symbols]

[0070] 1 Semiconductor device 1a Terminal section 1b Clamp circuit 1c1 First circuit 1c2 Second circuit T1 First terminal T2 Second terminal T3 Third terminal Vsg1 First overvoltage Vsg2 Second Overvoltage Isg1 First overcurrent ISG2 Second Overcurrent

Claims

1. A terminal section including a first terminal, a second terminal, and a third terminal, A clamping circuit that, when a first overvoltage is applied externally between the first terminal and the third terminal, causes a first overcurrent to flow from the first terminal towards the third terminal to clamp the first overvoltage, and when a second overvoltage is applied externally between the second terminal and the first terminal, causes a second overcurrent to flow from the second terminal towards the first terminal to clamp the second overvoltage, Semiconductor device.

2. The system comprises a first circuit connected to the first terminal and the third terminal, and a second circuit connected to the first terminal and the second terminal. The clamping circuit is The first overvoltage is clamped, and the potential of the first terminal is short-circuited to the potential of the third terminal to protect the first circuit from the first overvoltage. The second overvoltage is clamped, and the potential of the second terminal is short-circuited to the potential of the first terminal to protect the second circuit from the second overvoltage. The semiconductor device according to claim 1.

3. The clamping circuit is It comprises multiple Zener diodes connected in series in an n-stage (where n is a natural number) configuration. The semiconductor device according to claim 2.

4. The second terminal, when the second overvoltage is applied, becomes electrically connected to a predetermined wiring section inside the device. Of the positions of the series connection of the plurality of Zener diodes, When the device is in normal operation and the predetermined wiring section has a second potential, the predetermined wiring section is connected to a connection point that is higher than the second potential. The semiconductor device according to claim 3.

5. The second overvoltage is clamped when the second overcurrent flows in the forward direction through a predetermined Zener diode located between the first terminal and the connection position. The semiconductor device according to claim 4.

6. The clamping circuit is The first overvoltage is clamped when the first overcurrent flows in the reverse direction through the n-stage Zener diodes. The semiconductor device according to claim 5.

7. The plurality of Zener diodes are connected in parallel and include a switch circuit that includes a transistor, The high-potential terminal of the transistor is connected to the cathode and the first terminal of the first-stage first Zener diode. The low-potential terminal of the transistor is connected to the anode of the nth Zener diode of the nth stage and the third terminal. The control terminal of the transistor is connected to the third terminal via a resistor. The semiconductor device according to claim 3.

8. The transistor switches at an on-level determined when the plurality of Zener diodes conduct in the reverse direction due to the first overvoltage, thereby drawing the first overcurrent from the first terminal. The semiconductor device according to claim 7.

9. The control terminal of the transistor is electrically connected to the cathode of the nth Zener diode of the nth stage. The semiconductor device according to claim 8.

10. The second terminal, when the second overvoltage is applied, becomes electrically connected to a predetermined wiring section inside the device. Of the positions of the series connection of the plurality of Zener diodes, When the device is in normal operation and the predetermined wiring section has a second potential, the predetermined wiring section is connected to a connection point that is higher than the second potential. The semiconductor device according to claim 7.

11. The second overvoltage is clamped when the second overcurrent flows in the forward direction through a predetermined Zener diode located between the first terminal and the connection position. The semiconductor device according to claim 10.

12. The clamping circuit is The first overvoltage is clamped when the first overcurrent flows in the reverse direction through the n-stage Zener diodes. The semiconductor device according to claim 11.

13. The semiconductor device according to claim 1, wherein the first terminal is a power terminal, the second terminal is a signal terminal, and the third terminal is a ground terminal.

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