Semiconductor and display devices

Abstract

This suppresses the increase in contact resistance between the semiconductor part and the first electrode. [Solution] The semiconductor device 21 comprises a first insulating film 30 containing at least silicon and nitrogen, a second insulating film 31 disposed on the upper side of the first insulating film 30 and containing at least silicon and oxygen, a semiconductor portion 27D consisting of a part of a semiconductor film F1 disposed on the upper side of the second insulating film 31, a third insulating film 33 disposed on the upper side of the semiconductor film F1, and a first electrode 27C consisting of a part of a first transparent electrode film F2 disposed on the upper side of the third insulating film 33, with at least a part of it overlapping with a part of the semiconductor portion 27D. A first contact hole CH1 connecting the semiconductor portion 27D and the first electrode 27C is provided in the third insulating film 33 at a position that overlaps with at least a part of the semiconductor portion 27D and the first electrode 27C, and an opening 31A is provided in the second insulating film 31 at a position that overlaps with at least a part of the first contact hole CH1.

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a semiconductor device and a display device in which an increase in contact resistance between a semiconductor portion and a first electrode is suppressed.

Background Art

[0002] Conventionally, the one described in Patent Document 1 below is known as an example of a semiconductor device. Patent Document 1 describes an active matrix substrate used for a liquid crystal panel as a semiconductor device. The active matrix substrate described in Patent Document 1 includes: a substrate; a pixel TFT supported by the substrate and provided corresponding to each of a plurality of pixel regions, the pixel TFT having an oxide semiconductor layer; an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT; and an inorganic insulating layer disposed on the organic insulating layer in contact with an upper surface of the organic insulating layer, wherein a plurality of two-layer hole structures are provided in the organic insulating layer and the inorganic insulating layer, each of the two-layer hole structures includes a through hole provided in the inorganic insulating layer, and a bottomed hole provided in the organic insulating layer and located below the through hole, and when viewed from a normal direction of the substrate, the through hole is located inside an outer edge of the bottomed hole.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] In the active matrix substrate described in Patent Document 1 mentioned above, the pixel electrodes include a first electrode layer (lower electrode layer), a second electrode layer (intermediate electrode layer), and a third electrode layer (upper electrode layer), each formed from a transparent conductive material. The first, second, and third electrode layers are electrically connected to each other. Of these, the first electrode layer functions as a connecting electrode that electrically connects the drain contact region of the oxide semiconductor layer to the second electrode layer. However, the transparent electrode material constituting the first electrode layer contains oxygen. Therefore, if heat treatment is performed after the formation of the first electrode layer during the manufacturing process, there is a risk that oxygen will diffuse from the first electrode layer into the drain contact region of the oxide semiconductor layer. When oxygen diffuses into the drain contact region, the resistance of the drain contact region increases, and as a result, there is a risk that the contact resistance between the drain contact region and the first electrode layer will increase.

[0005] The technology described herein was developed based on the circumstances described above, and aims to suppress the increase in contact resistance between the semiconductor portion and the first electrode. [Means for solving the problem]

[0006] (1) A semiconductor device relating to the technology described herein comprises: a first insulating film containing at least silicon and nitrogen; a second insulating film disposed on the upper side of the first insulating film and containing at least silicon and oxygen; a semiconductor portion consisting of a part of a semiconductor film disposed on the upper side of the second insulating film; a third insulating film disposed on the upper side of the semiconductor film; and a first electrode consisting of a part of a first transparent electrode film disposed on the upper side of the third insulating film, with at least a part of it overlapping with a part of the semiconductor portion, wherein a first contact hole connecting the semiconductor portion and the first electrode is provided in the third insulating film at a position overlapping with at least a part of the semiconductor portion and the first electrode, and an opening is provided in the second insulating film at a position overlapping with at least a part of the first contact hole.

[0007] (2) In addition to (1) above, the semiconductor device may also be provided with a recess in the first insulating film at a position that overlaps with the opening.

[0008] (3) In addition to (1) or (2) above, the semiconductor device may also have the opening positioned so as to overlap both the semiconductor portion and the first electrode.

[0009] (4) In addition to (1) or (2) above, the semiconductor device may also have a portion of the first electrode that does not overlap with the semiconductor portion, a first contact hole that overlaps with the first electrode but does not overlap with the semiconductor portion, and an opening that overlaps with the first electrode but does not overlap with the semiconductor portion.

[0010] (5) In addition, the semiconductor device comprises, in addition to any of (1) to (4) above, a fourth insulating film disposed on the upper side of the semiconductor film and below the third insulating film, and positioned to overlap with a part of the semiconductor portion; a second electrode consisting of a part of the first metal film disposed on the upper side of the fourth insulating film and below the third insulating film, and positioned to overlap with the fourth insulating film and a part of the semiconductor portion; a third electrode consisting of a part of the second metal film disposed on the upper side of the third insulating film and below the first transparent electrode film, and positioned to overlap with a part of the semiconductor portion; and a fifth insulating film disposed on the upper side of the second metal film and below the first transparent electrode film. The third insulating film comprises a sixth insulating film disposed on the upper side of the first transparent electrode film, and a fourth electrode which is made of a part of the second transparent electrode film disposed on the upper side of the sixth insulating film, with a part of it overlapping with the first electrode. A second contact hole connecting the semiconductor portion and the third electrode is provided in the third insulating film at a position where it overlaps with both the semiconductor portion and the third electrode, and a third contact hole CH3 connecting the first electrode and the fourth electrode is provided in the sixth insulating film at a position where it overlaps with both the first electrode and the fourth electrode. The first contact hole may be provided in communication with the third insulating film and the fifth insulating film.

[0011] (6) A display device relating to the technology described herein comprises a semiconductor device described in any of (1) to (5) above, and a counter substrate disposed opposite to the semiconductor device. [Effects of the Invention]

[0012] According to the technology described herein, it is possible to suppress an increase in the contact resistance between the semiconductor portion and the first electrode. [Brief explanation of the drawing]

[0013] [Figure 1] A schematic perspective view showing the head-mounted display according to Embodiment 1 in a state where the user is wearing it on their head. [Figure 2] A schematic side view showing the optical relationship between the liquid crystal display device and lens portion of the head-mounted display according to Embodiment 1, and the user's eyeball. [Figure 3] Schematic plan view of the liquid crystal panel and flexible substrate included in the liquid crystal display device according to Embodiment 1. [Figure 4] schematic cross-sectional view of a liquid crystal panel according to Embodiment 1 [Figure 5] Plan view showing the pixel arrangement in the display area of ​​the array substrate provided in the liquid crystal panel according to Embodiment 1. [Figure 6] Cross-sectional view of the array substrate according to Embodiment 1, shown along line vi-vi in ​​Figure 5. [Figure 7] A cross-sectional view similar to Figure 6, showing the state before the first insulating film and the second insulating film are etched via the first photoresist film in the first step included in the array substrate manufacturing process according to Embodiment 1. [Figure 8] A cross-sectional view similar to Figure 6, showing the state in which the first insulating film and the second insulating film are etched via the first photoresist film in the first step included in the array substrate manufacturing process according to Embodiment 1. [Figure 9] A cross-sectional view similar to Figure 6, showing the state before the semiconductor film is etched via the second photoresist film in the second step included in the array substrate manufacturing process according to Embodiment 1. [Figure 10]Cross-sectional view similar to FIG. 6 showing a state where a semiconductor film is etched through a second photoresist film in the second step included in the array substrate manufacturing step according to Embodiment 1 [Figure 11] Cross-sectional view similar to FIG. 6 showing a state before a first interlayer insulating film and a second interlayer insulating film are etched through a third photoresist film in the seventh step included in the array substrate manufacturing step according to Embodiment 1 [Figure 12] Cross-sectional view similar to FIG. 6 showing a state where a first interlayer insulating film and a second interlayer insulating film are etched through a third photoresist film in the seventh step included in the array substrate manufacturing step according to Embodiment 1 [Figure 13] Cross-sectional view similar to FIG. 6 showing a state before a first transparent electrode film is etched through a fourth photoresist film in the eighth step included in the array substrate manufacturing step according to Embodiment 1 [Figure 14] Cross-sectional view similar to FIG. 6 showing a state where a first transparent electrode film is etched through a fourth photoresist film in the eighth step included in the array substrate manufacturing step according to Embodiment 1 [Figure 15] Plan view showing a pixel arrangement in a display region of an array substrate according to Embodiment 2 [Figure 16] Cross-sectional view along line xvi-xvi of FIG. 15 of the array substrate according to Embodiment 2 [Figure 17] Cross-sectional view similar to FIG. 16 showing a state before a first insulating film, a second insulating film, a first interlayer insulating film and a second interlayer insulating film are etched through a third photoresist film in the seventh step included in the array substrate manufacturing step according to Embodiment 2 [Figure 18] Cross-sectional view similar to FIG. 16 showing a state where a first insulating film, a second insulating film, a first interlayer insulating film and a second interlayer insulating film are etched through a third photoresist film in the seventh step included in the array substrate manufacturing step according to Embodiment 2 [Figure 19] Cross-sectional view similar to FIG. 16 showing a state before a first transparent electrode film is etched through a fourth photoresist film in the eighth step included in the array substrate manufacturing step according to Embodiment 2 [Figure 20]A cross-sectional view similar to Figure 16, showing the state in which the first transparent electrode film is etched via the fourth photoresist film in the eighth step included in the array substrate manufacturing process according to Embodiment 2. [Modes for carrying out the invention]

[0014] <Embodiment 1> Embodiment 1 will be described with reference to Figures 1 to 14. In this embodiment, a goggle-type head-mounted display (HMD) 10 and a liquid crystal display device (display device) 10 used therein are shown as examples. Note that parts of each drawing show the X, Y, and Z axes, and each axis is drawn so as to be in the direction shown in each drawing.

[0015] Figure 1 illustrates the appearance of the goggle-type head-mounted display 10HMD. As shown in Figure 1, the head-mounted display 10HMD includes a head-mounted device 10HMDa that is worn on the user's head 10HD. The head-mounted device 10HMDa surrounds both of the user's eyes.

[0016] The configuration of the head-mounted device 10HMDa will be explained using Figure 2. As shown in Figure 2, the head-mounted device 10HMDa incorporates at least a liquid crystal display device 10 that displays an image, and a lens unit 10RE that focuses the image displayed on the liquid crystal display device 10 onto the user's eyeball 10EY. The liquid crystal display device 10 comprises at least a liquid crystal panel (display device) 11 and a backlight device (illumination device) 12 that irradiates the liquid crystal panel 11 with light. The main surface of the liquid crystal panel 11 on the side of the lens unit 10RE is the display surface 11DS that displays the image. The lens unit 10RE is positioned between the liquid crystal display device 10 and the user's eyeball 10EY. The lens unit 10RE imparts a refractive effect to the light. By adjusting the focal length of this lens unit 10RE, the user can perceive that the image formed on the retina 10EYb via the lens 10EYa of the eyeball 10EY is displayed on a virtual display 10VD that appears to exist at a distance L2 from the eyeball 10EY. This distance L2 is much larger than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. As a result, the user can view an enlarged virtual image displayed on a virtual display 10VD with a screen size (e.g., tens to hundreds of inches) that is much larger than the screen size of the liquid crystal display device 10 (e.g., 0.something inches to several inches).

[0017] Furthermore, the head-mounted device 10HMDa can be equipped with one liquid crystal display device 10, which can display both the right-eye image and the left-eye image. Alternatively, the head-mounted device 10HMDa can be equipped with two liquid crystal display devices 10, with one displaying the right-eye image and the other displaying the left-eye image. The head-mounted device 10HMDa may also be equipped with earphones or similar devices that are placed against the user's ears to emit sound.

[0018] The configuration of the liquid crystal panel 11 provided in the liquid crystal display device 10 will be explained using Figure 3 and other figures. The configuration of the backlight device 12 is as known, and includes, for example, a light source such as an LED and an optical component that converts light from the light source into planar light by applying an optical effect. As shown in Figure 3, the liquid crystal panel 11 has a rectangular shape overall when viewed in plan. The central part of the liquid crystal panel 11 is the display area AA where an image is displayed. The outer peripheral part of the liquid crystal panel 11 that surrounds the display area AA on the screen is the non-display area NAA where no image is displayed. In Figure 3, the area enclosed by the dashed line is the display area AA. The liquid crystal panel 11 according to this embodiment is used in the head-mounted display 10 HMD described above, and therefore has extremely high resolution, with a pixel density of, for example, 1000 ppi or more.

[0019] As shown in Figure 3, the liquid crystal panel 11 is formed by bonding together a pair of substrates 20 and 21. Of the pair of substrates 20 and 21, the one placed on the front side is the opposing substrate (CF substrate) 20, and the one placed on the back side is the array substrate (semiconductor device, active matrix substrate) 21. Both the opposing substrate 20 and the array substrate 21 are made of glass substrates 20GS and 21GS that are almost transparent and have excellent light transmission, with various films laminated on the inner surface. The substrates 20GS and 21GS mainly contain, for example, alkali-free glass. The array substrate 21 is larger than the opposing substrate 20, and a part of it protrudes laterally from the opposing substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 has a structure in which a large number of wiring patterns are formed on a substrate that has insulating and flexible properties. One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control board (signal supply source). Various signals supplied from the control board are transmitted to the liquid crystal panel 11 via the flexible circuit board 13.

[0020] As shown in Figure 3, a circuit section (peripheral circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. The circuit section 14 includes a first circuit section 14A and a second circuit section 14B. The first circuit section 14A is arranged in pairs so as to sandwich the display area AA from both sides in the X-axis direction. The first circuit section 14A is provided in a strip-shaped area extending along the Y-axis direction. The first circuit section 14A is for supplying scanning signals to the gate wiring 25, which will be described later, and is monolithically provided on the array substrate 21. The first circuit section 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 14A includes a shift register circuit that outputs scanning signals at predetermined timings and a buffer circuit for amplifying scanning signals. The second circuit section 14B is located in a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit section 14B is provided in a strip-shaped area extending along the X-axis direction. The second circuit section 14B is for supplying image signals (data signals) to the source wiring 26, which will be described later, and is monolithically provided on the array substrate 21. The second circuit section 14B includes an SSD (Source Shared Driving) circuit, etc. The second circuit section 14B has a switch function, etc., for distributing the image signals supplied by the flexible substrate 13 to each source wiring 26. The second circuit section 14B may be arranged to superimpose on the opposing substrate 20, similar to the first circuit section 14A.

[0021] Next, the cross-sectional configuration of the liquid crystal panel 11 will be explained using Figure 4. As shown in Figure 4, the pair of substrates 20 and 21 are arranged opposite each other with a gap in the Z-axis direction, which is the normal direction to the main surfaces of the substrates 20 and 21. Between the pair of substrates 20 and 21, at least a liquid crystal layer 22 and a sealing portion 23 that seals the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change when an electric field is applied. The sealing portion 23 as a whole has a rectangular frame shape (endless ring) when viewed in plan, and surrounds the liquid crystal layer 22 all around in the non-display area (NAA). This sealing portion 23 maintains a gap (cell gap) equal to the thickness of the liquid crystal layer 22. Polarizing plates 24 are attached to the outer surfaces of the pair of substrates 20 and 21.

[0022] Figure 5 illustrates the pixel arrangement in the display area AA of the array substrate 21. As shown in Figure 5, multiple gate wirings (scanning wiring, first wiring) 25 and multiple source wirings (image wiring, second wiring) 26 are arranged on the inner surface of the display area AA of the array substrate 21. The gate wirings 25 extend along the X-axis direction (first direction) across the display area AA and are arranged in a row with gaps in the Y-axis direction. Scanning signals output from the first circuit section 14A described above are supplied to the multiple gate wirings 25. The source wirings 26 extend along the Y-axis direction (second direction intersecting the first direction) traversing the display area AA and intersect with the gate wirings 25. Multiple source wirings 26 are arranged with gaps in the X-axis direction. Therefore, the multiple gate wirings 25 and the multiple source wirings 26 form a grid when viewed in a plane. Image signals output from the second circuit section 14B described above are distributed to the source wirings 26.

[0023] As shown in Figure 5, a TFT (switching element) 27 and a pixel electrode (fourth electrode) 28 are provided near the intersection of the gate wiring 25 and the source wiring 26. Multiple TFTs 27 and pixel electrodes 28 are arranged regularly along the X-axis and Y-axis directions. The TFT 27 has at least a gate electrode (second electrode) 27A, a source electrode (third electrode) 27B, a drain electrode (first electrode) 27C, and a semiconductor portion 27D. The gate electrode 27A is formed from a part of the gate wiring 25. The source electrode 27B is formed from a part of the source wiring 26. The drain electrode 27C is connected to the pixel electrode 28. The semiconductor portion 27D is connected to the source electrode 27B and the drain electrode 27C, respectively, and is arranged superimposed on the gate electrode 27A with a gap in the Z-axis direction. The TFT 27 is driven based on a scanning signal supplied to the gate electrode 27A by the gate wiring 25. This scanning signal includes a potential higher than the threshold voltage of the TFT 27. As a result, a channel region is created in the semiconductor portion 27D, allowing charge to move between the source electrode 27B and the drain electrode 27C through the channel region. Therefore, the potential related to the image signal (data signal) supplied to the source electrode 27B by the source wiring 26 is supplied to the pixel drain electrode 27C via the semiconductor portion 27D. Consequently, the pixel electrode 28 is charged with the potential related to the image signal. The detailed configuration of the TFT 27 and the pixel electrode 28 will be explained later.

[0024] Next, the various films laminated on the glass substrate 21GS of the array substrate 21 will be explained in detail using Figure 6. As shown in Figure 6, the glass substrate 21GS of the array substrate 21 has at least the following films laminated in order from the bottom layer side (glass substrate 21GS side): a first insulating film 30, a second insulating film 31, a semiconductor film F1, a gate insulating film (fourth insulating film) 32, a first metal film, a first interlayer insulating film (third insulating film) 33, a second metal film, a second interlayer insulating film (fifth insulating film) 34, a first transparent electrode film F2, a third interlayer insulating film (sixth insulating film) 35, and a second transparent electrode film (see Figure 9 for semiconductor film F1 and Figure 13 for first transparent electrode film F2). The innermost layer (uppermost layer) of the array substrate 21 facing the liquid crystal layer 22 is provided with an alignment film (not shown) for aligning the liquid crystal molecules contained in the liquid crystal layer 22.

[0025] The first and second metal films are conductive by being single-layer films made of one type of metal material or multilayer films or alloys made of different types of metal materials. The first metal film constitutes the gate wiring 25 and gate electrode 27A, etc., as shown in Figure 6. The second metal film constitutes the source wiring 26 and source electrode 27B, etc. The first transparent electrode film F2 and the second transparent electrode film are made of transparent electrode materials such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) (see Figure 13). The first transparent electrode film F2 constitutes the drain electrode 27C, etc. The second transparent electrode film constitutes the pixel electrode 28, etc.

[0026] The semiconductor film F1 is made of an oxide semiconductor material (see Figure 9). More specifically, the semiconductor film F1 is made of an oxide thin film containing, for example, indium (In), gallium (Ga), and zinc (Zn), which are types of oxide semiconductors. The oxide thin film containing indium (In), gallium (Ga), and zinc (Zn) can be amorphous or crystalline. Compared to silicon semiconductor materials, the oxide semiconductor material of the semiconductor film F1 has a higher resistance value when no voltage is applied (off state). In addition, the oxide semiconductor material of the semiconductor film F1 has a higher electron mobility compared to amorphous silicon semiconductor materials.

[0027] As shown in Figure 6, the semiconductor film F1 constitutes the semiconductor portion 27D of the TFT 27. The semiconductor portion 27D, which is a part of the semiconductor film F1, is partially conductive (reduced resistance). Specifically, the portion of the semiconductor portion 27D that overlaps with the gate electrode 27A (gate wiring 25) is not conductive (non-conductive portion, non-low-resistance portion), while the portion that does not overlap with the gate electrode 27A is conductive (conductive portion, low-resistance portion). The non-conductive portion of the semiconductor portion 27D allows charge movement only under specific conditions (when a scanning signal is supplied to the gate electrode 27A). In other words, the non-conductive portion functions as a channel region under specific conditions. On the other hand, the non-conductive portion of the semiconductor portion 27D is always capable of charge movement and functions as a conductor.

[0028] The first insulating film 30, the second insulating film 31, the gate insulating film 32, the first interlayer insulating film 33, and the second interlayer insulating film 34 are all made of inorganic materials (inorganic resin materials). The first insulating film 30 is made of SiN x It consists of (silicon nitride) and contains at least silicon and nitrogen. In this embodiment, SiN x The first insulating film 30, which consists of the above, contains H2 (hydrogen). The reason the first insulating film 30 contains H2 is that the materials used in film formation include hydride gases such as SiH4 (silane gas), TEOS (Tetraethyl orthosilicate), and NH3. As shown in Figure 6, the first insulating film 30 is directly laminated on the glass substrate 21GS and is located on the lower layer side of the first metal film. The second insulating film 31 consists of SiO2 (silicon oxide) and contains at least silicon and oxygen. The second insulating film 31 is located on the upper layer side of the first insulating film 30 and on the lower layer side of the semiconductor film F1.

[0029] The gate insulating film 32 is made of SiO2 and contains at least silicon and oxygen. As shown in Figure 6, the gate insulating film 32 is located on the upper side of the semiconductor film F1 and on the lower side of the first metal film. The gate insulating film 32 is island-shaped when viewed in plan and is positioned to overlap with the semiconductor portion 27D of the TFT 27. The gate insulating film 32 is interposed between the semiconductor portion 27D and the gate electrode 27A to keep them in an insulating state. The first interlayer insulating film 33 is made of SiO2 and contains at least silicon and oxygen. The first interlayer insulating film 33 is located on the upper side of the first metal film and on the lower side of the second metal film. The first interlayer insulating film 33 is interposed between the gate wiring 25 and the source wiring 26 to keep them in an insulating state. The second interlayer insulating film 34 is made of SiO2 and SiN x The second interlayer insulating film 34 is located on the upper side of the second metal film and on the lower side of the first transparent electrode film F2. The second interlayer insulating film 34 is interposed between the source wiring 26 and the drain electrode 27C to keep them in an insulating state. The third interlayer insulating film 35 is made of an inorganic material or an organic material (organic resin material). If the third interlayer insulating film 35 is made of an inorganic material, the third interlayer insulating film 35 is made of SiO2 or SiN x The third interlayer insulating film 35 consists of the following. If the third interlayer insulating film 35 is made of an organic material, the third interlayer insulating film 35 consists of PMMA (acrylic resin), etc. The third interlayer insulating film 35 is located on the upper side of the first transparent electrode film F2 and on the lower side of the second transparent electrode film. The third interlayer insulating film 35 is interposed between the drain electrode 27C and the pixel electrode 28.

[0030] When the display mode of the liquid crystal panel 11 is, for example, FFS (Fringe Field Switching) mode, the array substrate 21 is laminated with a fourth interlayer insulating film on the upper side of the second transparent electrode film and a third transparent electrode film on the upper side of the fourth interlayer insulating film. In this case, the third transparent electrode film is at a common potential and constitutes a common electrode that superimposes on all pixel electrodes 28. On the other hand, when the display mode of the liquid crystal panel 11 is, for example, VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, etc., the opposing substrate 20 is provided with a counter electrode that superimposes on all pixel electrodes 28.

[0031] Here, the configurations of the TFT 27 and the pixel electrode 28 will be described in detail. In this embodiment, as shown in Figure 6, the TFT 27 is a so-called top-gate type, in which the gate electrode 27A is located on the upper layer side of the semiconductor portion 27D via the gate insulating film 32. As shown in Figure 5, the semiconductor portion 27D of the TFT 27 is L-shaped overall when viewed in a planar view, and consists of a portion extending along the X-axis and a portion extending along the Y-axis. Of the portion of the semiconductor portion 27D extending along the X-axis, the end opposite to the portion extending along the Y-axis (right side in Figure 5) overlaps the source wiring 26. Of the source wiring 26, the portion that overlaps with the semiconductor portion 27D constitutes the source electrode 27B. Of the portion of the semiconductor portion 27D extending along the Y-axis, one end (upper side in Figure 5) is connected to the portion extending along the X-axis, and the intermediate portion up to the other end (lower side in Figure 5) is arranged to intersect with the gate wiring 25. The portion of the gate wiring 25 that intersects (overlaps) with the semiconductor portion 27D constitutes the gate electrode 27A.

[0032] As shown in Figure 5, the drain electrode 27C extends along the Y-axis and has a vertically elongated rectangular shape when viewed in plan. The drain electrode 27C is wider than the portion of the semiconductor part 27D that extends along the Y-axis. The width of the drain electrode 27C is slightly smaller than the distance between two adjacent source wirings 26 in the X-axis direction. One end of the drain electrode 27C (upper side in Figure 5) overlaps with the gate wiring 25, and the other end (lower side in Figure 5) extends beyond the portion of the semiconductor part 27D that extends along the Y-axis. The drain electrode 27C overlaps with most of the portion of the semiconductor part 27D that extends along the Y-axis (excluding the end that connects to the portion that extends along the X-axis). The drain electrode 27C is connected to the other end of the portion of the semiconductor part 27D that extends along the Y-axis. Thus, the semiconductor portion 27D, which is L-shaped when viewed in a planar view, has both ends connected to the source electrode 27B and the drain electrode 27C, respectively, and the intermediate portion between these connections overlaps with the gate electrode 27A.

[0033] As shown in Figure 6, the pixel electrode 28 extends along the Y-axis and has a vertically elongated rectangular shape when viewed in plane. The pixel electrode 28 has approximately the same width as the drain electrode 27C. One end of the pixel electrode 28 (upper side in Figure 5) overlaps with the gate wiring 25, and the other end (lower side in Figure 5) extends beyond the drain electrode 27C to the vicinity of the adjacent gate wiring 25 on the lower side of Figure 5 in the Y-axis direction. In other words, the pixel electrode 28 is longer than the drain electrode 27C and overlaps with almost the entire area of ​​the drain electrode 27C. Thus, although the drain electrode 27C overlaps with most of the pixel electrode 28, it is composed of a light-transmitting first transparent electrode film F2. Therefore, compared to the case where the drain electrode 27C is made of a part of a metal film, a sufficiently large amount of light can be transmitted through the pixel electrode 28. In other words, the aperture ratio of the pixels can be improved, which is particularly useful when the resolution of the liquid crystal panel 11 is high. Furthermore, the other end of the pixel electrode 28 is superimposed on an L-shaped portion of the semiconductor part 27D that constitutes the TFT 27 to which the adjacent pixel electrode 28 on the lower side of Figure 5 is to be connected in the Y-axis direction. This portion is located between the part connected to the source electrode 27B and the part that intersects with the gate wiring 25.

[0034] As shown in Figure 6, a first interlayer insulating film 33 and a second interlayer insulating film 34 are interposed between the drain electrode 27C and the semiconductor portion 27D, which overlap each other. A first contact hole CH1 is provided in communication with at least the positions of the first interlayer insulating film 33 and the second interlayer insulating film 34 that overlap with both the drain electrode 27C and the semiconductor portion 27D. The drain electrode 27C and the semiconductor portion 27D are connected through the first contact hole CH1. The first contact hole CH1 is positioned to overlap with the end of the drain electrode 27C that extends along the Y-axis, opposite to the gate electrode 27A (lower side in Figure 5), and with the end of the portion of the semiconductor portion 27D that extends along the Y-axis, opposite to the gate electrode 27A (lower side in Figure 5).

[0035] As shown in Figure 6, a first interlayer insulating film 33 is interposed between the overlapping source electrode 27B and the semiconductor portion 27D. A second contact hole CH2 is provided in the first interlayer insulating film 33 at a position that overlaps with at least both the source electrode 27B and the semiconductor portion 27D. The source electrode 27B and the semiconductor portion 27D are connected through the second contact hole CH2.

[0036] As shown in Figure 6, a third interlayer insulating film 35 is interposed between the drain electrode 27C and the pixel electrode 28, which overlap each other. A third contact hole CH3 is provided in the third interlayer insulating film 35 at a position that overlaps with at least both the drain electrode 27C and the pixel electrode 28. The drain electrode 27C and the pixel electrode 28 are connected through the third contact hole CH3. The third contact hole CH3 is positioned to overlap with the gate electrode 27A side (upper side in Figure 5) of the drain electrode 27C which extends along the Y-axis, and with the gate electrode 27A side (upper side in Figure 5) of the pixel electrode 28 which extends along the Y-axis. In this embodiment, the third contact hole CH3 is positioned to overlap with the gate electrode 27A (gate wiring 25).

[0037] As shown in Figures 5 and 6, the second insulating film 31 provided in the array substrate 21 according to this embodiment has an opening 31A at a position that overlaps with at least a portion of the first contact hole CH1. In this embodiment, the opening 31A is positioned to overlap with both the semiconductor portion 27D and the drain electrode 27C. More specifically, the opening 31A is positioned to be concentric with the first contact hole CH1 when viewed in plane. The opening 31A is positioned to overlap with the end of the semiconductor portion 27D that extends along the Y-axis, on the side opposite to the gate electrode 27A (lower side in Figure 5). Therefore, it can also be said that the opening 31A is positioned to overlap with the end of the drain electrode 27C that extends along the Y-axis, on the side opposite to the gate electrode 27A (lower side in Figure 5). The opening 31A is provided in a manner that penetrates the second insulating film 31. Therefore, the portion of the first insulating film 30 that overlaps with the opening 31A is exposed to the upper layer through the opening 31A. Of the semiconductor portion 27D, the portion that overlaps with the opening 31A enters the opening 31A and comes into contact with the portion of the first insulating film 30 that is exposed through the opening 31A. Of the drain electrode 27C, the portion that overlaps with the opening 31A enters the opening 31A together with the semiconductor portion 27D, but does not come into direct contact with the first insulating film 30.

[0038] Here, since the first transparent electrode film F2 constituting the drain electrode 27C contains oxygen, there is a risk that oxygen may diffuse from the drain electrode 27C to the portion of the semiconductor portion 27D connected to the drain electrode 27C. In this embodiment, however, since an opening 31A is provided in the second insulating film 31 at a position overlapping with at least a part of the first contact hole CH1, the semiconductor portion 27D can be brought into contact with the first insulating film 30 through the opening 31A. Since this first insulating film 30 contains at least silicon and nitrogen, it will contain hydrogen during film formation. Therefore, hydrogen contained in the first insulating film 30 will directly diffuse into the semiconductor portion 27D that is in contact with the first insulating film 30 through the opening 31A. As a result, even if oxygen contained in the drain electrode 27C diffuses into the semiconductor portion 27D, hydrogen contained in the first insulating film 30 will diffuse into the semiconductor portion 27D, making it difficult for the resistance of the semiconductor portion 27D to increase, and consequently making it difficult for the contact resistance between the semiconductor portion 27D and the drain electrode 27C to become high. In particular, the portion of the semiconductor portion 27D that contacts the first insulating film 30 through the opening 31A is superimposed on at least a part of the first contact hole CH1. Therefore, hydrogen can be efficiently diffused to the portion of the semiconductor portion 27D where oxygen is easily diffused (the portion connected to the drain electrode 27C), thereby effectively suppressing the increase in resistance of the semiconductor portion 27D. As described above, the contact resistance between the semiconductor portion 27D and the drain electrode 27C is kept low, so that the image signal from the source electrode 27B is less likely to be blunted when transmitted to the drain electrode 27C via the channel region of the semiconductor portion 27D during TFT 27 operation. This allows the pixel electrode 28 to be charged to the potential related to the image signal, and the voltage retention rate of the pixel electrode 28 is kept high, resulting in good display quality for the image.

[0039] In this embodiment, the second insulating film 31, which is laminated on the lower side of the semiconductor film F1, contains at least silicon and oxygen, so it contains virtually no hydrogen during film formation. Therefore, it is virtually impossible for hydrogen to diffuse from the second insulating film 31 to the entire semiconductor portion 27D. Similarly, the gate insulating film 32 and the first interlayer insulating film 33, which are laminated on the upper side of the semiconductor film F1, contain at least silicon and oxygen, so they contain virtually no hydrogen during film formation. Therefore, it is virtually impossible for hydrogen to diffuse from the gate insulating film 32 and the first interlayer insulating film 33 to the entire semiconductor portion 27D.

[0040] Furthermore, in the array substrate 21 according to this embodiment, a recess 30A is provided in the first insulating film 30 at a position overlapping with the opening 31A, as shown in Figure 6. The recess 30A communicates with the overlapping opening 31A, and its inner surface is substantially flush with the inner surface of the opening 31A. The depth dimension of the recess 30A is smaller than the thickness of the first insulating film 30. Therefore, the first insulating film 30 is locally thinner where the recess 30A is formed compared to where the recess 30A is not formed. The inner surface and bottom surface of the recess 30A provided in the first insulating film 30 are exposed to the upper layer through the opening 31A. The portion of the semiconductor portion 27D that overlaps with the opening 31A and the recess 30A extends into the opening 31A and the recess 30A, and also contacts the inner surface and bottom surface of the recess 30A exposed through the opening 31A in the first insulating film 30. During manufacturing, when creating an opening 31A in the second insulating film 31, a recess 30A can be provided in the first insulating film 30 at a position that overlaps with the opening 31A. If the opening 31A is created in the second insulating film 31 in such a way that the recess 30A is not formed in the first insulating film 30, the certainty that the opening 31A penetrates the second insulating film 31 may decrease. However, if the opening 31A is created in the second insulating film 31 in such a way that the recess 30A is formed in the first insulating film 30, the certainty that the opening 31A penetrates the second insulating film 31 increases. This increases the certainty that the semiconductor portion 27D and the drain electrode 27C contact the first insulating film 30 through the opening 31A and the recess 30A.

[0041] This embodiment has the structure described above, and next, the manufacturing method of the liquid crystal panel 11 will be explained. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process for manufacturing the counter substrate 20, an array substrate manufacturing process for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and the array substrate 21 together. Below, the array substrate manufacturing process (manufacturing method of the array substrate 21) will be explained.

[0042] The array substrate manufacturing process includes at least the following steps: a first step of depositing and patterning a first insulating film 30 and a second insulating film 31; a second step of depositing and patterning a semiconductor film F1; a third step of depositing and patterning a gate insulating film 32; a fourth step of depositing and patterning a first metal film; a fifth step of depositing and patterning a first interlayer insulating film 33; a sixth step of depositing and patterning a second metal film; a seventh step of depositing and patterning a second interlayer insulating film 34; an eighth step of depositing and patterning a first transparent electrode film F2; a ninth step of depositing and patterning a third interlayer insulating film 35; and a tenth step of depositing and patterning a second transparent electrode film. The following will mainly describe the first, second, seventh, and eighth steps in detail.

[0043] The term "patterning" used above refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is deposited on the film to be processed, the photoresist film is exposed using an exposure device through a photomask having a predetermined aperture pattern, the photoresist film is developed, and etching is performed through the developed photoresist film to process the film, i.e., pattern the film.

[0044] In the first step, a first insulating film 30 is deposited on a glass substrate 21GS, and then a second insulating film 31 is deposited on the first insulating film 30. After that, a first photoresist film PR1 is deposited on the second insulating film 31. The first photoresist film PR1 may be either positive or negative. Subsequently, the first photoresist film PR1 is exposed using an exposure apparatus and a photomask (not shown, along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, the first photoresist film PR1 remains on the second insulating film 31 with the aperture pattern of the photomask transferred onto it, as shown in Figure 7. Specifically, if the first photoresist film PR1 is positive, an unexposed portion that does not overlap with the aperture of the photomask remains, and if the first photoresist film PR1 is negative, an exposed portion that overlaps with the aperture of the photomask remains. The remaining first photoresist film PR1 has a resist opening PR1A that overlaps with the planned formation positions of the opening 31A and recess 30A.

[0045] The second insulating film 31 is etched using the first photoresist film PR1 having this configuration as a mask. As a result, the portion of the second insulating film 31 that overlaps with the first photoresist film PR1 remains, and the portion exposed to the resist opening PR1A is selectively removed. By adjusting the etching rate and etching time at this time, as shown in Figure 8, an opening 31A that overlaps with the resist opening PR1A is formed through the second insulating film 31, and in addition, a recess 30A that overlaps with the resist opening PR1A and the opening 31A is formed in the first insulating film 30 located on the lower layer side of the second insulating film 31. This makes it highly certain that the opening 31A is formed through the second insulating film 31 and that the first insulating film 30 is exposed through the opening 31A.

[0046] In the second step, a semiconductor film F1 is deposited on the second insulating film 31, and then a second photoresist film PR2 is deposited on the semiconductor film F1. The second photoresist film PR2 may be either positive or negative. After that, the second photoresist film PR2 is exposed using an exposure apparatus and a photomask (not shown, neither of which is the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, the second photoresist film PR2 remains on the semiconductor film F1 with the aperture pattern of the photomask transferred onto it, as shown in Figure 9. The second photoresist film PR2 remains at the planned formation position of the semiconductor portion 27D.

[0047] The semiconductor film F1 is etched using the second photoresist film PR2, which has the configuration described above, as a mask. As a result, the portion of the semiconductor film F1 that overlaps with the second photoresist film PR2 remains, while the portion that does not overlap with the second photoresist film PR2 is selectively removed. This results in the formation of a semiconductor portion 27D, as shown in Figure 10. A portion of the semiconductor portion 27D penetrates into the interior of the opening 31A of the second insulating film 31 and the interior of the recess 30A of the first insulating film 30, and is in contact with the bottom surface and inner circumferential surface of the recess 30A.

[0048] In the third step, when the gate insulating film 32 is deposited and patterned, the gate insulating film 32 is provided in an island shape that overlaps with the intermediate portion of the semiconductor part 27D (see Figure 6). In the fourth step, when the first metal film is deposited and patterned, the gate electrode 27A and gate wiring 25 are provided (see Figure 6). In the fifth step, when the first interlayer insulating film 33 is deposited and patterned, the first interlayer insulating film 33 is provided with a second contact hole CH2 (see Figure 6). In the sixth step, when the second metal film is deposited and patterned, the source electrode 27B and source wiring 26 are provided (see Figure 6).

[0049] In the seventh step, a second interlayer insulating film 34 is formed on the second metal film, and then a third photoresist film PR3 is formed on the second interlayer insulating film 34. The third photoresist film PR3 may be either positive or negative. After that, the third photoresist film PR3 is exposed using an exposure apparatus and a photomask (not shown, along with the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, the third photoresist film PR3 remains on the second interlayer insulating film 34 with the aperture pattern of the photomask transferred onto it, as shown in Figure 11. The remaining third photoresist film PR3 has a resist opening PR3A that overlaps with the planned formation position of the first contact hole CH1.

[0050] The second interlayer insulating film 34 is etched using the third photoresist film PR3 having this configuration as a mask. As a result, the portion of the second interlayer insulating film 34 that overlaps with the third photoresist film PR3 remains, while the portion exposed to the resist opening PR3A is selectively removed. By adjusting the etching rate and etching time at this time, as shown in Figure 12, a portion of the first contact hole CH1 that overlaps with the resist opening PR3A is provided through the second interlayer insulating film 34, and the remaining portion of the first contact hole CH1 that overlaps with the resist opening PR3A is provided through the first interlayer insulating film 33 located on the lower side of the second interlayer insulating film 34. This provides a first contact hole CH1 that communicates with the first interlayer insulating film 33 and the second interlayer insulating film 34. The first contact hole CH1 is arranged to overlap with the opening 31A and the recess 30A.

[0051] In the eighth step, a first transparent electrode film F2 is formed on the second interlayer insulating film 34, and then a fourth photoresist film PR4 is formed on the first transparent electrode film F2. The fourth photoresist film PR4 may be either positive or negative. After that, the fourth photoresist film PR4 is exposed using an exposure apparatus and a photomask (not shown, neither of which is the exposure apparatus) having a predetermined aperture pattern, and then developed. As a result, the fourth photoresist film PR4 remains on the first transparent electrode film F2 with the aperture pattern of the photomask transferred onto it, as shown in Figure 13. The fourth photoresist film PR4 remains at the planned formation position of the drain electrode 27C.

[0052] The first transparent electrode film F2 is etched using the fourth photoresist film PR4, which has the configuration described above, as a mask. As a result, the portion of the first transparent electrode film F2 that overlaps with the fourth photoresist film PR4 remains, while the portion that does not overlap with the fourth photoresist film PR4 is selectively removed. This provides the drain electrode 27C, as shown in Figure 14. The drain electrode 27C is connected to the semiconductor portion 27D through a first contact hole CH1 that communicates with the first interlayer insulating film 33 and the second interlayer insulating film 34. Since the first contact hole CH1 is positioned to overlap with the opening 31A and the recess 30A, the drain electrode 27C is connected to the portion of the semiconductor portion 27D that is inside the opening 31A and the recess 30A.

[0053] Step 9 is performed, and the third interlayer insulating film 35 is deposited and patterned, and a third contact hole CH3 is provided in the third interlayer insulating film 35 (see Figure 6). Step 10 is performed, and the second transparent electrode film is deposited and patterned, and a pixel electrode 28 is provided (see Figure 6). The pixel electrode 28 is connected to the drain electrode 27C through the third contact hole CH3 of the third interlayer insulating film 35.

[0054] As described above, the array substrate (semiconductor device) 21 of this embodiment comprises a first insulating film 30 containing at least silicon and nitrogen, a second insulating film 31 disposed on the upper side of the first insulating film 30 and containing at least silicon and oxygen, a semiconductor portion 27D consisting of a part of a semiconductor film F1 disposed on the upper side of the second insulating film 31, a first interlayer insulating film (third insulating film) 33 disposed on the upper side of the semiconductor film F1, and a drain electrode (first electrode) 27C consisting of a part of a first transparent electrode film F2 disposed on the upper side of the first interlayer insulating film 33, with at least a part of it overlapping with a part of the semiconductor portion 27D. A first contact hole CH1 connecting the semiconductor portion 27D and the drain electrode 27C is provided in the first interlayer insulating film 33 at a position that overlaps with at least a part of the semiconductor portion 27D and the drain electrode 27C, and an opening 31A is provided in the second insulating film 31 at a position that overlaps with at least a part of the first contact hole CH1.

[0055] A semiconductor portion 27D, which is part of the semiconductor film F1, and a drain electrode 27C, which is part of the first transparent electrode film F2, are superimposed on each other and connected through a first contact hole CH1 of the first interlayer insulating film 33 interposed between them. Here, since the first transparent electrode film F2 that constitutes the drain electrode 27C contains oxygen, there is a risk that oxygen may diffuse from the drain electrode 27C to the portion of the semiconductor portion 27D that is connected to the drain electrode 27C. In this regard, an opening 31A is provided in the second insulating film 31 at a position that overlaps with at least a portion of the first contact hole CH1, so that the semiconductor portion 27D and the drain electrode 27C can be brought into contact with the first insulating film 30 through the opening 31A. Since this first insulating film 30 contains at least silicon and nitrogen, it will contain hydrogen during film formation. Therefore, hydrogen contained in the first insulating film 30 will diffuse to the semiconductor portion 27D and the drain electrode 27C that are in contact with the first insulating film 30 through the opening 31A. When the semiconductor portion 27D is in contact with the first insulating film 30, hydrogen contained in the first insulating film 30 diffuses directly into the semiconductor portion 27D. When the drain electrode 27C is in contact with the first insulating film 30, hydrogen contained in the first insulating film 30 diffuses indirectly into the semiconductor portion 27D via the drain electrode 27C. As a result, even if oxygen contained in the drain electrode 27C diffuses into the semiconductor portion 27D, the hydrogen contained in the first insulating film 30 diffuses into the semiconductor portion 27D, making it difficult for the resistance of the semiconductor portion 27D to increase, and consequently making it difficult for the contact resistance between the semiconductor portion 27D and the drain electrode 27C to increase. In particular, since the portion of the semiconductor portion 27D and the drain electrode 27C that is in contact with the first insulating film 30 through the opening 31A overlaps with at least a part of the first contact hole CH1, hydrogen can be efficiently diffused to the portion of the semiconductor portion 27D where oxygen is easily diffused, thereby effectively suppressing the increase in the resistance of the semiconductor portion 27D. Furthermore, the second insulating film 31, which is positioned beneath the semiconductor film F1, contains at least silicon and oxygen, and therefore contains virtually no hydrogen during film formation. Consequently, it is virtually impossible for hydrogen to diffuse from the second insulating film 31 throughout the semiconductor portion 27D.

[0056] Furthermore, a recess 30A is provided in the first insulating film 30 at a position overlapping with the opening 31A. During manufacturing, when providing the opening 31A in the second insulating film 31, the recess 30A can be provided in the first insulating film 30 at a position overlapping with the opening 31A. If the opening 31A is provided in the second insulating film 31 in such a way that the recess 30A is not formed in the first insulating film 30, the certainty that the opening 31A penetrates the second insulating film 31 may decrease. However, if the opening 31A is provided in the second insulating film 31 in such a way that the recess 30A is formed in the first insulating film 30, the certainty that the opening 31A penetrates the second insulating film 31 increases. This increases the certainty that the semiconductor portion 27D and the drain electrode 27C contact the first insulating film 30 through the opening 31A and the recess 30A.

[0057] Furthermore, the opening 31A is positioned to overlap both the semiconductor portion 27D and the drain electrode 27C. The portion of the semiconductor portion 27D that is connected to the drain electrode 27C through the first contact hole CH1 is in contact with the first insulating film 30 through the opening 31A. Hydrogen is directly diffused from the first insulating film 30 to the portion of the semiconductor portion 27D from the drain electrode 27C. This makes it less likely for the contact resistance between the semiconductor portion 27D and the drain electrode 27C to become high.

[0058] Furthermore, a gate insulating film (fourth insulating film) 32 is located on the upper side of the semiconductor film F1, below the first interlayer insulating film 33, and overlaps with a part of the semiconductor portion 27D; a gate electrode (second electrode) 27A is made of a part of the first metal film located on the upper side of the gate insulating film 32 and below the first interlayer insulating film 33, and overlaps with the gate insulating film 32 and a part of the semiconductor portion 27D; a source electrode (third electrode) 27B is made of a part of the second metal film located on the upper side of the first interlayer insulating film 33 and below the first transparent electrode film F2, and overlaps with a part of the semiconductor portion 27D; a second interlayer insulating film (fifth insulating film) 34 is located on the upper side of the second metal film and below the first transparent electrode film F2; and the upper side of the first transparent electrode film F2 The device comprises a third interlayer insulating film (sixth insulating film) 35 arranged on the upper side of the third interlayer insulating film 35, and a pixel electrode (fourth electrode) 28 which is made of a part of the second transparent electrode film arranged on the upper side of the third interlayer insulating film 35 and is arranged so as to overlap with the drain electrode 27C. A second contact hole CH2 is provided in the first interlayer insulating film 33 at a position where it overlaps with both the semiconductor part 27D and the source electrode 27B, connecting the semiconductor part 27D and the source electrode 27B. A third contact hole CH3 is provided in the third interlayer insulating film 35 at a position where it overlaps with both the drain electrode 27C and the pixel electrode 28, connecting the drain electrode 27C and the pixel electrode 28. The first contact hole CH1 is provided in communication with the first interlayer insulating film 33 and the second interlayer insulating film 34. When a potential above a predetermined level is supplied to the gate electrode 27A, which is superimposed on a portion of the semiconductor portion 27D via the gate insulating film 32, a channel region is created in the portion of the semiconductor portion 27D that is superimposed on the gate electrode 27A. As a result, the drain electrode 27C becomes at the same potential as the source electrode 27B via the channel region of the semiconductor portion 27D, and therefore the pixel electrode 28 also becomes at the same potential as the source electrode 27B. The semiconductor portion 27D, which is made up of a portion of the semiconductor film F1, and the source electrode 27B, which is made up of a portion of the second metal film, are superimposed on each other and connected through the second contact hole CH2 of the first interlayer insulating film 33 interposed between them. The drain electrode 27C, which is made up of a portion of the first transparent electrode film F2, and the pixel electrode 28, which is made up of a portion of the second transparent electrode film, are superimposed on each other and connected through the third contact hole CH3 of the third interlayer insulating film 35 interposed between them.The semiconductor portion 27D, which is part of the semiconductor film F1, and the drain electrode 27C, which is part of the first transparent electrode film F2, are connected through a first contact hole CH1 that communicates with the first interlayer insulating film 33 and the second interlayer insulating film 34 interposed between them. As described above, the pixel electrode 28 and the semiconductor portion 27D are connected via the drain electrode 27C. Since the drain electrode 27C superimposed on the pixel electrode 28 is made of part of the first transparent electrode film F2, the amount of light transmitted through the pixel electrode 28 can be increased compared to the case where the drain electrode 27C is made of part of a metal film.

[0059] Furthermore, the liquid crystal panel (display device) 11 according to this embodiment comprises the array substrate 21 described above and a counter substrate 20 arranged opposite to the array substrate 21. With such a liquid crystal panel 11, the contact resistance between the semiconductor portion 27D and the drain electrode 27C is suppressed, so that the signal transmitted between the semiconductor portion 27D and the drain electrode 27C is less likely to be degraded. As a result, good display quality can be obtained.

[0060] <Embodiment 2> Embodiment 2 will be described with reference to Figures 15 to 20. This Embodiment 2 shows a case where the arrangement of the first contact hole CH101, the opening 131A, and the recess 130A is changed. Note that redundant explanations of the structure, operation, and effects, which are the same as those of Embodiment 1 described above, will be omitted.

[0061] As shown in Figures 15 and 16, the semiconductor portion 127D according to this embodiment has a smaller length dimension (dimension in the Y-axis direction) compared to Embodiment 1. Accordingly, the drain electrode 127C has an extended portion that does not overlap with the semiconductor portion 127D, and this portion is designated as the non-overlapping portion 127C1. The portion of the drain electrode 127C that overlaps with the semiconductor portion 127D is designated as the overlapping portion 127C2. The non-overlapping portion 127C1 is positioned adjacent to the semiconductor portion 127D in the Y-axis direction, on the lower side of Figure 15 (right side of Figure 16). The overlapping portion 127C2 is connected to the end of the portion of the semiconductor portion 127D that extends along the Y-axis direction through the first contact hole CH101, which will be described below.

[0062] As shown in Figures 15 and 16, the first contact hole CH101 extends along the Y-axis direction and has a vertically elongated rectangular shape when viewed in plane, and is positioned to cross the end of the portion of the semiconductor part 127D that extends along the Y-axis direction. The first contact hole CH101 is positioned in a location that overlaps with both the drain electrode 127C and the semiconductor part 127D, as well as in a location that overlaps with the drain electrode 127C but does not overlap with the semiconductor part 127D. Hereinafter, the first contact hole CH101 will be divided into a first range CH101A that overlaps with both the drain electrode 127C and the semiconductor part 127D, and a second range CH101B that overlaps with the drain electrode 127C but does not overlap with the semiconductor part 127D. The first range CH101A of the first contact hole CH101 is considered to overlap with the overlapping portion 127C2 of the drain electrode 127C. The second range CH101B of the first contact hole CH101 is superimposed on the non-superimposed portion 127C1 of the drain electrode 127C.

[0063] As shown in Figures 15 and 16, the second insulating film 131 is positioned such that its opening 131A overlaps with the drain electrode 127C but does not overlap with the semiconductor portion 127D. In other words, the opening 131A is positioned to overlap with the non-overlapping portion 127C1 of the drain electrode 127C and overlaps with the second range CH101B of the first contact hole CH101. In this configuration, the semiconductor portion 127D does not enter the interior of the opening 131A. In contrast, the non-overlapping portion 127C1 of the drain electrode 127C, which overlaps with the opening 131A, enters the opening 131A and makes contact with the portion of the first insulating film 130 that is exposed through the opening 131A.

[0064] As shown in Figure 16, the first insulating film 130 is provided such that the recess 130A is positioned to overlap with the opening 131A described above. Therefore, the recess 130A, like the opening 131A, is positioned to overlap with the non-overlapping portion 127C1 of the drain electrode 127C, and is in a relationship to overlap with the second range CH101B of the first contact hole CH101. The non-overlapping portion 127C1 of the drain electrode 127C, which overlaps with the opening 131A and the recess 130A, enters into the opening 131A and the recess 130A, and also contacts the inner circumferential surface and bottom surface of the recess 130A that is exposed through the opening 131A of the first insulating film 130. Therefore, the hydrogen contained in the first insulating film 130 diffuses indirectly into the semiconductor portion 127D via the drain electrode 127C. As a result, even if oxygen contained in the drain electrode 127C diffuses into the semiconductor portion 127D, hydrogen contained in the first insulating film 130 diffuses into the semiconductor portion 127D via the drain electrode 127C, making it difficult for the resistance of the semiconductor portion 127D to increase, and consequently making it difficult for the contact resistance between the semiconductor portion 127D and the drain electrode 127C to become high. Furthermore, when providing the first contact hole CH101 in the first interlayer insulating film 133 and the second interlayer insulating film 134 during manufacturing, the opening 131A can be provided in the second insulating film 131 at a position that does not overlap with the semiconductor portion 127D. In the case where the opening 31A is located at a position that overlaps with the semiconductor portion 27D, as in Embodiment 1 described above, it is necessary to provide the opening 31A in the second insulating film 31 between the deposition of the second insulating film 31 and the deposition of the semiconductor film F1. In comparison, in this embodiment, the first contact hole CH101 and the opening 131A can be provided in a single process, thus shortening the cycle time.

[0065] This embodiment has the structure described above, and next, we will mainly describe the array substrate manufacturing process included in the manufacturing method of the liquid crystal panel 11. Below, we will describe the first, seventh, and eighth steps in detail. Steps 2 to 6, 9, and 10 are as described in Embodiment 1.

[0066] In the first step, a first insulating film 130 is deposited on the glass substrate 121GS, and then a second insulating film 131 is deposited on the first insulating film 130. However, unlike in Embodiment 1, the first insulating film 130 and the second insulating film 131 are not patterned (see Figure 16). Therefore, in the first step, it is not necessary to deposit a photoresist film on the second insulating film 131 or to expose and develop the photoresist film. This eliminates the need for various devices such as photomasks and shortens the cycle time.

[0067] In the seventh step, the third photoresist film PR103 deposited on the second interlayer insulating film 134 is exposed and developed, so that the third photoresist film PR103 is patterned as shown in Figure 17. The third photoresist film PR103 remaining on the second interlayer insulating film 134 has a resist opening PR103A that overlaps with the planned position for the formation of the first contact hole CH101. By using the third photoresist film PR103 with this configuration as a mask to etch the second interlayer insulating film 134 and the first interlayer insulating film 133, a first contact hole CH101 communicating with the first interlayer insulating film 133 and the second interlayer insulating film 134 is formed. By adjusting the etching rate and etching time at this time, the second insulating film 131 is provided with an opening 131A communicating with the second range CH101B of the first contact hole CH101, as shown in Figure 18. In addition, the first insulating film 130, located on the lower side of the second insulating film 131, is provided with a recess 130A communicating with the opening 131A. Note that the portions of the first insulating film 130 and the second insulating film 131 that overlap with the first range CH101A of the first contact hole CH101 are covered by the semiconductor portion 127D and are therefore not etched. As a result, the first contact hole CH101 is provided in the first interlayer insulating film 133 and the second interlayer insulating film 134, the opening 131A is provided in the second insulating film 131, and the recess 130A is provided in the first insulating film 130. In this way, the first contact hole CH101, the opening 131A, and the recess 130A are provided in a single process, which is advantageous for improving production efficiency.

[0068] In the eighth step, the fourth photoresist film PR104 deposited on the first transparent electrode film F102 is exposed and developed, so that the fourth photoresist film PR104 is patterned as shown in Figure 19. The fourth photoresist film PR104 remaining on the first transparent electrode film F102 is placed at the planned position for the drain electrode 127C. By etching the first transparent electrode film F102 using the fourth photoresist film PR104 configured in this way as a mask, the drain electrode 127C is provided as shown in Figure 20. The superimposed portion 127C2 of the drain electrode 127C is connected to the semiconductor portion 127D through the first range CH101A of the first contact hole CH101 which communicates with the first interlayer insulating film 133 and the second interlayer insulating film 134. On the other hand, the non-superimposed portion 127C1 of the drain electrode 127C enters the interior of the opening 131A and recess 130A through the second range CH101B of the first contact hole CH101, and comes into contact with the bottom surface and inner circumferential surface of the recess 130A in the first insulating film 130.

[0069] As described above, according to this embodiment, the drain electrode 127C has a portion that does not overlap with the semiconductor portion 127D, the first contact hole CH101 is positioned to overlap with the drain electrode 127C but not with the semiconductor portion 127D, and the opening 131A is positioned to overlap with the drain electrode 127C but not with the semiconductor portion 127D. The portion of the drain electrode 127C that does not overlap with the semiconductor portion 127D is in contact with the first insulating film 130 through the first contact hole CH101 and the opening 131A. Therefore, hydrogen contained in the first insulating film 130 diffuses indirectly to the semiconductor portion 127D via the drain electrode 127C. Furthermore, when providing the first contact hole CH101 in the first interlayer insulating film 133 during manufacturing, the opening 131A can be provided in the second insulating film 131 at a position that does not overlap with the semiconductor portion 127D. If the opening 31A is positioned to overlap with the semiconductor portion 27D, it would be necessary to create the opening 31A in the second insulating film 31 between the formation of the second insulating film 31 and the formation of the semiconductor film F1. In contrast, it is possible to create the first contact hole CH101 and the opening 131A in a single process, thus shortening the cycle time.

[0070] <Other Embodiments> The technology disclosed herein is not limited to the embodiments described above in the description and drawings, but also includes, for example, the following embodiments.

[0071] (1) In the configuration described in Embodiment 2, the opening 131A and the recess 130A may be extended to overlap with the semiconductor portion 127D. In this case, the semiconductor portion 127D and the drain electrode 127C will each be in direct contact with the first insulating film 130. The opening 131A and the recess 130A are provided in the first step as described in Embodiment 1.

[0072] (2) The formation range of the recesses 30A and 130A as viewed in plane may be narrower than the formation range of the openings 31A and 131A as viewed in plane.

[0073] (3) It is also possible to have a configuration in which the first insulating film 30, 130 does not have recesses 30A, 130A.

[0074] (4) The specific materials used for the first insulating film 30, 130 and the second insulating film 31, 131 can be changed as appropriate in addition to those mentioned above. The specific materials used for the gate insulating film 32, the first interlayer insulating films 33, 133, the second interlayer insulating films 34, 134 and the third interlayer insulating film 35 can also be changed as appropriate.

[0075] (5) The formation range of the first contact holes CH1 and CH101 as viewed in plan can be changed as appropriate, in addition to what is shown in the figure.

[0076] (6) The arrangement of the third contact hole CH3 can be changed as appropriate to a position other than that shown (for example, a position that does not overlap with the gate electrode 27A).

[0077] (7) The semiconductor film F1 may be an amorphous silicon thin film or a polycrystalline silicon thin film.

[0078] (8) The TFT27 is not limited to a top-gate type; it may also be a bottom-gate type or a double-gate type.

[0079] (9) Instead of the second circuit section 14B, the source driver may be attached to the array board 21.

[0080] (10) Instead of the second circuit section 14B, the source driver may be mounted on the flexible circuit board 13.

[0081] (11) Instead of the first circuit section 14A, the gate driver may be attached to the array board 21.

[0082] (12) The liquid crystal panel 11 may be of a type other than transmissive, such as reflective or semi-transmissive. If the liquid crystal panel 11 is of a reflective type, the backlight device 12 can be omitted.

[0083] (13) In addition to head-mounted displays (HMDs), this technology can also be applied to devices that enlarge images displayed on an LCD panel (LCD) using lenses or the like, such as head-up displays and projectors. It can also be applied to display devices that do not have a magnification function (such as television receivers, tablet terminals, and smartphones). [Explanation of symbols]

[0084] 11…Liquid crystal panel (display device), 20…Opposite substrate, 21…Array substrate (semiconductor device), 27A…Gate electrode (second electrode), 27B…Source electrode (third electrode), 27C,127C…Drain electrode (first electrode), 27D,127D…Semiconductor part, 28…Pixel electrode (fourth electrode), 30,130…First insulating film, 30A,130A…Recess, 31,131…Second insulating film, 31A,131A…Opening, 32…Gate insulating film (fourth insulating film), 33,133…First interlayer insulating film (third insulating film), 34,134…Second interlayer insulating film (fifth insulating film), 35…Third interlayer insulating film (sixth insulating film), CH1,CH101…First contact hole, CH2…Second contact hole, CH3…Third contact hole, F1…Semiconductor film, F2,F102…First transparent electrode film

Claims

1. A first insulating film containing at least silicon and nitrogen, Displaced on the upper side of the first insulating film, a second insulating film containing at least silicon and oxygen, A semiconductor portion consisting of a part of the semiconductor film disposed on the upper layer side of the second insulating film, A third insulating film is disposed on the upper side of the semiconductor film, The present invention comprises a first electrode which is made up of a part of a first transparent electrode film disposed on the upper side of the third insulating film, and at least a part of which is superimposed on a part of the semiconductor portion, In the third insulating film, a first contact hole is provided at a position where it overlaps with at least the semiconductor portion and the first electrode, connecting the semiconductor portion and the first electrode. A semiconductor device having an opening in the second insulating film at a position that overlaps with at least a portion of the first contact hole.

2. The semiconductor device according to claim 1, wherein a recess is provided in the first insulating film at a position that overlaps with the opening.

3. The semiconductor device according to claim 1 or claim 2, wherein the opening is positioned to overlap both the semiconductor portion and the first electrode.

4. The first electrode has a portion that does not overlap with the semiconductor portion, The first contact hole is also positioned so as to overlap with the first electrode but not with the semiconductor portion. The semiconductor device according to claim 1 or claim 2, wherein the opening is positioned to overlap with the first electrode and not overlap with the semiconductor portion.

5. A fourth insulating film is disposed on the upper side of the semiconductor film, below the third insulating film, and in a position overlapping with a part of the semiconductor portion. A second electrode is made of a part of the first metal film disposed on the upper side of the fourth insulating film and on the lower side of the third insulating film, and is positioned to overlap with the fourth insulating film and a part of the semiconductor portion. The third electrode is made of a part of the second metal film, which is positioned above the third insulating film and below the first transparent electrode film, and is positioned to overlap with a part of the semiconductor portion. A fifth insulating film is disposed on the upper side of the second metal film and on the lower side of the first transparent electrode film, A sixth insulating film is disposed on the upper side of the first transparent electrode film, The device comprises a fourth electrode which is made of a part of the second transparent electrode film disposed on the upper side of the sixth insulating film, and a part of which is arranged superimposed on the first electrode, In the third insulating film, a second contact hole is provided at a position where it overlaps with both the semiconductor portion and the third electrode, connecting the semiconductor portion and the third electrode. In the sixth insulating film, a third contact hole is provided at a position where it overlaps with both the first electrode and the fourth electrode, connecting the first electrode and the fourth electrode. The semiconductor device according to claim 1 or claim 2, wherein the first contact hole is provided in communication with the third insulating film and the fifth insulating film.

6. A semiconductor device according to claim 1 or claim 2, A display device comprising a semiconductor device and a counter substrate disposed opposite to it.

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