Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing dielectric breakdown. [Solution] The semiconductor device A10 comprises a lead 31, a lead 32 spaced apart from the lead 31 in a first direction x, a first semiconductor element 11 mounted on the lead 31, a plurality of second semiconductor elements 12 mounted on the lead 32, a third semiconductor element 13 mounted on the lead 31 or lead 32, and a sealing resin 5 covering the lead 31, the lead 32, the first semiconductor element 11, the plurality of second semiconductor elements 12, and the third semiconductor element 13. The third semiconductor element 13 is electrically interposed such that the first semiconductor element 11 has a different potential from the plurality of second semiconductor elements 12. The plurality of second semiconductor elements 12 are arranged along a second direction y that is perpendicular to the first direction x.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background Art]

[0002] A conventional inverter device includes switching elements such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a control element, and a driving element. In a conventional inverter device, while the power supply voltage supplied to the control element is a low voltage (approximately 5V), the power supply voltage supplied to the driving element may be a high voltage (about 600V or higher). As described above, an insulating element is sometimes used as means for transmitting signals between a plurality of elements having different power supply voltages. For example, Patent Document 1 discloses an example of a semiconductor device (intelligent power module) including an insulating element. When a plurality of circuits are formed in a single element as in the semiconductor device disclosed in Patent Document 1, unintended mutual interference may occur between the plurality of circuits. Such interference is a cause of failure of the semiconductor device and may reduce the reliability of the semiconductor device. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2009-49035

[0004] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional ones. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of reducing the occurrence of dielectric breakdown.

[0005] A semiconductor device provided by a first aspect of this disclosure comprises: a first lead; a second lead spaced apart from the first lead in a first direction; at least one first semiconductor element mounted on the first lead; a plurality of second semiconductor elements mounted on the second lead; a third semiconductor element mounted on the first or second lead; and a sealing resin covering the first lead, the second lead, the at least one first semiconductor element, the plurality of second semiconductor elements, and the third semiconductor element. The third semiconductor element is interposed between the at least one first semiconductor element and the plurality of second semiconductor elements such that the at least one first semiconductor element and the plurality of second semiconductor elements have different potentials. The plurality of second semiconductor elements are aligned along a second direction perpendicular to the first direction.

[0006] Other features and advantages of this disclosure will become more apparent from the detailed description below, based on the accompanying drawings. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of Figure 1, with the sealing resin indicated by dashed lines. [Figure 3] Figure 3 is a front view showing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a left side view showing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a right side view showing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7] Figure 7 is a cross-sectional view along the line VII-VII in Figure 2. [Figure 8] Figure 8 is an enlarged cross-sectional view of a portion of Figure 7. [Figure 9]Figure 9 is a cross-sectional view showing the internal structure of one of the multiple semiconductor elements (insulating element) of the semiconductor device according to the first embodiment. [Figure 10] Figure 10 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 11] Figure 11 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 12] Figure 12 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 13] Figure 13 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 14] Figure 14 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 15] Figure 15 is a plan view showing one step in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 16] Figure 16 is an electrical schematic diagram showing a semiconductor device according to the first embodiment. [Figure 17] Figure 17 is a plan view showing a semiconductor device according to a first modification of the first embodiment, in which the sealing resin is indicated by dashed lines. [Figure 18] Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figure 17. [Figure 19] Figure 19 is a plan view showing a semiconductor device according to a second embodiment, in which the sealing resin is indicated by dashed lines. [Figure 20] Figure 20 is an enlarged view of region XX in Figure 19. [Figure 21] Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 19. [Figure 22] Figure 22 is a plan view showing a semiconductor device according to a first modification of the second embodiment, in which the sealing resin is indicated by dashed lines. [Figure 23] Figure 23 is a cross-sectional view along the line XXIII-XXIII in Figure 22. [Figure 24]FIG. 24 is a plan view showing the semiconductor device according to the third embodiment, in which a sealing resin is indicated by imaginary lines. [Figure 25] FIG. 25 is an enlarged view of region XXV in FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24. [Figure 27] FIG. 27 is an electrical schematic diagram showing the semiconductor device according to the third embodiment. [Figure 28] FIG. 28 is a plan view showing the semiconductor device according to the fourth embodiment, in which a sealing resin is indicated by imaginary lines. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28. [Figure 30] FIG. 30 is an electrical schematic diagram showing the semiconductor device according to the fourth embodiment.

[0008] [Detailed Description] Preferred embodiments of the semiconductor device and the method for manufacturing the same according to the present disclosure will be described below with reference to the drawings. The components illustrated in the drawings are an example for describing the semiconductor device of the present disclosure. The invention recited in the claims does not require all of the components shown in the drawings and the specification.

[0009] First Embodiment: FIGS. 1 to 9 show a semiconductor device A10 according to the first embodiment. As shown in these drawings, the semiconductor device A10 includes a plurality of semiconductor elements 11, 12, 13, a conductive support 3, a plurality of connecting members 4, and a sealing resin 5.

[0010] This disclosure refers to and describes the mutually orthogonal first direction x, second direction y, and third direction z. The third direction z corresponds, for example, to the third direction of the conductive support 3. In the following description, "plan view" refers to the view in the third direction z. One side of the third direction z may be referred to as "up" and the other as "down." Note that terms such as "up," "down," "upper," "downward," "upper surface," and "lower surface" indicate the relative positional relationship of each component in the third direction z, and do not necessarily define a relationship with the direction of gravity.

[0011] The semiconductor device A10 can be surface-mounted on a wiring board of an inverter device such as an electric vehicle or hybrid vehicle. The inverter device generates three-phase AC power for motor drive from DC power from an on-board battery. The semiconductor device A10 is configured to control the switching operation of switching elements such as IGBTs or MOSFETs. More specifically, the semiconductor device A10 may include a control element (controller) to which a control signal from an ECU (Engine Control Unit) is input, a drive element (gate driver) that converts the control signal into a PWM (Pulse Width Modulation) signal and transmits it to the target (e.g., six switching elements), and an intermediary element that transmits signals between multiple elements with different power supply voltages. The package format of the semiconductor device A10 is an SOP (Small Outline Package), as can be seen from Figures 1 and 3 to 5. The package format of the semiconductor device A10 is not limited to SOP.

[0012] Multiple semiconductor elements 11, 12, and 13 can serve as the functional core of the semiconductor device A10. In this embodiment, the multiple semiconductor elements 11, 12, and 13 comprise semiconductor element 11, multiple semiconductor elements 12, and semiconductor element 13. Semiconductor element 11 is an example of a control element. Multiple semiconductor elements 12 are an example of a driving element. Semiconductor element 13 is an example of an intermediary element. In the first direction x, semiconductor element 13 is located between semiconductor element 11 and the multiple semiconductor elements 12. As a result, semiconductor element 13 is electrically interposed such that semiconductor element 11 has a different potential from the multiple semiconductor elements 12. In a plan view, each of the multiple semiconductor elements 11, 12, and 13 has a rectangular shape with the second direction y as its longer side. Note that the plan view shapes of the multiple semiconductor elements 11, 12, and 13 are not limited to the illustrated examples.

[0013] The semiconductor element 11 may include a circuit that converts a control signal input from an ECU or the like into a PWM signal, a transmitting circuit for transmitting the signal to the semiconductor element 13, and a receiving circuit that receives an electrical signal from the semiconductor element 13.

[0014] The semiconductor element 11 may have a main surface 11a and a back surface 11b. The main surface 11a and the back surface 11b are separated in a third direction z. The main surface 11a is the upper surface of the semiconductor element 11, and the back surface 11b is the lower surface of the semiconductor element 11. The back surface 11b faces the lead 31. The main surface 11a may be provided with a plurality of pads 111. The composition of each of the plurality of pads 111 may include, for example, aluminum (Al).

[0015] Each of the multiple semiconductor elements 12 may include a receiving circuit for receiving a PWM signal, a circuit for driving a switching element based on the signal, and a transmitting circuit for transmitting an electrical signal to the semiconductor element 11. An electrical signal is, for example, an output signal from a temperature sensor located near the motor. The number of multiple semiconductor elements 12 is not limited, but there are four in the illustrated example.

[0016] Each semiconductor element 12 may have a main surface 12a and a back surface 12b. The main surface 12a and the back surface 12b are separated in a third direction z. The main surface 12a is the upper surface of the semiconductor element 12, and the back surface 12b is the lower surface of the semiconductor element 12. The back surface 12b faces the lead 32. The main surface 12a may be provided with a plurality of pads 121. The composition of each of the plurality of pads 121 may include, for example, Al.

[0017] Each semiconductor element 12, in plan view, includes a first side 12a1, a second side 12a2, a third side 12a3, and a fourth side 12a4. The first side 12a1, the second side 12a2, the third side 12a3, and the fourth side 12a4 correspond to the ends of each main surface 12a in the first direction x and the second direction y. The first side 12a1 and the second side 12a2 are separated from each other in the second direction y. The third side 12a3 and the fourth side 12a4 are separated from each other in the first direction x. The shape of the main surface 12a is not limited to the illustrated example, and the main surface 12a does not have to include at least one of the first side 12a1, the second side 12a2, the third side 12a3, and the fourth side 12a4.

[0018] Multiple semiconductor elements 12 are arranged along the second direction y. The multiple semiconductor elements 12 are arranged with a spacing d1 between them in the second direction y. The spacing d1 is illustrated in Figure 2. The first side 12a1 faces the second side 12a2 of the adjacent semiconductor element 12 in the second direction y. The spacing d1 corresponds to the distance between the first side 12a1 and the second side 12a2 of two adjacent semiconductor elements 12. The spacing d1 is, for example, between 150 μm and 1500 μm. The multiple semiconductor elements 12 overlap each other when viewed in the second direction y. In the example shown in Figure 2, the multiple semiconductor elements 12 are in the same position in the first direction x. Alternatively, the multiple semiconductor elements 12 may be in different positions in the first direction x.

[0019] Figure 6 illustrates an example of a cross-section of multiple semiconductor elements 12. As shown in this figure, the multiple semiconductor elements 12 have their main surfaces 12a at the same position in the third direction z. That is, the multiple semiconductor elements 12 have the same thickness. Alternatively, the positions of the main surfaces 12a in the third direction z may differ from one another, and the multiple semiconductor elements 12 may have different thicknesses.

[0020] In the motor driver circuit of an inverter device, a half-bridge circuit is generally configured, including a low-side (low-potential side) switching element and a high-side (high-potential side) switching element. Below, we will describe an example where these switching elements are MOSFETs. In the low-side switching element, the reference potential of the source of the element and the reference potential of the gate driver that drives the element are both ground. On the other hand, in the high-side switching element, the reference potential of the source of the element and the reference potential of the gate driver that drives the element are both equivalent to the potential at the output node of the half-bridge circuit. Since the potential at the output node changes depending on the driving of the high-side switching element and the low-side switching element, the reference potential of the gate driver that drives the high-side switching element changes. When the high-side switching element is ON, the reference potential is equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or higher). In semiconductor device A10, the ground of semiconductor element 11 and the ground of the multiple semiconductor elements 12 are separated. Therefore, when semiconductor device A10 is used as a gate driver to drive a high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the multiple semiconductor elements 12.

[0021] The semiconductor element 13 may include an isolation transformer for transmitting signals between the control circuit and the arm circuit in an isolated state. An isolation transformer is an example of an inductive semiconductor element 13. Alternatively, the semiconductor element 13 may be capacitive. An example of a capacitive semiconductor element 13 is a capacitor. Or, the semiconductor element 13 may be a photocoupler.

[0022] The semiconductor element 13 may have a main surface 13a and a back surface 13b. The main surface 13a and the back surface 13b are separated in a third direction z. The main surface 13a is the upper surface of the semiconductor element 13, and the back surface 13b is the lower surface of the semiconductor element 13. The back surface 13b faces the lead 31.

[0023] Figures 2, 8, and 9 illustrate examples of the configuration of the semiconductor element 13. As shown in these figures, the semiconductor element 13 may include a semiconductor substrate 130, a plurality of pads 131, a plurality of pads 132, a seal ring portion 133, a protective film 1341, a passivation film 1342, a coil protective film 1343, a functional portion 135, a laminated structure 137, and a wiring portion 138. The internal structure of the semiconductor element 13 is not limited to the examples shown in Figures 8 and 9.

[0024] The semiconductor substrate 130 can be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or the like. The semiconductor element 13 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 130.

[0025] Multiple pads 131, 132 are provided on the main surface 13a. The composition of each of the multiple pads 131, 132 includes, for example, Al.

[0026] The seal ring portion 133 is formed along each of the four outer peripheries of the semiconductor element 13 in a plan view, surrounding the outer periphery of the circuit formation region. The seal ring portion 133 is erected on the semiconductor substrate 130 and penetrates the laminated structure 137 in the third direction z. The potential of the seal ring portion 133 may be the same as the potential of the semiconductor substrate 130. The composition of the seal ring portion 133 includes, for example, copper (Cu), Al, etc.

[0027] The protective film 1341 is laminated on the laminated structure 137. The protective film 1341 contains, for example, silicon dioxide (SiO2) and has a thickness of about 150 nm. The passivation film 1342 is laminated on the protective film 1341. The passivation film 1342 contains, for example, silicon nitride (SiN) and has a thickness of about 1000 nm. The coil protective film 1343 is on the passivation film 1342 and selectively covers the region directly above the upper winding 135a. The coil protective film 1343 contains, for example, polyimide and has a thickness of about 4000 nm. As can be seen from Figure 9, the protective film 1341, the passivation film 1342, and the coil protective film 1343 have pad openings formed to expose each pad 131 and each pad 132. The constituent materials and thicknesses of the protective film 1341, passivation film 1342, and coil protective film 1343 are not limited to the examples described above.

[0028] The laminated structure 137 is formed on a semiconductor substrate 130. As shown in Figure 9, the laminated structure 137 includes a plurality of insulating layers 1371. The plurality of insulating layers 1371 are laminated on the upper surface of the semiconductor substrate 130. Except for the bottom insulating layer 1371 that is in contact with the upper surface of the semiconductor substrate 130, each of the plurality of insulating layers 1371 has a laminated structure with a lower etching stopper film and an upper interlayer insulating film. The bottom insulating layer 1371 consists only of an interlayer insulating layer. As the etching stopper film, for example, a SiN film (silicon nitride film), SiC film (silicon carbide film), SiCN film (silicon carbonitride film), etc. can be used, and as the interlayer insulating film, for example, an SiO2 film (silicon oxide film) can be used. The dimension of the plurality of insulating layers 1371 in the third direction z is not limited in any way, but for example it is 2.4 μm. The thickness of each of the plurality of insulating layers 1371 can be changed as appropriate. The number of insulating layers 1371 is not limited to the illustrated example and can be appropriately changed, for example, depending on the magnitude of the voltage applied to each pad 131 and each pad 132.

[0029] The functional unit 135 plays a central role in the function of transmitting electrical signals in an insulated state within the semiconductor element 13. In the third direction z, the functional unit 135 includes a plurality of upper windings 135a and a plurality of lower windings 135b between the semiconductor substrate 130 and the pad 132. The plurality of upper windings 135a and the plurality of lower windings 135b are magnetically coupled to each other. As a result, each upper winding 135a forms a functional pair with one of the plurality of lower windings 135b. That is, the functional unit 135 has a plurality of pairs of upper windings 135a and lower windings 135b inside. The plurality of upper windings 135a and the plurality of lower windings 135b are each wound, for example, in a planar manner. The upper windings 135a and the lower windings 135b may each have a plurality of insulating layers 1371 wound three-dimensionally around them. However, in order to reduce the thickness of the semiconductor element 13, it is preferable that the upper winding 135a and the lower winding 135b are each wound in a planar manner on a single insulating layer 1371.

[0030] Figure 8 illustrates one of several sets of upper windings 135a and lower windings 135b. Multiple sets of upper windings 135a and lower windings 135b may similarly possess the characteristics shown in Figure 8. In the following, multiple sets of upper windings 135a and lower windings 135b may be described without distinction as "upper winding 135a" and "lower winding 135b". The upper winding 135a and lower winding 135b are separated and facing each other in the third direction z.

[0031] The upper winding 135a and the lower winding 135b are provided in different insulating layers 1371 within the laminated structure 137. That is, the upper winding 135a and the lower winding 135b face each other with one or more insulating layers 1371 in between. In the illustrated example, the lower winding 135b is formed in the fourth insulating layer 1371 from the semiconductor substrate 130, and the upper winding 135a is formed in the 15th insulating layer 1371, with 10 insulating layers 1371 in between it and the lower winding 135b. The more insulating layers 1371 there are between the upper winding 135a and the lower winding 135b, the higher the dielectric strength of the semiconductor element 13 can be, but the thicker the semiconductor element 13 (dimension in the third direction z) becomes. On the other hand, the fewer the number of insulating layers 1371 between the upper winding 135a and the lower winding 135b, the lower the dielectric strength of the semiconductor element 13, but the thinner the semiconductor element 13 (dimension in the third direction z), the smaller the thickness of the semiconductor element 13.

[0032] The wiring section 138 electrically connects each pad 131 to the corresponding lower winding 135b, and each pad 132 to the corresponding upper winding 135a. Each wiring section 138 includes a plurality of through-wirings 1381 and lead-out wirings 1382. The plurality of through-wirings 1381 each penetrate one or more insulating layers 1371 in a third direction z. In the example shown in Figure 9, the plurality of through-wirings 1381 include those connecting pad 131 to lead-out wiring 1382, those connecting lead-out wiring 1382 to the lower winding 135b, and those connecting pad 132 to the upper winding 135a. The lead-out wiring 1382 is formed on the bottom insulating layer 1371. The lead-out wiring 1382 forms part of the conductive path between pad 131 and the lower winding 135b.

[0033] The conductive support 3 constitutes a conductive path between the plurality of semiconductor elements 11, 12, and 13 and the wiring board on which the semiconductor device A10 is mounted. The conductive support 3 can be obtained, for example, from the same lead frame. As shown in Figures 1, 2, 6, and 7, the conductive support 3 has leads 31, leads 32, a plurality of leads 33, and a plurality of leads 34. The shape and arrangement of leads 31 and leads 32, as well as the shape, arrangement, and number of the plurality of leads 33 and a plurality of leads 34, are not limited to the illustrated examples.

[0034] Leads 31 and 32 are separated from each other in the first direction x. In semiconductor device A10, semiconductor elements 11 and 13 are mounted on lead 31, and multiple semiconductor elements 12 are mounted on lead 32.

[0035] The lead 31 includes an island portion 311. The island portion 311 has a mounting surface 311a facing one direction (upward) in the third direction z. That is, the mounting surface 311a faces the same direction as the main surface 11a. In this embodiment, a semiconductor element 11 is bonded to the mounting surface 311a via a conductive bonding material 119, and a semiconductor element 13 is bonded via a conductive bonding material 139. Each conductive bonding material 119, 139 is, for example, solder, metal paste, or sintered metal. The island portion 311 may be at the same potential as the semiconductor substrate 130 of the semiconductor element 13. The island portion 311 is covered with a sealing resin 5. In the illustrated example, the island portion 311 is rectangular in plan view. The thickness of the island portion 311 is, for example, 100 μm or more and 300 μm or less. Optionally, the island portion 311 may be provided with a plurality of through holes 313. Each through-hole 313 penetrates the island portion 311 in the third direction z. Each through-hole 313 is oval-shaped and extends along the second direction y in a plan view. Each through-hole 313 is located between the semiconductor element 11 and the semiconductor element 13.

[0036] The potential of lead 31 is the same as the potential of the semiconductor substrate 130 because the semiconductor element 13 is joined to lead 31. Furthermore, lead 31 is electrically connected to the lower winding 135b via the semiconductor element 11. Therefore, the potential of lead 31 is also the same as the potential of the lower winding 135b. In other words, the potential of lead 31 is the same as the potential of the semiconductor substrate 130 and the potential of the lower winding 135b.

[0037] The lead 31 further includes two terminal portions 312. The two terminal portions 312 extend from both sides of the island portion 311 in the second direction y. The two terminal portions 312 are spaced apart from each other in the second direction y. At least one of the two terminal portions 312 is conductive to the ground of the semiconductor element 11.

[0038] Each terminal portion 312 includes a covered portion 312a and an exposed portion 312b. The covered portion 312a is connected to the island portion 311 and is covered by the sealing resin 5. The exposed portion 312b is connected to the covered portion 312a and is exposed from the sealing resin 5. In plan view, the exposed portion 312b extends along the first direction x. As can be seen from Figure 3, the exposed portion 312b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 312b may be plated, for example, with tin (Sn).

[0039] The lead 32 includes an island portion 321. The island portion 321 has a mounting surface 321a facing one direction (upward) in the third direction z. That is, the mounting surface 321a faces the same direction as each main surface 12a. The semiconductor element 12 is bonded to the mounting surface 321a via a conductive bonding material 129. Each conductive bonding material 129 is, for example, solder, metal paste, or sintered metal. The island portion 321 is covered with a sealing resin 5. In the illustrated example, the island portion 321 is rectangular in plan view. The thickness of the island portion 321 is, for example, 100 μm or more and 300 μm or less.

[0040] The lead 32 further includes two terminal portions 322. The two terminal portions 322 extend from both sides of the island portion 321 in the second direction y. The two terminal portions 322 are spaced apart from each other in the second direction y. At least one of the two terminal portions 322 is conductive to the ground of the semiconductor element 12.

[0041] Each terminal portion 322 includes a covered portion 322a and an exposed portion 322b. The covered portion 322a is connected to the island portion 321 and is covered by the sealing resin 5. The exposed portion 322b is connected to the covered portion 322a and is exposed from the sealing resin 5. In plan view, the exposed portion 322b extends along the first direction x. As can be seen from Figure 3, the exposed portion 322b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 322b may be tin-plated, for example.

[0042] The multiple leads 33 are located on the opposite side of the island 321 with respect to the island 311. The multiple leads 33 are aligned along the second direction y. At least one of the multiple leads 33 is conductive to the semiconductor element 11. The multiple leads 33 include multiple (six in the illustrated example) intermediate leads 33A and two side leads 33B. The two side leads 33B are located on either side of the multiple intermediate leads 33A in the second direction y. Each side lead 33B is located in the second direction y between one of the two terminal portions 312 and the intermediate lead 33A closest to that terminal portion 312. Unlike the illustrated example, the multiple leads 33 may include leads 31 that are positioned outward from either of the two terminal portions 312.

[0043] Each lead 33 includes a covered portion 331 and an exposed portion 332. The covered portion 331 is covered with a sealing resin 5. In the illustrated example, the dimension in the first direction x of each covered portion 331 of the two side leads 33B is greater than the dimension in the first direction x of each covered portion 331 of the multiple intermediate leads 33A. The exposed portion 332 is connected to the covered portion 331 and is exposed from the sealing resin 5. In plan view, the exposed portion 332 extends along the first direction x. As can be seen from Figure 7, when viewed along the second direction y, the exposed portion 332 is bent in a gull-wing shape. The shape of the exposed portion 332 is equal to the shape of each exposed portion 312b of the lead 31. The surface of the exposed portion 332 may be tin-plated, for example.

[0044] The multiple leads 34 are located on the opposite side of the multiple leads 33 with respect to the island portion 311. The multiple leads 34 are aligned along the second direction y. Each of the multiple leads 34 is electrically connected to one of the multiple semiconductor elements 12. The multiple leads 34 include multiple (six in the illustrated example) intermediate leads 34A and two side leads 34B. The two side leads 34B are located one on each side of the multiple intermediate leads 34A in the second direction y. In the second direction y, one of the two terminal portions 322 of a lead 32 is located between one of the two side leads 34B and the intermediate lead 34A closest to that side lead 34B.

[0045] Each lead 34 includes a covering portion 341 and an exposed portion 342. The covering portion 341 is covered with a sealing resin 5. In the illustrated example, the dimension of each covering portion 341 of the two side leads 34B in the first direction x is greater than the dimension of each covering portion 341 of the multiple intermediate leads 34A in the first direction x. The exposed portion 342 is connected to the covering portion 341 and is exposed from the sealing resin 5. In plan view, the exposed portion 342 extends along the first direction x. As can be seen from Figure 7, when viewed along the second direction y, the exposed portion 342 is bent in a gull-wing shape. The shape of the exposed portion 342 is equal to the shape of each exposed portion 322b of the lead 32. The surface of the exposed portion 342 may be tin-plated, for example. Unlike the illustrated example, each of the two side leads 34B may be located in the second direction y between one of the two terminal portions 322 of the lead 32 and the intermediate lead 34A closest to that terminal portion 322.

[0046] Each of the multiple connecting members 4 provides electrical conductivity between two components that are separated from each other. As shown in Figures 1 and 2, the multiple connecting members 4 include multiple wires 41-45. Each of the multiple connecting members 4 is made of a metallic material. The metallic material includes, for example, gold, copper, or copper alloys (e.g., palladium-copper alloy). Unlike the illustrated example, each connecting member 4 may be a bonding ribbon or a plate-shaped metallic member instead of a bonding wire. Alternatively, each connecting member 4 may consist of a core material (e.g., copper) and a surface layer (e.g., palladium) covering the core material.

[0047] Each wire 41 is joined to one of the multiple pads 121 of each semiconductor element 12 and to one of the multiple pads 132 of the semiconductor element 13. Each wire 42 is joined to one of the multiple pads 111 of the semiconductor element 11 and to one of the multiple pads 131 of the semiconductor element 13. Each wire 43 is joined to one of the multiple pads 111 of the semiconductor element 11 and to the covering portion 312a of one of the two terminal portions 312. Each wire 44 is joined to one of the multiple pads 111 of the semiconductor element 11 and to one of the covering portions 331 of the lead 33. Each wire 45 is joined to one of the multiple pads 121 of each semiconductor element 12 and to one of the covering portions 341 of the lead 34. Each connection of the multiple connecting members 4 in the drawing is an example and is not intended to limit the connection relationships. Each connection of the multiple connecting members 4 can be appropriately changed depending on the configuration of the semiconductor device A10.

[0048] Multiple wires 41 electrically connect multiple semiconductor elements 12 and semiconductor elements 13. The multiple wires 41 are arranged along the second direction y. In a plan view, each wire 41 is provided across the island portion 311 of lead 31 and the island portion 321 of lead 32.

[0049] Each wire 41 includes junctions 411, 412 and a loop 413. Junction 411 is the end opposite junction 412. The loop 413 connects junction 411 and junction 412. Figure 8 shows one of the multiple wires 41. Junction 411 is located on pad 132 of semiconductor element 13. Junction 412 is located on pad 121 of one of the multiple semiconductor elements 12. The loop 413 curves from junction 411 toward junction 412.

[0050] Multiple wires 42 electrically connect semiconductor element 11 and semiconductor element 13. Multiple wires 42 are aligned along the second direction y. In a plan view, each wire 42 overlaps each through hole 313.

[0051] Each wire 42 includes joints 421, 422 and a loop 423. Joint 421 is the opposite end of joint 422. The loop 423 connects joints 421 and 422. Figure 8 shows one of several wires 41. The loop 423 connects joints 421 and 422. Joint 421 is located on pad 131 of semiconductor element 13. Joint 422 is located on pad 111 of semiconductor element 11. The loop 423 curves from joint 421 toward joint 422.

[0052] As shown in Figure 8, the highest point of wire 42 in the third direction z is located lower (closer to the island portions 311 and 321 in the third direction z) than the highest point of wire 41 in the third direction z. Alternatively, the highest point of wire 41 in the third direction z may be at the same position as the highest point of wire 42 in the third direction z, or it may be located lower.

[0053] Multiple wires 43 electrically connect the semiconductor element 11 and the lead 31. In this embodiment, one of the two terminal portions 312 is connected to the ground of the semiconductor element 11 via the wire 43.

[0054] Multiple wires 44 electrically connect the semiconductor element 11 and the multiple leads 33. In other words, at least one of the multiple leads 33 conducts to the semiconductor element 13 via the wires 44.

[0055] Multiple wires 45 electrically connect multiple semiconductor elements 12 and multiple leads 34. In other words, at least one of the multiple leads 34 conducts to one of the multiple semiconductor elements 12 via the wires 45.

[0056] The semiconductor device A10 includes a first circuit whose components include a semiconductor element 11, a lead 31, a plurality of leads 33, a plurality of wires 42-44, and a part of the semiconductor element 13 (such as each pad 131 and each lower winding 135b), and a second circuit whose components include a plurality of semiconductor elements 12, a lead 32, a plurality of leads 34, a plurality of wires 41, 45, and a part of the semiconductor element 13 (such as each pad 132 and each upper winding 135a). The plurality of semiconductor elements 12 require a power supply voltage higher than the power supply voltage required for semiconductor element 11. Therefore, a potential difference is generated between semiconductor element 11 and each semiconductor element 12. In other words, the potentials of the first circuit and the second circuit are relatively different. Specifically, the potential of the second circuit is higher than the potential of the first circuit. For example, in inverter devices for electric vehicles and hybrid vehicles, the voltage applied to the ground of semiconductor element 11 is approximately 0V, while the voltage applied to the ground of semiconductor element 12 can transiently exceed 600V. Depending on the specifications of the inverter device, the voltage applied to the ground of semiconductor element 12 can exceed 3750V. The first and second circuits are isolated from each other by semiconductor element 13. Furthermore, semiconductor element 13 can relay signals between the first and second circuits.

[0057] As shown in Figure 1, the sealing resin 5 covers a portion of the conductive support 3, the semiconductor element 11, the multiple semiconductor elements 12, the semiconductor element 13, and the multiple connecting members 4. The sealing resin 5 has electrical insulating properties. The sealing resin 5 insulates the components of the first circuit (e.g., lead 31) from the components of the second circuit (e.g., lead 32). The sealing resin 5 is made of a material including, for example, black epoxy resin. In the illustrated example, the sealing resin 5 is rectangular in plan view.

[0058] As shown in Figures 2 to 5, the sealing resin 5 has a top surface 51, a bottom surface 52, two side surfaces 53, and two side surfaces 54. The top surface 51 and the bottom surface 52 are separated from each other in the third direction z. Each of the top surface 51 and the bottom surface 52 is substantially flat. The two side surfaces 53 are connected to the top surface 51 and the bottom surface 52 and are separated from each other in the first direction x. The two side surfaces 54 are connected to the top surface 51 and the bottom surface 52 and are separated from each other in the second direction y.

[0059] From one of the two sides 53, the exposed portions 312b of the two terminal portions 312 and the exposed portions 332 of the multiple leads 33 are exposed. From the other of the two sides 53, the exposed portions 322b of the two terminal portions 322 and the exposed portions 342 of the multiple leads 34 are exposed. Each of the two sides 53 includes an upper portion 531, a lower portion 532, and an intermediate portion 533. The upper portion 531 has one side in the third direction z connected to the top surface 51 and the other side in the third direction z connected to the intermediate portion 533. The upper portion 531 is inclined with respect to the top surface 51. The lower portion 532 has one side in the third direction z connected to the bottom surface 52 and the other side in the third direction z connected to the intermediate portion 533. The lower portion 532 is inclined with respect to the bottom surface 52. The intermediate portion 533 is connected to the upper portion 531 on one side in the third direction z, and to the lower portion 532 on the other side in the third direction z. The in-plane direction of the intermediate portion 533 is the third direction z and the second direction y. In a plan view, the intermediate portion 533 is located outward from the top surface 51 and the bottom surface 52. From the intermediate portion 533 of the two sides 53, the exposed portions 312b of the two terminal portions 312 (leads 31), the exposed portions 322b of the two terminal portions 322 (leads 32), the exposed portions 332 of the multiple leads 33, and the exposed portions 342 of the multiple leads 34 protrude, respectively.

[0060] Neither of the two sides 54 has exposed leads. Each of the two sides 54 includes an upper section 541, a lower section 542, and an intermediate section 543. The upper section 541 has one side in the third direction z connected to the top surface 51 and the other side in the third direction z connected to the intermediate section 543. The upper section 541 is inclined with respect to the top surface 51. The lower section 542 has one side in the third direction z connected to the bottom surface 52 and the other side in the third direction z connected to the intermediate section 543. The lower section 542 is inclined with respect to the bottom surface 52. The intermediate section 543 has one side in the third direction z connected to the upper section 541 and the other side in the third direction z connected to the lower section 542. The in-plane direction of the intermediate section 543 is the third direction z and the second direction y. In plan view, the intermediate section 543 is located outward from the top surface 51 and the bottom surface 52.

[0061] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 10 to 15. The method for manufacturing the semiconductor device A10 includes a lead frame preparation step, a lead frame processing step, an element mounting step, a wire bonding step, a sealing step, and a piece formation step.

[0062] First, the lead frame preparation process shown in Figure 10 is performed. In the lead frame preparation process, the lead frame 81 is prepared. The lead frame 81 includes a flat plate portion 810, a plurality of support leads 811b, 812b, a plurality of leads 813, 814, an outer frame 815, and a dam bar 816. The lead frame 81 is formed, for example, by punching out a rectangular copper plate in plan view. The plurality of support leads 811b, 812b are connected to the flat plate portion 810 and the dam bar 816. The plurality of leads 813, 814 are connected to the dam bar 816. The dam bar 816 is connected to the outer frame 815. Therefore, the plurality of support leads 811b, 812b and the plurality of leads 813, 814 are connected via the outer frame 815 and the dam bar 816. Of the lead frame 81, the outer frame 815 and the dam bar 816 do not constitute the semiconductor device A10. The lead frame 81 is made of, for example, copper or a copper alloy.

[0063] Next, the lead frame processing steps shown in Figures 11 and 12 are performed. In the lead frame processing steps, first, a resist 82 is formed on the lead frame 81 as shown in Figure 11. In Figure 12, dots are drawn on the resist 82. Then, the lead frame 81 on which the resist 82 has been formed is etched. As a result, the portion of the lead frame 81 exposed from the resist 82 is removed, the flat plate portion 810 is divided into two islands 811a and 812a, and multiple through holes 811c are formed in the flat plate portion 810 (island 811a). After that, the resist 82 is removed to form the lead frame 81 shown in Figure 12. The lead frame 81 has leads 811 and leads 812 formed on it. Lead 811 includes island 811a and multiple support leads 811b connected to island 811a. Lead 812 includes island 812a and multiple support leads 812b connected to island 812a. Thus, in the lead frame processing process, the flat plate portion 810 of the lead frame 81 is divided into two islands 811a and 812a.

[0064] Next, the element mounting process shown in Figure 13 is performed. In the element mounting process, three semiconductor elements 11, 12, and 13 are prepared and mounted on the lead frame 81. Specifically, two semiconductor elements 11 and 13 are bonded to island 811a using a conductive bonding material (not shown), and multiple semiconductor elements 12 are bonded to island 812a using a conductive bonding material (not shown). The multiple semiconductor elements 12 are arranged at intervals d1 in the second direction y.

[0065] Next, the wire bonding process shown in Figure 14 is performed. In the wire bonding process, multiple wires 41 to 45 are formed. Each wire 41 to 45 can be formed using a well-known wire bonder. Wires 41 and 42 can be formed, for example, by ball bonding. In this case, each wire 41 is first bonded to one of the multiple pads 132 to form a joint 411, and then second bonded to the corresponding one of the multiple pads 121 to form a joint 412. Similarly, each wire 42 is first bonded to the corresponding one of the multiple pads 131 to form a joint 421, and then second bonded to one of the multiple pads 111 to form a joint 422. The other wires 43 to 45 can be formed in a similar manner. Alternatively, each wire 41 to 45 can be formed by other methods such as wedge bonding. The order in which each wire 41 to 45 is formed is not particularly limited.

[0066] Next, the sealing process shown in Figure 15 is performed. In the sealing process, a sealing resin 5 is formed. The sealing resin 5 is formed by transfer molding. Specifically, the sealing resin 5 is formed by pouring and filling molten resin from the inlet G. In Figure 15, the sealing resin 5 is shown by a dashed line (double-dotted line), and the inlet G is shown by a dotted line. The inlet G is located near the lowest of the multiple leads 814 (i.e., in the lower right of Figure 15). Alternatively, the inlet G may be located near the lowest of the multiple leads 813 (i.e., in the lower left of Figure 15). In the first direction x, the inlet G is in the same position as the island 812a. In the third direction z, the inlet G may be located below the island 812a.

[0067] Finally, the semiconductor device A10 is manufactured by performing a piece-forming process. In the piece-forming process, the device is pieced by dicing. Specifically, multiple leads 811, 812, 813, and 814, which were connected to each other by the outer frame 815 and dam bar 816, are separated as appropriate. Leads 33, 32, 33, and 34 are formed from leads 811, 812, 813, and 814, respectively. Island 811a becomes island portion 311, and each support lead 811b becomes terminal portion 312. Island 812a becomes island portion 321, and each support lead 812b becomes terminal portion 322. Multiple leads 33 (multiple leads 813) and multiple leads 34 (multiple leads 814) may be bent during the punching process in the piece-forming process or the lead frame preparation process.

[0068] The method for manufacturing the semiconductor device A10 is not limited to the examples described above. For example, the lead frame processing step can be omitted by forming two islands 811a and 812a by punching in the lead frame preparation step. Alternatively, for example, a rectangular copper plate in plan view can be prepared in the lead frame preparation step, and the leads 811 (island 811a and multiple support leads 811b), leads 812 (island 812a and multiple support leads 812b), multiple leads 813 and 814, an outer frame 815, and a dam bar 816 can be formed all at once from the prepared copper plate by forming a resist 82 and etching in the lead frame processing step.

[0069] Next, an example of the electrical configuration of semiconductor device A10 will be explained with reference to Figure 16. Figure 16 schematically illustrates semiconductor element 11, multiple semiconductor elements 12, semiconductor element 13, multiple wires 41, and multiple wires 42. Furthermore, Figure 16 illustrates the electrical configuration of each semiconductor element 11, 12, and 13 with dashed lines.

[0070] Semiconductor elements 11 and 13 include the same number of electrical configurations as the number of semiconductor elements 12. In the illustrated example, semiconductor element 11 includes four circuits 11C, each of the four semiconductor elements 12 includes one circuit 12C, and semiconductor element 13 includes four circuits 13C. The four circuits 11C are electrically connected to the four circuits 12C, respectively, via corresponding wires 41 and 42, and the four circuits 13C. That is, semiconductor device A10 may include multiple physically independent electrical configurations depending on the number of semiconductor elements 12. In the example shown in the figure, two adjacent circuits 12C are arranged with a gap d11 between them.

[0071] The operation and effects of semiconductor device A10 are as follows:

[0072] The semiconductor device A10 is advantageous in reducing interference between multiple circuits. Generally, in semiconductor devices comprising multiple semiconductor elements, interference between circuits can occur if the distance between the electrical contacts of the semiconductor elements is insufficient. In contrast, in semiconductor device A10, the multiple semiconductor elements 12 have a different potential from the semiconductor element 11 and are spaced apart so as to be aligned along the second direction y. With this configuration, short circuits between the electrical contacts of the multiple semiconductor elements 12 can be reliably prevented. In other words, this configuration is advantageous in reducing interference between circuits.

[0073] Each of the multiple semiconductor elements 12 includes a circuit 12C. A portion of the sealing resin 5 is interposed between adjacent circuits 12C. This makes it possible to further enhance the insulation between adjacent circuits 12C and reduce the spacing d11. For example, unlike this example, in a configuration in which one semiconductor element 12 contains multiple circuits 12C, two adjacent circuits 12C can be connected by a semiconductor material. In this case, in order to properly ensure the insulation between two adjacent circuits 12C, it may be necessary to make the distance between them greater than the spacing d11. Therefore, the semiconductor device A10 can be miniaturized.

[0074] The semiconductor device A10 is advantageous for miniaturization. Conventionally, in semiconductor devices having two leads with a potential difference, when a semiconductor element is provided on one of the leads, a method has been employed to reduce dielectric breakdown by making the element large. On the other hand, the semiconductor device A10 includes a plurality of semiconductor elements 12 spaced apart from each other on the lead 32. Therefore, the distance between the plurality of semiconductor elements 12 can be shortened, and the lead 32 can be miniaturized. Thus, with this configuration, the semiconductor device A10 can be miniaturized.

[0075] The semiconductor elements 11 and 13 each include multiple circuits 11C and 13C, respectively, corresponding to the number of semiconductor elements 12. The circuit 11C of semiconductor element 11 may be electrically connected to one of the circuits 12C of the multiple semiconductor elements 12. In such a configuration, for example, an electrical signal via each lead 33 is transmitted individually from semiconductor element 11 through semiconductor element 13 to one of the multiple semiconductor elements 12. This means that electrical signals can be transmitted independently through each of the multiple semiconductor elements 12. Compared to the case where such a circuit configuration is realized with a single semiconductor element 12, the semiconductor device A10 has a sealing resin 5 interposed between the multiple semiconductor elements 12, so that electrical signals are separated more reliably between the multiple semiconductor elements 12. Therefore, the multiple semiconductor elements 12 can be placed close to each other. Thus, such a configuration is advantageous for miniaturization.

[0076] Next, other embodiments and modifications of the semiconductor device of the present disclosure will be described. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise. Hereinafter, the same or similar components are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. In addition, descriptions of the manufacturing methods of the semiconductor device according to the other embodiments and modifications will be omitted as appropriate. The semiconductor device according to the other embodiments and modifications can be manufactured in the same manner as semiconductor device A10, taking into consideration common technical knowledge.

[0077] Figures 17 and 18 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the position of the semiconductor element 13. Specifically, in the semiconductor device A10, the semiconductor element 13 is located on lead 31 (island portion 311), whereas in the semiconductor device A11, it is mounted on lead 32 (island portion 321).

[0078] In semiconductor device A11, the semiconductor element 13 is bonded to the island portion 321 by a conductive bonding material 139. In this configuration, the semiconductor substrate 130 and the seal ring portion 133 of the semiconductor element 13 are at the same potential as the lead 32. That is, the seal ring portion 133 is at the same potential as the second circuit described above.

[0079] Each wire 41 is provided across leads 31 and 32. In semiconductor device A11, unlike semiconductor device A10, the semiconductor element 13 is mounted on lead 32, so the seal ring portion 133 is at the same potential as the island portion 321 and can become a component of the second circuit. On the other hand, since the wire 41 is conductive to the semiconductor element 11, it is at the same potential as the semiconductor element 11 and remains a component of the first circuit. In other words, relatively, the seal ring portion 133 is at a higher potential and the wire 41 is at a lower potential, resulting in a potential difference between the seal ring portion 133 and the wire 41.

[0080] In semiconductor device A11, the semiconductor element 13 is bonded to the island portion 321 by a conductive bonding material 139. In this configuration, the semiconductor substrate 130 and the seal ring portion 133 of the semiconductor element 13 are at the same potential as the lead 32. In other words, the seal ring portion 133 is at the same potential as the second circuit described above.

[0081] Semiconductor device A11, like semiconductor device A10, is advantageous in reducing the occurrence of dielectric breakdown. As can be seen from this modification, in the semiconductor device of the present disclosure, the semiconductor element 13 may be mounted on either lead 31 or lead 32.

[0082] Second embodiment: Figures 19 to 21 show a semiconductor device A20 according to the second embodiment. The arrangement of the multiple semiconductor elements 12 in semiconductor device A20 differs from that of semiconductor device A10.

[0083] In this embodiment, the plurality of semiconductor elements 12 includes a plurality of semiconductor elements 12A arranged in a first column and a plurality of semiconductor elements 12B arranged in a second column spaced apart from the first column in a first direction x. The first column is closer to the lead 31 than the second column. A "column" refers to the arrangement of a group of elements that are aligned in a certain direction. In the illustrated example, the first and second columns are straight lines parallel to the second direction y. Alternatively, the first and second columns do not have to be parallel to the second direction y and may be curved. Furthermore, the number of columns in which the plurality of semiconductor elements 12 are arranged may be two or more. The number of semiconductor elements 12 arranged in the first or second column is not particularly limited, but in the illustrated example, two semiconductor elements 12A and two semiconductor elements 12B are provided. Alternatively, the number of semiconductor elements arranged in the first or second column may be one.

[0084] Multiple semiconductor elements 12A are regularly arranged between multiple semiconductor elements 12B. Specifically, multiple semiconductor elements 12A may be arranged point-symmetrically with respect to multiple semiconductor elements 12B. In the illustrated example, multiple semiconductor elements 12 are arranged in a staggered pattern. A "staggered pattern" refers to an arrangement of multiple elements where adjacent rows are alternately offset. That is, multiple semiconductor elements 12A arranged in the first row are located between multiple semiconductor elements 12B arranged in the second row in the second direction y. Two adjacent semiconductor elements 12 are not facing each other in the second direction y. In the illustrated example, multiple semiconductor elements 12 are arranged with a gap d1 between them in the second direction y. The gap d1 corresponds to the distance along the second direction y between the extension of the first side 12a1 and the second side 12a2 of two adjacent semiconductor elements 12 (i.e., between semiconductor element 12A and semiconductor element 12B). The distance between adjacent semiconductor elements 12A and semiconductor elements 12B in the second direction y may be irregular.

[0085] Each semiconductor element 12 includes a third side 12a3 at the position furthest from the lead 31. The third side 12a3 of each semiconductor element 12A is spaced at a distance d2 along the first direction relative to the extension of the third side 12a3 of each semiconductor element 12B. The distance d2 is illustrated in Figure 20. When multiple semiconductor elements 12 are arranged linearly along the second direction y, as in semiconductor device A10, there is a possibility of placement errors in the first direction x for each of the multiple semiconductor elements 12. It is preferable that the distance d2 is greater than such errors. For example, the distance d2 is 50 μm or more. In other words, the edge of semiconductor element 12A in the first direction x is spaced at least 50 μm along the first direction x relative to the edge of semiconductor element 12B in the first direction x. The distances along the first direction x between multiple semiconductor elements 12A and multiple semiconductor elements 12B may all be equal.

[0086] Each semiconductor element 12 includes a fourth side 12a4 at the position closest to the lead 31. In the illustrated example, the fourth side 12a4 of each semiconductor element 12B coincides with the third side 12a3 of each semiconductor element 12A when viewed in the second direction y. Alternatively, the fourth side 12a4 of each semiconductor element 12B does not have to coincide with the third side 12a3 of each semiconductor element 12A when viewed in the second direction y.

[0087] Referring to Figures 19 and 20, the first geometric centroid Ga of multiple semiconductor elements 12A as viewed in the third direction z, and the second geometric centroid Gb of multiple semiconductor elements 12B as viewed in the third direction z are illustrated. In semiconductor device A20, the first geometric centroid Ga is located diagonally to the second geometric centroid Gb in a plan view. Therefore, compared to semiconductor device A10, the distance between the geometric centroids of multiple semiconductor elements 12 is larger in semiconductor device A20. Although optional, the first geometric centroid Ga of multiple semiconductor elements 12A may be aligned in the first direction x. Furthermore, the second geometric centroid Gb of multiple semiconductor elements 12B may be aligned in the first direction x.

[0088] Furthermore, Figure 20 illustrates the angle θ. The angle θ corresponds to the angle formed by the line segments connecting the second geometric centroids Gb of the multiple semiconductor elements 12B with respect to the first geometric centroid Ga of one of the multiple semiconductor elements 12A. Alternatively, the angle θ corresponds to the angle formed by the line segments connecting the two first geometric centroids Ga of the multiple semiconductor elements 12A with respect to the second geometric centroid Gb of one of the multiple semiconductor elements 12B. The angle θ is, for example, between 30° and 330°. The semiconductor device A10 according to the first embodiment corresponds to the case where the angle θ is 180°. The semiconductor device A20 according to this embodiment corresponds to the case where the angle θ is between 30° and less than 180°.

[0089] The operation and effects of semiconductor device A20 are as follows:

[0090] Similar to semiconductor device A10, semiconductor device A20 is configured such that multiple semiconductor elements 12 are spaced apart along the second direction y, which is advantageous in reducing the occurrence of dielectric breakdown.

[0091] The semiconductor device A20 can reduce the occurrence of voids in the encapsulating resin 5. Voids in the encapsulating resin 5 are a cause of dielectric breakdown. The semiconductor device A20 includes a plurality of semiconductor elements 12A arranged in a first row and a plurality of semiconductor elements 12B arranged in a second row spaced apart from the first row in a first direction x. With this configuration, when manufacturing the semiconductor device A20, the resin poured in from the inlet G can easily flow around the plurality of semiconductor elements 12. This is because the resin can easily get between the first side 12a1 and the second side 12a2 of two adjacent semiconductor elements 12. As a result, air bubbles are less likely to remain near the plurality of semiconductor elements 12, thus reducing the occurrence of voids in the encapsulating resin 5. Therefore, the semiconductor device A20 is even more advantageous in reducing the occurrence of dielectric breakdown.

[0092] The semiconductor device A20 can reduce the wire flow of the wire 45. Of the multiple semiconductor elements 12, the semiconductor element 12 closest to the inlet G is closer to one of the two side leads 34B in semiconductor device A20 compared to semiconductor device A10. As a result, the distance between the pad 121 of the semiconductor element 12 and the covering portion 341 of the side lead 34B becomes smaller. Consequently, the component of the wire 45 that is joined to the pad 121 and the covering portion 341 that extends in the first direction x is reduced. Therefore, the direction in which the wire 45 extends tends to be parallel to the flow of the resin. This reduces the influence of the poured resin on the wire 45 and reduces the possibility of defects occurring in the wire 45.

[0093] Each semiconductor element 12A includes a third side 12a3 at the position furthest from the lead 31, and each semiconductor element 12B includes a third side 12a3 at the position furthest from the lead 31. The third side 12a3 of each semiconductor element 12A may be separated from the third side 12a3 of each semiconductor element 12B by 50 μm or more along the first direction. Such a configuration is even more advantageous in reducing the occurrence of dielectric breakdown because a distance is ensured between each semiconductor element 12A and each semiconductor element 12B.

[0094] Each semiconductor element 12B includes a fourth side 12a4 closest to the lead 31. The fourth side 12a4 of each semiconductor element 12B does not need to overlap with the third side 12a3 of each semiconductor element 12A when viewed in the second direction y. This means that there is a gap in the first direction x between each semiconductor element 12A and each semiconductor element 12B. Due to this gap, the resin flowing from the inlet G toward the multiple semiconductor elements 12 can spread more smoothly in the second direction y. As a result, fewer bubbles remain near the multiple semiconductor elements 12, thus reducing the generation of voids in the sealing resin 5. Therefore, such a configuration is even more advantageous in reducing the occurrence of dielectric breakdown.

[0095] The multiple semiconductor elements 12B may include a semiconductor element 12B positioned between two semiconductor elements 12A arranged in the first row in the second direction y. That is, the first side 12a1 and the second side 12a2 of any two adjacent semiconductor elements 12 do not need to face each other. This makes it easier for the resin to penetrate between the first side 12a1 and the second side 12a2 of two adjacent semiconductor elements 12. For this reason, such a configuration can further reduce the occurrence of voids in the sealing resin 5.

[0096] Each semiconductor element 12A contains a first geometric centroid Ga when viewed in the third direction z, and each first geometric centroid Ga may be aligned in the first direction x. With this configuration, it becomes easier to arrange multiple semiconductor elements 12 densely in the second direction y, and thus the dimensions of the semiconductor device A20 in the second direction y can be reduced.

[0097] Furthermore, each semiconductor element 12B includes a second geometric centroid Gb when viewed in the third direction z, and each second geometric centroid Gb may be aligned in the first direction x. With this configuration, since the multiple semiconductor elements 12 are regularly arranged in two rows in the first direction x, heat from the multiple semiconductor elements 12 can be efficiently dispersed.

[0098] Multiple semiconductor elements 12A can be arranged point-symmetrically with respect to multiple semiconductor elements 12B. With this configuration, the bias in the arrangement of multiple semiconductor elements 12 on the island portion 321 can be reduced. This is advantageous in making the lead 32 less prone to deformation.

[0099] Figures 22 and 23 show a semiconductor device A21 according to the first modification of the second embodiment. The arrangement of the multiple semiconductor elements 12 in semiconductor device A21 differs from that of semiconductor device A20. Specifically, the staggered arrangement of the multiple semiconductor elements 12 is reversed. More specifically, the positions of the first row (multiple semiconductor elements 12A) and the second row (multiple semiconductor elements 12B) in the first direction x are swapped. That is, the second row is closer to the lead 31 than the first row. This corresponds to the case where the angle θ described above is greater than 180° and less than or equal to 330°.

[0100] Semiconductor device A21 provides similar effects to semiconductor device A20. For example, semiconductor device A21 is advantageous in reducing the occurrence of dielectric breakdown. As can be seen from this modification, the arrangement of each semiconductor element 12A and each semiconductor element 12B in the semiconductor device of this disclosure is not particularly limited.

[0101] When the claims include examples shown in semiconductor device A20 and semiconductor device A21, the terms may correspond as follows: Leads 31, 32, and 34 correspond to “first lead,” “second lead,” and “third lead,” respectively. Furthermore, semiconductor element 11 and the plurality of semiconductor elements 12 may correspond to “at least one first semiconductor element” and “the plurality of second semiconductor elements,” respectively. Furthermore, pad 121 may correspond to “first pad.” Furthermore, the third side 12a3 of semiconductor element 12A, the third side 12a3 of semiconductor element 12B, and the fourth side 12a4 of semiconductor element 12A may correspond to “first end,” “second end,” and “third end,” respectively. Furthermore, wires 45 and 41 may correspond to “first wire” and “second wire,” respectively. In addition, pad 132 may correspond to the "second pad," pad 131 to the "third pad," and seal ring portion 133 to the "seal ring portion."

[0102] Third embodiment: Figures 24 to 27 show a semiconductor device A30 according to the third embodiment. The configuration of the multiple semiconductor elements 11, 12, and 13 in semiconductor device A30 differs from that of semiconductor device A10 and semiconductor device A20. Specifically, semiconductor device A30 comprises multiple semiconductor elements 11 arranged in a staggered pattern on a lead 31, one semiconductor element 12 arranged on a lead 32, and one semiconductor element 13 arranged on a lead 32. That is, the number of semiconductor elements 11 in this embodiment is two or more, and they are arranged in two rows in the first direction x. In the manufacturing of semiconductor device A30, it is preferable that the inlet G is provided near the lead 31.

[0103] Multiple semiconductor elements 11 are arranged along a second direction y. The multiple semiconductor elements 11 include multiple semiconductor elements 11A arranged in a first column and multiple semiconductor elements 11B arranged in a second column spaced apart from the first column in the first direction x. The first column is closer to the lead 31 than the second column. As explained in semiconductor device A21, the second column may be closer to the lead 31 than the first column. The number of columns in which the multiple semiconductor elements 11 are arranged may be two or more. The multiple semiconductor elements 11A overlap each other when viewed in the second direction y, and the multiple semiconductor elements 11B overlap each other when viewed in the second direction y.

[0104] Each semiconductor element 11, in plan view, includes a first side 11a1, a second side 11a2, a third side 11a3, and a fourth side 11a4. The first side 11a1, the second side 11a2, the third side 11a3, and the fourth side 11a4 correspond to the ends of each main surface 11a in the first direction x and the second direction y. The first side 11a1 and the second side 11a2 are separated from each other in the second direction y. The third side 11a3 and the fourth side 11a4 are separated from each other in the first direction x. The shape of the main surface 11a is not limited to the illustrated example, and the main surface 11a does not have to include at least one of the first side 11a1, the second side 11a2, the third side 11a3, and the fourth side 11a4.

[0105] Multiple semiconductor elements 11A are regularly arranged between multiple semiconductor elements 11B. Specifically, multiple semiconductor elements 11A may be arranged point-symmetrically with respect to multiple semiconductor elements 11B. In the illustrated example, multiple semiconductor elements 11 are arranged in a staggered pattern. Multiple semiconductor elements 11A arranged in the first column are located between multiple semiconductor elements 11B arranged in the second column in the second direction y. Two adjacent semiconductor elements 11 are not facing each other in the second direction y. Referring to Figures 24 and 25, multiple semiconductor elements 11 are arranged at intervals d1 from each other in the second direction y. Each semiconductor element 11 includes a first side 11a1 and a second side 11a2 separated in the second direction y in a plan view. The first side 11a1 of semiconductor element 1B faces the second side 11a2 of the adjacent semiconductor element 11A in the second direction y. The interval d1 corresponds to the distance between the first side 11a1 and the second side 11a2 of two adjacent semiconductor elements 11. The distance between adjacent semiconductor elements 11A and 11B in the second direction y may be irregular.

[0106] Each semiconductor element 11 includes a fourth side 11a4 at the position furthest from the lead 32. The fourth side 11a4 of semiconductor element 11A is spaced d2 apart along the first direction from the extension of the fourth side 11a4 of semiconductor element 11B. Referring to Figure 25, the spacing d2 in this embodiment is illustrated. The distances along the first direction x between multiple semiconductor elements 11A and multiple semiconductor elements 11B may be different from each other.

[0107] Each semiconductor element 11 includes a third side 11a3 at the position closest to the lead 32. In the illustrated example, the third side 11a3 of each semiconductor element 11A does not overlap with the fourth side 11a4 of each semiconductor element 11B when viewed in the second direction y. Alternatively, the third side 11a3 of each semiconductor element 11A may overlap with the fourth side 11a4 of each semiconductor element 11B when viewed in the second direction y.

[0108] Figures 24 and 25 illustrate the first geometric centroid Ga of a plurality of semiconductor elements 11A as viewed in the third direction z, and the second geometric centroid Gb of a plurality of semiconductor elements 11B as viewed in the third direction z. In semiconductor device A30, the first geometric centroid Ga is located diagonally to the second geometric centroid Gb in a plan view. Therefore, in semiconductor device A30, similar to semiconductor device A20, the distance between the geometric centroids of the plurality of semiconductor elements 11 is large. Although optional, the first geometric centroids Ga of the plurality of semiconductor elements 11A may be aligned in the first direction x. Furthermore, the second geometric centroids Gb of the plurality of semiconductor elements 11B may be aligned in the first direction x. Furthermore, the plurality of semiconductor elements 11 are configured to form an angle θ. The angle θ corresponds to the angle formed by the line segments connecting the two second geometric centroids Gb of the plurality of semiconductor elements 11B with respect to the first geometric centroid Ga of one of the plurality of semiconductor elements 11A. Alternatively, angle θ corresponds to the angle formed by the line segments connecting the two first geometric centroids Ga of the multiple semiconductor elements 11A to the second geometric centroid Gb of one of the multiple semiconductor elements 11B.

[0109] Next, an example of the electrical configuration of semiconductor device A30 will be explained with reference to Figure 27. Figure 27 schematically illustrates multiple semiconductor elements 11, 12, 13, multiple wires 41, and multiple wires 42. Furthermore, Figure 27 illustrates the electrical configuration of each semiconductor element 11, 12, and 13 with dashed lines.

[0110] Semiconductor elements 12 and 13 include the same number of electrical configurations as the number of semiconductor elements 11. In the illustrated example, four semiconductor elements 11 each include one circuit 11C, semiconductor element 12 includes four circuits 12C, and semiconductor element 13 includes four circuits 13C. The four circuits 11C are electrically connected to the four circuits 12C via corresponding wires 41 and 42, and via the four circuits 13C. That is, the semiconductor device A30 may include multiple physically independent electrical configurations depending on the number of semiconductor elements 11. In the example shown in the figure, two adjacent circuits 11C are placed with a gap d11 between them.

[0111] The operation and effects of semiconductor device A30 are as follows:

[0112] Similar to semiconductor device A10, semiconductor device A30 is configured such that multiple semiconductor elements 12 are spaced apart along the second direction y, which is advantageous in reducing the occurrence of dielectric breakdown.

[0113] The semiconductor device A30 includes a plurality of semiconductor elements 11 arranged in two rows in a first direction x. With this configuration, the lead 31 (especially the island portion 311) can be miniaturized. Furthermore, when manufacturing the semiconductor device A30, the resin poured in from the inlet G can easily flow around the plurality of semiconductor elements 11. In particular, when the inlet G is located near the lead 31, the resin can easily flow around the plurality of semiconductor elements 11 in the resin flow path. As a result, air bubbles are less likely to remain near the plurality of semiconductor elements 11, and voids are less likely to occur in the sealing resin 5. Therefore, the semiconductor device A30 is even more advantageous in reducing dielectric breakdown while miniaturizing the device.

[0114] The semiconductor device A30 can reduce the wire flow of the wire 44. Of the multiple semiconductor elements 11, the semiconductor element 11 closest to the inlet G is close to the tip of one of the two side leads 33B. Therefore, the distance between the pad 111 of the semiconductor element 11 and the covering portion 331 of the side lead 33B becomes smaller. As a result, the component of the wire 44 that extends in the first direction x is reduced when joined between the pad 111 and the covering portion 331. Therefore, the direction in which the wire 44 extends tends to be parallel to the flow of the resin. This reduces the influence of the poured resin on the wire 44 and reduces the possibility of defects occurring in the wire 44.

[0115] Each semiconductor element 11A arranged in the first row includes a fourth side 11a4 at the position furthest from the lead 32, and each semiconductor element 11B arranged in the second row includes a fourth side 11a4 at the position furthest from the lead 32. The fourth side 11a4 of each semiconductor element 11A may be separated from the fourth side 11a4 of each semiconductor element 11B by 50 μm or more along the first direction. Such a configuration is even more advantageous in reducing the occurrence of dielectric breakdown because a distance is ensured between each semiconductor element 11A and each semiconductor element 11B.

[0116] Each semiconductor element 11A includes a third side 11a3 at the position closest to the lead 32. The third side 11a3 of each semiconductor element 11A does not need to overlap with the fourth side 11a4 of each semiconductor element 11B arranged in the first row when viewed in the second direction y. This means that there is a gap in the first direction x between each semiconductor element 11A and each semiconductor element 11B. Due to this gap, the resin flowing from the inlet G toward the multiple semiconductor elements 11 can spread more smoothly in the second direction y. As a result, fewer bubbles remain near the multiple semiconductor elements 11, thus reducing the generation of voids in the sealing resin 5. Therefore, such a configuration is even more advantageous in reducing the occurrence of dielectric breakdown.

[0117] The semiconductor element 11B arranged in the second row may be located between the two semiconductor elements 11A arranged in the first row in the second direction y. That is, the first side 11a1 and the second side 11a2 of any two adjacent semiconductor elements 11 do not have to face each other. This makes it easier for the resin to penetrate between the first side 11a1 and the second side 11a2 of the two adjacent semiconductor elements 11. For this reason, this configuration can further reduce the occurrence of voids in the sealing resin 5.

[0118] Each semiconductor element 11A arranged in the first row includes a first geometric centroid Ga when viewed in the third direction z, and each first geometric centroid Ga may be aligned in the first direction x. With this configuration, it becomes easier to arrange multiple semiconductor elements 11 densely in the second direction y, and thus the dimensions of the semiconductor device A30 in the second direction y can be reduced.

[0119] Furthermore, each semiconductor element 11B arranged in the second column includes a second geometric centroid Gb when viewed in the third direction z, and each second geometric centroid Gb may be aligned in the first direction x. With this configuration, since the multiple semiconductor elements 11 are regularly arranged in two columns in the first direction x, heat from the multiple semiconductor elements 11 can be efficiently dispersed.

[0120] Multiple semiconductor elements 11A can be arranged point-symmetrically with respect to multiple semiconductor elements 11B. With this configuration, the bias in the arrangement of multiple semiconductor elements 11 on the island portion 311 can be reduced. This is advantageous in making the lead 31 less prone to deformation.

[0121] The semiconductor elements 12 and 13 each include multiple circuits 12C and 13C, respectively, corresponding to the number of semiconductor elements 11. The circuit 12C of semiconductor element 12 may be electrically connected to one of the circuits 11C of the multiple semiconductor elements 11. In such a configuration, for example, electrical signals via each lead 34 are individually transmitted from semiconductor element 12 through semiconductor element 13 to one of the multiple semiconductor elements 11. This means that electrical signals can be transmitted independently through each of the multiple semiconductor elements 11. Compared to the case where such a circuit configuration is realized with a single semiconductor element 11, the semiconductor device A30 has a sealing resin 5 interposed between the multiple semiconductor elements 11, so that electrical signals are separated more reliably between the multiple semiconductor elements 11. Therefore, the multiple semiconductor elements 11 can be placed close to each other. Thus, such a configuration is advantageous for miniaturization while reducing dielectric breakdown.

[0122] If the claims include the example shown in semiconductor device A30, the terms may correspond as follows: Leads 31, 32, and 33 correspond to "second lead," "first lead," and "third lead," respectively. Furthermore, the multiple semiconductor elements 11 and 12 may correspond to "multiple second semiconductor elements" and "at least one first semiconductor element," respectively. Furthermore, pad 111 may correspond to "first pad." Furthermore, the fourth side 11a4 of semiconductor element 11A, the fourth side 11a4 of semiconductor element 11B, and the third side 11a3 of semiconductor element 11A may correspond to "first end," "second end," and "third end," respectively. Furthermore, wires 44 and 41 may correspond to "first wire" and "second wire," respectively. In addition, pad 132 may correspond to "second pad," pad 131 to "third pad," and seal ring portion 133 to "seal ring portion."

[0123] Fourth embodiment: Figures 28 to 30 show a semiconductor device A40 according to the fourth embodiment. The configuration of the multiple semiconductor elements 11, 12, and 13 in semiconductor device A40 differs from that of semiconductor devices A10, A20, and A30. In semiconductor device A40, multiple semiconductor elements 12 are arranged in a staggered pattern, as in semiconductor device A20, and multiple semiconductor elements 11 are arranged in a staggered pattern, as in semiconductor device A30. In the description of semiconductor device A40, parts that overlap with semiconductor devices A20 and A30 have been omitted.

[0124] In this embodiment, the plurality of semiconductor elements 11 includes a plurality of semiconductor elements 11A arranged in a first column and a plurality of semiconductor elements 11B arranged in a second column spaced apart from the first column in a first direction x. Furthermore, the plurality of semiconductor elements 12 includes a plurality of semiconductor elements 12A arranged in a third column and a plurality of semiconductor elements 12B arranged in a fourth column spaced apart from the third column in a first direction x. The first and second columns may be reversed, and furthermore, the third and fourth columns may be reversed.

[0125] The first side 11a1 and the second side 11a2 of two adjacent semiconductor elements 11 may be separated by a distance d1. Furthermore, the first side 12a1 and the second side 12a2 of two adjacent semiconductor elements 12 may be separated by a distance d1. The fourth side 11a4 of semiconductor element 11B may be separated by a distance d2 along the first direction from the extension of the fourth side 11a4 of semiconductor element 11A. Furthermore, the third side 12a3 of semiconductor element 12A may be separated by a distance d2 along the first direction from the extension of the third side 12a3 of semiconductor element 12B. In this way, multiple semiconductor elements 11 may be arranged regularly, similar to multiple semiconductor elements 12. More specifically, the geometric centroids of multiple semiconductor elements 11 and multiple semiconductor elements 12 may be located similarly. Figure 28 illustrates the first geometric centroid Ga of multiple semiconductor elements 11A as viewed in the third direction z, the second geometric centroid Gb of multiple semiconductor elements 11B as viewed in the third direction z, the third geometric centroid Ga of multiple semiconductor elements 12A as viewed in the third direction z, and the fourth geometric centroid Gb of multiple semiconductor elements 12B as viewed in the third direction z. Each first geometric centroid Ga may be aligned with each third geometric centroid Ga in the second direction y, and each second geometric centroid Gb may be aligned with each fourth geometric centroid Gb in the second direction y.

[0126] Next, an example of the electrical configuration of semiconductor device A40 will be explained with reference to Figure 30. Figure 30 schematically illustrates multiple semiconductor elements 11, multiple semiconductor elements 12, multiple semiconductor elements 13, multiple wires 41, and multiple wires 42. Furthermore, Figure 30 illustrates the electrical configuration of each semiconductor element 11, 12, and 13 with dashed lines.

[0127] The semiconductor element 13 includes the same number of electrical configurations as the plurality of semiconductor elements 11 and plurality of semiconductor elements 12. In the illustrated example, four semiconductor elements 11 each include one circuit 11C, four semiconductor elements 12 each include one circuit 12C, and semiconductor element 13 includes four circuits 13C. The four circuits 11C are electrically connected to the four circuits 12C, respectively, via the four circuits 13C through the corresponding wires 41 and 42. That is, the semiconductor device A40 may include multiple physically independent electrical configurations depending on the number of plurality of semiconductor elements 11 and plurality of semiconductor elements 12. In the example shown in the figure, two adjacent circuits 11C and two adjacent circuits 12C are arranged with a gap d11 between them. Alternatively, the gap between two adjacent circuits 11C may be different from the gap between two adjacent circuits 12C.

[0128] The operation and effects of semiconductor device A40 are as follows:

[0129] Similar to semiconductor device A10, semiconductor device A40 is configured such that multiple semiconductor elements 12 are spaced apart along the second direction y, which is advantageous in reducing the occurrence of dielectric breakdown. Furthermore, semiconductor device A40 can achieve similar effects to semiconductor devices A20 and A30 by sharing the same configuration.

[0130] The semiconductor device A40 includes a plurality of semiconductor elements 12 arranged in a staggered pattern and a plurality of semiconductor elements 11 arranged in a staggered pattern. Therefore, both the lead 31 (especially the island portion 311) and the lead 32 (especially the island portion 321) can be miniaturized.

[0131] In semiconductor device A40, multiple semiconductor elements 11 and multiple semiconductor elements 12 are arranged in a regular pattern. This allows for efficient heat dissipation in both leads 31 and 32. This is advantageous for passing large currents through semiconductor device A40.

[0132] In semiconductor device A40, each first geometric centroid Ga may be aligned with each third geometric centroid Ga in the second direction y, and each second geometric centroid Gb may be aligned with each fourth geometric centroid Gb in the second direction y. With such a configuration, the manufacturing of semiconductor device A40 becomes more efficient. This is because the positions of the geometric centroids of the multiple semiconductor elements 11,12 are aligned, making it easier to perform alignment such as wire bonding.

[0133] The semiconductor element 13 includes multiple circuits 13C corresponding to the number of semiconductor elements 11 and 12. With this configuration, a signal passing through one of the semiconductor elements 11 is transmitted to one of the semiconductor elements 12 via one of the circuits 13C. A sealing resin 5 is interposed between the semiconductor elements 11 and also between the semiconductor elements 12. Therefore, the semiconductor device A40 can transmit current through the leads 33 more independently. This is advantageous for further improving the dielectric strength of the semiconductor device A40.

[0134] If the claims include the example shown in semiconductor device A40, the terms may correspond as follows: Leads 31, 32, and 34 correspond to "first lead," "second lead," and "third lead," respectively. Furthermore, the plurality of semiconductor elements 11 and plurality of semiconductor elements 12 may correspond to "at least one first semiconductor element" and "plural second semiconductor elements," respectively. Furthermore, pad 121 may correspond to "first pad." Furthermore, the third side 12a3 of semiconductor element 12A, the third side 12a3 of semiconductor element 12B, and the fourth side 12a4 of semiconductor element 12A may correspond to "first end," "second end," and "third end," respectively. Furthermore, wires 45 and 41 may correspond to "first wire" and "second wire," respectively. In addition, pad 132 may correspond to "second pad," pad 131 to "third pad," and seal ring portion 133 to "seal ring portion."

[0135] The semiconductor device and method for manufacturing the semiconductor device as claimed in this disclosure are not limited to the embodiments described above. The specific configuration of each part of the semiconductor device and the specific processing of each step of the method for manufacturing the semiconductor device are subject to various design modifications. For example, the semiconductor device and method for manufacturing the semiconductor device include embodiments relating to the following appendices. Examples of each component and each step (each processing) in the following appendices are shown in parentheses using the reference numerals from the embodiments (including modified examples) described above, but are not limited thereto. Note 1. First lead (31,32), A second lead (31,32) separated from the first lead (31,32) in the first direction (x), At least one first semiconductor element (11,12) mounted on the first lead (31,32), Multiple second semiconductor elements (11, 12) mounted on the second lead (31, 32), A third semiconductor element (13) mounted on the first lead (31,32) or the second lead (31,32), The device comprises a sealing resin (5) covering the first leads (31, 32), the second leads (31, 32), the at least one first semiconductor element (11, 12), the plurality of second semiconductor elements (11, 12), and the third semiconductor element (13), The third semiconductor element (13) is interposed between the at least one first semiconductor element (11,12) and the plurality of second semiconductor elements (11,12) such that the plurality of second semiconductor elements (11,12) have different potentials. The plurality of second semiconductor elements (11,12) are arranged along a second direction (y) that is orthogonal to the first direction (x), forming a semiconductor device (A10, A20, A30, A40). Note 2. The plurality of second semiconductor elements (11, 12) include second semiconductor elements (11A, 12A) arranged in a first row and second semiconductor elements (11B, 12B) arranged in a second row spaced apart from the first row in the first direction (x), as described in Appendix 1, the semiconductor device (A20, A30, A40). Note 3. The second semiconductor elements (11A, 12A) arranged in the first row include a first end (11a4, 12a3) at the position furthest from the first lead (31), The second semiconductor element (11B, 12B) arranged in the second row includes a second end (11a4, 12a3) at the position furthest from the first lead (31), The semiconductor device (A20, A30, A40) described in Appendix 2, wherein the first end portion (11a4, 12a3) is separated from the second end portion (11a4, 12a3) by 50 μm or more along the first direction (x). Note 4. The second semiconductor element (11B, 12B) arranged in the second row includes a third end (11a3, 12a4) closest to the first lead (31), The semiconductor device (A20, A30, A40) described in Appendix 3, wherein the first end portion (11a4, 12a3) does not overlap with the third end portion (11a3, 12a4) when viewed in the second direction (y). Appendix 4-1. The second semiconductor element (11B, 12B) arranged in the second row includes a third end (11a3, 12a4) closest to the first lead (31), The first end portion (11a4, 12a3) overlaps with the third end portion (11a3, 12a4) when viewed in the second direction (y), as described in Appendix 3, for the semiconductor device (A20, A30, A40). Note 5. The number of second semiconductor elements (11A, 12A) arranged in the first column is 2 or more. The second semiconductor elements (11B, 12B) arranged in the second column are located between two or more second semiconductor elements (11A, 12A) arranged in the first column in the second direction (y), and the semiconductor device (A20, A30, A40) is as described in any of appendices 2 to 4. Appendix 5-1. The plurality of second semiconductor elements (11, 12) include two second semiconductor elements (11A, 12A) arranged in the first row and one second semiconductor element (11B, 12B) arranged in the second row. The semiconductor device (A20, A30, A40) described in any of Appendix 2 to 4, wherein the line segment connecting the geometric centroid (Ga) of each of the two second semiconductor elements (11A, 12A) as viewed in a third direction (z) perpendicular to the first direction (x) and the second direction (y), and the geometric centroid (Gb) of one of the second semiconductor elements (11B, 12B) as viewed in the third direction (z), is between 60° and 120°. Note 6. Each of the two or more second semiconductor elements (11A, 12A) arranged in the first row includes a first geometric centroid (Ga) when viewed in a third direction (z) orthogonal to the first direction (x) and the second direction (y). Each of the first geometric centroids (Ga) is located in the semiconductor device described in Appendix 5 (A20, A30, A40), which overlaps when viewed in the second direction (y). Note 7. The semiconductor device (A10, A20, A30) described in any of Appendix 1 to 6, wherein the at least one first semiconductor element (11, 12) and the third semiconductor element (13) each include a plurality of circuits (11C, 12C, 13C) corresponding to the number of the plurality of second semiconductor elements (11, 12). Note 8. The semiconductor device (A10, A20, A30, A40) described in Appendix 7, wherein the circuit (11C, 12C) of at least one first semiconductor element (11, 12) is electrically connected to one circuit (11C, 12C) of the plurality of second semiconductor elements (11, 12). Note 9. The semiconductor device (A40) according to any one of appendices 2 to 6, wherein the number of at least one first semiconductor element (11,12) is 2 or more, and they are arranged in two rows in the first direction (x). Note 10. The semiconductor device (A40) described in Appendix 9, wherein the third semiconductor element (13) includes a plurality of circuits (13C) corresponding to the number of at least one first semiconductor element (11,12) and the plurality of second semiconductor elements (11,12). Note 11. The third semiconductor element (13) is a semiconductor device (A10, A20, A21, A40) mounted on the first lead (31) as described in any of appendices 1 to 10. Note 12. The third semiconductor element (13) is a semiconductor device (A11, A30) as described in any of appendices 1 to 10, mounted on the second lead (32). Note 13. A semiconductor device (A10, A20, A30, A40) according to any one of appendices 1 to 12, wherein two adjacent second semiconductor elements (11, 12) in the plurality of second semiconductor elements (11, 12) are spaced 150 μm or more and 1500 μm or less along the second direction (y). Note 14. Multiple third leads (33, 34) electrically connected to the multiple second semiconductor elements (11, 12), A semiconductor device (A10, A20, A30, A40) according to any one of appendices 1 to 13, further comprising a plurality of first wires (44, 45) that electrically connect the plurality of third leads (33, 34) and the plurality of second semiconductor elements (11, 12), respectively. Note 14-1. Each of the plurality of second semiconductor elements (11, 12) includes a first pad (111, 121), The plurality of first wires (44, 45) are bonded to one of the plurality of second semiconductor elements (11, 12) first pads (111, 121), as described in Appendix 14, semiconductor device (A10, A20, A30, A40). Note 15. The semiconductor device (A10, A20, A30, A40) according to any one of the appendices 1 to 14, wherein the third semiconductor element (13) is an insulating element for transmitting electrical signals between the at least one first semiconductor element (11) and the plurality of second semiconductor elements (12) in an insulated state. Note 16. The third semiconductor element (13) includes an upper winding (135a) and a lower winding (135b) separated in the third direction (z), and a semiconductor substrate (130) that is at the same potential as the first leads (31, 32). The semiconductor substrate (130) is located between the lower winding (135b) and the first lead (31) in the third direction (z), and is a semiconductor device (A10, A20, A30, A40) as described in any of Appendix 1 to Appendix 15. Note 17. The device further comprises a plurality of second wires (41) that electrically connect the third semiconductor element (13) and the plurality of second semiconductor elements (12), The third semiconductor element (13) includes a main surface (13a) facing one of the third directions (z) and a plurality of second pads (132) arranged on the main surface (13a), The semiconductor device (A10, A20, A40) described in Appendix 16, wherein the plurality of second wires (41) are each joined to the plurality of second pads (132). Note 18. The lower winding (135b) is at the same potential as the semiconductor substrate (130), as described in Appendix 17 (A10, A20, A40). Note 19. The third semiconductor element (13) includes a third pad (131) disposed on the main surface (13a), The semiconductor device (A10, A20, A40) described in Appendix 17 or 18, wherein the potential of the third pad (131) is different from the potential of the second pad (132). Note 20. The upper winding (135a) is electrically connected to the second pad (132), The lower winding (135b) is electrically connected to the third pad (131) and is a semiconductor device (A10, A20, A40) as described in Appendix 19.

[0136] Finally, the terms used in this disclosure are explained below. Unless otherwise specified, the following terms in this disclosure correspond as follows: "Object A is formed on Object B" includes "Object A is directly formed on Object B" and "Object A is formed on Object B with another object interposed between Object A and Object B." "Object A is positioned on Object B" includes "Object A is directly positioned on Object B" and "Object A is positioned on Object B with another object interposed between Object A and Object B." "Multiple A's are positioned along direction B" means that multiple A's are aligned along direction B, but may be offset in any direction other than direction B. "Object A overlaps with Object B when viewed in a certain direction" includes "Object A overlaps with all of Object B" and "Object A overlaps with part of Object B." "Some object A (or its material) contains some material C" includes cases where "some object A (or its material) consists of some material C" and cases where the main component of some object A (or its material) is some material C. "Some surface A faces a certain direction B (one or the other side)" is not limited to cases where the angle of surface A with respect to direction B is 90°, but also includes cases where surface A is inclined with respect to direction B. "Some surface A is perpendicular to some surface B" is not limited to cases where the angle of surface A with respect to surface B is 90°, but also includes cases where surface A is inclined with respect to surface B. "Rectangular" is not limited to a quadrilateral with four 90° angles, but may also be a quadrilateral with four angles within the range of 90°±5°, or a rounded quadrilateral with four rounded corners. "Geometric centroid" means the centroid of the shape when a particular face of an element is viewed in one direction. "Dimension A is the same as (or equal to) dimension B" may include differences that are generally accepted as manufacturing tolerances. "A and B are aligned in direction C" means that A and B are in the same position in direction C, including errors that are generally recognized as manufacturing tolerances. [Explanation of Symbols]

[0137] A10, A11, A20, A21, A30, A40: Semiconductor equipment 11~13, 11A, 11B, 12A, 12B: Semiconductor devices 11C, 12C, 13C: Circuit 11a~13a: Main surface 11b~13b: Back side 11a1~11a4: Side 1~Side 4 12a1~12a4: Side 1~Side 4 111,121,131,132: Pad 130: Semiconductor substrate 133: Seal ring section 1341: Protective film 1342: Passivation film 1343: Coil protective film 135: Functional part 135a: Upper winding 135b: Lower winding 136: Functional parts 137: Laminated structures 1371: Insulation layer 138: Wiring section 1381: Through-hole wiring 1382: Output wiring 119,129,139: Conductive bonding material 3: Conductive support 31,32,33,34: Leads 311,321: Island section 311a,321a: Mounting surface 312,322:Terminal part 313:Through hole 312a, 322a, 331, 341: Covering part 312b, 322b, 332, 342: Exposed part 33A: Intermediate lead 33B: Side lead 34A: Intermediate lead 34B: Side lead 4: Connecting components 41-47: Wires 411~413,421,422,431,432:Joint part 423,433: Loop section 5: Sealing resin 51: Top surface 52: Bottom surface 53: Side 531: Top 532: Bottom 533: Middle section 54: Side 541: Top 542: Lower part 543: Middle part 81: Lead frame 810: Flat plate section 811,812,813,814: Reed 811a, 812a: Island 811b, 812b: Support leads 811c: Through hole 815: Outer frame 816: Dam Bar 82: Resist

Claims

1. First lead, A second lead separated from the first lead in the first direction, At least one first semiconductor element mounted on the first lead, Multiple second semiconductor elements mounted on the second lead, A third semiconductor element mounted on the first lead or the second lead, The device comprises a first lead, a second lead, at least one first semiconductor element, a plurality of second semiconductor elements, and a sealing resin covering the third semiconductor element, The third semiconductor element is interposed between the at least one first semiconductor element and the plurality of second semiconductor elements such that the at least one first semiconductor element and the plurality of second semiconductor elements have different potentials. The plurality of second semiconductor elements are arranged along a second direction perpendicular to the first direction, forming a semiconductor device.

2. The semiconductor device according to claim 1, wherein the plurality of second semiconductor elements include second semiconductor elements arranged in a first row and second semiconductor elements arranged in a second row spaced apart from the first row in the first direction.

3. The second semiconductor element arranged in the first row includes a first end at the position furthest from the first lead, The second semiconductor element arranged in the second row includes a second end at the position furthest from the first lead. The semiconductor device according to claim 2, wherein the first end is separated from the second end by 50 μm or more along the first direction.

4. The second semiconductor element arranged in the second row includes a third end closest to the first lead, The semiconductor device according to claim 3, wherein the first end does not overlap with the third end when viewed in the second direction.

5. The number of second semiconductor elements arranged in the first row is two or more. The semiconductor device according to claim 2, wherein the second semiconductor element arranged in the second row is located between two or more second semiconductor elements arranged in the first row in the second direction.

6. Each of the two or more second semiconductor elements arranged in the first row includes a first geometric centroid when viewed in a third direction perpendicular to the first and second directions. The semiconductor device according to claim 5, wherein each of the first geometric centroids overlaps when viewed in the second direction.

7. The semiconductor device according to claim 1, wherein the at least one first semiconductor element and the third semiconductor element each include a plurality of circuits corresponding to the number of the plurality of second semiconductor elements.

8. The semiconductor device according to claim 7, wherein the circuit of at least one first semiconductor element is electrically connected to the circuit of one of the plurality of second semiconductor elements.

9. The semiconductor device according to claim 2, wherein the number of at least one first semiconductor element is two or more, and the elements are arranged in two rows in the first direction.

10. The semiconductor device according to claim 9, wherein the third semiconductor element includes a plurality of circuits corresponding to the number of at least one first semiconductor element and the plurality of second semiconductor elements.

11. The semiconductor device according to claim 1, wherein the third semiconductor element is mounted on the first lead.

12. The semiconductor device according to claim 1, wherein the third semiconductor element is mounted on the second lead.

13. The semiconductor device according to claim 1, wherein two adjacent second semiconductor elements in the plurality of second semiconductor elements are spaced 150 μm or more and 1500 μm or less along the second direction.

14. Multiple third leads electrically connected to the plurality of second semiconductor elements, The semiconductor device according to claim 1, further comprising a plurality of first wires that electrically connect the plurality of third leads and the plurality of second semiconductor elements.

15. The semiconductor device according to any one of claims 1 to 14, wherein the third semiconductor element is an insulating element for transmitting electrical signals between the at least one first semiconductor element and the plurality of second semiconductor elements in an insulated state.

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