In-vehicle devices and information processing circuits

Abstract

Maintain harmony between the timing of buffer access by the processor and the timing of buffer access by direct memory access. [Solution] The in-vehicle device includes an information processing circuit and a connector connected to an associated device related to the processing of the information processing circuit, the information processing circuit includes a first buffer, a second buffer, a third buffer, a processor capable of reading or writing data to each of the first buffer, the second buffer, and the third buffer, an interface connected to the connector for performing at least one of data input and output to and from the associated device, registers included in the interface, and a direct memory access controller for transferring data to and from each of the first buffer, the second buffer, and the third buffer.

Description

Technical Field

[0001] The present disclosure relates to an in-vehicle device and an information processing circuit.

Background Art

[0002] A vehicle is equipped with various types of in-vehicle devices, including control-system ECUs (Electronic Control Units) that control engines, transmissions, etc., body-system ECUs that control headlights, power windows, etc., and information-system ECUs for navigation devices, multimedia devices, etc. Each in-vehicle device is connected to an in-vehicle network and can communicate with each other. Such an in-vehicle device is equipped with a microcontroller (MCU: Micro Controller Unit), and application programs for implementing various functions are executed by the MCU.

[0003] Patent Document 1 discloses an MCU that performs data transfer by DMA (Direct Memory Access) between a peripheral circuit including a serial communication interface for communicating with external devices such as sensors and a RAM (Random Access Memory).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0005] In automotive devices that require real-time processing, such as vehicle driving control, the MCU performs real-time processing. In the MCU, the CPU and DMA controller synchronize the input and output of data to and from buffers in RAM within a certain period. However, if an interrupt occurs in the CPU, for example, the DMA may start sending data from the buffer before the CPU has finished writing to the buffer. This disrupts the synchronization between the timing of buffer access by the CPU and the timing of buffer access by the DMA, which may prevent normal processing. [Means for solving the problem]

[0006] An in-vehicle device according to one aspect of the present disclosure comprises an information processing circuit and a connector connected to an associated device related to the processing of the information processing circuit, wherein the information processing circuit includes a first buffer, a second buffer, a third buffer, a processor capable of reading or writing data to each of the first buffer, the second buffer, and the third buffer, an interface connected to the connector for performing at least one of data input and output to and from the associated device, registers included in the interface, and a direct memory access controller for transferring data to each of the first buffer, the second buffer, and the third buffer, wherein the processor processes the first buffer in the i-th main cycle The direct memory access controller performs data read or write to the first buffer, performs data read or write to the second buffer in the (i+1)th main cycle, performs data read or write to the third buffer in the (i+2)th main cycle, performs data transfer between the first buffer and the register from the middle of the (i+1)th main cycle to the middle of the (i+2)th main cycle, performs data transfer between the second buffer and the register from the middle of the (i+2)th main cycle to the middle of the (i+3)th main cycle, and performs data transfer between the third buffer and the register from the middle of the (i+3)th main cycle to the middle of the (i+4)th main cycle. However, i is a variable of a natural number. [Effects of the Invention]

[0007] According to this disclosure, even when an interrupt occurs in the processor, it is possible to maintain harmony between the timing of buffer access by the processor and the timing of buffer access by direct memory access. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of an ECU according to the embodiment. [Figure 2] Figure 2 is a block diagram showing an example of the hardware configuration of the MCU according to the present invention. [Figure 3] Figure 3 is a schematic diagram illustrating an example of data flow in an MCU. [Figure 4] Figure 4 is a timing chart showing an example of buffer access timing in a double buffer. [Figure 5] Figure 5 is a timing chart showing an example of buffer access timing in a triple buffer system. [Modes for carrying out the invention]

[0009] <Summary of the embodiments of this disclosure> The embodiments of this disclosure are outlined below.

[0010] (1) The in-vehicle device according to this embodiment includes an information processing circuit and a connector connected to an associated device related to the processing of the information processing circuit, wherein the information processing circuit includes a first buffer, a second buffer, a third buffer, a processor capable of reading or writing data to each of the first buffer, the second buffer, and the third buffer, an interface connected to the connector for performing at least one of data input and output to and from the associated device, registers included in the interface, and a direct memory access controller for transferring data to each of the first buffer, the second buffer, and the third buffer, wherein the processor, in the i-th main cycle, reads the first buffer The direct memory access controller performs data reading or writing to the corresponding data, performs data reading or writing to the second buffer in the (i+1)th main cycle, performs data reading or writing to the third buffer in the (i+2)th main cycle, performs data transfer between the first buffer and the register from the middle of the (i+1)th main cycle to the middle of the (i+2)th main cycle, performs data transfer between the second buffer and the register from the middle of the (i+2)th main cycle to the middle of the (i+3)th main cycle, and performs data transfer between the third buffer and the register from the middle of the (i+3)th main cycle to the middle of the (i+4)th main cycle. However, i is a variable of a natural number. This creates a gap between the period when the processor accesses the buffer and the period when the direct memory access controller accesses the corresponding buffer. Therefore, even if an interrupt occurs to the processor, the timing of buffer access by the processor and the timing of buffer access by direct memory access can be maintained in harmony.

[0011] (2) In (1) above, the information processing device outputs data to the associated device, the first buffer includes a first transmit buffer, the second buffer includes a second transmit buffer, the third buffer includes a third transmit buffer, and the direct memory access controller may transfer data written to the first transmit buffer by the processor in the i-th main cycle from the first transmit buffer to the register between the middle of the (i+1)th main cycle and the middle of the (i+2)th main cycle, transfer data written to the second transmit buffer by the processor in the (i+1)th main cycle from the second transmit buffer to the register between the middle of the (i+2)th main cycle and the middle of the (i+3)th main cycle, and transfer data written to the third transmit buffer by the processor in the (i+2)th main cycle from the first transmit buffer to the register between the middle of the (i+3)th main cycle and the middle of the (i+4) main cycle. This creates a gap between the time the processor accesses the transmit buffer and the time the direct memory access controller accesses the corresponding transmit buffer when the processor outputs data written to the transmit buffer to the associated device. Therefore, even if an interrupt occurs in the processor, it is possible to maintain harmony between the timing of the processor's access to the transmit buffer and the timing of the direct memory access to the transmit buffer.

[0012] (3) In (2) above, the related device may include an actuator, and the data may be data for controlling the actuator. This allows the actuator to be controlled normally even if an interrupt occurs in the processor.

[0013] (4) In any one of (1) to (3) above, the associated device outputs data to the information processing device, the first buffer includes a first receive buffer, the second buffer includes a second receive buffer, and the third buffer includes a third receive buffer. The processor may read the output data from the associated device, which was transferred from the register to the first receive buffer by the direct memory access controller between the middle of the (i-2)th main cycle and the middle of the (i-1)th main cycle, from the first receive buffer in the i-th main cycle, read the output data from the associated device, which was transferred from the register to the second receive buffer by the direct memory access controller between the middle of the (i-1)th main cycle and the i+1th main cycle, from the second receive buffer in the i+2 main cycle, and read the output data from the associated device, which was transferred from the register to the third receive buffer by the direct memory access controller between the middle of the i-th main cycle and the i+1th main cycle, from the third receive buffer in the i+2 main cycle. This creates a gap between the period when the processor reads data output by the associated device from the receive buffer and the period when the processor accesses the corresponding receive buffer directly. Therefore, even if an interrupt occurs to the processor, it is possible to maintain harmony between the timing of the processor's access to the receive buffer and the timing of the direct memory access to the receive buffer.

[0014] (5) In (4) above, the related device may include a sensor, and the data may be data output from the sensor. This allows the processor to perform processing using the data output from the sensor normally, even if an interrupt occurs.

[0015] (6) The information processing circuit according to this embodiment comprises a first buffer, a second buffer, a third buffer, a processor capable of reading or writing data to each of the first buffer, the second buffer, and the third buffer, an interface connected to an associated device for performing at least one of data input and output to and from the associated device, registers included in the interface, and a direct memory access controller for transferring data to each of the first buffer, the second buffer, and the third buffer, wherein the processor performs data reading or writing to the first buffer in the i-th main cycle, and the i+1th During the main cycle, the direct memory access controller performs data reading or writing to the second buffer, and during the (i+2)th main cycle, it performs data reading or writing to the third buffer. The direct memory access controller performs data transfer between the first buffer and the register from the middle of the (i+1)th main cycle to the middle of the (i+2)th main cycle, performs data transfer between the second buffer and the register from the middle of the (i+2)th main cycle to the middle of the (i+3)th main cycle, and performs data transfer between the third buffer and the register from the middle of the (i+3)th main cycle to the middle of the (i+4)th main cycle. However, i is a variable of a natural number. This creates a gap between the period when the processor accesses the buffer and the period when the direct memory access controller accesses the corresponding buffer. Therefore, even if an interrupt occurs to the processor, the timing of buffer access by the processor and the timing of buffer access by direct memory access can be maintained in harmony.

[0016] The present disclosure can be implemented not only as an in-vehicle device having the above characteristic configuration and an information processing apparatus having the above characteristic configuration, but also as an in-vehicle system including the in-vehicle device, as a buffer access method including characteristic steps, and part or all of the information processing apparatus can be implemented as a semiconductor integrated circuit.

[0017] <Details of Embodiments of the Present Disclosure> Hereinafter, details of embodiments of the present invention will be described with reference to the drawings. At least part of the embodiments described below may be arbitrarily combined with each other.

[0018] [1. ECU] FIG. 1 is a block diagram showing an example of the configuration of an ECU according to the embodiment. The ECU 10 is mounted on a vehicle.

[0019] The ECU 10 according to the present embodiment includes an MCU 100, connectors 11_A and 11_B, and a network interface 12. The ECU 10 is an example of the "in-vehicle device".

[0020] The MCU 100 executes application software and implements the functions of the ECU 10 (for example, control of an actuator). The MCU 100 is an example of an "information processing circuit". The configuration of the MCU 100 will be described later.

[0021] The connectors 11_A and 11_B are connectors for data input and output. The connector 11_A is connected to the actuator 20_1A via a signal line 21_A. The connector 11_B is connected to the sensor 20_1B via a signal line 21_B. The actuator 20_A and the sensor 20_B are examples of "external devices". Each of the connectors 11_A and 11_B is connected to the MCU 100 via a signal line inside the ECU 10.

[0022] The network interface 12 conforms to a specific communication protocol (e.g., CAN (Control Area Network), Ethernet®). The network interface 12 is connected to the in-vehicle network via a communication line 22. Multiple ECUs are connected to the in-vehicle network. Multiple ECUs connected to the in-vehicle network can communicate with each other using the specific communication protocol described above. Multiple ECUs connected to the in-vehicle network constitute an in-vehicle system. In the in-vehicle system, multiple ECUs cooperate to realize a specific function or service. The network interface 12 is connected to the MCU 100 via a signal line inside the ECU 10.

[0023] [2. MCU] Figure 2 is a block diagram showing an example of the hardware configuration of the MCU according to the present invention.

[0024] The MCU100 is, for example, a single-chip semiconductor integrated circuit. The MCU100 includes a processor 101, flash memory 102, RAM 103, DMA controller 104, and peripheral circuitry 105. The processor 101, flash memory 102, RAM 103, DMA controller 104, and peripheral circuitry 105 are interconnected via a bus 107.

[0025] RAM 103 is a volatile memory, such as a semiconductor memory like SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). Flash memory 102 is a non-volatile memory, such as a semiconductor memory.

[0026] The processor 101 is, for example, a CPU (Central Processing Unit). However, the processor 101 is not limited to a CPU. The processor 101 may also be a GPU (Graphics Processing Unit). In a specific example, the processor 101 is a multi-core processor. The processor 101 may also be a single-core processor. The processor 101 may include multiple processors or cores and be capable of performing parallel processing. The processor 101 is configured to execute computer programs. The processor 101 may include, for example, an ASIC (Application Specific Integrated Circuit) as part, or programmable hardware such as an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) as part.

[0027] The flash memory 102 stores application software (hereinafter also referred to as "APP") 110, which is a computer program, and data used to execute APP 110. APP 110 can be stored on recording media such as flash memory, ROM, or CD-ROM. The processor 101 implements specific functions using APP 110.

[0028] The peripheral circuit 105 is a circuit that enables various functions of the MCU 100. The peripheral circuit 105 includes interfaces (hereinafter also referred to as "IF") 300_A, 300_B, and 300_C. Each of IF300_A, 300_B, and 300_C is a circuit that performs at least one of data input and output to and from a connected device. For example, IF300_A, 300_B, and 300_C are input / output interfaces such as general-purpose input / output ports (GPIO), analog / digital converters, and PWM (Puls Width Modulation), or serial communication interfaces compliant with serial communication standards such as UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface).

[0029] IF300_A is connected to connector 11_A via a signal line. That is, IF300_A is connected to actuator 20_A. IF300_B is connected to connector 11_B via a signal line. That is, IF300_B is connected to sensor 20_B. IF300_C is connected to network interface 12 via a signal line.

[0030] IF300_A includes register 310_A, IF300_B includes register 310_B, and IF300_C includes register 310_C. Each of registers 310_A, 310_B, and 310_C is a memory circuit that temporarily stores input and output data. Specifically, register 310_A temporarily stores data to be output to actuator 20_A. Register 310_B temporarily stores data input from sensor 20_B. Register 310_C temporarily stores data received from and transmitted from the in-vehicle network.

[0031] The DMA controller 104 can directly access the RAM 103 without the intervention of the processor 101. The DMA controller 104 can also access each of the registers 310_A, 310_B, and 310_C. In other words, the DMA controller 104 controls DMA-based data transfer between the RAM 103 and the registers 310_A, 310_B, and 310_C (data transfer from RAM 103 to registers 310_A, 310_B, and 310_C, and data transfer from registers 310_A, 310_B, and 310_C to RAM 103).

[0032] RAM103 includes buffers 200_A, 200_B, and 200_C. Each of buffers 200_A, 200_B, and 200_C is a memory area that temporarily stores data input to and output from processor 101.

[0033] Buffer 200_A includes the receive buffer 200R_A and the transmit buffer 200T_A. Buffer 200_B includes the receive buffer 200R_B and the transmit buffer 200T_B. Buffer 200_C includes the receive buffer 200R_C and the transmit buffer 200T_C.

[0034] Each of the receive buffers 200R_A, 200R_B, and 200R_C temporarily stores data to be input to the processor 101. The processor 101 can read data from each of the receive buffers 200R_A, 200R_B, and 200R_C. Each of the transmit buffers 200T_A, 200T_B, and 200T_C temporarily stores data to be output from the processor 101. The processor 101 can write data to each of the transmit buffers 200T_A, 200T_B, and 200T_C.

[0035] RAM103 is equipped with a database (hereinafter also referred to as "DB") 111. DB111 stores data that is input to APP110 and data that is output from APP110.

[0036] The flash memory 102 also stores driver software (hereinafter also referred to as "driver SW") 120 and data used to execute driver SW 120. Driver SW is a computer program that allows the processor 101 to access buffers 200_A, 200_B, 200_C, and DB 111, respectively.

[0037] The peripheral circuit 105 further includes timers 106_A and 106_B. Timer 106_A measures time and outputs a notification to the processor 101 for each main period used for executing APP 110. Timer 106_B measures time and outputs a notification to the DMA controller 104 for each sub-period used by the DMA controller 104. In this embodiment, the main period and the sub-period have the same length but different phases.

[0038] [3. Data flow in the MCU] Figure 3 is a schematic diagram illustrating an example of data flow in an MCU.

[0039] The data flow in the MCU will be explained using the example of APP110 outputting control data for actuator 20_A using detection data output from sensor 20_B.

[0040] The detection data output from sensor 20_B is input to peripheral circuit 105 and stored in register 310_B of IF300_B. The detection data stored in register 310_B is transferred by DMA from register 310_B to one of the receive buffers 200R_A, 200R_B, or 200R_C.

[0041] The driver SW120, executed by the processor 101, reads detection data from one of the receive buffers 200R_A, 200R_B, or 200R_C, and the read detection data is stored in DB111.

[0042] The APP110, executed by the processor 101, reads the detection data from the DB111. Based on the read detection data, the APP110 generates control data to control the actuator 20_A and stores the generated control data in the DB111.

[0043] The driver SW120, executed by the processor 101, reads control data from DB111, and the read control data is stored in one of the transmit buffers 200T_A, 200T_B, or 200T_C.

[0044] The control data stored in one of the transmit buffers 200T_A, 200T_B, or 200T_C is transferred via DMA from one of the transmit buffers 200T_A, 200T_B, or 200T_C to register 310_A of IF300_A in peripheral circuit 105. The control data stored in register 310_A is output to actuator 20_A and used to control actuator 20_A.

[0045] The above data input / output cycle is repeated between the MCU110 and related devices (actuator 20_A and sensor 20_B).

[0046] [4. Buffer Access] [4-1. Double buffering] As a comparative example, data input / output between the processor 101 and the peripheral circuit 105 in a configuration using two buffers 200_A and 200_B (double buffer) will be described. Figure 4 is a timing chart showing an example of buffer access timing in a double buffer configuration.

[0047] Hereafter, the xth main period will also be referred to as "main period #x". Buffers 200_A and 200_B will also be referred to as "buffer A" and "buffer B". Similarly, buffer 200_C will also be referred to as "buffer C". Receive buffer 200R_A will also be referred to as "receive buffer A", and receive buffer 200R_B will also be referred to as "receive buffer B". Transmit buffer 200T_A will also be referred to as "transmit buffer A", and transmit buffer 200T_B will also be referred to as "transmit buffer B". Receive buffer 200R_C will also be referred to as "receive buffer C", and transmit buffer 200T_C will also be referred to as "transmit buffer C".

[0048] In a double buffer configuration, the DMA controller 104 must operate according to the main cycle. With i as an integer variable, the processor 101 (driver SW120) accesses buffer A from the start of main cycle #i. Specifically, the processor 101 reads data from receive buffer A and writes data to transmit buffer A.

[0049] At some point during main cycle #i, the reading of data from receive buffer A and the writing of data to transmit buffer A are completed. From the end of access to buffer A until the end of main cycle #i is idle time, and access to buffer A is suspended.

[0050] The DMA controller 104 accesses buffer B between the start and end of main cycle #i. Specifically, data is transferred from register 310_B to receive buffer B via DMA, and data is transferred from transmit buffer B to register 310_A via DMA. Since processor 101 accesses buffer A during main cycle #i as described above, there is no conflict (overlap) in accessing the same buffer between processor 101 and DMA.

[0051] At the end of main cycle i, DMA access to buffer B has finished. Processor 101 (driver SW120) accesses buffer B from the start of main cycle #i+1. Specifically, processor 101 reads data from receive buffer B and writes data to transmit buffer B.

[0052] At some point during the main cycle #i+1, the reading of data from receive buffer B and the writing of data to transmit buffer B are completed. From the end of access to buffer B until the end of the main cycle #i+1 is idle time, and access to buffer B is suspended.

[0053] The DMA controller 104 accesses buffer A between the start and end of main cycle #i+1. That is, data is transferred from register 310_B to receive buffer A via DMA, and data is transferred from transmit buffer A to register 310_A via DMA. In main cycle #i+1, as described above, processor 101 accesses buffer B, so there is no conflict (duplicate) in accessing the same buffer between processor 101 and DMA.

[0054] Similarly to the above, in main cycle #i+2, processor 101 accesses buffer A and DMA controller 104 accesses buffer B. In main cycle #i+3, processor 101 accesses buffer B and DMA controller 104 accesses buffer A. In main cycle #i+4, processor 101 accesses buffer A and DMA controller 104 accesses buffer B. In this way, processor 101 alternately accesses buffer A and buffer B in each main cycle, and DMA controller 104 alternately accesses buffer B and buffer A in each main cycle. In each main cycle, buffer access is controlled so that processor 101 and DMA controller 104 do not access the same buffer simultaneously.

[0055] For example, if an interrupt occurs in processor 101, causing a delay in processor 101's access to buffer A during main cycle #i, the delay within the idle time is acceptable. In other words, if the delay time is shorter than the idle time, processor 101 can complete its access to buffer A during main cycle #i. That is, at the end of main cycle #i, processor 101 can complete reading from receive buffer A and complete writing to transmit buffer A.

[0056] On the other hand, if the delay time is longer than the idle time, the processor 101 cannot complete its access to buffer A during the main cycle #i. In this case, the processor 101 will not complete reading from the receive buffer A, and the data read by the processor 101 will be incomplete. Furthermore, the processor 101 will not complete writing to the transmit buffer A, and the data output to register 310_A by DMA will be incomplete.

[0057] [4-2. Triple Buffer] Next, we will describe the data input / output between the processor 101 and the peripheral circuit 105 in a configuration using the three buffers 200_A, 200_B, and 200_C (triple buffer) according to this disclosure. Figure 5 is a timing chart showing an example of buffer access timing in the triple buffer configuration.

[0058] In a triple buffer, the DMA controller 104 operates according to sub-periods. Sub-periods have the same length as main periods, but are in a different phase. That is, sub-period #x starts partway through main period #x+1 and ends partway through main period #x+2. In a specific example, the phase of the sub-period lags the phase of the main period by 540°. That is, sub-period #x starts halfway through the length of main period #x+1 and ends halfway through the length of main period #x+2.

[0059] With i as an integer variable (where i > 3), the processor 101 (driver SW120) accesses buffer A from the start of main cycle #i. Specifically, the processor 101 reads data from receive buffer A and writes data to transmit buffer A.

[0060] At the end of main cycle #i, the reading of data from receive buffer A and the writing of data to transmit buffer A are completed. However, the period from the start to the end of main cycle #i is allocated to accessing buffer A, and it is not necessary to read data from receive buffer A and write data to transmit buffer A until the end of main cycle #i. In other words, processor 101 only needs to have finished reading data from receive buffer A and writing data to transmit buffer A before the end of main cycle #i.

[0061] The processor accesses buffer B from the start of the main cycle #i+1. Specifically, processor 101 reads data from receive buffer B and writes data to transmit buffer B.

[0062] At the end of the main cycle #i+1, the reading of data from the receive buffer B and the writing of data to the transmit buffer B are completed.

[0063] Sub-period #i-1 starts midway through main period #i and ends midway through main period #i+1. The DMA controller 104 accesses buffer C between the start and end of sub-period #i-1. Specifically, data is transferred from register 310_B to receive buffer C via DMA, and data is transferred from transmit buffer C to register 310_A via DMA. The data transferred from transmit buffer C in sub-period #i-1 is the data written to transmit buffer C by processor 101 in main period #i-1. In sub-period #i-1, as described above, processor 101 accesses buffers A and B, so there is no conflict in accessing the same buffer between processor 101 and DMA.

[0064] The end of sub-period #i-1 is midway through main period #i+1 (half the length of the main period has elapsed from the start of main period #i+1). Therefore, main period #i+2 begins when half the length of the main period has elapsed after sub-period #i-1 has ended. Processor 101 accesses buffer C from the start of main period #i+2. Specifically, processor 101 reads data from receive buffer C and writes data to transmit buffer C. The data read by processor 101 from receive buffer C in main period #i+2 is the data that was transferred to receive buffer C by DMA in sub-period #i-1.

[0065] Sub-period #i starts midway through main period #i+1 and ends midway through main period #i+2. The DMA controller 104 accesses buffer A between the start and end of sub-period #i. That is, data is transferred from register 310_B to receive buffer A via DMA, and data is transferred from transmit buffer A to register 310_A via DMA. The data transferred from transmit buffer A in sub-period #i is the data written to transmit buffer A by processor 101 in main period #i. Since processor 101 accesses buffers B and C in sub-period #i, there is no conflict in accessing the same buffer between processor 101 and DMA.

[0066] The end of sub-period #i is midway through main period #i+2 (half the length of the main period has elapsed from the start of main period #i+2). Therefore, main period #i+3 begins when half the length of the main period has elapsed after sub-period #i has ended. Processor 101 accesses buffer A from the start of main period #i+3. Specifically, processor 101 reads data from receive buffer A and writes data to transmit buffer A. The data read by processor 101 from receive buffer A in main period #i+3 is the data that was transferred to receive buffer A by DMA in sub-period #i.

[0067] Sub-period #i+1 starts midway through main period #i+2 and ends midway through main period #i+3. The DMA controller 104 accesses buffer B between the start and end of sub-period #i+1. Specifically, data is transferred from register 310_B to receive buffer B via DMA, and data is transferred from transmit buffer B to register 310_A via DMA. The data transferred from transmit buffer B in sub-period #i+1 is the data written to transmit buffer B by processor 101 in main period #i+1. Since processor 101 accesses buffers C and A in sub-period #i+1, there is no conflict in accessing the same buffer between processor 101 and DMA.

[0068] The end of sub-period #i+1 is midway through main period #i+3 (half the length of the main period has elapsed from the start of main period #i+3). Therefore, main period #i+4 begins when half the length of the main period has elapsed after sub-period #i+1 has ended. Processor 101 accesses buffer B from the start of main period #i+4. Specifically, processor 101 reads data from receive buffer B and writes data to transmit buffer B. The data read by processor 101 from receive buffer B in main period #i+4 is the data that was transferred to receive buffer B by DMA in sub-period #i+1.

[0069] Sub-period #i+2 starts midway through main period #i+3 and ends midway through main period #i+4. The DMA controller 104 accesses buffer C between the start and end of sub-period #i+2. Specifically, data is transferred from register 310_B to receive buffer C via DMA, and data is transferred from transmit buffer C to register 310_A via DMA. The data transferred from transmit buffer C in sub-period #i+2 is the data written to transmit buffer C by processor 101 in main period #i+2. Since processor 101 accesses buffers A and B in sub-period #i+2, there is no conflict in accessing the same buffer between processor 101 and DMA.

[0070] Similarly to the above, the processor 101 repeatedly accesses buffers A, B, and C in the order of buffer A, buffer B, and buffer C in each main cycle, and the DMA controller 104 repeatedly accesses buffers A, B, and C in the order of buffer C, buffer A, and buffer B in each sub cycle.

[0071] Access to buffer A by DMA begins at least half the length of the main cycle after processor 101 has finished accessing buffer A. In other words, a period (hereinafter referred to as "gap period GP1") is ensured between the access period of buffer A by processor 101 and the access period of buffer A by DMA during which neither processor 101 nor DMA controller 104 accesses buffer A. The length of gap period GP1 is, for example, about half the main cycle. Gap period GP1 is sufficiently longer than the idle time in double buffering. Therefore, even if an interrupt occurs in processor 101, processor 101 can complete its access to buffer A before DMA access to buffer A begins.

[0072] After the DMA access to buffer A is completed and a period of half the length of the main cycle has elapsed, the processor 101 begins accessing buffer A. In other words, between the DMA access period for buffer A and the processor 101 access period for buffer A, there is a period during which neither the processor 101 nor the DMA controller 104 accesses buffer A (hereinafter referred to as "gap period GP2"). The length of gap period GP2 is, for example, about half the main cycle. Gap period GP2 is sufficiently larger than the idle time in double buffering. Therefore, even if the processor 101 accesses buffer A earlier, the DMA access to buffer A is completed before the processor 101 begins accessing buffer A. The above explanation uses access to buffer A as an example, but the same applies to buffers B and C.

[0073] [5. Variant] In the above embodiment, the phase delay of the sub-period relative to the main period was set to half the main period, but this is not limited to this. For example, the phase of the sub-period may be delayed by 510° to 720° from the phase of the main period.

[0074] [6. Supplementary Notes] The embodiments disclosed herein are illustrative in all respects and are not restrictive. The scope of the present invention is indicated by the claims rather than by the embodiments described above, and includes all modifications within the meaning and scope of the equivalents of the claims. [Explanation of symbols]

[0075] 10 ECU 11_A, 11_B connectors 12 Network Interfaces 20_1A Actuator 20_1B Sensor 22 Communication lines 100 MCU 101 Processors 102 Flash Memory 103 RAM 104 DMA Controller 105 Peripheral Circuits 106_A, 106_B Timer 107 Bus 110 Application Software (APP) 111 Database (DB) 120 Driver Software (Driver SW) 200_A, 200_B, 200_C buffer 200R_A, 200R_B, 200R_C Receive buffer 200T_A, 200T_B, 200T_C Transmit Buffers 300_A, 300_B, 300_C Interface (IF) 310_A, 310_B, 310_C registers GP1, GP2 gap period

Claims

1. Information processing circuit and, A connector connected to related devices related to the processing of the information processing circuit, Equipped with, The aforementioned information processing circuit is The first buffer and, The second buffer, The third buffer, A processor capable of reading or writing data to the first buffer, the second buffer, and the third buffer, An interface connected to the connector for performing at least one of data input and output to and from the associated device, A direct memory access controller that transfers data between the registers included in the interface and the first buffer, the second buffer, and the third buffer, Includes, The aforementioned processor, In the i-th main cycle, read or write data to the first buffer. In the (i+1)th main cycle, read or write data to the second buffer. In the i+2th main cycle, read or write data to the third buffer. The aforementioned direct memory access controller is Between the middle of the (i+1)th main cycle and the middle of the (i+2)th main cycle, data transfer is performed between the first buffer and the register. Between the middle of the (i+2)th main cycle and the middle of the (i+3)th main cycle, data transfer is performed between the second buffer and the register. The data transfer between the third buffer and the register is performed between the middle of the (i+3)th main cycle and the middle of the (i+4)th main cycle. In-vehicle device. However, i is a natural number variable.

2. The information processing device outputs data to the associated device. The first buffer includes a first transmit buffer, The aforementioned second buffer includes a second transmit buffer, The third buffer includes the third transmit buffer. The aforementioned direct memory access controller is The data written to the first transmit buffer by the processor during the i-th main cycle is transferred from the first transmit buffer to the register between the middle of the (i+1)th main cycle and the middle of the (i+2)th main cycle. The data written to the second transmit buffer by the processor during the (i+1)th main cycle is transferred from the second transmit buffer to the register between the middle of the (i+2)th main cycle and the middle of the (i+3)th main cycle. The data written to the third transmit buffer by the processor during the i+2th main cycle is transferred from the first transmit buffer to the register between the middle of the i+3rd main cycle and the middle of the i+4th main cycle. The in-vehicle device according to claim 1.

3. The aforementioned related device includes an actuator, The aforementioned data is data for controlling the actuator. The in-vehicle device according to claim 2.

4. The related device outputs data to the information processing device. The first buffer includes the first receive buffer, The aforementioned second buffer includes a second receive buffer, The Qualified 3 buffer includes the third receive buffer, The aforementioned processor, The output data from the associated device, which was transferred from the register to the first receive buffer by the direct memory access controller between the middle of the i-2 main cycle and the middle of the i-1 main cycle, is read from the first receive buffer during the i main cycle. The output data from the associated device, which was transferred from the register to the second receive buffer by the direct memory access controller between the middle of the (i-1)th main cycle and the middle of the ith main cycle, is read from the second receive buffer in the (i+1)th main cycle. The output data from the associated device, which was transferred from the register to the third receive buffer by the direct memory access controller between the middle of the i-th main cycle and the middle of the (i+1)-th main cycle, is read from the third receive buffer during the (i+2)-th main cycle. The in-vehicle device according to any one of claims 1 to 3.

5. The aforementioned related device includes a sensor, The aforementioned data is data output from the sensor. The in-vehicle device according to claim 4.

6. The first buffer and, The second buffer, The third buffer, A processor capable of reading or writing data to the first buffer, the second buffer, and the third buffer, An interface connected to an associated device for performing at least one of data input and output to and from the associated device, A direct memory access controller that transfers data between the registers included in the interface and the first buffer, the second buffer, and the third buffer, Equipped with, The aforementioned processor, In the i-th main cycle, read or write data to the first buffer. In the (i+1)th main cycle, read or write data to the second buffer. In the i+2th main cycle, read or write data to the third buffer. The aforementioned direct memory access controller is Between the middle of the (i+1)th main cycle and the middle of the (i+2)th main cycle, data transfer is performed between the first buffer and the register. Between the middle of the (i+2)th main cycle and the middle of the (i+3)th main cycle, data transfer is performed between the second buffer and the register. The data transfer between the third buffer and the register is performed between the middle of the (i+3)th main cycle and the middle of the (i+4)th main cycle. Information processing circuit. However, i is a natural number variable.

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