Semiconductor memory

Abstract

The present invention provides a semiconductor memory device comprising multiple semiconductor dies stacked on top of each other, having a novel configuration different from conventional semiconductor memory devices. [Solution] The semiconductor memory device includes memory dies 1-1 and 1-2 stacked on top of each other. The memory dies 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between them. Each of the memory dies 1-1 and 1-2 has a front and back surface facing each other and a plurality of first terminals located on the front surface. In each of the memory dies 1-1 and 1-2, the plurality of first terminals are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the front and back surfaces. The memory dies 1-1 and 1-2 are stacked such that the surface of memory die 1-1 is in contact with the surface of memory die 1-2, and the plurality of first terminals of memory die 1-1 are connected to the plurality of first terminals of memory die 1-2.

Description

[[Technical Field]]

[0001] The present disclosure relates to a semiconductor memory device. [[Background Art]]

[0002] In recent years, along with the performance improvement of Graphics Processing Units (GPUs) and Central Processing Units (CPUs), the demand for large-capacity, high-performance semiconductor memory devices has increased significantly. However, in order to satisfy the constraints on power supply and / or thermal management for the entire system, high performance while maintaining low power consumption is required at the same time.

[0003] As a solution to such problems, semiconductor memory devices in which semiconductor dies are three-dimensionally stacked have been proposed. The High Bandwidth Memory (HBM) series has also been standardized by the Joint Electron Device Engineering Council (JEDEC), and products are actually supplied to the market.

[0004] For example, Patent Document 1 discloses a semiconductor memory device including a plurality of semiconductor dies stacked vertically. [[Prior Art Documents]] [[Patent Documents]]

[0005] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2011-166147 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0006] According to the semiconductor memory device described in Patent Document 1, multiple semiconductor dies are stacked by repeatedly connecting the back surface of one semiconductor die onto the front surface of another semiconductor die. Hereinafter, in this specification, such a connection of semiconductor dies will be referred to as "F2B (face to back) connection".

[0007] To provide high-capacity, high-performance, and low-power three-dimensional memory at a low price, semiconductor memory devices in various forms, not limited to F2B connections, are required.

[0008] The object of this disclosure is to provide a semiconductor memory device having a novel configuration different from conventional ones, comprising a plurality of semiconductor dies stacked on top of each other. [Means for solving the problem]

[0009] A semiconductor memory device relating to one aspect of this disclosure is A semiconductor memory device comprising a plurality of semiconductor dies stacked on top of each other, The plurality of semiconductor dies include circuit elements and wiring arranged in the same layout between the plurality of semiconductor dies, Each of the plurality of semiconductor dies has first and second faces facing each other, and a plurality of first terminals arranged on the first face, In each of the plurality of semiconductor dies, the plurality of first terminals are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the first and second planes. The plurality of semiconductor dies include a first semiconductor die and a second semiconductor die. The first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the plurality of first terminals of the first semiconductor die are connected to the plurality of first terminals of the second semiconductor die. [Effects of the Invention]

[0010] According to one aspect of this disclosure, it is possible to provide a semiconductor memory device having a novel configuration different from conventional F2B connections. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view showing the terminal layout of memory dies 1-1 and 1-2 of a semiconductor memory device according to the first embodiment. [Figure 2] This is a longitudinal cross-sectional view showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 3] This is a plan view showing the terminal layout of memory dies 2-1 and 2-2 of the semiconductor memory device according to the first comparative example. [Figure 4] This is a longitudinal cross-sectional view showing the configuration of a semiconductor memory device relating to the first comparative example. [Figure 5] This is a plan view showing the terminal layout of memory dies 3-1 and 3-2 of the semiconductor memory device relating to the second comparative example. [Figure 6] This is a longitudinal cross-sectional view showing the configuration of a semiconductor memory device relating to the second comparative example. [Figure 7] This is a longitudinal cross-sectional view showing another configuration of the semiconductor memory device according to the first embodiment. [Figure 8] This is a plan view showing the terminal layout of memory dies 4-1 to 4-4 of the semiconductor memory device according to the second embodiment. [Figure 9] Figure 8 is a longitudinal cross-sectional view showing the wiring layout of memory die 4-1. [Figure 10] This is a longitudinal cross-sectional view showing the configuration of a semiconductor memory device according to the second embodiment. [Figure 11] This diagram shows a multidrop connection of a semiconductor memory device. [Figure 12] This diagram shows the spiral connection of a semiconductor memory device. [Figure 13] Figure 10 shows the manufacturing process of semiconductor memory devices. [Figure 14] This figure shows the manufacturing process of a semiconductor memory device related to the third comparative example. [Figure 15]It is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a third comparative example. [Figure 16] It is a plan view showing the terminal layout of memory dies 7-1 to 7-4 of a semiconductor memory device according to a modified example of the second embodiment. MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, a semiconductor memory device according to an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same reference numeral denotes the same component.

[0013] [First Embodiment] FIG. 1 is a plan view showing the terminal layout of memory dies 1-1 and 1-2 of a semiconductor memory device according to the first embodiment. FIG. 2 is a vertical cross-sectional view showing the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device in FIGS. 1 and 2 includes memory dies 1-1 and 1-2 stacked on each other.

[0014] In FIGS. 1 and 2, Xa, Ya, and Za indicate the local coordinate system of the memory die 1-1, and Xb, Yb, and Zb indicate the local coordinate system of the memory die 1-2. Further, X, (Y,) Z indicate the global coordinate system of the semiconductor memory device. Similarly, the local coordinate system and the global coordinate system are referred to in other drawings.

[0015] Memory dies 1-1 and 1-2 are an example of a semiconductor die including memory circuit elements formed on a semiconductor substrate. The memory dies 1-1 and 1-2 generally have the same structure as each other. At least, the memory dies 1-1 and 1-2 include circuit elements and wirings arranged in the same layout between the memory dies 1-1 and 1-2.

[0016] Referring to Figure 1, the memory die 1-1 has a semiconductor substrate with opposing surfaces 10a-1 and a back surface 10b-1. Furthermore, the memory die 1-1 has terminals 21-1 to 28-1 located on the surface 10a-1 and terminals 31-1 to 38-1 located on the back surface 10b-1. The terminals 21-1 to 28-1 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the surface 10a-1 and the back surface 10b-1. Similarly, the terminals 31-1 to 38-1 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0017] Similarly, the memory die 1-2 has a semiconductor substrate with opposing surfaces 10a-2 and a back surface 10b-2. The memory die 1-2 has terminals 21-2 to 28-2 located on surface 10a-2 and terminals 31-2 to 38-2 located on back surface 10b-2. The terminals 21-2 to 28-2 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to surface 10a-2 and back surface 10b-2. Similarly, the terminals 31-2 to 38-2 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0018] In this specification, the front surface of the semiconductor substrate is also referred to as the "first surface," and the back surface is also referred to as the "second surface." Furthermore, in this specification, terminals located on the front surface of the semiconductor substrate are also referred to as the "first terminals," and terminals located on the back surface of the semiconductor substrate are also referred to as the "second terminals."

[0019] The memory die 1-1 comprises circuit elements 11-1 to 14-1 formed in an internal layer of the semiconductor substrate. The circuit elements 11-1 to 14-1 are associated with predetermined functions of the semiconductor memory device and include, for example, memory elements, input / output circuits, address (e.g., row address) decoders, command decoders, power supplies, etc. Circuit element 11-1 is connected to terminals 21-1, 22-1, 31-1, and 32-1. Circuit element 12-1 is connected to terminals 23-1, 24-1, 33-1, and 34-1. Circuit element 13-1 is connected to terminals 25-1, 26-1, 35-1, and 36-1. Circuit element 14-1 is connected to terminals 27-1, 28-1, 37-1, and 38-1.

[0020] Similarly, the memory die 1-2 includes circuit elements 11-2 to 14-2 formed in layers inside the semiconductor substrate. The circuit elements 11-2 to 14-2 are associated with predetermined functions of the semiconductor memory device. Circuit element 11-2 is connected to terminals 21-2, 22-2, 31-2, and 32-2. Circuit element 12-2 is connected to terminals 23-2, 24-2, 33-2, and 34-2. Circuit element 13-2 is connected to terminals 25-2, 26-2, 35-2, and 36-2. Circuit element 14-2 is connected to terminals 27-2, 28-2, 37-2, and 38-2.

[0021] As shown in Figure 2, memory dies 1-1 and 1-2 are stacked such that the surface 10a-2 of memory die 1-2 is in contact with the surface 10a-1 of memory die 1-1. As a result, terminals 21-2 to 28-2 of memory die 1-2 are connected to terminals 21-1 to 28-1 of memory die 1-1. Hereinafter, in this specification, such a connection of memory dies will be referred to as "F2F (face to face) connection". When memory dies 1-1 and 1-2 are stacked in this manner, each pair of terminals assigned the same symbols A to H in Figure 1 are connected to each other. Terminal 21-1 of memory die 1-1 is connected to terminal 24-2 of memory die 1-2 (symbol A), terminal 22-1 of memory die 1-1 is connected to terminal 23-2 of memory die 1-2 (symbol B), and so on, until terminal 28-1 of memory die 1-1 is connected to terminal 25-2 of memory die 1-2 (symbol H).

[0022] In Figure 1 and other diagrams, the thick dashed lines indicate that the two memory dies are stacked so that their front or back surfaces are in contact with each other.

[0023] Memory die 1-1 includes wiring formed in an internal layer of semiconductor substrate 10-1, including a wiring layer 41-1, wiring vias 42-1, and a TSV (through silicon via) 43-1. Terminal 21-1 is connected to circuit element 11-1 of memory die 1-1 via wiring layer 41-1, wiring vias 42-1, and TSV 43-1. Similarly, memory die 1-2 includes wiring formed in an internal layer of semiconductor substrate 10-2, including wiring layer 41-2, wiring vias 42-2, and TSV 43-2. ​​Terminal 24-2 is connected to circuit element 12-2 of memory die 1-2 via wiring layer 41-2, wiring vias 42-2, and TSV 43-2. ​​By connecting terminals 21-1 and 24-2 to each other, the wiring and circuit elements of different memory dies 1-1 and 1-2 are connected to each other. Figure 2 shows only the parts related to terminals 21-1 and 24-2 for the sake of simplicity, but the remaining terminals are similarly connected to the wiring and circuit elements of memory dies 1-1 and 1-2.

[0024] Referring to Figure 1, each pair of terminals 21-1 to 28-1 on memory die 1-1, which are arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with the same function. Similarly, each pair of terminals 21-2 to 28-2 on memory die 1-2, which are arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with the same function. Here, the wiring includes data signal lines, address signal lines, command signal lines, power lines, etc.

[0025] For example, consider the case where the circuit elements 11-1 to 14-1 of memory die 1-1 and the circuit elements 11-2 to 14-2 of memory die 1-2 are memory arrays. In this case, terminals 21-1 and 22-1 of memory die 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 11-1, respectively. Also, terminals 23-1 and 24-1 of memory die 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 12-1, respectively. Furthermore, terminals 25-1 and 26-1 of memory die 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 13-1, respectively. Also, terminals 27-1 and 28-1 of memory die 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 14-1, respectively. Similarly, terminals 21-2 to 28-2 of memory die 1-2 are also connected to the address signal lines and data signal lines of circuit elements 11-2 to 14-2.

[0026] When memory dies 1-1 and 1-2 are stacked in an F2F connection, as described above, terminal 21-1 of memory die 1-1 is connected to terminal 24-2 of memory die 1-2. In this case, since both terminals 21-1 and 24-2 are connected to the address signal line RA0 of the memory array, addresses are transmitted normally through terminals 21-1 and 24-2 and the wiring connected to them. Similarly, addresses and data are transmitted normally through each other pair of terminals on memory dies 1-1 and 1-2 that are connected to each other and the wiring connected to them.

[0027] Thus, in each of the memory dies 1-1 and 1-2, terminals connected to wiring associated with the same function are arranged mirror-symmetrically with respect to the plane of symmetry. Therefore, each pair of terminals connected to each other in the memory dies 1-1 and 1-2, that is, each pair of terminals assigned the same designation A to H in Figure 1, are connected to wiring associated with the same function.

[0028] The terminals of memory dies 1-1 and 1-2 are arranged mirror-symmetrically with respect to the plane of symmetry, but other components of memory dies 1-1 and 1-2, such as circuit elements and wiring, do not necessarily have to be arranged mirror-symmetrically.

[0029] Memory dies 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between them. Therefore, memory dies 1-1 and 1-2 can be manufactured using substantially identical mask sets. Here, "substantially identical mask sets" means that all or part of the mask sets for forming each layer of the memory die are identical. Even if the masks differ partially in all or part of layers unrelated to the features of this embodiment, those masks are included in the "substantially identical mask sets."

[0030] Here, with reference to Figures 3 to 6, a semiconductor memory device relating to a comparative example will be described.

[0031] Figure 3 is a plan view showing the terminal layout of memory dies 2-1 and 2-2 of the semiconductor memory device according to the first comparative example. Figure 4 is a longitudinal cross-sectional view showing the configuration of the semiconductor memory device according to the first comparative example. The semiconductor memory devices in Figures 3 and 4 include memory dies 2-1 and 2-2 stacked on top of each other.

[0032] Memory dies 2-1 and 2-2 generally have the same structure as each other.

[0033] Referring to Figure 3, memory die 2-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, memory die 2-1 has terminals 21-1 to 24-1 located on the front surface 10a-1 and terminals 31-1 to 34-1 located on the back surface 10b-1. Memory die 2-1 also includes circuit elements 11-1 and 12-1. Similarly, memory die 2-2 has a front surface 10a-2 and a back surface 10b-2. Memory die 2-2 has terminals 21-2 to 24-2 located on the front surface 10a-2 and terminals 31-2 to 34-2 located on the back surface 10b-2. Memory die 2-2 also includes circuit elements 11-2 and 12-2.

[0034] As shown in Figure 4, memory dies 2-1 and 2-2 are stacked in an F2B connection such that the back surface 10b-2 of memory die 2-2 is in contact with the front surface 10a-1 of memory die 2-1. As a result, terminals 31-2 to 34-2 of memory die 2-2 are connected to terminals 21-1 to 24-1 of memory die 2-1. When memory dies 2-1 and 2-2 are stacked in this manner, each pair of terminals assigned the same designation A to D in Figure 3 are connected to each other.

[0035] According to the semiconductor memory devices shown in Figures 3 and 4, by stacking memory dies 2-1 and 2-2 having the same structure in an F2B connection, the corresponding terminals of memory dies 2-1 and 2-2 can be easily connected.

[0036] Figure 5 is a plan view showing the terminal layout of memory dies 3-1 and 3-2 of the semiconductor memory device according to the second comparative example. Figure 6 is a longitudinal cross-sectional view showing the configuration of the semiconductor memory device according to the second comparative example. The semiconductor memory devices in Figures 5 and 6 include memory dies 3-1 and 3-2 stacked on top of each other.

[0037] Referring to Figure 5, memory die 3-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, memory die 3-1 has terminals 21-1 to 24-1 located on the front surface 10a-1 and terminals 31-1 to 34-1 located on the back surface 10b-1. Memory die 3-1 also includes circuit elements 11-1 and 12-1. Similarly, memory die 3-2 has a front surface 10a-2 and a back surface 10b-2. Memory die 3-2 has terminals 21-2 to 24-2 located on the front surface 10a-2 and terminals 31-2 to 34-2 located on the back surface 10b-2. Memory die 3-2 also includes circuit elements 11-2 and 12-2.

[0038] As shown in Figure 6, memory dies 3-1 and 3-2 are stacked in an F2F connection such that the surface 10a-2 of memory die 3-2 is in contact with the surface 10a-1 of memory die 3-1. As a result, terminals 21-2 to 24-2 of memory die 3-2 are connected to terminals 21-1 to 24-1 of memory die 3-1. When memory dies 3-1 and 3-2 are stacked in this manner, each pair of terminals assigned the same designation A to D in Figure 5 are connected to each other.

[0039] According to the semiconductor memory devices shown in Figures 5 and 6, in order to stack memory dies 3-1 and 3-2 in an F2F connection and connect the corresponding terminals of memory dies 2-1 and 2-2, memory dies 3-1 and 3-2 must have terminals arranged in different layouts. Therefore, at least two sets of masks with different terminal-related parts are required, which increases manufacturing costs.

[0040] On the other hand, according to the semiconductor memory device of the first embodiment shown in Figures 1 and 2, by stacking memory dies 1-1 and 1-2, which have terminals arranged mirror-symmetrically with respect to the plane of symmetry, in an F2F connection, it is possible to provide a semiconductor memory device with a novel configuration different from conventional F2B and F2F connections. According to the semiconductor memory device of the first embodiment, since the memory dies 1-1 and 1-2 can be manufactured using substantially the same mask set, the manufacturing cost can be reduced compared to the semiconductor memory devices of Figures 5 and 6. Therefore, according to the semiconductor memory device of the first embodiment, a semiconductor memory device with large capacity, high performance, and low power consumption can be provided at a low price.

[0041] Next, we will describe the other connections of the memory die's terminals and wiring.

[0042] In each of the memory dies 1-1 and 1-2, each pair of terminals arranged mirror-symmetrically with respect to the plane of symmetry may be connected to wiring associated with different functions, rather than being limited to wiring associated with the same function. In this case, in each of the memory dies 1-1 and 1-2, the plurality of terminals on surface 10a-1 include first and second terminal groups, and the first and second terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry. The first and second terminal groups are connected to plurality of wiring associated with the same function group. Here, “function group” refers to, for example, a plurality of bits of address, command, or data, and “a plurality of wiring associated with the same function group” refers to a plurality of signal lines that transmit a plurality of bits of address, command, or data.

[0043] Referring to Figure 1, the terminals 21-1 to 28-1 of the memory die 1-1 include, for example, a first terminal group 21-1, 22-1 and a second terminal group 23-1, 24-1, where the first terminal group 21-1, 22-1 and the second terminal group 23-1, 24-1 are arranged mirror-symmetrically with respect to the plane of symmetry. In this case, the first terminal group 21-1, 22-1 may be connected to the address signal lines RA0, RA1 of the circuit element 11-1, respectively, and the second terminal group 23-1, 24-1 may be connected to the address signal lines RA0, RA1 of the circuit element 12-1, respectively. In other words, the first terminal group 21-1, 22-1 and the second terminal group 23-1, 24-1 are connected to multiple wires associated with the same functional group. A pair of terminals 21-1 and 24-1, arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with different functions, namely address signal lines RA0 and RA1, respectively, although they belong to the same functional group. Similarly, a pair of terminals 22-1 and 23-1, arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with different functions, namely address signal lines RA1 and RA0, respectively, although they belong to the same functional group.

[0044] Similarly, terminals 21-2 to 28-2 of memory die 1-2 may also include first and second groups of terminals arranged mirror-symmetrically with respect to a plane of symmetry, and may include first and second groups of terminals connected to a plurality of wires associated with the same functional group.

[0045] Each pair of terminals, arranged mirror-symmetrically with respect to a plane of symmetry, is connected to signal lines that transmit different bits of the address. However, the first and second groups of terminals as a whole are connected to multiple wires associated with the same multiple bits of the address. The address is transmitted normally through the first and second groups of terminals as a whole and the wires connected to them.

[0046] However, when testing a memory array, if the address, command, or data signals do not have a pattern that applies appropriate noise or stress to the memory array, it may not be possible to detect a defect in the memory array. With this in mind, the first and second groups of terminals may be selected to apply appropriate noise or stress to the memory array when testing it.

[0047] Next, other configurations of the semiconductor memory device according to the first embodiment will be described.

[0048] Figure 7 is a longitudinal cross-sectional view showing another configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device in Figure 7 includes memory dies 1-1 to 1-4 stacked on top of each other.

[0049] Memory dies 1-1 to 1-2 in Figure 7 are configured in the same way as memory dies 1-1 to 1-2 in Figures 1 and 2.

[0050] Memory dies 1-3 to 1-4 are configured in the same way as memory dies 1-1 to 1-2 in Figures 1 and 2. Memory dies 1-3 and 1-4 are stacked in an F2F connection such that the surface of memory die 1-4 is in contact with the surface of memory die 1-3. As a result, the terminals on the surface of memory die 1-4 are connected to the terminals on the surface of memory die 1-3.

[0051] Memory dies 1-2 and 1-3 are stacked so that the back surface of memory die 1-3 is in contact with the back surface of memory die 1-2. This connects the terminals on the back surface of memory die 1-3 to the terminals on the back surface of memory die 1-2. Hereinafter, in this specification, such a connection of memory dies will be referred to as a "B2B (back to back) connection".

[0052] In each of the memory dies 1-1 to 1-4, each pair of terminals arranged mirror-symmetrically with respect to the plane of symmetry, among the multiple terminals located on the back surface of the memory die, may be connected to wiring associated with the same function. In addition, in each of the memory dies 1-1 to 1-4, the multiple terminals located on the back surface of the memory die may include third and fourth groups of terminals arranged mirror-symmetrically with respect to the plane of symmetry, and third and fourth groups of terminals connected to multiple wiring associated with the same group of functions. The third and fourth groups of terminals may be selected to apply appropriate noise or stress to the memory array when testing the memory array.

[0053] In the semiconductor memory device shown in Figure 7, memory dies 1-1 to 1-4 are stacked alternately in F2F and B2B connections. Similarly, more than four memory dies may be stacked alternately in F2F and B2B connections.

[0054] [Second Embodiment] In the second embodiment, the load on the signal lines connected to the terminals of the memory die is reduced to improve the signal transmission speed.

[0055] Figure 8 is a plan view showing the terminal layout of memory dies 4-1 to 4-4 of the semiconductor memory device according to the second embodiment.

[0056] Memory dies 4-1 to 4-4 generally have the same structure as each other. At a minimum, memory dies 4-1 to 4-4 include circuit elements and wiring arranged in the same layout among memory dies 4-1 to 4-4.

[0057] The memory die 4-1 has a front surface 10a-1 and a back surface 10b-1. Furthermore, the memory die 4-1 has terminals 21-1 to 28-1 located on the front surface 10a-1 and terminals 31-1 to 38-1 located on the back surface 10b-1. The terminals 21-1 to 28-1 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the front surface 10a-1 and the back surface 10b-1. Similarly, the terminals 31-1 to 38-1 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0058] The memory die 4-2 has a front surface 10a-2 and a back surface 10b-2. The memory die 4-2 has terminals 21-2 to 28-2 located on the front surface 10a-2 and terminals 31-2 to 38-2 located on the back surface 10b-2. The terminals 21-2 to 28-2 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the front surface 10a-2 and the back surface 10b-2. Similarly, the terminals 31-2 to 38-2 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0059] The memory die 4-3 has a front surface 10a-3 and a back surface 10b-3. Furthermore, the memory die 4-3 has terminals 21-3 to 28-3 located on the front surface 10a-3 and terminals 31-3 to 38-3 located on the back surface 10b-3. The terminals 21-3 to 28-3 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the front surface 10a-3 and the back surface 10b-3. Similarly, the terminals 31-3 to 38-3 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0060] The memory die 4-4 has a front surface 10a-4 and a back surface 10b-4. Furthermore, the memory die 4-4 has terminals 21-4 to 28-4 located on the front surface 10a-4 and terminals 31-4 to 38-4 located on the back surface 10b-4. The terminals 21-4 to 28-4 are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the front surface 10a-4 and the back surface 10b-4. Similarly, the terminals 31-4 to 38-4 are also arranged mirror-symmetrically with respect to the same plane of symmetry.

[0061] The memory die 4-1 includes circuit elements 11-1 and 12-1 formed in an internal layer of the semiconductor substrate. Circuit element 11-1 is connected to terminals 22-1 and 31-1. Circuit element 12-1 is connected to terminals 28-1 and 37-1.

[0062] The memory die 4-2 includes circuit elements 11-2 and 12-2 formed in an internal layer of the semiconductor substrate. Circuit elements 11-2 are connected to terminals 22-2 and 31-2. Circuit elements 12-2 are connected to terminals 28-2 and 37-2.

[0063] The memory die 4-3 includes circuit elements 11-3 and 12-3 formed in an internal layer of the semiconductor substrate. Circuit elements 11-3 are connected to terminals 22-3 and 31-3. Circuit elements 12-3 are connected to terminals 28-3 and 37-3.

[0064] The memory die 4-4 includes circuit elements 11-4 and 12-4 formed in an internal layer of the semiconductor substrate. Circuit elements 11-4 are connected to terminals 22-4 and 31-4. Circuit elements 12-4 are connected to terminals 28-4 and 37-4.

[0065] Figure 9 is a longitudinal cross-sectional view showing the wiring layout of the memory die 4-1 in Figure 8. The memory die 4-1 comprises wiring including a wiring layer 41, wiring vias 42, and TSV 43 formed in an internal layer of the semiconductor substrate 10-1. Terminals 21-1 to 28-1 on the surface 10a-1 are connected to the intermediate wiring layer 41 via wiring vias 42. The intermediate wiring layer 41 is connected to terminals 31-1 to 38-1 on the back surface 10b-1 via TSV 43. The wiring vias 42 and TSV 43 are connected to the wiring layer 41 at different positions that are shifted horizontally.

[0066] The terminals 21-1 to 28-1 on the surface 10a-1 include a first terminal group 21-1 to 24-1 and a second terminal group 25-1 to 28-1, with the first and second terminal groups arranged mirror symmetrically with respect to the plane of symmetry. The terminals 31-1 to 38-1 on the back surface 10b-1 include a third terminal group 31-1 to 34-1 and a fourth terminal group 35-1 to 38-1, with the third and fourth terminal groups arranged mirror symmetrically with respect to the plane of symmetry. The first terminal group 21-1 to 24-1 and the third terminal group 31-1 to 34-1 are located on the same side (left side in Figure 9) with respect to the plane of symmetry. The second terminal group 25-1 to 28-1 and the fourth terminal group 35-1 to 38-1 are also located on the same side (right side in Figure 9) with respect to the plane of symmetry.

[0067] The first group of terminals 21-1 to 24-1 and the third group of terminals 31-1 to 34-1 are connected to each other via the first group of wiring. Specifically, terminals 21-1 to 24-1 are connected to terminals 34-1, 31-1, 32-1, and 33-1, respectively. Also, the second group of terminals 25-1 to 28-1 and the fourth group of terminals 35-1 to 38-1 are connected to each other via the second group of wiring. Specifically, terminals 25-1 to 28-1 are connected to terminals 38-1, 35-1, 36-1, and 37-1, respectively.

[0068] The first and second wiring groups have layouts that are asymmetrical with respect to the plane of symmetry. For example, as shown in Figure 9, the second wiring group may have a layout that is a translational shift of the first wiring group, i.e., a layout that is translationally symmetrical with respect to the first wiring group.

[0069] As described above, circuit element 11-1 is connected to terminals 22-1 and 31-1, and circuit element 12-1 is connected to terminals 28-1 and 37-1. Therefore, only one wire from the first wiring group, namely the wire connecting terminals 22-1 and 31-1 to each other, is connected to circuit element 11-1, and the remaining wires from the first wiring group are not connected to the circuit element. Similarly, only one wire from the second wiring group, namely the wire connecting terminals 28-1 and 37-1 to each other, is connected to circuit element 12-1, and the remaining wires from the second wiring group are not connected to the circuit element. In memory die 4-1, the wires not connected to either circuit element 11-1 or 11-2 are connected to one of the circuit elements 11-2 to 11-4 of the other memory dies 4-2 to 4-3, as will be described later.

[0070] Memory dies 4-2 to 4-4 in Figure 8 are also configured in the same way as memory die 4-1 in Figure 9.

[0071] Figure 10 is a longitudinal cross-sectional view showing the configuration of a semiconductor memory device according to the second embodiment. Figure 10 shows a simplified representation of the wiring in Figure 9. The semiconductor memory device in Figure 10 includes memory dies 4-1 to 4-4 stacked alternately in F2F and B2B connections, similar to the case in Figure 7. When memory dies 4-1 to 4-4 are stacked in this manner, the terminals assigned the same reference numerals A to H in Figure 8 are connected to each other either directly or via the wiring of each memory die 4-1 to 4-4.

[0072] Referring to Figure 10, only circuit element 11-1 is connected to the terminals designated with code A and the wiring connecting them, and no other circuit elements are connected. Similarly, only circuit element 11-2 is connected to the terminals designated with code B and the wiring connecting them, and no other circuit elements are connected. Furthermore, only circuit element 11-3 is connected to the terminals designated with code C and the wiring connecting them, and no other circuit elements are connected. Finally, only circuit element 11-4 is connected to the terminals designated with code D and the wiring connecting them, and no other circuit elements are connected. As a result, the semiconductor memory device in Figure 10 connects circuit elements 11-1 to 11-4 to the wiring of each memory die 4-1 to 4-4 in a spiral manner.

[0073] Figure 11 shows a multidrop connection of a semiconductor memory device. The semiconductor memory device in Figure 11 includes memory dies 5-1 to 5-4 stacked on top of each other. Symbols A to D indicate signal lines spanning multiple memory dies 5-1 to 5-4, including the terminals of each memory die 5-1 to 5-4 and the wiring connecting the terminals to each other. Memory die 5-1 has four circuit elements 11-1 to 14-1, and the other memory dies 5-2 to 5-3 also each have four circuit elements. These circuit elements are, for example, transmit and receive circuits for signals transmitted via signal lines. Four circuit elements 11-1 to 11-4 are connected to signal line A, and four circuit elements are also connected to the other signal lines B to D. Figure 11 shows a "multidrop connection" in which multiple circuit elements from multiple memory dies 5-1 to 5-4 are connected to each single signal line. For example, when a controller (not shown) of a semiconductor memory device communicates with circuit element 11-1 via signal line A, circuit elements 11-2 to 11-4 connected to the same signal line A become inactive and stop transmitting and receiving signals. However, even though circuit elements 11-2 to 11-4 are inactive, they still act as a load for circuit element 11-1. Therefore, multidrop connections are unsuitable for high-speed signal transmission.

[0074] Figure 12 shows a spiral connection of a semiconductor memory device. Figure 12 is equivalent to the configuration of the semiconductor memory device in Figure 10. As shown in Figure 12, only circuit element 11-1 is connected to signal line A, and no other circuit elements are connected. Also, only circuit element 11-2 is connected to signal line B, and no other circuit elements are connected. Also, only circuit element 11-3 is connected to signal line C, and no other circuit elements are connected. Also, only circuit element 11-4 is connected to signal line D, and no other circuit elements are connected. Figure 12 shows a "spiral connection" in which the connection points of signal lines and circuit elements shift as the memory die moves. Circuit elements 11-1 to 11-4 can operate in parallel or simultaneously. Since no extra load-inducing circuit elements are connected to signal lines A to D, it is suitable for high-speed signal transmission.

[0075] Memory dies 4-1 to 4-4 include circuit elements and wiring arranged in the same layout among them. Therefore, memory dies 4-1 to 4-4 can be manufactured using substantially the same mask set.

[0076] Figure 13 shows the manufacturing process of the semiconductor memory device shown in Figure 10. Referring to Figure 13, we will explain how a spiral connection is achieved by alternately stacking memory dies 4-1 to 4-4 with F2F and B2B connections. As mentioned above, memory dies 4-1 to 4-4 generally have the same structure as each other, so memory dies 4-1 and 4-2 in Figure 13 also have the same structure as each other. The terminal groups of memory dies 4-1 and 4-2 are arranged mirror-symmetrically with respect to the plane of symmetry, and the wiring groups of memory dies 4-1 and 4-2 have a translationally symmetrical layout, so memory die 4-2 rotated 180 degrees has substantially the same structure as before the rotation. By alternately stacking memory dies 4-1 to 4-4 with F2F and B2B connections, the semiconductor memory device shown in Figure 10 is obtained, and a spiral connection is achieved.

[0077] Figure 14 is a diagram showing the manufacturing process of a semiconductor memory device according to the third comparative example. Figure 15 is a longitudinal cross-sectional view showing the configuration of the semiconductor memory device according to the third comparative example. The semiconductor memory devices in Figures 14 and 15 include memory dies 6-1 to 6-4 stacked on top of each other. Each of the memory dies 6-1 to 6-4 has two sets of wiring groups that are mirror-symmetric with respect to the plane of symmetry. In this case, terminals 31-2 to 38-2 on the back surface 10b-2 of memory die 6-2 (middle of Figure 14), which has been rotated 180 degrees, are connected via wiring to terminals 31-1 to 38-1 on the back surface 10b-2 of memory die 6-1, respectively. As a result, as shown in Figure 15, it can be seen that spiral connection cannot be achieved even if memory dies 6-1 to 6-4 are stacked alternately in F2F and B2B connections.

[0078] When circuit elements 11-1 to 11-4 are connected to the wiring of each memory die 4-1 to 4-4 in a spiral manner, the wiring included in the first and second wiring groups may be associated with the same functional group in each of the memory dies 4-1 to 4-4. Furthermore, the wiring included in the first wiring group may be associated with at least two functions in each of the memory dies 4-1 to 4-4, and the wiring included in the second wiring group may be associated with at least two functions.

[0079] For example, referring to Figure 10, on the surfaces 10a-1 to 10a-4 of each memory die 4-1 to 4-4, odd-numbered terminals on the left side of the symmetry plane (e.g., terminals 21-1, 23-1) have the same function as even-numbered terminals on the right side of the symmetry plane (e.g., terminals 26-1, 28-1). Similarly, even-numbered terminals on the left side of the symmetry plane (e.g., terminals 22-1, 24-1) must have the same function as odd-numbered terminals on the right side of the symmetry plane (e.g., terminals 25-1, 27-1). In other combinations, terminals for signals with different functions and / or power supplies at different levels may be arranged symmetrically. Consider the case where terminal 31-1 of memory die 4-1 is connected to an address decoder, and terminal 38-1 at its mirror-symmetrical position is connected to an input / output circuit. In this case, since terminal 28-2 of memory die 4-2 is connected to a different signal line than terminal 31-1, addresses and data are transmitted correctly even though they are not associated with the same function. The terminal 21-3 of memory die 4-3 has the same coordinates as the terminal 21-1 of memory die 4-1 with respect to the XY plane. Therefore, terminal 21-3 is connected to the address decoder. Similarly, since terminal 28-4 of memory die 4-4 is connected to a different signal line than terminal 31-1, addresses and data are transmitted correctly even though they are not associated with the same function.

[0080] According to the semiconductor memory device of the second embodiment shown in Figures 8 to 10, memory dies 4-1 to 4-4, each having terminals arranged mirror-symmetrically with respect to the symmetry plane, can be alternately stacked using F2F and B2B connections. Furthermore, according to the semiconductor memory device of the second embodiment, by providing a group of terminals arranged mirror-symmetrically with respect to the symmetry plane and a group of wiring that is translationally symmetrical, a spiral connection can be realized by alternately stacking memory dies 4-1 to 4-4 using F2F and B2B connections. This makes it possible to provide a semiconductor memory device with a novel configuration different from conventional F2B and conventional F2F connections. According to the semiconductor memory device of the second embodiment, since memory dies 4-1 to 4-4 can be manufactured using substantially the same mask set, manufacturing costs can be reduced. Therefore, according to the semiconductor memory device of the second embodiment, a high-capacity, high-performance, and low-power consumption semiconductor memory device can be provided at a low price.

[0081] Here, a spiral connection does not necessarily require the wiring to have a physical spiral shape, as long as the connection points of the signal lines and circuit elements logically shift as they move along the memory die.

[0082] Figure 16 is a plan view showing the terminal layout of memory dies 7-1 to 7-4 of a semiconductor memory device according to a modified example of the second embodiment. Memory dies 7-1 to 7-4 generally have the same structure as each other. At least memory dies 7-1 to 7-4 include circuit elements and wiring arranged in the same layout among memory dies 7-1 to 7-4. Memory dies 7-1 to 7-4 have terminals arranged in a different layout than in Figure 8. The semiconductor memory device of Figure 16, like the semiconductor memory devices of Figures 8 to 10, can also achieve spiral connection by alternately stacking memory dies 7-1 to 7-4 in F2F and B2B connections.

[0083] [Other embodiments] A semiconductor memory device may have more than four memory dies.

[0084] The semiconductor memory device may have a different terminal layout than that described.

[0085] When using F2F and / or B2B connections, the layout of the terminals on the front surface of each memory die may differ from the layout of the terminals on the back surface.

[0086] [Summary of Embodiments] A semiconductor memory device relating to the first aspect of this disclosure is A semiconductor memory device comprising a plurality of semiconductor dies stacked on top of each other, The plurality of semiconductor dies include circuit elements and wiring arranged in the same layout between the plurality of semiconductor dies, Each of the plurality of semiconductor dies has first and second faces facing each other, and a plurality of first terminals arranged on the first face, In each of the plurality of semiconductor dies, the plurality of first terminals are arranged mirror-symmetrically with respect to a plane of symmetry orthogonal to the first and second planes. The plurality of semiconductor dies include a first semiconductor die and a second semiconductor die. The first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the plurality of first terminals of the first semiconductor die are connected to the plurality of first terminals of the second semiconductor die.

[0087] According to the semiconductor memory device of the second aspect of this disclosure, in the semiconductor memory device of the first aspect, In each of the plurality of semiconductor dies, each pair of first terminals, which are arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with the same function.

[0088] According to the semiconductor memory device of the third aspect of this disclosure, in the semiconductor memory device of the first aspect, In each of the plurality of semiconductor dies, the plurality of first terminals include first and second terminal groups, the first and second terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry, and the first and second terminal groups are connected to a plurality of wires associated with the same functional group.

[0089] According to the semiconductor memory device of the fourth aspect of this disclosure, in a semiconductor memory device of one of the first to third aspects, Each of the plurality of semiconductor dies further has a plurality of second terminals arranged on the second surface, In each of the plurality of semiconductor dies, the plurality of second terminals are arranged mirror-symmetrically with respect to the plane of symmetry. The plurality of semiconductor dies include a third and a fourth semiconductor die. The third and fourth semiconductor dies are stacked such that the first surface of the third semiconductor die is in contact with the first surface of the fourth semiconductor die, and the plurality of first terminals of the third semiconductor die are connected to the plurality of first terminals of the fourth semiconductor die. The second and third semiconductor dies are stacked such that the second surface of the second semiconductor die is in contact with the second surface of the third semiconductor die, and the plurality of second terminals of the second semiconductor die are connected to the plurality of second terminals of the third semiconductor die.

[0090] According to the semiconductor memory device of the fifth aspect of this disclosure, in the semiconductor memory device of the fourth aspect, In each of the plurality of semiconductor dies, each pair of second terminals, which are arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with the same function.

[0091] According to the semiconductor memory device of the sixth aspect of this disclosure, in the semiconductor memory device of the fourth aspect, In each of the plurality of semiconductor dies, the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry, and the third and fourth terminal groups are connected to a group of wiring associated with the same functional group.

[0092] According to the semiconductor memory device of the seventh aspect of this disclosure, in the semiconductor memory device of one of the fourth to sixth aspects, in each of the plurality of semiconductor dies, The plurality of first terminals include first and second terminal groups, and the first and second terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry. The plurality of second terminals include third and fourth terminal groups, and the third and fourth terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry. The first and third groups of terminals are arranged on the same side with respect to the plane of symmetry. The first and third terminal groups are connected to each other via the first wiring group. The second and fourth terminal groups are connected to each other via the second wiring group. The first and second wiring groups have an asymmetrical layout with respect to the plane of symmetry.

[0093] According to the semiconductor memory device of the eighth aspect of this disclosure, in the semiconductor memory device of the seventh aspect, In each of the plurality of semiconductor dies, the second wiring group is the same as the first wiring group It has a translationally symmetrical layout with respect to [a certain point].

[0094] According to the semiconductor memory device of the ninth aspect of this disclosure, in the semiconductor memory device of the seventh or eighth aspect, In each of the aforementioned plurality of semiconductor dies, Only one wire from the first group of wires is connected to the circuit element, and the remaining wires from the first group of wires are not connected to the circuit element. Only one of the second group of wires is connected to the circuit element, and the remaining wires of the second group of wires are not connected to the circuit element.

[0095] According to the semiconductor memory device of the tenth aspect of this disclosure, in a semiconductor memory device of one of the seventh to ninth aspects, In each of the aforementioned plurality of semiconductor dies, the wiring included in the first and second wiring groups is associated with the same functional group.

[0096] According to the semiconductor memory device of the tenth aspect of this disclosure, in a semiconductor memory device of one of the seventh to ninth aspects, In each of the aforementioned plurality of semiconductor dies, The wiring included in the first group of wirings is associated with at least two functions, The wiring included in the second group of wirings is associated with at least two of the functions. [Industrial applicability]

[0097] According to one aspect of this disclosure, a semiconductor memory device having a novel configuration different from conventional F2B connections is provided. [Explanation of Symbols]

[0098] 1-1~1-4,4-1,4-4,7-1~7-4 memory die 10-1~10-4 Semiconductor substrates 10a-1~10a-4 Surface of semiconductor substrate 10b-1~10b-4 Back surface of semiconductor substrate 11-1~11-4 Circuit Elements 21-1~28-4 Surface terminals 31-1~38-4 Surface terminals 41,41-1~41-4 Wiring layer 42, 42-1~42-4 Wiring vias 43,43-1~43-4 TSV(through silicon via)

Claims

1. A semiconductor memory device comprising a plurality of semiconductor dies stacked on top of each other, The plurality of semiconductor dies include circuit elements and wiring arranged in the same layout between the plurality of semiconductor dies, Each of the plurality of semiconductor dies has first and second surfaces facing each other, and a plurality of first terminals arranged on the first surface. In each of the plurality of semiconductor dies, the plurality of first terminals are arranged mirror-symmetrically with respect to a plane of symmetry perpendicular to the first and second planes. The plurality of semiconductor dies include a first semiconductor die and a second semiconductor die. The first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the plurality of first terminals of the first semiconductor die are connected to the plurality of first terminals of the second semiconductor die. Semiconductor memory device.

2. In each of the plurality of semiconductor dies, each pair of first terminals arranged mirror-symmetrically with respect to the plane of symmetry is connected to wiring associated with the same function. The semiconductor memory device according to claim 1.

3. In each of the plurality of semiconductor dies, the plurality of first terminals include first and second terminal groups, the first and second terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry, and the first and second terminal groups are connected to a plurality of wires associated with the same functional group. The semiconductor memory device according to claim 1.

4. Each of the plurality of semiconductor dies further has a plurality of second terminals arranged on the second surface, In each of the plurality of semiconductor dies, the plurality of second terminals are arranged mirror-symmetrically with respect to the plane of symmetry. The plurality of semiconductor dies include a third and a fourth semiconductor die. The third and fourth semiconductor dies are stacked such that the first surface of the third semiconductor die is in contact with the first surface of the fourth semiconductor die, and the plurality of first terminals of the third semiconductor die are connected to the plurality of first terminals of the fourth semiconductor die. The second and third semiconductor dies are stacked such that the second surface of the second semiconductor die is in contact with the second surface of the third semiconductor die, and the plurality of second terminals of the second semiconductor die are connected to the plurality of second terminals of the third semiconductor die. The semiconductor memory device according to claim 1.

5. In each of the plurality of semiconductor dies, each pair of second terminals, arranged mirror-symmetrically with respect to the plane of symmetry, are connected to wiring associated with the same function. The semiconductor memory device according to claim 4.

6. In each of the plurality of semiconductor dies, the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry, and the third and fourth terminal groups are connected to a group of wiring associated with the same functional group. The semiconductor memory device according to claim 4.

7. In each of the aforementioned plurality of semiconductor dies, The plurality of first terminals include first and second terminal groups, and the first and second terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry. The plurality of second terminals include third and fourth terminal groups, and the third and fourth terminal groups are arranged mirror-symmetrically with respect to the plane of symmetry. The first and third groups of terminals are arranged on the same side with respect to the plane of symmetry. The first and third terminal groups are connected to each other via the first wiring group. The second and fourth terminal groups are connected to each other via the second wiring group. The first and second wiring groups have an asymmetrical layout with respect to the plane of symmetry. The semiconductor memory device according to claim 4.

8. In each of the plurality of semiconductor dies, the second wiring group has a layout that is translationally symmetric with respect to the first wiring group. The semiconductor memory device according to claim 7.

9. In each of the aforementioned plurality of semiconductor dies, Only one of the first group of wires is connected to the circuit element, and the remaining wires of the first group of wires are not connected to the circuit element. Only one of the second group of wires is connected to the circuit element, and the remaining wires of the second group of wires are not connected to the circuit element. The semiconductor memory device according to claim 8.

10. In each of the aforementioned plurality of semiconductor dies, the wiring included in the first and second wiring groups is associated with the same functional group. The semiconductor memory device according to claim 9.

11. In each of the aforementioned plurality of semiconductor dies, The wiring included in the first group of wirings is associated with at least two functions, The wiring included in the second group of wirings is associated with at least two of the functions. The semiconductor memory device according to claim 9.

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