Semiconductor equipment

Abstract

This provides technology suitable for providing reliable semiconductor devices. [Solution] The semiconductor device includes a substrate 21 and a pad 50. The pad 50 is exposed at the top. The substrate 21 includes a semiconductor layer 22 and an insulating layer 23. The insulating layer 23 includes a first wiring layer 31 and a second wiring layer 35. The second wiring layer 35 is located above the first wiring layer 31. The pad 50 includes a first layer 51 and a second layer 52. The second layer 52 contains a different material from the first layer 51. The lower end 50b of the pad 50 is located at the same height as the lower end of the first wiring layer 31 or above the lower end of the first wiring layer 31. The upper end 50a of the pad 50 is located at the same height as the upper end of the second wiring layer 35 or below the upper end of the second wiring layer 35.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background Art]

[0002] A pixel region of an image pickup apparatus includes a photoelectric conversion unit. There are various types of photoelectric conversion units. In the image pickup apparatus of Patent Document 1, a photodiode is provided in a semiconductor substrate. In the image pickup apparatus of Patent Document 2, a photoelectric conversion layer is provided outside the semiconductor substrate. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. WO 2013 / 190759 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2015-233128 [Summary of Invention] [Problem to be Solved by the Invention]

[0004] The present disclosure provides a technique suitable for providing a reliable semiconductor device. [Means for Solving the Problem]

[0005] The present disclosure provides: a substrate, a pad exposed at an upper side, comprising: the substrate includes a semiconductor layer and an insulating layer, the insulating layer includes a first wiring layer and a second wiring layer located above the first wiring layer, the pad includes a first layer and a second layer containing a material different from that of the first layer, a lower end of the pad is at the same height as a lower end of the first wiring layer or is located above the lower end of the first wiring layer, The upper end of the pad is located at the same height as the upper end of the second wiring layer or below the upper end of the second wiring layer. We provide semiconductor devices. [Effects of the Invention]

[0006] The technology described herein is suitable for providing reliable semiconductor devices. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a circuit diagram of an imaging device according to Embodiment 1. [Figure 2] Figure 2 is a circuit diagram of a pixel according to Embodiment 1. [Figure 3] Figure 3 is a cross-sectional view of the imaging device according to Embodiment 1. [Figure 4] Figure 4 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 5] Figure 5 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 6] Figure 6 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 7] Figure 7 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 8] Figure 8 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 9] Figure 9 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 10] Figure 10 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 11] Figure 11 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 12] Figure 12 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 13] Figure 13 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 14] Figure 14 is an explanatory diagram of the manufacturing method of the imaging device according to Embodiment 1. [Figure 15] Fig. 15 is an explanatory view of the method for manufacturing the image pickup apparatus according to the first embodiment. [Figure 16] Fig. 16 is a cross-sectional view of the image pickup apparatus according to the second embodiment. [Figure 17] Fig. 17 is a cross-sectional view of the image pickup apparatus according to the third embodiment. [Figure 18] Fig. 18 is a cross-sectional view of the image pickup apparatus according to the fourth embodiment. [Figure 19] Fig. 19 is a cross-sectional view of the image pickup apparatus according to the fifth embodiment. [Figure 20] Fig. 20 is a cross-sectional view of the image pickup apparatus according to the sixth embodiment. [Figure 21] Fig. 21 is a cross-sectional view of the image pickup apparatus according to the seventh embodiment. [Figure 22] Fig. 22 is a cross-sectional view of the image pickup apparatus according to the eighth embodiment. [Figure 23] Fig. 23 is a cross-sectional view of the image pickup apparatus according to the ninth embodiment. [Figure 24] Fig. 24 is a cross-sectional view of the image pickup apparatus according to the tenth embodiment. [Figure 25] Fig. 25 schematically shows a configuration example of a camera system according to the eleventh embodiment. MODE FOR CARRYING OUT THE INVENTION

[0008] In the embodiments, terms such as "upper" and "lower" are used solely to specify the mutual positions between elements, and are not intended to limit the posture of the semiconductor device when in use. In the embodiments, "height" refers to a position in the vertical direction, "in-plane direction" refers to a direction orthogonal to the vertical direction, and "plan view" refers to a view when seen from the vertical direction. In the example illustrated in the embodiments, the vertical direction is the thickness direction of the first semiconductor layer (22).

[0009] In embodiments, a "via" includes a conductor located within a hole. A "trench" refers to a groove. Unless otherwise specified, "connection" and "electrically connected" may be interpreted interchangeably. A "metal" may be a single metal, a metal compound, or an alloy.

[0010] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, processes, process sequences, etc., shown in the embodiments below are examples only and are not intended to limit the disclosure. Furthermore, components in the embodiments below that are not described in an independent claim are described as optional components. In embodiments 1 to 10 described below, the semiconductor device is an imaging device. Unless otherwise inconsistent, "imaging device" can be read as "semiconductor device" in the following description.

[0011] (Embodiment 1) Figure 1 is a circuit diagram of an imaging device 1A according to Embodiment 1. The imaging device 1A includes a pixel region R1 and a peripheral region R2. In a plan view, the peripheral region R2 is located outside the pixel region R1. The pixel region R1 includes a pixel array 11. The pixel array 11 includes a plurality of pixels 88. The peripheral region R2 includes peripheral circuits.

[0012] In the pixel array 11, multiple pixels 88 are arranged in two dimensions, in the row and column directions. Figure 1 typically shows four pixels 88 arranged in a 2x2 grid. However, an actual pixel array 11 may contain more pixels 88. In the pixel array 11, multiple pixels 88 may also be arranged in one dimension. In this case, the imaging device 1A can be used as a line sensor.

[0013] Each pixel 88 is supplied with a power supply voltage via a power supply wiring 122. In each pixel 88, a photoelectric conversion unit converts incident light into electricity to generate a signal, and a signal detection circuit detects the signal. Each pixel 88 is supplied with voltage via a storage control line 117.

[0014] The peripheral circuits of the imaging device 1A include a vertical scanning circuit 116, a plurality of load circuits 119, a plurality of column signal processing circuits 120, a plurality of inverting amplifiers 124, and a horizontal signal readout circuit 121. The load circuits 119, column signal processing circuits 120, and inverting amplifiers 124 are arranged for each column of pixels 88 arranged in two dimensions.

[0015] The vertical scanning circuit 116 selects multiple pixels 88 arranged in each row on a row-by-row basis by applying a voltage to the address signal line 130. By selecting multiple pixels 88 on a row-by-row basis, the signal voltage of the selected pixels 88 is read out and the signal charge is reset. The vertical scanning circuit 116 forms a feedback loop that negatively feeds back the output of the pixels 88 by applying a voltage to the feedback control line 128. Negative feedback can reduce kTC noise. The vertical scanning circuit 116 may apply a voltage to the reset signal line 126 when resetting the signal charge and when forming the feedback loop. The vertical scanning circuit 116 may supply voltage to multiple pixels 88 via the sensitivity adjustment line 132.

[0016] Each column of pixels 88 is provided with a vertical signal line 118 and a feedback line 125. Each vertical signal line 118 connects the corresponding pixel 88 to a load circuit 119, a column signal processing circuit 120, and an inverting amplifier 124. The column signal processing circuit 120 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 121 is connected to the column signal processing circuit 120. The horizontal signal readout circuit 121 sequentially reads signals from multiple column signal processing circuits 120 to a horizontal common signal line 123. The negative input terminal of the inverting amplifier 124 is connected to the corresponding vertical signal line 118. A voltage Vref is supplied to the positive input terminal of the inverting amplifier 124. Vref is, for example, a positive voltage of 1V or near 1V. The output terminal of the inverting amplifier 124 is connected to a pixel 88 connected to the negative input terminal of the inverting amplifier 124 via the corresponding feedback line 125.

[0017] Figure 2 is a circuit diagram of a pixel 88 according to Embodiment 1. The pixel 88 includes a photoelectric conversion unit 80 and a signal detection circuit 112. The imaging device 1A includes a feedback circuit 113 that provides negative feedback to the output of the signal detection circuit 112. A feedback loop is formed in the feedback circuit 113.

[0018] The photoelectric conversion unit 80 includes a counter electrode 82, a photoelectric conversion film 81, and a pixel electrode 71. The photoelectric conversion film 81 is positioned between the counter electrode 82 and the pixel electrode 71. The counter electrode 82 is connected to a storage control line 117. The pixel electrode 71 is connected to a charge storage node 144.

[0019] The counter electrode 82 is transparent. Light passes through the counter electrode 82 and reaches the photoelectric conversion film 81. By controlling the potential of the counter electrode 82 via the storage control line 117, the pixel electrode 71 can collect a charge of one polarity from the positive and negative charge pairs generated by photoelectric conversion in the photoelectric conversion film 81. The positive and negative charge pairs are typically hole-electron pairs. When using holes as signal charges, the potential of the counter electrode 82 should be higher than that of the pixel electrode 71. The following is an example of using holes as signal charges. For example, a voltage of about 10V is applied to the counter electrode 82 via the storage control line 117. As a result, signal charges are stored in the charge storage node 144. Electrons may also be used as signal charges.

[0020] The signal detection circuit 112 includes an amplifying transistor 74, a reset transistor 76, a feedback transistor 138, an address transistor 140, a first capacitance element 141, and a second capacitance element 142. The amplifying transistor 74 outputs a signal corresponding to the amount of signal charge stored in the charge storage node 144. The reset transistor 76 resets the signal charge in the charge storage node 144. The feedback transistor 138 works in cooperation with the amplifying transistor 74 and the inverting amplifier 124 to form a feedback circuit 113. The address transistor 140 determines the timing at which the amplifying transistor 74 outputs a signal. The capacitance value of the second capacitance element 142 is smaller than the capacitance value of the first capacitance element 141.

[0021] The following describes an example in which N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as the amplification transistor 74, reset transistor 76, feedback transistor 138, and address transistor 140.

[0022] The gate of the amplification transistor 74 is connected to the charge storage node 144. The drain of the amplification transistor 74 is connected to the power supply wiring 122, which serves as a source follower power supply. The source of the amplification transistor 74 is connected to the vertical signal line 118. The amplification transistor 74 and the load circuit 119 (see Figure 1) constitute a source follower circuit.

[0023] An address transistor 140 is connected between the source of the amplifying transistor 74 and the vertical signal line 118. The gate of the address transistor 140 is connected to the address signal line 130. When signal charge is accumulated in the charge storage node 144, a voltage corresponding to the amount of accumulated signal charge is applied to the gate of the amplifying transistor 74. The amplifying transistor 74 amplifies this voltage. When the address transistor 140 is turned on, the voltage amplified by the amplifying transistor 74 is selectively read out as the signal voltage.

[0024] One electrode of the first capacitance element 141 is connected to a sensitivity adjustment wire 132. Typically, the potential of the sensitivity adjustment wire 132 is fixed at a constant potential, such as 0V. The sensitivity adjustment wire 132 can control the potential of the charge storage node 144. The other electrode of the first capacitance element 141 is connected to a reset drain node 146.

[0025] One electrode of the second capacitance element 142 is connected to the reset drain node 146. The other electrode of the second capacitance element 142 is connected to the charge storage node 144, and therefore to the pixel electrode 71. A reset transistor 76 is connected in parallel with the second capacitance element 142.

[0026] One of the source and drain ends of the feedback transistor 138 is connected to the reset drain node 146. The other source and drain end of the feedback transistor 138 is connected to the feedback line 125. The gate of the feedback transistor 138 is connected to the feedback control line 128.

[0027] Figure 3 is a cross-sectional view of the imaging device 1A according to Embodiment 1. The imaging device 1A is a front-side illumination (FSI) type. Furthermore, the imaging device 1A according to Embodiment 1 is a color imaging device.

[0028] The imaging device 1A includes a first substrate 21, a second substrate 25, a pad 50, an insulating layer 69, a plurality of pixel electrodes 71, a control electrode 72, a photoelectric conversion film 81, a counter electrode 82, an insulating film 83, a light-shielding film 84, a protective film 85, a color filter 86, a microlens 87, a plurality of pixel vias 73, and a through electrode 10.

[0029] The first substrate 21 is located above the second substrate 25. The first substrate 21 includes a first semiconductor layer 22 and a first insulating layer 23. The first insulating layer 23 is located above the first semiconductor layer 22.

[0030] The first insulating layer 23 includes insulating layer 60, insulating layer 61, insulating layer 62, and insulating layer 63. Insulating layer 61 is located above insulating layer 60. Insulating layer 62 is located above insulating layer 61. Insulating layer 63 is located above insulating layer 62.

[0031] The first insulating layer 23 includes a plurality of wiring layers 30. The plurality of wiring layers 30 include a first wiring layer 31, a wiring layer 32, a wiring layer 33, a wiring layer 34, and a second wiring layer 35. In this embodiment, the plurality of pixel electrodes 71 and control electrodes 72 are not included in the plurality of wiring layers 30.

[0032] The first wiring layer 31, wiring layer 32, wiring layer 33, wiring layer 34, and second wiring layer 35 are arranged in this order from bottom to top. In the multiple wiring layers 30, the first wiring layer 31 is the lowest wiring layer, and the second wiring layer 35 is the highest wiring layer.

[0033] The first wiring layer 31, wiring layer 32, wiring layer 33, and wiring layer 34 are included in the insulating layer 60. In the insulating layer 60, the first wiring layer 31 is the lowest wiring layer, and wiring layer 34 is the highest wiring layer. The second wiring layer 35 is included in the insulating layer 62.

[0034] The first wiring layer 31 includes wiring 39. Wiring 39 is the first layer 51 of the pad 50. The wiring layer 34 includes wiring 36 and multiple pixel wirings 37. Wiring 36 is located in peripheral region R2. Multiple pixel wirings 37 are located in pixel region R1. The second wiring layer 35 includes connection wiring 13 for the through-electrode 10. The through-electrode 10 is located in peripheral region R2.

[0035] The insulating layer 69 is located above the first insulating layer 23, specifically above the insulating layer 63. The insulating layer 69, the control electrode 72, and the multiple pixel electrodes 71 are located at the same height.

[0036] In a planar view, in the pixel region R1, multiple pixels 88 are arranged on the first substrate 21. Each of the multiple pixels 88 includes a pixel wiring 37, a pixel via 73, a pixel electrode 71, a photoelectric conversion film 81, a counter electrode 82, a color filter 86, and a microlens 87. The counter electrode 82 is located above the pixel electrode 71. The photoelectric conversion film 81 is located between the pixel electrode 71 and the counter electrode 82. The color filter 86 is located above the counter electrode 82. The microlens 87 is located above the color filter 86.

[0037] The second substrate 25 includes a second semiconductor layer 26 and a second insulating layer 27. The second insulating layer 27 is located above the second semiconductor layer 26. The second insulating layer 27 includes at least one wiring layer 40. The at least one wiring layer 40 includes a wiring layer 45. The wiring layer 45 includes a wiring 46. The wiring 46 is located in the peripheral region R2. In the example of Figure 3, at least one wiring layer 40 is multiple wiring layers 40. In the multiple wiring layers 40, the wiring layer 45 is the uppermost wiring layer.

[0038] The imaging device 1A has a face-to-back structure in which a second semiconductor layer 26, a second insulating layer 27, a first semiconductor layer 22, and a first insulating layer 23 are arranged in order from bottom to top. Multiple pixels 88 are provided on the first substrate 21. A logic circuit is provided on the second substrate 25. The multiple pixels 88 are controlled by the logic circuit.

[0039] In the pixel region R1, the photoelectric conversion film 81 is located above the insulating layer 69 and the multiple pixel electrodes 71. The counter electrode 82 is located above the photoelectric conversion film 81. The insulating film 83 is located above the counter electrode 82.

[0040] The light-shielding film 84 is located above the insulating layer 69, the control electrode 72, and the insulating film 83. The protective film 85 is located above the insulating layer 69 and the light-shielding film 84. The color filter 86 is located above the protective film 85. The microlens 87 is located above the color filter 86.

[0041] The through-electrode 10 is located in the peripheral region R2 and penetrates the first insulating layer 23 and the first semiconductor layer 22. In the peripheral region R2, the through-electrode 10 electrically connects the wiring 46 and the wiring 36. In a plan view, at least a portion of the uppermost surface 10a of the through-electrode 10, specifically the entire uppermost surface 10a, does not overlap with the photoelectric conversion film 81. In Embodiment 1, the uppermost surface 10a constitutes the upper end of the second wiring layer 35.

[0042] The through-electrode 10 includes vias 11 and 12 and a connecting wire 13. The connecting wire 13 is located above the first wiring layer 31 and also above vias 11 and 12. Vias 11 and 12 are directly connected to the connecting wire 13. Via 11 extends deeper downwards than via 12. Via 11 penetrates the insulating layer 61, insulating layer 60, and first semiconductor layer 22 in that order and is directly connected to the upper surface 46a of wiring 46. Wiring 36 is located below the connecting wire 13. Via 12 is directly connected to the upper surface 36a of wiring 36. The connecting wire 13 is flat. The connecting wire 13 has an uppermost surface 10a. The connecting wire 13 is at the same height as the insulating layer 62. The insulating layer 63 is located above the connecting wire 13.

[0043] In this embodiment, via 11 is a TSV (Through silicon via). In Embodiment 1, via 11, which is a TSV, is provided in the peripheral region R2, but no TSV is provided in the pixel region R1.

[0044] Multiple pixel wirings 37, multiple pixel vias 73, and multiple pixel electrodes 71 are arranged in a one-to-one correspondence. Each of the multiple pixel vias 73 is connected to its corresponding pixel electrode 71 and pixel wiring 37. Specifically, each of the multiple pixel vias 73 is directly connected to its corresponding pixel electrode 71 and directly connected to its corresponding pixel wiring 37. Note that in Figure 3, one of the multiple pixel electrodes 71 is shown. The same applies to the pixel vias 73 and pixel wiring 37.

[0045] The light-shielding film 84 is light-shielding and conductive. The light-shielding film 84 shields one or more of the multiple pixels 88. The shielded pixels 88 function as optical black pixels. The light-shielding film 84 also electrically connects the control electrode 72 and the counter electrode 82. In the example in Figure 3, in a plan view, the light-shielding film 84 overlaps with at least a portion of the through electrode 10, specifically the entire through electrode 10.

[0046] The photoelectric conversion film 81 is located above the first substrate 21 and converts incident light into electric charge. This configuration broadens the selectivity of the wavelength of light. The electric charge is used as a signal charge. The signal charge may be a hole or an electron. Specifically, when a control voltage is applied to the counter electrode 82 via the control electrode 72 and the light-shielding film 84, light is shone on the photoelectric conversion film 81, generating an electric charge which is then collected by the pixel electrode 71.

[0047] Although not shown in Figure 3, the first semiconductor layer 22 is provided with an amplification transistor 74, a reset transistor 76, and a charge storage region. Charge collected by the pixel electrode 71 is sent from the pixel electrode 71 to the charge storage region via the pixel via 73 and pixel wiring 37, and is stored in the charge storage region. The amplification transistor 74 generates and outputs a signal corresponding to the potential of the charge storage region. The reset transistor 76 can reset the charge and potential in the charge storage region. One of the source and drain of the reset transistor 76 may be the charge storage region. The charge storage region is included in the charge storage node 144. The source and drain of the amplification transistor 74, the source and drain of the reset transistor 76, and the charge storage region are located within the first semiconductor layer 22. The gates of the amplification transistor 74 and the reset transistor 76 are located above the first semiconductor layer 22 and within the insulating layer 60.

[0048] The first semiconductor layer 22 and the second semiconductor layer 26 include, for example, silicon. The insulating layer 60 and the second insulating layer 27 include, for example, an oxide such as silicon oxide. The insulating layers 61, 62, 63, and 69 each include, for example, at least one selected from the group consisting of silicon oxide and silicon nitride. In the example in Figure 3, the insulating layers 61, 62, 63, and 69 are in the form of films.

[0049] The pixel electrode 71 may contain a metal. Examples of elemental metals that may be included in the pixel electrode 71 include copper, titanium, tantalum, and aluminum. Examples of metal compounds that may be included in the pixel electrode 71 include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 71 may also contain polysilicon that has been doped with impurities to impart conductivity.

[0050] The materials exemplified for the pixel electrode 71 can be used as the material for the control electrode 72. The material for the control electrode 72 may be the same as the material for the pixel electrode 71. In the imaging device 1A, the number of control electrodes 72 may be one or multiple. In this embodiment, "the same material" means that the types of elements contained in the material are the same.

[0051] In this embodiment, the photoelectric conversion film 81 contains an organic substance. The organic substance may be an organic semiconductor. The photoelectric conversion film 81 may contain one or more organic semiconductor layers. Organic p-type semiconductors and organic n-type semiconductors can be used for the organic semiconductor layers.

[0052] In this embodiment, the counter electrode 82 is transparent to the light to be detected. Furthermore, the counter electrode 82 is a conductive semiconductor. For example, the counter electrode 82 contains indium tin oxide (ITO).

[0053] In this embodiment, the insulating film 83 includes at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, organic polymer materials, and inorganic polymer materials. The insulating film 83 may be transparent to light of the wavelength to be detected by the imaging device 1A. The insulating film 83 may have a single-layer structure or a multilayer structure. The insulating film 83 may include a passivation film.

[0054] In this embodiment, the light-shielding film 84 includes a metal. In one specific example, the light-shielding film 84 includes at least one selected from the group consisting of titanium, titanium nitride, aluminum, silicon, copper-added aluminum, copper, and tungsten. The light-shielding film 84 may also include an alloy containing at least two of the materials listed in the above specific example.

[0055] The protective film 85 is insulating. The protective film 85 includes, for example, at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, organic polymer materials, and inorganic polymer materials. The protective film 85 may be transparent to light of wavelengths to be detected by the imaging device 1A. The materials contained in the protective film 85 and the materials contained in the insulating film 83 may be the same or different. The protective film 85 may have a single-layer structure or a multilayer structure.

[0056] The through electrode 10 may contain a metal. The metal may include, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. In this embodiment, the through electrode 10 contains copper as its main component. Here, the main component means the component that is present in the largest amount by mass. In one example, the main component is a component that makes up more than 50% by mass. In one specific example, the main component is a component that makes up more than 80% by mass.

[0057] The materials exemplified for the through-electrode 10 can be used as the materials for the multiple wiring layers 30. The materials for the multiple wiring layers 30 may be the same as the materials for the through-electrode 10. These points also apply to at least one wiring layer 40 and multiple pixel vias 73.

[0058] The pad 50 is provided on the first substrate 21. The imaging device 1A is provided with a pad hole 55. The pad hole 55 exposes the pad 50 upwards. In Embodiment 1, the pad 50 is for wire bonding and also for inspection of the imaging device 1A. The probe of the inspection device and the pad 50 are electrically connected by wire bonding. Specifically, the inspection is a PCM (Process Control Monitor) inspection. The pad 50 can be used not only for inspection purposes but also for other purposes. For example, the conductive part of the ceramic package and the pad 50 can be electrically connected by wire bonding.

[0059] Specifically, the pad 50 is provided on the first insulating layer 23. This is advantageous from the viewpoint of realizing a reliable imaging device 1A for the following reasons. In other words, the imaging device 1A is configured as a wafer stack structure in which a structure including a first semiconductor layer 22 and a structure including a second semiconductor layer 26 are joined together. The bonding interface of the wafer stack structure is located between the second insulating layer 27 and the first semiconductor layer 22. When the pad 50 is provided on the first insulating layer 23, it is easier to improve the reliability of the bonding interface compared to when the pad 50 is provided on the second insulating layer 27. This is because the pad 50 is less likely to obstruct the flatness of the bonding interface.

[0060] In Embodiment 1, the pad holes 55 are provided in the first insulating layer 23 without penetrating the first semiconductor layer 22, and a portion of the pad 50 is exposed upward. The configuration in which the pad holes 55 do not penetrate the first semiconductor layer 22 can facilitate the manufacture of the imaging device 1A. As can be seen from the manufacturing method described later, this configuration is compatible with the imaging device being a surface-illuminated type. In the example in Figure 3, the pad holes 55 do not include any portion within the first semiconductor layer 22.

[0061] The pad 50 includes a first layer 51 and a second layer 52. The second layer 52 is located above the first layer 51. The lower surface of the second layer 52 is in contact with the upper surface of the first layer 51. The pad hole 55 exposes the second layer 52 upwards. With respect to the vertical direction Dv, the dimensions of the second layer 52 are greater than the dimensions of the first layer 51.

[0062] The first layer 51 and the second layer 52 contain different materials. This can give the first layer 51 and the second layer 52 different properties. For example, the first layer 51 may have good conductivity, and the second layer 52 may have good oxidation resistance.

[0063] The material for the first layer 51 can be the same as the material for the through electrode 10. The material for the first layer 51 may also be the same as the material for the through electrode 10. The second layer 52 contains, for example, a metal. The metal contained in the second layer 52 includes, for example, aluminum. In Embodiment 1, the first layer 51 contains copper and the second layer 52 contains aluminum. The fact that the first layer 51 contains copper and the second layer 52 contains aluminum is advantageous from the viewpoint of stably manufacturing the imaging device 1A by the manufacturing method described later. Specifically, in Embodiment 1, the first layer 51 contains copper as its main component and the second layer 52 contains aluminum as its main component.

[0064] The shape and dimensions of the second layer 52 offer a great deal of flexibility. Various shapes and dimensions of the second layer 52 allow for proper establishment of electrical connections between the first layer 51 and the second layer 52.

[0065] In Figure 3, the first width W1 is the width of the bottom surface (specifically, the lowest surface) of the second layer 52 in a cross section parallel to the vertical direction Dv. The second width W2 is the width of the top surface (specifically, the highest surface) of the second layer 52 in a cross section parallel to the vertical direction Dv. In Embodiment 1, the first width W1 is different from the second width W2. Specifically, the first width W1 is smaller than the second width W2.

[0066] Having a first width W1 smaller than a second width W2 can be advantageous in the manufacturing method described later. Specifically, it is advantageous in that it reduces the area of ​​the upper surface of the first layer 51 that is exposed to etching and prevents the material of the first layer 51 from scattering due to etching.

[0067] In Embodiment 1, the second layer 52 includes a tapered portion in a cross-section parallel to the vertical direction Dv. A tapered shape in a cross-section parallel to the vertical direction Dv means that the side surface of the element is inclined with respect to the vertical direction Dv such that the width of the element decreases downwards in the cross-section, or that the side surface of the element is inclined with respect to the vertical direction Dv such that the width of the element increases downwards in the cross-section. Specifically, the tapered shape is a forward tapered shape. A forward tapered shape in a cross-section parallel to the vertical direction Dv means that the side surface of the element is inclined with respect to the vertical direction Dv such that the width of the element decreases downwards in the cross-section.

[0068] In Embodiment 1, in a plan view, the contact surfaces of the first layer 51 and the second layer 52 are contained within the outer edge of the first layer 51. This configuration makes it easier to make the first layer 51 function as an etching stopper in the manufacturing method described later. Furthermore, this configuration makes it easier to suppress the area of ​​the upper surface of the first layer 51 that is exposed to etching, and to prevent the material of the first layer 51 from scattering due to etching. Specifically, in a plan view, the entire contact surface of the first layer 51 and the second layer 52 is contained within the outer edge of the first layer 51.

[0069] In Embodiment 1, the lower end 50b of the pad 50 is located at the same height as the lower end of the first wiring layer 31 or above the lower end of the first wiring layer 31. The upper end 50a of the pad 50 is located (A) at the same height as the upper end of the second wiring layer 35 or below the upper end of the second wiring layer 35, and / or (B) at the same height as the uppermost surface 10a of the connecting wiring 13 or below the uppermost surface 10a. This configuration is advantageous from the viewpoint of realizing a reliable imaging device 1A.

[0070] Specifically, in Embodiment 1, since the lower end 50b of the pad 50 is positioned as described above, the pad 50 is less likely to be positioned excessively low, and in the illustrated example, the pad hole 55 is less likely to become excessively deep. Therefore, problems are less likely to occur during wire bonding to the pad 50. Therefore, problems are less likely to occur in the electrical connection between the pad 50 and the external elements of the imaging device 1A. This can contribute to improving the reliability of the imaging device 1A. For example, this can achieve a good electrical connection between the probe of the inspection device by wire bonding and the pad 50, improve the accuracy of inspection during the manufacturing of the imaging device 1A, and improve the reliability of the completed imaging device 1A. Also, for example, this can achieve a good electrical connection between the conductive part of the ceramic package by wire bonding and the pad 50, and improve the reliability of the operation of the imaging device 1A.

[0071] Furthermore, in the manufacturing method described later, the uppermost surface 10a of the connecting wiring 13 of the through electrode 10 is smoothed by CMP (Chemical Mechanical Polishing). During CMP, material from the connecting wiring 13 may scatter. In this respect, in the example of Figure 3, the upper end 50a of the pad 50 is located below the uppermost surface 10a of the connecting wiring 13. Therefore, during CMP, at least one layer is provided on the upper surface of the pad 50, and this layer prevents the scattered material from adhering to the upper surface of the pad 50. This is advantageous in that it prevents corrosion of the upper surface of the pad 50 and makes it less likely for defects in wire bonding to the pad 50 to occur. In the manufacturing method described later, at least one layer is an insulating layer 61 and an insulating layer 62. The layout in which the upper end 50a is located below the uppermost surface 10a of the connecting wiring 13 is compatible with the layout in which the pixel electrode 71 is positioned above the pad 50.

[0072] On the other hand, in Embodiment 1, since the upper end 50a is positioned as described above, the pad 50 is less likely to be positioned excessively high, and in the illustrated example, the pad hole 55 is less likely to be excessively shallow. Therefore, foreign matter is less likely to come into contact with the pad 50. This can contribute to improving the reliability of the imaging device 1A.

[0073] Furthermore, in Embodiment 1, a layout is adopted in which the pixel electrode 71 is positioned above the pad 50. Because of this layout, the height of the pixel electrode 71 can be suppressed by preventing the pad 50 from being positioned excessively high, and the length of the pixel via 73 can be prevented from becoming excessively long. This can suppress parasitic capacitance between the pixel via 73 of one pixel 88 and the pixel via 73 of the adjacent pixel 88, suppress crosstalk between those pixels 88, and improve the reliability of the operation of the imaging device 1A. In a color imaging device, suppression of crosstalk can suppress color mixing. In the example in Figure 3, the length Dv in the vertical direction of the portion of the pixel via 73 located above the upper end of the second wiring layer 35 is shorter than the depth of the pad hole 55. Specifically, the length Dv in the vertical direction of the pixel via 73 is shorter than the depth of the pad hole 55. Here, the depth of the pad hole 55 is the dimension Dv in the vertical direction of the pad hole 55.

[0074] Specifically, in Embodiment 1, the upper end 50a is located below the upper end of the second wiring layer 35 and below the uppermost surface 10a of the connecting wiring 13. The upper end 50a is located above the upper end of the wiring layer 34. The lower end 50b is at the same height as the lower end of the first wiring layer 31.

[0075] Furthermore, in Embodiment 1, the pad 50 is located within the first substrate 21, while the photoelectric conversion film 81 is located above the first substrate 21. This layout allows for the formation of the photoelectric conversion film 81 after the formation of the pad 50 in the manufacturing method described later. This prevents the degradation of the characteristics of the photoelectric conversion film 81 due to the heat generated during the formation of the pad 50. This can contribute to improving the reliability of the imaging device 1A.

[0076] Figures 4 to 15 are explanatory diagrams for the manufacturing method of the imaging device 1A according to Embodiment 1. In reality, there may be a step in which the substrate that will become part of the imaging device 1A is physically inverted, but such a step will be omitted from the description below. In the following description as well, terms such as "up" and "down" are used solely to specify the relative positions of elements.

[0077] As shown in Figure 4, structure 2A is fabricated. Structure 2A includes a first semiconductor layer 22 and an insulating layer 60. The insulating layer 60 includes a first wiring layer 31, a wiring layer 32, a wiring layer 33, and a wiring layer 34. Although not shown in the figure, in structure 2A, a coating layer is provided on the upper surface 39a of the wiring 39 of the first wiring layer 31. The coating layer includes, for example, silicon nitride.

[0078] Next, as shown in Figure 5, holes 28 are formed in the insulating layer 60 by etching. This exposes the upper surface 39a of the wiring 39 upwards. Specifically, in this etching process, the wiring 39 and the coating layer act as etching stoppers. The coating layer suppresses the scattering of wiring 39 material during etching. During etching, the coating layer is removed, and the upper surface 39a of the wiring 39 is exposed. In this way, structure 2B is fabricated.

[0079] Next, as shown in Figure 6, the material for the second layer 52 is filled into the hole 28 to form the second layer 52. This forms the pad 50 and creates structure 2C. Next, as shown in Figure 7, the support substrate 29 is bonded to the upper surface of structure 2C via insulating layers 61 and 62 to create structure 2D. Next, as shown in Figure 8, the first semiconductor layer 22 is thinned by shaving it to create structure 2E.

[0080] Next, as shown in Figure 9, the second substrate 25 is bonded to the lower surface of the first semiconductor layer 22. That is, wafer bonding is performed. This forms a wafer stacked structure in which the structure including the first semiconductor layer 22 and the structure including the second semiconductor layer 26 are bonded to each other. Structure 2F is thus fabricated. When forming the wafer stacked structure, the pad 50 is provided on the first insulating layer 23 rather than the second insulating layer 27, so the pad 50 is less likely to obstruct the flatness of the bonding interface. Next, as shown in Figure 10, the support substrate 29 is removed from structure 2F to fabricate structure 2G.

[0081] Next, as shown in Figure 11, trenches are formed in the insulating layer 62. Then, first holes are formed in the insulating layer 61, insulating layer 60, first semiconductor layer 22, and second insulating layer 27, and second holes are formed in the insulating layer 61 and insulating layer 60. Next, electrode material is embedded in the first holes, second holes, and trenches. This forms vias 11 in the first holes, vias 12 in the second holes, and connection wiring 13 in the trenches. This forms through electrodes 10. Next, the top surface 10a of the connection wiring 13 and the top surface of the insulating layer 62 are smoothed by CMP. In this way, structure 2H is fabricated. During CMP, since the pad 50 is covered from above by the insulating layer 61 and insulating layer 62, the material of the connection wiring 13 is prevented from scattering onto the top surface of the pad 50.

[0082] Next, as shown in Figure 12, an insulating layer 63 is deposited on the insulating layer 62 and the through electrode 10. Next, third holes are formed in the insulating layer 63, insulating layer 62, insulating layer 61 and insulating layer 60. Next, electrode material is embedded in the third holes. This forms pixel vias 73 in the third holes. Next, an insulating layer 69 is deposited on the insulating layer 63 and the pixel vias 73. Next, the portion of the insulating layer 69 that is to be formed for the control electrode 72 and the multiple pixel electrodes 71 is etched. Next, the etched portion is filled with electrode material that will become the control electrode 72 and the pixel electrode 71. At this time, electrode material is also deposited on the insulating layer 69. Next, polishing is performed so that the portion of the electrode material on the insulating layer 69 is removed and the upper surface of the portion of the electrode material corresponding to the control electrode 72 and the upper surface of the portion corresponding to the multiple pixel electrodes 71 are smoothed. This polishing is performed by CMP. In this way, structure 2I is created.

[0083] Next, as shown in Figure 13, a photoelectric conversion film 81, a counter electrode 82, an insulating film 83, a light-shielding film 84, and a protective film 85 are formed on the control electrode 72, a plurality of pixel electrodes 71, and an insulating layer 69 to create structure 2J. Next, as shown in Figure 14, a pad hole 55 is formed that penetrates the protective film 85, insulating layer 69, insulating layer 63, insulating layer 62, and insulating layer 61 in that order so that the upper surface of the pad 50 is exposed to create structure 2K. Once structure 2K is obtained, PCM inspection is performed using the pad 50. Next, as shown in Figure 15, a color filter 86 and a microlens 87 are formed on the protective film 85 to create the imaging device 1A.

[0084] Other embodiments will be described below. In the following, elements common to embodiments already described and those described later will be given the same reference numerals, and their descriptions may be omitted. The descriptions of each embodiment may be mutually applicable, as long as they do not conflict technically. As long as they do not conflict technically, each embodiment may be combined with another. From the descriptions of each embodiment, it will be understood that there are degrees of freedom in the configuration and manufacturing method of the imaging apparatus according to this disclosure. For example, there are degrees of freedom in the height and shape of the pad 50.

[0085] (Embodiment 2) Figure 16 is a cross-sectional view of the imaging device 1B according to Embodiment 2. In the imaging device 1B, the upper end 50a of the pad 50 is located below the lower end of the wiring layer 34.

[0086] (Embodiment 3) Figure 17 is a cross-sectional view of the imaging device 1C according to Embodiment 3. In the imaging device 1C, the lower end 50b of the pad 50 is located above the lower end of the first wiring layer 31. Specifically, the lower end 50b is at the same height as the lower end of the wiring layer 32.

[0087] (Embodiment 4) Figure 18 is a cross-sectional view of the imaging device 1D according to Embodiment 4. In the imaging device 1D, the first width W1 is equal to the second width W2. Specifically, in the imaging device 1D, the side surface of the second layer 52 of the pad 50 extends parallel to the vertical direction Dv. In a cross-section parallel to the vertical direction Dv, the width of the second layer 52 is the same in all parts of the vertical direction Dv. A shape with the same width in all parts of the vertical direction Dv can be called a straight shape.

[0088] In the imaging device 1D, in a cross-section parallel to the vertical direction Dv, the width of the upper surface of the first layer 51 is the same as the width of the lower surface of the second layer 52. Specifically, the shape and dimensions of the upper surface of the first layer 51 are the same as the shape and dimensions of the lower surface of the second layer 52. The side surface of the first layer 51 and the side surface of the second layer 52 are continuous.

[0089] (Embodiment 5) Figure 19 is a cross-sectional view of the imaging device 1E according to Embodiment 5. Unlike the imaging device 1D according to Embodiment 4, in the imaging device 1E, in a plan view, the contact surfaces of the first layer 51 and the second layer 52 are contained within the outer edge of the first layer 51. Specifically, in a plan view, the entire contact surface is contained within the outer edge of the first layer 51. With this configuration, an electrical connection between the first layer 51 and the second layer 52 can be properly established.

[0090] (Embodiment 6) Figure 20 is a cross-sectional view of the imaging device 1F according to Embodiment 6. In the imaging device 1F, the width of the second layer 52 is smaller in a cross-section parallel to the vertical direction Dv compared to the imaging device 1A according to Embodiment 1. With this configuration, the electrical connection between the first layer 51 and the second layer 52 can be properly established.

[0091] (Embodiment 7) Figure 21 is a cross-sectional view of the imaging device 1G according to Embodiment 7. In the imaging device 1G, the first width W1 is greater than the second width W2. In the imaging device 1G, in a cross section parallel to the vertical direction Dv, the second layer 52 includes a tapered portion, and specifically, the tapered shape extends over the entire vertical direction Dv. Specifically, the tapered shape is an inverse tapered shape. In a cross section parallel to the vertical direction Dv, an element being an inverse tapered shape means that the side surface of the element is inclined with respect to the vertical direction Dv such that the width of the element increases downwards in that cross section.

[0092] In the imaging device 1G, in a cross-section parallel to the vertical direction Dv, the width of the upper surface of the first layer 51 is the same as the width of the lower surface of the second layer 52. Specifically, the shape and dimensions of the upper surface of the first layer 51 are the same as the shape and dimensions of the lower surface of the second layer 52. The side surface of the first layer 51 and the side surface of the second layer 52 are continuous.

[0093] (Embodiment 8) Figure 22 is a cross-sectional view of the imaging device 1H according to Embodiment 8. In the imaging device 1H, the first width W1 is smaller than the second width W2. In the imaging device 1H, in a cross-section parallel to the vertical direction Dv, the second layer 52 includes a tapered portion. Specifically, the tapered shape is a forward taper shape. In a cross-section parallel to the vertical direction Dv, the second layer 52 includes a portion in which the width changes in a step-like manner downwards. In a plan view, the contact surface of the first layer 51 and the second layer 52 is contained within the outer edge of the first layer 51. Specifically, in a plan view, the entire contact surface is contained within the outer edge of the first layer 51.

[0094] The second layer 52 includes a first portion 52a and a second portion 52b. The first portion 52a is located above the second portion 52b. In a cross section parallel to the vertical direction Dv, the width of the second layer 52 changes in a stepped manner at the boundary between the first portion 52a and the second portion 52b. In a cross section parallel to the vertical direction Dv, the width of the second portion 52b is smaller than the minimum width of the first portion 52a. In embodiment 8, the second portion 52b is a via. The first portion 52a includes a tapered portion in a cross section parallel to the vertical direction Dv. Specifically, the tapered shape is a forward taper shape.

[0095] (Embodiment 9) Figure 23 is a cross-sectional view of the imaging device 1I according to Embodiment 9. The imaging devices 1A to 1H according to Embodiments 1 to 8 described above are surface-illuminated types. In contrast, the imaging device 1I is a back-side illumination (BSI) type.

[0096] The first substrate 21 and the second substrate 25 are joined together such that the first insulating layer 23 and the second insulating layer 27 face each other. Specifically, the second semiconductor layer 26, the second insulating layer 27, the first insulating layer 23, and the first semiconductor layer 22 are arranged in order from bottom to top.

[0097] The first substrate 21 includes an amplifying transistor 74, a transfer transistor 75, a photodiode 78, and a charge storage region 79. The first semiconductor layer 22 is provided with the amplifying transistor 74, the transfer transistor 75, the photodiode 78, and the charge storage region 79.

[0098] The first insulating layer 23 includes an insulating layer 60. The insulating layer 60, the first semiconductor layer 22, the insulating layer 61, the insulating layer 62, and the insulating layer 63 are arranged in order from bottom to top. In Embodiment 9, the insulating layers 61, 62, and 63 are insulating layers separate from the first insulating layer 23.

[0099] The insulating layer 60 includes a plurality of wiring layers 30. The plurality of wiring layers 30 include a first wiring layer 31, a wiring layer 32, a wiring layer 33, and a wiring layer 34. The first wiring layer 31, a wiring layer 32, a wiring layer 33, and a wiring layer 34 are arranged in this order from bottom to top. In the first insulating layer 23, the first wiring layer 31 is the lowest wiring layer, and the wiring layer 34 is the highest wiring layer.

[0100] The wiring layer 34 includes wiring 36 and wiring 38. In the example in Figure 23, wiring 36 is located in peripheral region R2. However, wiring 36 may also be located in pixel region R1. At least a portion of wiring 38 is located in pixel region R1.

[0101] The amplifying transistor 74 includes a source 74s, a drain 74d, and a gate 74g. The transfer transistor 75 includes a source, a drain, and a gate 75g. One of the source and drain of the transfer transistor 75 is connected to a photodiode 78, and the other constitutes a charge storage region 79.

[0102] As shown in Figure 23, the source 74s and drain 74d of the amplifying transistor 74, the photodiode 78, and the charge storage region 79 are located within the first semiconductor layer 22. The gate 74g of the amplifying transistor 74 and the gate 75g of the transfer transistor 75 are located below the first semiconductor layer 22 and within the insulating layer 60.

[0103] The through-electrode 10 includes vias 11, 12, 14, and a connecting wire 13. The connecting wire 13 is located above the first wiring layer 31 and also above vias 11, 12, and 14. Vias 11, 12, and 14 are directly connected to the connecting wire 13. Via 11 extends deeper than vias 12 and 14. Via 11 penetrates the first semiconductor layer 22 and the first insulating layer 23 and is directly connected to wiring 46. Via 12 penetrates the first semiconductor layer 22 and is connected to wiring 36. Via 14 penetrates the first semiconductor layer 22 and is connected to wiring 38. The connecting wire 13 is flattened. The connecting wire 13 has an uppermost surface 10a.

[0104] In the example shown in Figure 23, via 11 is directly connected to the upper surface 46a of wiring 46. Via 12 is directly connected to the upper surface 36a of wiring 36. Via 14 is directly connected to the upper surface 38a of wiring 38. The connecting wiring 13 is at the same height as the insulating layer 61. The insulating layer 62 is located above the connecting wiring 13 and the insulating layer 61. The insulating layer 63 is located above the insulating layer 62. The light-shielding film 84 is located above the insulating layer 63.

[0105] Wiring 38 is electrically connected to the charge storage region 79 and the gate 74g. When light is shone on the photodiode 78, an electric charge is generated. The transfer transistor 75 transfers the charge from the photodiode 78 to the charge storage region 79. The amplification transistor 74 generates and outputs a signal corresponding to the potential of the charge storage region 79.

[0106] The light-shielding film 84 is located above the uppermost surface 10a of the through electrode 10. The protective film 85 is located above the light-shielding film 84. The color filter 86 is located above the protective film 85. The microlens 87 is located above the color filter 86.

[0107] The light-shielding film 84 blocks light from one or more of the multiple pixels 88. The light-shielded pixels 88 function as optical black pixels.

[0108] In the imaging device 1I, the upper end 50a of the pad 50 is located below the uppermost surface 10a of the connecting wiring 13. The upper end 50a is located above the upper end of the wiring layer 34. The lower end 50b of the pad 50 is located at the same height as the lower end of the first wiring layer 31 or above the lower end of the first wiring layer 31. Specifically, the lower end 50b is at the same height as the lower end of the first wiring layer 31.

[0109] In imaging device 1I, in a cross-section parallel to the vertical direction Dv, the first width W1 is different from the second width W2. Specifically, the first width W1 is smaller than the second width W2. In imaging device 1I, in a cross-section parallel to the vertical direction Dv, the second layer 52 includes a portion in which the width changes in a stepped manner toward the bottom. In imaging device 1H, in a plan view, the contact surface of the first layer 51 and the second layer 52 is contained within the outer edge of the first layer 51. Specifically, in a plan view, the entire contact surface is contained within the outer edge of the first layer 51.

[0110] The second layer 52 includes a first portion 52a and a second portion 52b. The first portion 52a is located above the second portion 52b. In a cross section parallel to the vertical direction Dv, the width of the second layer 52 changes in a stepped manner at the boundary between the first portion 52a and the second portion 52b. In a cross section parallel to the vertical direction Dv, the width of the second portion 52b is smaller than the minimum width of the first portion 52a. In embodiment 9, the second portion 52b is a via. The first portion 52a has a straight shape in which its width is the same in all parts in the vertical direction Dv.

[0111] (Embodiment 10) Figure 24 is a cross-sectional view of the imaging device 1J according to Embodiment 10. The imaging device 1J is a back-illuminated type. Similar to the imaging device 1A in Figure 3, the imaging device 1J has a photoelectric conversion film 81 located above the first semiconductor layer 22. Photoelectric conversion takes place in the photoelectric conversion film 81.

[0112] The first substrate 21 includes an amplification transistor 74, a reset transistor 76, and a charge storage region 77. The first semiconductor layer 22 is provided with the amplification transistor 74, the reset transistor 76, and the charge storage region 77. In embodiment 10, the reset transistor 76 includes a source, a drain, and a gate 76g. One of the source and drain of the reset transistor 76 is the charge storage region 77.

[0113] As shown in Figure 24, the source 74s and drain 74d of the amplification transistor 74, the source and drain of the reset transistor 76, and the charge storage region 77 are located within the first semiconductor layer 22. The gate 74g of the amplification transistor 74 and the gate 76g of the reset transistor 76 are located below the first semiconductor layer 22 and within the insulating layer 60.

[0114] The wiring layer 34 includes wiring 36 and pixel wiring 37. Pixel vias 73 penetrate the first semiconductor layer 22. Pixel electrodes 71, gates 74g, and charge storage regions 77 are electrically connected by pixel vias 73 and pixel wiring 37.

[0115] When light is shone on the photoelectric conversion film 81, an electric charge is generated. The generated charge is collected by the pixel electrode 71 and sent from the pixel electrode 71 to the charge storage region 77 via the pixel via 73 and pixel wiring 37, where it is stored. The amplification transistor 74 generates and outputs a signal corresponding to the potential of the charge storage region 77. The reset transistor 76 can reset the charge and potential in the charge storage region 77.

[0116] Various technologies can be applied to Embodiments 1 to 10. For example, the imaging device may be a color imaging device or a monochrome imaging device.

[0117] In embodiments 1 to 10 described above, the semiconductor device is an imaging device. In the case of an imaging device, the benefits of reliability improvement based on embodiments 1 to 10 can be enjoyed in the form of improved image quality reliability. However, the semiconductor device may be a device other than an imaging device, such as a semiconductor memory such as DRAM (Dynamic Random Access Memory) or a solar cell. The technology related to imaging devices described above can be applied to devices other than imaging devices.

[0118] As can be understood from embodiments 1 to 10 described above, in a cross section parallel to the vertical direction Dv, part or all of the pad 50 may be tapered. The tapered shape may be a forward taper or an inverse taper. Furthermore, the tapered shape may have a straight side surface in a cross section parallel to the vertical direction Dv, or a curved side surface in a cross section parallel to the vertical direction Dv.

[0119] The form of the pad 50 is not limited to the embodiments 1 to 10 described above. In one example, which is not shown, the width of the second portion 52b is greater than the minimum width of the first portion 52a in a cross section parallel to the vertical direction Dv.

[0120] In the back-illuminated imaging devices of embodiments 9 and 10 described above, the first portion 52a has a straight shape. However, it is not essential that the first portion 52a has a straight shape. The first portion 52a can have any shape. For example, the first portion 52a may have the same shape as the first portion 52a described in embodiments 1 to 8.

[0121] The pad 50 may be constructed using wiring or not. Specifically, the first layer 51 may or may not be wiring.

[0122] (Embodiment 11) Referring to Figure 25, the camera system 90 according to Embodiment 11 will be described.

[0123] Figure 25 schematically shows an example configuration of a camera system 90 according to Embodiment 11. The camera system 90 includes a lens optical system 91, an imaging device 92, a system controller 93, and a camera signal processing circuit 94. The camera system 90 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0124] The lens optical system 91 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The lens optical system 91 focuses light onto the imaging plane of the imaging device 92. As the imaging device 92, imaging devices according to embodiments 1 to 10 described above and their modifications can be widely used.

[0125] The system controller 93 controls the entire camera system 90. The system controller 93 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0126] The camera signal processing circuit 94 has the function of processing the output signal from the imaging device 92. The camera signal processing circuit 94 receives output data from the imaging device 92 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 92 and the camera signal processing circuit 94 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 92 as part can be made smaller. The camera signal processing circuit 94 may be, for example, a DSP (Digital Signal Processor).

[0127] (Note) This disclosure provides for the following technologies:

[0128] (Technology 1) circuit board and The pad that is exposed at the top, Equipped with, The substrate includes a semiconductor layer and an insulating layer. The insulating layer includes a first wiring layer and a second wiring layer located above the first wiring layer. The pad comprises a first layer and a second layer containing a material different from the first layer. The lower end of the pad is located at the same height as the lower end of the first wiring layer or above the lower end of the first wiring layer. The upper end of the pad is located at the same height as the upper end of the second wiring layer or below the upper end of the second wiring layer. Semiconductor equipment.

[0129] (Technology 2) vias penetrating the aforementioned semiconductor layer, The system includes a connecting wire that connects directly to the via, The upper end of the pad is located at the same height as or below the uppermost surface of the connecting wiring. The semiconductor device described in Technical 1.

[0130] (Technology 3) The insulating layer is provided without penetrating the semiconductor layer and includes a pad hole that exposes a portion of the pad, A semiconductor device as described in Technical 1 or 2.

[0131] (Technology 4) The insulating layer is located above the semiconductor layer. A semiconductor device as described in any one of the three technical specifications.

[0132] (Technology 5) It further includes a photoelectric conversion film that converts incident light into electric charge, A semiconductor device as described in any one of the technical items 1 to 4.

[0133] (Technology 6) The pad is located within the substrate, The photoelectric conversion film is located above the substrate, The semiconductor device described in Technical 5.

[0134] (Technology 7) The second layer is located above the first layer. In a cross-section parallel to the vertical direction, the first width of the lower surface of the second layer is different from the second width of the upper surface of the second layer. A semiconductor device as described in any one of the technical items 1 to 6.

[0135] (Technology 8) The first width is smaller than the second width. A semiconductor device as described in Technical 7.

[0136] (Technology 9) The first width is larger than the second width. A semiconductor device as described in Technical 7.

[0137] (Technology 10) In a cross-section parallel to the vertical direction, the second layer includes a tapered portion. A semiconductor device as described in any one of the technical items 1 to 9.

[0138] (Technology 11) In a cross-section parallel to the vertical direction, the second layer includes a portion in which the width changes in a stepped manner toward the bottom. A semiconductor device as described in any one of the technical specifications 1 to 10.

[0139] (Technology 12) In a plan view, the contact surface between the first layer and the second layer is contained within the outer edge of the first layer. A semiconductor device as described in any one of the technical specifications 1 to 11.

[0140] (Technology 13) circuit board and The pad that is exposed at the top, Beer and, Equipped with connecting wiring, The substrate includes a semiconductor layer and an insulating layer. The insulating layer includes a first wiring layer, The via penetrates the semiconductor layer, The aforementioned connection wiring is directly connected to the via, The pad comprises a first layer and a second layer containing a material different from the first layer. The lower end of the pad is located at the same height as the lower end of the first wiring layer or above the lower end of the first wiring layer. The upper end of the pad is located at the same height as or below the uppermost surface of the connecting wiring. Semiconductor equipment.

[0141] (Technology 14) The semiconductor device is an imaging device, as described in any one of the Art 1 to 13.

[0142] (Technology 15) The imaging apparatus described in Technical 14, The imaging device comprises a lens optical system that focuses light onto the imaging surface, A camera signal processing circuit that processes the output signal from the imaging device, Equipped with, Camera system.

[0143] (Technology 16) A method for manufacturing a semiconductor device as described in any one of the Technical Items 1 to 14, The semiconductor device further comprises a photoelectric conversion film that converts incident light into electric charge, Forming the aforementioned pad, The method comprises forming the photoelectric conversion film after forming the pad, Manufacturing method. [Industrial applicability]

[0144] According to this disclosure, reliable semiconductor devices can be provided. [Explanation of Symbols]

[0145] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 92 Imaging devices 10 Through electrode 10a Top surface 11, 12, 14, 73 Beer 13 Connection Wiring 21, 25, 29 circuit boards 22, 26 Semiconductor layer 23, 27 Insulating layer 32, 33, 34, 45 wiring layer 31 1st wiring layer 35 2nd wiring layer Wiring 36, 37, 38, 39, 46 50 pads 50a top end 50b bottom end 51 1st layer 52 2nd layer 52a Part 1 52b Part 2 55 pad holes 60, 61, 62, 63, 69 Insulating layer 71 Pixel electrodes 72 Control electrodes 74, 75, 76 transistors 77, 79 Charge storage region 78 Photodiode 81 Photoelectric conversion film 82 Counterelectrode 83 Insulating Film 84 Light-shielding film 85 Protective film 86 Color Filters 87 Microlenses 88 pixels 90 Camera System 91 Lens Optics 93 System Controller 94 Camera signal processing circuit 112 Signal detection circuit 113 Feedback Circuit 116 Vertical scanning circuit 117 Accumulation control line 118 Vertical signal line 119 Load circuit 120-column signal processing circuit 121 Horizontal signal readout circuit 122 Power wiring 123 Horizontal common signal line 124 Inverting Amplifier 125 Feedback Line 126 Reset signal line 128 Feedback control line 130 Address signal line 132 Sensitivity adjustment line 138 Feedback Transistors 140 Address Transistors 141 First Capacitance Element 142 Second Capacitive Element 144 Charge Storage Nodes 146 Reset Drain Node Dv vertical direction R1 Pixel Region R2 surrounding area

Claims

1. circuit board and The pad that is exposed at the top, Equipped with, The substrate includes a semiconductor layer and an insulating layer. The insulating layer includes a first wiring layer and a second wiring layer located above the first wiring layer. The pad comprises a first layer and a second layer containing a material different from the first layer. The lower end of the pad is located at the same height as the lower end of the first wiring layer or above the lower end of the first wiring layer. The upper end of the pad is located at the same height as the upper end of the second wiring layer or below the upper end of the second wiring layer. Semiconductor equipment.

2. vias penetrating the aforementioned semiconductor layer, The system includes a connecting wire that connects directly to the via, The upper end of the pad is located at the same height as or below the uppermost surface of the connecting wiring. The semiconductor device according to claim 1.

3. The insulating layer is provided without penetrating the semiconductor layer and includes a pad hole that exposes a portion of the pad, The semiconductor device according to claim 1.

4. The insulating layer is located above the semiconductor layer. The semiconductor device according to claim 1.

5. It further includes a photoelectric conversion film that converts incident light into electric charge, The semiconductor device according to claim 1.

6. The pad is located within the substrate, The photoelectric conversion film is located above the substrate, The semiconductor device according to claim 5.

7. The second layer is located above the first layer. In a cross-section parallel to the vertical direction, the first width of the lower surface of the second layer is different from the second width of the upper surface of the second layer. The semiconductor device according to claim 1.

8. The first width is smaller than the second width. The semiconductor device according to claim 7.

9. The first width is larger than the second width. The semiconductor device according to claim 7.

10. In a cross-section parallel to the vertical direction, the second layer includes a tapered portion. The semiconductor device according to claim 1.

11. In a cross-section parallel to the vertical direction, the second layer includes a portion in which the width changes in a stepped manner toward the bottom. The semiconductor device according to claim 1.

12. In a plan view, the contact surface between the first layer and the second layer is contained within the outer edge of the first layer. The semiconductor device according to claim 1.

13. circuit board and The pad that is exposed at the top, Beer and, Equipped with connecting wiring, The substrate includes a semiconductor layer and an insulating layer. The insulating layer includes a first wiring layer, The via penetrates the semiconductor layer, The aforementioned connection wiring is directly connected to the via, The pad comprises a first layer and a second layer containing a material different from the first layer. The lower end of the pad is located at the same height as the lower end of the first wiring layer or above the lower end of the first wiring layer. The upper end of the pad is located at the same height as or below the uppermost surface of the connecting wiring. Semiconductor equipment.

14. The semiconductor device is an imaging device, as described in any one of claims 1 to 13.

Images