3D memory device and method for manufacturing the same

Abstract

The present invention provides a three-dimensional memory device and a method for manufacturing the same, which improve the electrical and memory characteristics of three-dimensionally highly integrated memory elements. [Solution] The three-dimensional memory device according to the present invention includes a substrate, a filler CS having a capping layer CPL, a fluorine-doping layer FDL, a channel layer CHL, and a memory layer CML, and a gate electrode layer. The capping layer extends in the height direction DR3 on the substrate. The fluorine-doping layer surrounds the sides of the capping layer, extends in the height direction, and contains a fluoropolymer. The channel layer surrounds the sides of the fluorine-doping layer, extends in the height direction, and contains polysilicon in which fluorine is diffused. The memory layer surrounds the sides of the channel layer and extends in the height direction. The gate electrode layer surrounds the sides of the memory layer.

Description

[Technical Field]

[0001] The present invention relates to a memory semiconductor, and more particularly to a three-dimensional memory device and a method for manufacturing the same. [Background technology]

[0002] Memory semiconductors can be classified into volatile memory and non-volatile memory. Volatile memory (e.g., DRAM and SRAM) has fast read / write speeds, but the stored data is lost if the power supply is cut off. On the other hand, non-volatile memory can retain data even if the power supply is interrupted. A typical example of non-volatile memory is flash memory. Flash memory is widely used as a storage device in electronic devices such as personal computers, smartphones, and digital cameras.

[0003] The absolute amount of data to be processed is rapidly increasing due to the advancement of AI technology, the rise of IoT, autonomous driving, and smart systems (smart homes, farms, factories, etc.). Flash memory is demanding increased storage capacity and higher integration density to meet this trend. As a result, flash memory with memory elements arranged in three dimensions is gaining attention. Three-dimensional memory devices have the advantage of high integration density and high storage capacity relative to area. However, as the integration density increases in a three-dimensional arrangement, the electrical characteristics and memory characteristics of the memory may deteriorate. [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention aims to provide a three-dimensional memory device with improved electrical and memory characteristics under a high integration density of memory elements.

[0005] Furthermore, the present invention aims to provide a method for manufacturing a three-dimensional memory device that can uniformly diffuse fluorine throughout the channel layer while reducing damage to the channel layer, in order to improve the performance of the three-dimensional memory device. [Means for solving the problem]

[0006] A three-dimensional memory device according to one embodiment of the present invention includes a substrate, a capping layer, a doping layer, a channel layer, a memory layer, and a gate electrode layer. The capping layer extends in the height direction away from the substrate on the substrate. The fluorine-doping layer surrounds the sides of the capping layer, extends in the height direction, and contains a fluoropolymer. The channel layer surrounds the sides of the fluorine-doping layer, extends in the height direction, and contains polysilicon in which fluorine is diffused. The memory layer surrounds the sides of the channel layer. The gate electrode layer surrounds the sides of the memory layer.

[0007] As an example, the fluoropolymer may include at least one polymer from among PFDA (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-Heptadecafluorodecyl acrylate), PFDMA (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluorodecyl methacrylate), C6FA (3,3,4,4,5,5,6,6,7,7,8,8,8-Tridecafluorooctyl acrylate), and C4FA (3,3,4,4,5,5,6,6,6-Nonafluorohexyl acrylate).

[0008] As an example, the fluorine-doping layer may be in contact with the inner surface of the channel layer and cover the entire inner surface of the channel layer.

[0009] For example, the capping layer may contain aluminum oxide.

[0010] For example, the fluorine doping concentration in the channel layer may be higher than that in the capping layer.

[0011] For example, the outer surface of the channel layer may be in contact with the memory layer and may contain diffused fluorine.

[0012] As an example, the memory layer may include a tunnel layer adjacent to and surrounding the side of the channel layer, a charge trapping layer surrounding the side of the tunnel layer, and a blocking layer surrounding the side of the charge trapping layer.

[0013] For example, a fluorine-doped layer can face a gate electrode layer with a channel layer in between.

[0014] A method for manufacturing a three-dimensional memory device according to one embodiment of the present invention includes the steps of: forming a laminated structure on a substrate; forming channel holes that penetrate the laminated structure in the height direction; forming a memory layer on the inner surface of the laminated structure defined by the channel holes; forming a channel layer on the inner surface of the memory layer; forming a fluorine-doping layer containing a fluoropolymer on the inner surface of the channel layer; forming a capping layer on the inner surface of the fluorine-doping layer; and diffusing fluorine from the fluorine-doping layer to the channel layer by heat treatment.

[0015] As an example, the step of forming a fluorine-doped layer may include injecting a monomer containing an initiator and fluorine in a gaseous state so that it reaches the layered structure; heating the initiator to generate radicals; adsorbing the monomer and radicals onto the surface of the channel layer; and forming a thin film containing a fluorine polymer based on a polymer polymerization reaction by the radicals.

[0016] For example, the monomer may contain at least one of PFDA, PFDMA, C6FA, and C4FA, and the fluoropolymer may contain at least one of pPFDA (poly-PFDA), pPFDMA (poly-PFDMA), pC6FA (poly-C6FA), and pC4FA (poly-C4FA).

[0017] As an example, the initiator may be DTBP (di-tert-butyl peroxide).

[0018] As an example, the step of generating radicals may comprise the step of decomposing the initiator into radicals by means of a heating filament disposed spaced apart above the laminated structure.

[0019] As an example, the temperature of the substrate caused by heating in the step of generating radicals may be lower than the temperature of the substrate caused by heat treatment in the step of diffusing fluorine.

[0020] As an example, the method may further comprise the step of removing the fluorine-doped layer and the capping layer after the step of diffusing fluorine.

[0021] As an example, the method may further comprise the step of filling a filler into a position where the fluorine-doped layer and the capping layer have been removed.

[0022] As an example, the capping layer may comprise aluminum oxide.

[0023] As an example, in the step of diffusing fluorine, diffusion of fluorine in a direction away from the channel layer by the capping layer may be suppressed.

[0024] As an example, in the step of diffusing fluorine, fluorine may diffuse to an outer surface of the channel layer.

[0025] As an example, the step of forming the memory layer may comprise the step of forming a blocking layer on an inner surface of the laminated structure, the step of forming a charge trapping layer on an inner surface of the blocking layer, and the step of forming a tunnel layer on an inner surface of the charge trapping layer. Effects of the Invention

[0026] According to one embodiment of the present invention, a three-dimensional memory device can improve the electrical and memory characteristics of highly integrated three-dimensional memory elements by diffusing fluorine into the channel layer using a fluorine-doping layer and a capping layer.

[0027] Furthermore, according to one embodiment of the present invention, a three-dimensional memory device and a method for manufacturing the same can uniformly diffuse fluorine throughout the channel layer while minimizing damage to the channel layer by forming a fluorine-doped layer using iCVD (initiated Chemical Vapor Deposition) technology. [Brief explanation of the drawing]

[0028] [Figure 1] This is a perspective view of a three-dimensional memory device according to one embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram of a 3D memory device. [Figure 3] This is a diagram illustrating the filler in Figure 1 in an illustrative way. [Figure 4] Figure 3 is a cross-sectional view illustrating the process of fluorine diffusion in the filler. [Figure 5] This is a diagram illustrating the filler in Figure 1 in an illustrative way. [Figure 6] Figure 1 is an illustrative sequence diagram of a manufacturing method for a three-dimensional memory device. [Figure 7a] Figure 1 is a cross-sectional view showing the manufacturing steps of a three-dimensional memory device. [Figure 7b] Figure 1 is a cross-sectional view showing the manufacturing steps of a three-dimensional memory device. [Figure 7c] Figure 1 is a cross-sectional view showing the manufacturing steps of a three-dimensional memory device. [Figure 7d] Figure 1 is a cross-sectional view showing the manufacturing steps of a three-dimensional memory device. [Figure 7e] Figure 1 is a cross-sectional view showing the manufacturing steps of a three-dimensional memory device. [Figure 8] Figure 6 is a step-by-step diagram illustrating the steps involved in forming the doping control layer. [Figure 9]Figure 6 is a schematic diagram illustrating the steps involved in forming the doping control layer. [Figure 10] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 11] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 12] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 13] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 14] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 15] This graph illustrates the improvement in the electrical characteristics of a three-dimensional memory device according to an embodiment of the present invention. [Figure 16] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Figure 17] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Figure 18] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Figure 19] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Figure 20] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Figure 21] This graph illustrates the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] Preferred embodiments of the present invention will be described in more detail below with reference to the attached drawings. In the drawings, the proportions and dimensions of the components may be exaggerated for the sake of effective explanation of the technical content.

[0030] Terms such as "includes" should be understood to indicate the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, without prejudice to the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0031] Furthermore, when the term "above" is used for a component, it means either above or below that component, and does not necessarily mean that it is located on the upper side relative to the direction of gravity.

[0032] Furthermore, when it is stated that one component is “connected” or “joined” with another component, this may include not only cases where the component is directly connected or joined to another component, but also cases where the component is indirectly connected or joined through another component.

[0033] Furthermore, while terms such as "first," "second," etc., may be used to describe a particular component, such terms are used to distinguish that component from other components, and are not intended to limit the essence, order, or sequence of that component.

[0034] Figure 1 is a perspective view of a three-dimensional memory device according to one embodiment of the present invention. To illustrate the three-dimensional memory device MEM according to an embodiment of the present invention, first to third directions DR1 to DR3 perpendicular to each other are defined. The three-dimensional memory device MEM may include, but is not limited to, V-NAND flash memory, and can be applied to various memory devices arranged in three dimensions. Referring to Figure 1, the three-dimensional memory device MEM includes a substrate SUB, a gate electrode layer GE, an insulating layer IL, a filler CS, and an upper conductive pattern.

[0035] The substrate SUB may be a semiconductor substrate, and for example, it may be a p-type substrate. The substrate SUB has planes defined by a first direction DR1 and a second direction DR2. For example, as shown in the figure, a common source line CSL may be provided to the substrate SUB. The common source line CSL may extend in the first direction DR1. The common source line CSL is electrically connected to a channel formed in the filler CS.

[0036] The gate electrode layer GE and the insulating layer IL are placed on the substrate SUB. The gate electrode layer GE and the insulating layer IL can be repeatedly stacked in a third direction DR3. Such a stacked structure can be called a stacked structure. The gate electrode layer GE and the insulating layer IL surround the filler CS. Contrary to the illustration, the memory layer where data is stored and the insulating layer IL may be stacked, and the gate electrode layer may surround the stacked structure. Such a stacked structure may be made by stacking target layers (for example, the gate electrode layer GE and the insulating layer IL), but it can also be made by repeatedly stacking a first target layer and a sacrificial layer, forming the filler CS so that it penetrates them, then removing the sacrificial layer and forming a second target layer in the position where the sacrificial layer was removed.

[0037] The gate electrode layer GE contains a conductive material and is arranged in a third direction DR3. The gate electrode layer GE surrounds at least a portion of the side surface of the filler CS. The gate electrode layer GE includes a string selection line SSL, word lines WL0 to WL7, and a ground selection line GSL. The string selection line SSL, together with the filler CS, can form a string selection transistor SST. The word lines WL0 to WL7, together with the filler CS, can form a memory cell transistor MCT. The ground selection line GSL, together with the filler CS, can form a ground selection transistor GST. The string selection line SSL, word lines WL0 to WL7, and ground selection line GSL can electrically connect the string selection transistor SST, the memory cell transistor MCT, and the ground selection transistor GST to a drive circuit (not shown), respectively.

[0038] The insulating layer IL contains an insulating material and is arranged in the third direction DR3. The insulating layer IL surrounds at least a portion of the sides of the filler CS. The insulating layer IL may contain an oxide. The insulating layer IL can isolate the string selection line SSL, the word lines WL0-WL7, and the ground selection line GSL from each other, and can isolate the string selection transistor SST, the memory cell transistor MCT, and the ground selection transistor GST from each other.

[0039] The filler CS extends in the third direction DR3, penetrating the insulating layer IL and the gate electrode layer GE. The filler CS is arranged two-dimensionally with respect to the first direction DR1 and the second direction DR2. The filler CS is in contact with the substrate SUB and can be electrically connected to the common source line CSL. The filler CS forms a channel between the upper conductive pattern and the common source line CSL. The specific details of the filler CS will be described later.

[0040] The upper conductive pattern contains a conductive material and is positioned on top of the laminated structure STS and filler CS. The upper conductive pattern includes a contact pattern DR and bit lines BL0 to BL2. The contact pattern DR can electrically connect the bit lines BL0 to BL2 and the filler CS. The bit lines BL0 to BL2 may be extended in a second direction DR2 and arranged in a first direction DR1.

[0041] Figure 2 is a circuit diagram of the three-dimensional memory device shown in Figure 1. Referring to Figure 2, the three-dimensional memory device MEM includes a common source line CSL, bit lines BL0 to BL2, string selection line SSL, word lines WL0 to WL7, ground selection line GSL, and cell string CS. The cell string CS includes a string selection transistor SST, a memory cell transistor MCT, and a ground selection transistor GST.

[0042] Bit lines BL0 to BL2 may be arranged in the first direction DR1. Multiple cell strings CS may be connected in parallel to each of the bit lines BL0 to BL2. Multiple cell strings CS may be connected in common to a common source line CSL. Multiple cell strings CS may be placed between multiple bit lines BL0 to BL2 and one common source line CSL. There may be multiple common source lines CSL, and multiple common source lines CSL may be arranged in the second direction DR2. However, this is not limited to this, and there may be only one common source line CSL. The same voltage may be applied electrically to the common source line CSL, but this is not limited to this.

[0043] A cell string CS may consist of a ground-selection transistor GST connected to a common source line CSL, a string-selection transistor SST connected to one of the bit lines BL0 to BL2, and a memory cell transistor MCT positioned between the ground-selection transistor GST and the string-selection transistor SST. One ground-selection transistor GST, multiple memory cell transistors MCT, and one string-selection transistor SST may be connected in series. The common source line CSL may be connected in common to the sources of multiple ground-selection transistors GST.

[0044] The ground selection line GSL, word lines WL0-WL7, and string selection line SSL can be used as gate electrodes for the ground selection transistor GST, memory cell transistor MCT, and string selection transistor SST, respectively. The ground selection transistor GST can connect the cell string CS to the common source line CSL based on the selection signal received from the connected ground selection line GSL. The string selection transistor SST can connect the cell string CS to one of the bit lines BL0-BL2 based on the selection signal received from the connected string selection line SSL.

[0045] Furthermore, each memory cell transistor (MCT) can be selected to enable read or write operations based on selection signals received from word lines WL0 to WL7. The memory cell transistor (MCT) includes a memory element for storing data by trapping charge. The memory element can perform write operations to store data by trapping charge, read operations to output data by controlling the current flowing through the channel based on the trapped charge, and erase stored data by releasing the trapped charge.

[0046] The need to increase the integration density of memory cell transistors (MCTs) leads to an increase in the number of MCTs arranged in the third direction DR3, and a decrease in the spacing between them. In other words, the height of the filler CS in Figure 1 increases, and the height of the word lines WL0 to WL7 decreases. The short channel effect associated with the shorter gate length can be mitigated by reducing the cell diameter and increasing gate controllability. In other words, the diameter of the filler CS decreases, and the channel can become thinner.

[0047] Increasing the height of the filler CS increases the channel resistance and decreases the cell string current. A thinner channel reduces the grain size, also decreasing the cell string current. Furthermore, an increase in grain boundaries within the channel raises the transistor's threshold voltage. These problems caused by changes in electrical characteristics can be solved by passivating the interface trap site created by the dangling bond between the channel and the gate insulating layer. This invention allows for fluorine passivation using iCVD technology, and the specific details of this will be described later.

[0048] Figure 3 is an illustrative diagram of the filler in Figure 1. Referring to Figure 3, the filler CS includes the memory layer CML, the channel layer CHL, and the doping control layer DCL. The memory layer CML, the channel layer CHL, and the doping control layer DCL are extended in the third direction DR3. The filler CS is surrounded by the gate electrode layer GE.

[0049] The memory layer CML corresponds to the memory elements described in Figure 2 and can store data by trapping charge. The memory layer CML is located between the gate electrode layer GE and the channel layer CHL as described. The memory layer CML surrounds the sides of the channel layer CHL. One filler CS may consist of one memory layer CML, but is not limited to this; it can be separated as many times as there are memory cell transistors MCTs. In this case, the memory layer CML may surround the channel layer CHL at the position corresponding to one memory cell transistor MCT. The memory layer CML may include a tunnel layer TNL, a charge trapping layer CTL, and a blocking layer BLL. However, it is not limited to these; any layer that can trap charge and store data may be called a memory layer CML even if it differs from the aforementioned layers.

[0050] The blocking layer (BLL) is positioned between the gate electrode layer (GE) and the charge trapping layer (CTL). The blocking layer (BLL) surrounds the sides of the charge trapping layer (CTL). Contrary to the illustration, the blocking layer (BLL) may be separated by the number of memory cell transistors (MCTs), and may further cover the upper and lower parts of the similarly separated charge trapping layers (CTL). The blocking layer (BLL) is configured to block the movement of charges trapped in the charge trapping layer (CTL) from the channel layer (CHL) to the gate electrode layer (GE). The blocking layer (BLL) contains an insulating material, which may be aluminum oxide (Al2O3) as an example. The blocking layer (BLL) may have a higher bandgap energy than the charge trapping layer (CTL). For example, the blocking layer (BLL) may be formed by atomic layer deposition (ALD).

[0051] The charge trapping layer (CTL) is positioned between the blocking layer (BLL) and the tunnel layer (TNL). The charge trapping layer (CTL) surrounds the sides of the tunnel layer (TNL). Contrary to the illustration, the charge trapping layer (CTL) may be isolated for each memory cell transistor (MCT), and may further cover the upper and lower parts of the similarly isolated tunnel layer (TNL). The charge trapping layer (CTL) is configured to trap charges injected from the channel layer (CHL) by a gate voltage applied from the gate electrode layer (GE). Exemplarily, the charge trapping layer (CTL) may be Si3N4 formed by atomic layer deposition.

[0052] The tunnel layer (TNL) is located between the charge trapping layer (CTL) and the channel layer (CHL). The tunnel layer (TNL) surrounds the sides of the channel layer (CHL). Contrary to the illustration, the tunnel layer (TNL) can be isolated as many times as there are memory cell transistors (MCTs). Exemplarily, the insulating layer (IS) of a stacked structure (STS) can be used to form isolated tunnel layers (TNL). As an example, the tunnel layer (TNL) may contain, but is not limited to, an oxide such as silicon oxide. Exemplarily, the tunnel layer (TNL) can be formed by atomic layer deposition.

[0053] The tunnel layer (TNL) is configured to control the movement of charge between the charge trapping layer (CTL) and the channel layer (CHL) by a gate voltage. When the band gap energy between the CTL and CHL is large due to the gate voltage, the band gradient of the TNL changes. This tunneling allows charge to move between the CTL and CHL. Otherwise, the TNL can act as an energy barrier.

[0054] The channel layer CHL is located between the memory layer CML and the doping control layer DCL. The channel layer CHL surrounds the sides of the doping control layer DCL. The channel layer CHL extends along a third direction DR3. The channel layer CHL is configured to form a channel through which charge moves between the bit lines BL0-BL2 and the common source line CSL. Charge present in the channel layer CHL can be injected into the memory layer CML based on the gate voltage. Charge injected into the memory layer CML can be released into the channel layer CHL based on the gate voltage. Exemplarily, the channel layer CHL may, but is not limited to, polysilicon.

[0055] The channel layer CHL contains fluorine diffused from the doping control layer DCL. As described above, increasing integration density reduces the thickness of the channel layer CHL in the second direction DR2 and increases its length in the third direction DR3. This reduces the cell string current and increases the transistor threshold voltage. For this reason, the entire inner surface of the channel layer CHL is in contact with the doping control layer DCL and can be doped with fluorine flowing in from the doping control layer DCL. The diffused fluorine can be provided to the outer surface of the channel layer CHL that is in contact with the memory layer CHL. This can passivate the interface trap region.

[0056] The doping control layer DCL may diffuse fluorine into the channel layer CHL to improve the electrical properties caused by the increase in height and decrease in diameter of the filler CS and the decrease in thickness of the channel layer CHL mentioned above. For this purpose, the doping control layer DCL may include a fluorine doping layer FDL and a capping layer CPL. The doping control layer DCL is in contact with the inner surface of the channel layer CHL.

[0057] The fluorine-doped layer FDL is positioned between the channel layer CHL and the capping layer CPL. The fluorine-doped layer FDL is in contact with the inner surface of the channel layer CHL and surrounds the sides of the capping layer CPL. The fluorine-doped layer FDL contains a fluoropolymer. Fluorine has a higher bonding energy with silicon than hydrogen. Therefore, higher stability and reliability from external stress can be ensured compared to hydrogen passivation. In addition, because fluorine has a smaller atomic radius and higher electronegativity than hydrogen, it may have a higher trap passivation efficiency compared to hydrogen.

[0058] A fluorine-doped layer (FDL) can be formed on top of a channel layer (CHL) by iCVD technology. Plasma treatment or ion implantation processes can be considered to passivate fluorine into the channel layer (CHL). When fluorine is passivated by a plasma treatment process, it is difficult to form a uniform plasma inside the channel pores. Furthermore, fluorine-based plasmas (e.g., SF6, CF4, C2F6) can induce surface damage to the channel layer (CHL) due to the low selectivity of polysilicon channels. In the case of ion implantation, there are regions inside the channel pores that ions cannot reach due to the shadow effect, and ion bombardment during the fluorine ion implantation process can induce surface damage to the channel layer (CHL).

[0059] The iCVD process is an all-dry process with advantages such as the absence of surface tension during the formation of the fluorine-doped layer (FDL), the ability to achieve uniform deposition by isotropically diffusing monomers and radicals, and reduced cooling time due to low-temperature processing. As a result, the fluorine-doped layer (FDL) is formed uniformly across the entire inner surface of the channel layer (CHL), minimizing damage to the channel layer (CHL).

[0060] The fluorine-doped layer (FDL) can be formed by injecting a monomer containing an initiator and fluorine, heating the initiator to generate radicals, adsorbing the monomer and radicals onto the surface of the channel layer (CHL), and then polymerizing them. Thus, the fluorine-doped layer (FDL) may contain a fluoropolymer, exemplified by pPFDA (poly-perfluorodecanoic acid). After the fluorine-doped layer (FDL) is formed, fluorine can be diffused from the fluorine-doped layer (FDL) to the channel layer (CHL) by heat treatment.

[0061] The capping layer (CPL) is positioned on the inner surface of the fluorine-doped layer (FDL). The capping layer (CPL) can fill the interior of the fluorine-doped layer (FDL). The capping layer (CPL) may be configured to block the movement of fluorine in the opposite direction to the channel layer (CHL) during the diffusion of fluorine into the channel layer (CHL). To this end, the capping layer (CPL) may contain an insulating material that blocks the movement of fluorine, and may include aluminum oxide (Al2O3) as an example. The capping layer (CPL) may have a higher band gap energy than the channel layer (CHL). For example, the capping layer (CPL) may be formed by atomic layer deposition (ALD).

[0062] Figure 4 is a cross-sectional view illustrating the process of fluorine diffusion in the filler of Figure 3. Referring to Figure 4, the filler CS includes a memory layer CML, a channel layer CHL, and a doping control layer DCL. The memory layer CML includes a layer TNL, a charge trapping layer CTL, and a blocking layer BLL. The doping control layer DCL includes a fluorine doping layer FDL and a capping layer CPL.

[0063] A fluorine-doped layer (FDL) containing a fluoropolymer can have fluorine diffused into the channel layer (CHL) through a heat treatment process. For example, fluorine can be diffused deep into the channel layer (CHL) through a drive-in process. Fluorine diffuses into the polysilicon of the channel layer (CHL) along the grain boundaries. Fluorine can compensate for defects in the channel layer (CHL) by passivating trapping regions at the grain boundaries. Fluorine can also diffuse to the outer surface of the channel layer (CHL) in contact with the tunnel layer (TNL). This can improve the electrical properties of the channel layer (CHL).

[0064] The capping layer (CPL) can prevent fluorine outgassing from the fluorine-doped layer (FDL) in the opposite direction to the channel layer (CHL). The capping layer (CPL) contains an insulating material that blocks fluorine movement. Fluorine may not diffuse from the fluorine-doped layer (FDL) to the capping layer (CPL). As a result, the fluorine doping concentration in the channel layer (CHL) is higher than the fluorine doping concentration in the capping layer (CPL).

[0065] Figure 5 is an illustrative diagram of the filler in Figure 1. Referring to Figure 5, the filler CS_2 includes the memory layer CML, the channel layer CHL, and the filler layer FLL. The memory layer CML includes the tunnel layer TNL, the charge trapping layer CTL, and the blocking layer BLL. For ease of explanation, Figure 5 will be explained in comparison to Figure 3.

[0066] The filler layer FLL can fill the interior of the channel layer CHL. The filler layer FLL can be placed on the inner surface of the channel layer CHL instead of the doping control layer DCL in Figure 3. The doping control layer DCL can be removed after the fluorine diffusion process described in Figures 3 and 4. The filler layer FLL can then be filled in the space where the doping control layer DCL was removed. The filler layer FLL contains an insulating material for purposes such as preventing leakage current, and may contain silicon oxide as an example.

[0067] Figure 6 is an exemplary sequence diagram of the manufacturing method for the three-dimensional memory device of Figure 1. Figures 7a to 7e are cross-sectional views showing the manufacturing steps of the three-dimensional memory device of Figure 1. Each step of the manufacturing method described in Figure 6 is understood to be exemplary. In particular, steps other than steps S400, S500, and S600, in which a doping control layer DCL is formed in the channel layer CHL and fluorine is diffused, can be carried out in various ways, with changes in order, additions, and deletions. Each step in Figure 6 is described with reference to the cross-sectional views in Figures 7a to 7e.

[0068] Referring to Figure 7a, in step S100, a laminated structure STS is formed on the substrate SUB. Here, the laminated structure STS may mean a structure in which a gate electrode layer GE and an insulating layer IL are repeatedly stacked in the third direction DR3, as explained in Figure 1. However, it is not limited to this, and the laminated structure STS may be a structure in which a sacrificial layer is stacked instead of the gate electrode layer GE or the insulating layer IL. The sacrificial layer is later removed, and the gate electrode layer GE or insulating layer IL may be formed in the position where the sacrificial layer was removed. As an example, the laminated structure STS may be a structure in which an insulating layer IL, which is an oxide, and a sacrificial layer, which is a nitride, are stacked.

[0069] In step S200, a channel hole HL is formed that penetrates the laminated structure STS. The channel hole HL extends deep and narrow in a third direction DR3. The channel hole HL can be etched for a high aspect ratio structure. For example, it can be formed by a special etching method such as DRIE (Deep Reactive Ion Etching), but is not limited to this.

[0070] In step S300, a memory layer CML is formed. The memory layer CML may be formed in a channel pore HL. The memory layer CML may be formed on the inner surface of the stacked structure STS. As described above, the memory layer CML includes a blocking layer BLL, a charge trapping layer CTL, and a tunnel layer TNL. However, it is not limited to these, and any layer that can trap charge and store data may be called a memory layer CML even if it differs from the aforementioned layers. The blocking layer BLL, the charge trapping layer CTL, and the tunnel layer TNL may be formed sequentially. The blocking layer BLL may be formed on the inner surface of the stacked structure STS, the charge trapping layer CTL on the inner surface of the blocking layer BLL, and the tunnel layer TNL on the inner surface of the charge trapping layer CTL. Exemplarily, the memory layer CML may be formed by atomic layer deposition.

[0071] The memory layer CML is not limited to the structure shown in Figure 7a. For example, the memory layer CML can be separated by the number of memory cell transistors (MCTs). Also, the memory layer CML may not be formed inside the channel hole HL but under the stacked structure STS. The memory layer CML may be formed away from the inner surface of the stacked structure STS by the channel hole HL. For example, the insulating layer of the stacked structure STS may be used to form the tunnel layer TNL of the memory layer CML. In this case, the memory layer CML may be generated by further forming a charge trapping layer CTL and a blocking layer BLL on the tunnel layer TNL, or the channel layer CHL may be formed directly on the inner surface of the channel hole HL or the stacked structure STS. Therefore, step S300 may be performed after step S400 in which the channel layer CHL is formed.

[0072] Referring to Figure 7b, in step S400, a channel layer CHL is formed on the channel layer HL. The channel layer CHL is formed on the inner surface of the memory layer CML. The channel layer CHL can cover the entire side surface of the channel pore HL. For example, amorphous silicon can be deposited on the channel pore HL at low temperature and crystallized into polysilicon via SPC (Solid Phase Crystallization) to form the channel layer CHL. For example, a conductive layer CDL can be further formed on top of the channel layer CHL. The conductive layer CDL may be part of the contact pattern DR included in the upper conductive pattern in Figure 1.

[0073] Referring to Figure 7c, in step S500, a doping control layer DCL is formed on the inner surface of the channel layer CHL. The doping control layer DCL includes a fluorine doping layer FDL and a capping layer CPL. The fluorine doping layer FDL is formed on the inner surface of the channel layer CHL. The fluorine doping layer FDL can be formed uniformly to cover the entire side surface of the channel layer CHL by the iCVD method. The fluorine doping layer FDL contains a fluoropolymer. The fluorine doping layer FDL is extended along the channel layer CHL in a third direction DR3 and may be further extended to cover at least a portion of the laminated structure STS and the conductive layer CDL on a plane perpendicular to the third direction DR3.

[0074] The capping layer (CPL) is formed on the inner surface of the fluorine-doped layer (FDL). The capping layer (CPL) may be formed to fill the interior of the channel pores (HL). The capping layer (CPL) may be extended along the fluorine-doped layer (FDL) in a third direction (DR3) and may be further extended to cover at least a portion of the fluorine-doped layer (FDL) in a plane perpendicular to the third direction (DR3). Exemplarily, the capping layer (CPL) may be formed by atomic layer deposition.

[0075] Referring to Figure 7d, in step S600, fluorine can be diffused from the fluorine-doped layer FDL into the channel layer CHL. The drive-in process can cause the fluorine to diffuse deep into the channel layer CHL. Heat treatment can cause the fluorine to diffuse to the outer surface of the channel layer CHL in contact with the tunnel layer TNL. In addition, vias can be formed in the conductive layer CDL. Contact patterns electrically connected to bit lines BL0-BL2 can be further formed in the vias.

[0076] Referring to Figure 7e, the fluorine-doped layer FDL and capping layer CPL generated in step S500 may be removed, and the filler layer FLL may be filled into the channel pore HL. As described in Figure 5, the fluorine may be diffused into the channel layer CHL before the fluorine-doped layer FDL and capping layer CPL are removed. In this case, the filler layer FLL may be formed before the vias are formed.

[0077] Figure 8 is a sequence diagram illustrating the steps for forming the doping control layer shown in Figure 6. Figure 9 is a schematic diagram illustrating the steps for forming the doping control layer shown in Figure 6. Referring to Figures 8 and 9, it can be understood that the steps of the iCVD process for forming the fluorine doping layer FDL within the doping control layer DCL are illustrated. Each step in Figure 8 is explained with reference to Figure 9.

[0078] In step S510, the initiator and monomer may be injected so as to reach the memory substrate containing the stacked structure STS. The initiator and monomer are injected in a gaseous state. Here, the initiator is understood as a molecule for generating radicals. For example, the initiator may be DTBP, but is not limited to this, and may include at least one of a variety of substances capable of generating radicals, such as TBPO (tert-butyl peroxide) or TBPOB (t-butyl peroxybenzoate). The monomer is understood as a raw material for forming a thin film. The monomer contains fluorine, and for example may be PFDA (perfluorodecanoic acid). However, is not limited to this, and may include at least one of a variety of substances containing fluorine, such as PFDMA (perfluorodecyl methacrylate), C6FA, or C4FA.

[0079] In step S520, the initiator is heated to generate radicals. The initiator may be heated by a heating filament HT. For example, the heating filament HT may be spaced apart on the stacked structure STS of the memory substrate. For instance, the heating filament HT may be arranged two-dimensionally on a plane perpendicular to the height direction (third direction DR3) so that the entire plane of the memory substrate can be heated. The initiator is thermally decomposed into radicals by the heating filament HT.

[0080] In step S530, monomers and radicals are adsorbed onto the surface of the memory substrate. More specifically, monomers and radicals may be adsorbed onto the surface of the channel layer CHL formed in the channel pore HL.

[0081] In step S540, a polymer polymerization reaction occurs due to radicals. The adsorbed radicals initiate the polymerization of monomers. This forms polymer chains, which grow as a thin film on the surface of memory MEMb, specifically on the surface of the channel layer CHL. In other words, monomers containing fluorine are polymerized to form a fluoropolymer. As an example, the fluoropolymer may be pPFDA. However, it is not limited to this, and the fluoropolymer may be the result of a polymer polymerization reaction of at least one of the monomers mentioned in step S510, such as pPFDA, pPFDMA, pC6FA, or pC4FA.

[0082] When a fluorine-doped layer (FDL) is formed in steps S510 to S540, it is carried out in a dry process and, because there is no surface tension, a uniform thin film can be formed. The fluorine-doped layer (FDL) is formed by isotropically diffusing monomers and radicals, enabling uniform deposition. Furthermore, it is carried out at low temperatures, minimizing surface damage to the memory substrate including the channel layer (CHL), and potentially reducing the cooling time and energy required for subsequent steps.

[0083] Figures 10 to 15 are graphs illustrating the improvement in the electrical characteristics of a 3D memory device according to an embodiment of the present invention. The comparison is with a 3D memory device in which the trap region is passivated with hydrogen by forming gas annealing.

[0084] Referring to Figure 10, the transfer characteristics of the 3D memory device (I DS -V GS The graph shows the following: The horizontal axis is defined as the gate-source voltage, and the vertical axis is defined as the cell string current (drain-source current) or transconductance (drain-source voltage is 0.1V). The solid line is understood to be the cell string current, and the dotted line is understood to be the transconductance. The arrows shown indicate the graph of characteristic changes according to the present invention compared to a comparison target.

[0085] When a 3D memory device according to the present invention includes channels in which fluorine has been diffused by an iCVD process, it exhibits improved transfer characteristics compared to hydrogen passivation. Specifically, referring to the solid line, the On current is improved, and the threshold voltage has shifted negatively from approximately 3.5V to approximately 1.5V. Furthermore, the transconductance shows an improvement of approximately three times.

[0086] This improvement in electrical properties means that the fluorine doped into the channel layer (CHL) passedivated defects and trapped regions at grain boundaries. Furthermore, it indicates that fluorine, with its higher electronegativity compared to hydrogen, more effectively passedivated these trapped regions. This can be interpreted as a reduction in deep states, or unsaturated bonds, located near the intermediate gap within the polysilicon energy bandgap of the channel layer (CHL).

[0087] Referring to Figure 11, the cumulative distribution function due to threshold voltage and subthreshold swing is shown. Compared to the comparison, in the case of the present invention, the threshold voltage shifted in the negative direction from approximately 3.5V to approximately 1.5V. Furthermore, the subthreshold swing is shown to have improved by approximately 30%, from 389mV / decade to 278mV / decade. This means that fluorine is diffused to the interface between the tunnel layer (TNL) and the channel layer (CHL), effectively passing through the interface trap compared to hydrogen passivation.

[0088] Referring to Figure 12, the output characteristics of the 3D memory device (I DS -V DS The graph shows the following: The horizontal axis is defined as the drain-source voltage, and the vertical axis is defined as the cell string current (drain-source current). The output characteristics are directly correlated with field-effect mobility, which is used to determine the resolvability of the degradation of the polysilicon channel's mobility. The gate voltage (V) reflects the threshold voltage. GS -VTH A comparison of the drain-source current saturated with respect to ) shows that the present invention achieves a 300% improvement compared with the comparative example.

[0089] Referring to FIG. 13, the field effect mobility of a three-dimensional memory device is shown (drain-source voltage is 0.1 V). The field effect mobility can be extracted from the mutual conductance mentioned in FIG. 10. The field effect mobility of the comparative example is 8.4 cm 2 / V*sec, and the field effect mobility of the present invention is 25.1 cm 2 / V*sec. It is thereby shown that the field effect mobility is improved by about three times compared with the comparative example. The results of FIG. 12 and FIG. 13 indicate that the fluorine doping technique using the iCVD method improves channel mobility.

[0090] Referring to FIG. 14, positive bias stress (PBS) is shown. The horizontal axis is defined as gate-source voltage, and the vertical axis is defined as cell string current (drain-source current) (drain-source voltage is 0.1 V). In consideration of the scheme of a V-NAND flash memory to which a relatively higher electric field is applied compared with other memory elements, there is shown a PBS test for observing a change in transfer characteristics while applying a constant electric field to the gate. Referring to the comparative example, as stress time increases under the condition that an electric field of 3 MV / cm is applied to the gate, subthreshold swing characteristics are degraded. On the contrary, in the case of the present invention, after 10 4 seconds of stress time, the subthreshold swing characteristics are still maintained.

[0091] Referring to FIG. 15, the subthreshold swing versus stress time is shown. Under the condition that an electric field of 1 MV / cm and 3 MV / cm is applied to the gate, the comparative example has a section in which the swing greatly increases as the stress time increases. On the contrary, in the present invention, even if the stress time increases, the subthreshold swing characteristics are maintained constant.

[0092] The results shown in Figures 14 and 15 demonstrate that diffusion by fluorine doping provides superior stability to PBS compared to hydrogen passivation. This result can be interpreted as fluorine having a stronger binding energy than hydrogen, thus suppressing passivation depassivation by an external electric field. Thus, the present invention can ensure stability in PBS.

[0093] Figures 16 to 21 are graphs illustrating the improvement in memory characteristics of a 3D memory device according to an embodiment of the present invention. The comparison is with a 3D memory device in which the trap region is passivated with hydrogen by forming gas annealing.

[0094] Referring to Figure 16, the program / erase speed characteristics are shown. The horizontal axis is defined as program / erase time, and the vertical axis is defined as threshold voltage. The empty patterns indicate the threshold voltage due to program time, and the packed patterns indicate the threshold voltage due to erase time. 20V is applied to the gate when the program is running, and -25V is applied to the gate during the erase operation. Compared to the comparison target, the present invention has a faster program speed at a specific threshold voltage.

[0095] Referring to Figure 17, the program time required for a threshold voltage of 3V is shown to be approximately 30 times shorter for the present invention compared to the comparison. The program time required for a threshold voltage of 5V is shown to be approximately 15 times shorter for the present invention compared to the comparison. The results in Figures 16 and 17 demonstrate an improvement in memory operating speed.

[0096] Referring to Figure 18, the characteristics of ISPP (Incremental Step Programming Pulse) are shown. The horizontal axis is defined as the program voltage, and the vertical axis is defined as the threshold voltage. The program time is specified as 100 μs. When comparing the gradient of the present invention with that of the comparison target, it is shown that the ISPP characteristics of the present invention, which are close to 1, are improved.

[0097] Referring to Figure 19, the identification of the ISPP gradient is shown. The average value of the ISPP gradient extracted from around the operating voltage is shown. Comparing the average value of the gradient of the present invention with that of the comparison target, when fluorine doping is applied, it is 0.9V / V, which is close to the theoretical upper limit of 1V / V, and higher than the comparison target which has 0.75V / V. Furthermore, it is shown that the voltage at which the gradient begins is lower for the present invention compared to that of the comparison target. The results in Figures 18 and 19 show an improvement in the ISPP characteristics, and together with the improvement in the PBS characteristics mentioned above, the stability and reliability of the 3D memory device can be ensured.

[0098] Referring to Figure 20, the endurance characteristics are shown. As the program / erase cycle increases, the present invention has a constant threshold voltage, while the comparison object has a range where the threshold voltage increases. The deterioration of endurance characteristics is due to the escape of electrons from the charge trapping layer (CTL) during the erase operation and the deterioration of the interface by electrons during pore injection. Therefore, it is shown that fluorine, which has a stronger bonding energy with silicon than hydrogen, has strong endurance characteristics.

[0099] Referring to Figure 21, the retention characteristics are shown. It is shown that, as the data retention time increases, neither the present invention nor the comparative study shows a significant deterioration in data. In other words, it indicates that the adverse effects of fluorine are not as apparent as those of hydrogen.

[0100] As described with reference to the examples, a person skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and scope of the invention as described in the claims below. Furthermore, the disclosed examples of the present invention are not intended to limit the technical spirit of the invention, and all technical spirit within the claims below and equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]

[0101] MEM: 3D memory device SUB: substrate IL: Insulating layer GE: Grid gate layer CS: Filler CML: Memory Layer BLL: Blocking layer CTL: Charge trapping layer TNL: Tunnel layer CHL: Channel layer DCL: Doping Control Layer FDL: Fluorine Doping Layer CPL: Capping layer FLL: Filler layer

Claims

1. circuit board and A capping layer extending in the height direction away from the substrate on the substrate, A fluorine-doping layer containing a fluoropolymer surrounds the side surface of the capping layer, extends in the height direction, and comprises: A channel layer containing polysilicon in which fluorine is diffused surrounds the side surface of the fluorine-doped layer, extends in the height direction, and surrounds the side surface of the fluorine-doped layer. A memory layer surrounding the side of the channel layer, A three-dimensional memory device including a gate electrode layer surrounding the side surface of the memory layer.

2. The fluoropolymers are PFDA (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-Heptadecafluorodecyl acrylate), PFDMA (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-Heptadecafluorodecyl methacrylate), C6FA (3,3,4,4,5,5,6,6,7,7,8,8,8-Tridecafluorooctyl acrylate), and C4FA (3,3,4,4,5,5,6,6,6-Nonafluorohexyl A three-dimensional memory device according to claim 1, comprising at least one polymer from among acrylate.

3. The fluorine-doping layer is in contact with the inner surface of the channel layer and covers the entire inner surface of the channel layer, as described in claim 1.

4. The three-dimensional memory device according to claim 1, wherein the capping layer comprises aluminum oxide.

5. The three-dimensional memory device according to claim 1, wherein the doping concentration of fluorine in the channel layer is higher than the doping concentration of fluorine in the capping layer.

6. The three-dimensional memory device according to claim 1, wherein the outer surface of the channel layer is in contact with the memory layer and contains diffused fluorine.

7. The aforementioned memory layer is A tunnel layer adjacent to the channel layer and surrounding the side surface of the channel layer, A charge trapping layer surrounding the side surface of the tunnel layer, The three-dimensional memory device according to claim 1, further comprising a blocking layer surrounding the side surface of the charge trapping layer.

8. The three-dimensional memory device according to claim 1, wherein the fluorine-doping layer faces the gate electrode layer with the channel layer in between.

9. The steps include forming a laminated structure on a substrate, The steps include forming channel holes that penetrate the stacked structure in the height direction, The steps include forming a memory layer on the inner surface of the stacked structure defined by the channel holes, The steps include forming a channel layer on the inner surface of the memory layer, The steps include forming a fluorine-doped layer containing a fluorine polymer on the inner surface of the channel layer, The steps include forming a capping layer on the inner surface of the fluorine-doped layer, A method for manufacturing a three-dimensional memory device, comprising the step of diffusing fluorine from the fluorine-doped layer to the channel layer by heat treatment.

10. The step of forming the fluorine-doped layer is, A step of injecting a monomer containing an initiator and fluorine in a gaseous state so that it reaches the layered structure, The steps include heating the initiator to generate radicals, The steps include adsorbing the monomer and the radical onto the surface of the channel layer, A method for manufacturing a three-dimensional memory device according to claim 9, comprising the step of forming a thin film containing the fluoropolymer based on the polymer polymerization reaction by the radical.

11. The method for manufacturing a three-dimensional memory device according to claim 10, wherein the monomer comprises at least one of PFDA, PFDMA, C6FA, and C4FA, and the fluoropolymer comprises at least one of pPFDA (poly-PFDA), pPFDMA (poly-PFDMA), pC6FA (poly-C6FA), and pC4FA (poly-C4FA).

12. The method for manufacturing a three-dimensional memory device according to claim 10, wherein the initiator is DTBP (di-tert-butyl peroxide).

13. The step of generating the radical is: A method for manufacturing a three-dimensional memory device according to claim 10, comprising the step of decomposing the initiator into radicals by heating filaments arranged spaced apart on the laminated structure.

14. A method for manufacturing a three-dimensional memory device according to claim 10, wherein the temperature of the substrate due to heating in the step of generating the radicals is lower than the temperature of the substrate due to the heat treatment in the step of diffusing the fluorine.

15. A method for manufacturing a three-dimensional memory device according to claim 9, further comprising the step of removing the fluorine doping layer and the capping layer after the step of diffusing the fluorine.

16. A method for manufacturing a three-dimensional memory device according to claim 15, further comprising the step of filling the positions where the fluorine-doping layer and the capping layer have been removed with a filler.

17. The method for manufacturing a three-dimensional memory device according to claim 9, wherein the capping layer comprises aluminum oxide.

18. The method for manufacturing a three-dimensional memory device according to claim 9, wherein, in the step of diffusing fluorine, the diffusion of fluorine away from the channel layer is suppressed by the capping layer.

19. The method for manufacturing a three-dimensional memory device according to claim 9, wherein in the step of diffusing fluorine, the fluorine is diffused to the outer surface of the channel layer.

20. The step of forming the memory layer is: The steps include forming a blocking layer on the inner surface of the laminated structure, The steps include forming a charge trapping layer on the inner surface of the blocking layer, A method for manufacturing a three-dimensional memory device according to claim 9, comprising the step of forming a tunnel layer on the inner surface of the charge trapping layer.

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