Display devices and display panels

Abstract

The present invention provides a display device and a display panel that can prevent moisture from entering the link region that transmits drive signals to the display panel via the drive circuit. [Solution] The display device according to the embodiment of the present disclosure includes a display panel including a display area on which a plurality of subpixels are formed and a non-display area divided into a plurality of inorganic layer areas according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer on the outer edge of the display area, a data driving circuit coupled to a pad area of ​​the display panel, and a timing controller for controlling the data driving circuit, wherein in a link area adjacent to the pad area, the distance between the end of a driving voltage line that transmits a driving voltage to a plurality of subpixels and the end of the first inorganic sealing layer is configured to be greater than the distance between the end of the first inorganic sealing layer and the outermost primary dam.

Description

[[Technical Field]]

[0001] The present disclosure relates to a display device and a display panel, and more specifically, to a display device and a display panel capable of preventing defects caused by moisture permeation. [[Background Art]]

[0002] Typical examples of display devices that display images using digital data include liquid crystal displays (LCDs) using liquid crystals, and organic light emitting display devices using organic light emitting diodes (OLEDs, hereinafter referred to as OLEDs).

[0003] Among display devices, organic light emitting display devices use light emitting diodes that emit light on their own, resulting in fast response speed and advantages in terms of contrast ratio, luminous efficiency, luminance, viewing angle, and the like. In this case, the light emitting diode may be formed of an inorganic material or an organic material.

[0004] An organic light emitting display device includes an organic light emitting diode disposed in each of a plurality of subpixels arranged on a display panel, and controls the luminance represented by each subpixel to display an image by causing the organic light emitting diodes to emit light through controlling the voltage applied to the organic light emitting diodes. [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] Many display devices, including such organic light emitting display devices, may have degraded performance such as reliability when moisture penetrates into the interior thereof, so they need to be designed to block the penetration or propagation of moisture into the interior through various methods.

[0006] In particular, if moisture penetrates the link area that transmits drive signals to the display panel, it can cause malfunctions in the drive signal line, making it difficult for the display device to operate normally.

[0007] This disclosure provides a display device and a display panel that can prevent moisture from flowing into the link region that transmits drive signals to the display panel via the drive circuit.

[0008] This disclosure provides a display device and a display panel that can prevent water inflow due to seam defects by positioning the edge portion of the drive signal line formed in the link region inside the dam.

[0009] The problems of the embodiments of this disclosure are not limited to those mentioned herein, and other problems not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] A display device according to an embodiment of the present disclosure includes a display panel including a display area on which a plurality of subpixels are formed and a non-display area divided into a plurality of inorganic layer areas on the outer edge of the display area according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer; a data driving circuit coupled to a pad area of ​​the display panel; and a timing controller for controlling the data driving circuit, wherein in a link area adjacent to the pad area, the distance between the end of a driving voltage line that transmits a driving voltage to the plurality of subpixels and the end of the first inorganic sealing layer is greater than the distance between the end of the first inorganic sealing layer and an inner primary dam.

[0011] A display panel according to an embodiment of the present disclosure includes a display area on which a plurality of subpixels are formed, a non-display area divided into a plurality of inorganic layer areas on the outer edge of the display area according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer, a pad area on which a data driving circuit is coupled, and a link area on which a driving voltage line that transmits a driving voltage to the plurality of subpixels extends through the pad area, wherein the distance between the end of the driving voltage line and the end of the first inorganic sealing layer is greater than the distance between the end of the first inorganic sealing layer and the inner primary dam. [Effects of the Invention]

[0012] According to this disclosure, it is possible to provide a display device and a display panel that can prevent moisture from flowing into the link region that transmits drive signals to the display panel via the drive circuit.

[0013] According to this disclosure, a display device and a display panel can be provided that prevent water inflow due to seam defects by positioning the edge portion of the drive signal line formed in the link region inside the dam.

[0014] According to embodiments of this disclosure, process optimization can be achieved by preventing moisture from flowing into the drive signal lines of the link region, and a lightweight display device and display panel having a narrow bezel can be provided.

[0015] The effects of the embodiments of this disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the claims. [Brief explanation of the drawing]

[0016] [Figure 1] This figure schematically shows a display device according to an embodiment of the present disclosure. [Figure 2]This figure illustrates a subpixel circuit of a display device according to an embodiment of the present disclosure. [Figure 3] This figure illustrates a cross-section of a display panel according to an embodiment of the present disclosure. [Figure 4] This figure illustrates a plan view of a display device according to an embodiment of the present disclosure. [Figure 5] This figure illustrates a plan view of a display panel in which a first inorganic sealing layer and a second inorganic sealing layer are formed, according to an embodiment of the present disclosure. [Figure 6] This figure illustrates a cross-section of the first inorganic layer region in a display device according to an embodiment of the present disclosure. [Figure 7] This is an enlarged plan view of a second inorganic layer region in a display device according to an embodiment of the present disclosure, in which the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer gradually approach each other. [Figure 8] This figure illustrates a cross-section obtained by cutting the CD section of the second inorganic layer region in a display device according to an embodiment of the present disclosure. [Figure 9] This is an enlarged plan view of a third inorganic layer region in a display device according to an embodiment of the present disclosure, in which the position of the end of the first inorganic encapsulation layer and the position of the end of the second inorganic encapsulation layer are the same. [Figure 10] This figure illustrates a cross-section obtained by cutting the EF section of the third inorganic layer region in a display device according to an embodiment of the present disclosure. [Figure 11] This figure illustrates a plan view of a display device according to an embodiment of the present disclosure, in which the position of the point where the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer touch is moved to the outside of the link region. [Modes for carrying out the invention]

[0017] The content of the present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings. The detailed description and the accompanying drawings are provided solely for illustrative purposes and are not intended to limit the content of the present disclosure.

[0018] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to components in each drawing, the same components may be assigned the same reference numerals as much as possible even if they appear on other drawings. In describing the present disclosure, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "comprising", "having", and "consisting of" are used herein, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include the plural unless explicitly stated otherwise.

[0019] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are only for distinguishing the components from other components, and do not limit the essence, order, sequence or number of the components by virtue of such terms.

[0020] In the description of the positional relationship of components, when it is stated that two or more components are "coupled", "combined" or "connected", the two or more components may be directly "coupled", "combined" or "connected", but it should be understood that another component may further "intervene" between the two or more components, and the two or more components and the other component may also be "coupled", "combined" or "connected" accordingly. Here, the other component may be included in at least one of the two or more components that are mutually "coupled", "combined" or "connected".

[0021] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0022] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0023] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0024] Figure 1 is a schematic diagram showing a display device according to an embodiment of the present disclosure.

[0025] Referring to Figure 1, the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a drive circuit for driving the display panel 110.

[0026] The display panel 110 may include a display area DA where images are displayed and a non-display area NDA where images are not displayed. The non-display area NDA is also called the bezel area.

[0027] The display panel 110 may include multiple subpixels SP for displaying images. For example, multiple subpixels SP may be located in the display area DA. In some cases, at least one subpixel SP may be located in the non-display area NDA. The at least one subpixel SP located in the non-display area NDA is also called a dummy subpixel.

[0028] The display panel 110 may include multiple signal lines for driving multiple subpixels SP. For example, the multiple signal lines may include multiple data lines DL and multiple gate lines GL. Depending on the structure of the subpixels SP, the signal lines may further include signal lines different from the multiple data lines DL and multiple gate lines GL. For example, the other signal lines may include drive voltage lines and reference voltage lines.

[0029] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL may be arranged extending in a first direction. Each of the multiple gate lines GL may be arranged extending in a second direction, where the first direction is the column direction and the second direction is the row direction. In this specification, the column direction and the row direction are relative. For example, the column direction may be the vertical direction and the row direction may be the horizontal direction. In another example, the column direction may be the horizontal direction and the row direction may be the vertical direction.

[0030] The drive circuit may include a data drive circuit 130 for driving multiple data lines DL and a gate drive circuit 120 for driving multiple gate lines GL. The drive circuit may further include a timing controller 140 for controlling the data drive circuit 130 and the gate drive circuit 120.

[0031] The data drive circuit 130 is a circuit for driving multiple data lines DL and can output data signals (also called data voltages) corresponding to video signals to multiple data lines DL. The gate drive circuit 120 is a circuit for driving multiple gate lines GL and can generate gate signals and output gate signals to multiple gate lines GL. The gate signals may include one or more scan signals and light emission signals.

[0032] The timing controller 140 can start scanning according to the timing realized in each frame and control the data drive at the appropriate time in accordance with the scan. The timing controller 140 can switch the input video data received from an external source to match the data signal format used by the data drive circuit 130 and supply the switched video data DATA to the data drive circuit 130.

[0033] The timing controller 140 can receive display drive control signals from an external host system 200 along with input video data. For example, the display drive control signals may include vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, and the like.

[0034] The timing controller 140 can generate a data drive control signal DCS and a gate drive control signal GCS based on a display drive control signal input from the host system 200. The timing controller 140 can control the drive operation and drive timing of the data drive circuit 130 by supplying the data drive control signal DCS to the data drive circuit 130. The timing controller 140 can control the drive operation and drive timing of the gate drive circuit 120 by supplying the gate drive control signal GCS to the gate drive circuit 120.

[0035] The data driving circuit 130 may include one or more source driving integrated circuits (SDICs). Each source driving integrated circuit may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. Each source driving integrated circuit may optionally further include an analog-to-digital converter (ADC).

[0036] For example, each source-driven integrated circuit can be connected to the display panel 110 using a Tape Automated Bonding (TAB) method, connected to the bonding pads of the display panel 110 using a Chip On Glass (COG) or Chip On Panel (COP) method, or connected to the display panel 110 using a Chip On Film (COF) method.

[0037] The gate drive circuit 120 can output a gate signal at the turn-on level voltage or a gate signal at the turn-off level voltage, depending on the control of the timing controller 140. The gate drive circuit 120 can sequentially drive multiple gate lines GL by sequentially supplying gate signals at the turn-on level voltage to multiple gate lines GL.

[0038] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs).

[0039] The gate drive circuit 120 can be connected to the display panel 110 by tape automated bonding (TAB), or to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) method, or to the display panel 110 by chip-on-film (COF) method. Alternatively, the gate drive circuit 120 may be of the gate-in-panel (GIP) type and formed in the non-display area (NDA) of the display panel 110. The gate drive circuit 120 may be placed on the substrate or connected to the substrate. That is, if the gate drive circuit 120 is of the gate-in-panel (GIP) type, it can be placed in the non-display area (NDA) of the substrate. If the gate drive circuit 120 is of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., it can be connected to the substrate.

[0040] On the other hand, at least one of the data drive circuit 130 and the gate drive circuit 120 may be placed in the display area DA. For example, at least one of the data drive circuit 130 and the gate drive circuit 120 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or completely overlap with the subpixel SP.

[0041] The data drive circuit 130 may be connected to one side of the display panel 110 (for example, the top or bottom). Depending on the drive method, panel design method, etc., the data drive circuit 130 may be connected to both sides of the display panel 110 (for example, the top and bottom), or to two or more of the four sides of the display panel 110.

[0042] The gate drive circuit 120 may be connected to one side of the display panel 110 (for example, the left or right side). Depending on the drive method, panel design method, etc., the gate drive circuit 120 may be connected to both sides of the display panel 110 (for example, the left and right sides), or to two or more of the four sides of the display panel 110.

[0043] The timing controller 140 may be implemented as a separate component from the data drive circuit 130, or it may be integrated with the data drive circuit 130 and implemented as an integrated circuit. The timing controller 140 may be a controller used in ordinary display technology, a control device that includes the timing controller 140 and can further perform other control functions, or a circuit within the control device. The timing controller 140 can be implemented as various circuits and electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0044] The timing controller 140 is mounted on a printed circuit board, flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 130 and the gate drive circuit 120 via the printed circuit board, flexible printed circuit board, etc. The timing controller 140 can send and receive signals with the data drive circuit 130 according to one or more predetermined interfaces. Here, for example, the interface can include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Point-to-point Interface), an SPI (Serial Peripheral Interface), etc.

[0045] The display device 100 according to the embodiments of this disclosure may be a self-emissive display device in which the display panel 110 emits light on its own. When the display device 100 according to the embodiments of this disclosure is a self-emissive display device, each of the plurality of subpixels SP may include a light-emitting element. For example, the display device 100 according to the embodiments of this disclosure may be an organic light-emitting display device in which the light-emitting elements are realized by organic light-emitting diodes (OLEDs). As another example, the display device 100 according to the embodiments of this disclosure may be an inorganic light-emitting display device in which the light-emitting elements are realized by inorganic-based light-emitting diodes. As yet another example, the display device 100 according to the embodiments of this disclosure may be a quantum dot display device in which the light-emitting elements are realized by quantum dots, which are semiconductor crystals that emit light on their own.

[0046] In this case, each subpixel SP arranged on the display panel 110 within the display device 100 can be composed of a light-emitting element and circuit elements such as a drive transistor for driving it.

[0047] The types and number of circuit elements that make up each subpixel SP can be determined in various ways depending on the function provided and the design method.

[0048] Figure 2 is a diagram illustrating an exemplary subpixel circuit of a display device according to an embodiment of the present disclosure.

[0049] Referring to Figure 2, the subpixel circuit of the display device 100 according to an embodiment of the present disclosure may include a light-emitting element ED, a drive transistor DRT for driving the light-emitting element ED, a plurality of switching transistors T1 to T7, and a plurality of capacitors Cst, CA.

[0050] The subpixel circuit may operate in the following sequence: initialization period, sensing period, data writing period, anode reset period, and emission period.

[0051] The subpixel circuit can be connected to a data line DL to which the data voltage Vdata is applied, and to gate lines to which gate signals EM1, EM2, SC1, SC2, and SC3 are applied.

[0052] Furthermore, the subpixel circuit may be connected to a pixel high-voltage line to which a pixel high-voltage EVDD is applied, a pixel low-voltage line to which a pixel low-voltage EVSS is applied, a reset voltage line to which a reset voltage VAR is applied, and a reference voltage line to which a reference voltage Vref is applied.

[0053] All subpixels SP arranged on the display panel 110 can be connected to a common constant voltage line. In this case, the levels of the constant voltages EVDD, EVSS, VAR, and Vref applied to the subpixel circuit can be set considering the voltage margin in the saturation region of the drive transistor DRT. For example, the levels of the constant voltages EVDD, EVSS, VAR, and Vref can be set under the condition EVDD > Vref > VAR > EVSS.

[0054] The gate signals EM1, EM2, SC1, SC2, and SC3 include pulses that swing between a turn-on level gate high voltage and a turn-off level gate low voltage. The gate high voltage may be set to a voltage level higher than the pixel high potential voltage EVDD, and the gate low voltage may be set to a voltage level lower than the pixel low potential voltage EVSS.

[0055] The gate signals EM1, EM2, SC1, SC2, and SC3 include a first light emission signal EM1, a second light emission signal EM2, a first scan signal SC1, a second scan signal SC2, and a third scan signal SC3. The first light emission signal EM1 may be interpreted as the first gate signal, the second light emission signal EM2 as the second gate signal, the first scan signal SC1 as the third gate signal, the second scan signal SC2 as the fourth gate signal, and the third scan signal SC3 as the fifth gate signal.

[0056] The drive transistor DRT generates a current in response to the gate-source voltage and drives the light-emitting element ED. The drive transistor DRT includes a first electrode connected to a first node N1, a gate electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0057] The light-emitting element (ED) can be realized using an organic light-emitting diode (OLED). The light-emitting element (ED) includes an anode electrode, a cathode electrode, and an organic compound layer formed between these electrodes. The anode electrode of the light-emitting element (ED) may be connected to a fourth node N4, and the cathode electrode may be connected to a pixel low voltage line to which a pixel low voltage EVSS is applied.

[0058] The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0059] When a voltage is applied to the anode and cathode electrodes of a light-emitting element (ED), holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the light-emitting layer (EML), forming excitons. At this time, visible light is emitted from the light-emitting layer (EML). The light-emitting element (ED) can be realized as a tandem structure in which multiple light-emitting layers are stacked. A tandem structured light-emitting element (ED) can improve the brightness and lifetime of subpixels.

[0060] The first capacitor Cst is connected between the first node N1 and the second node N2. After being initialized during the initialization period, the first capacitor Cst stores the threshold voltage of the drive transistor DRT during the sensing period. During the data writing period, the first capacitor Cst stores a data voltage Vdata compensated only by the threshold voltage of the drive transistor DRT, and can then maintain the gate-source voltage of the drive transistor DRT during the anode reset period and the light emission period.

[0061] A second capacitor CA is connected between the first node N1 and the seventh switching transistor T7. When the seventh switching transistor T7 is turned on, the second capacitor CA is charged to a reference voltage Vref and maintains the first node N1 at the reference voltage Vref.

[0062] The first switching transistor T1 is connected between the pixel high potential voltage line to which the pixel high potential voltage EVDD is applied and the third node N3 of the drive transistor DRT, and is turned on in response to the first light emission signal EM1. When the first switching transistor T1 is turned on, the pixel high potential voltage EVDD is applied to the third node N3. The first switching transistor T1 is formed as a P-type transistor and turns on when the voltage of the first light emission signal EM1 is the gate low voltage.

[0063] The second switching transistor T2 is connected between the first node N1 and the fourth node N4 and is turned on in response to the second light emission signal EM2. When the second switching transistor T2 is turned on, the first node N1 is connected to the fourth node N4. The second switching transistor T2 is formed as an N-type transistor and turns on when the second light emission signal EM2 is at a gate high voltage.

[0064] A third switching transistor T3 is connected between the data line to which the data voltage Vdata is applied and the second node N2, and is turned on in response to the first scan signal SC1. When the third switching transistor T3 is turned on, the data voltage Vdata is applied to the second node N2 of the drive transistor DRT. The third switching transistor T3 is formed as an N-type transistor and turns on when the first scan signal SC1 is at a gate high voltage.

[0065] The fourth switching transistor T4 is connected between a reference voltage line to which a reference voltage Vref is applied and the second node N2 of the drive transistor DRT, and is turned on in response to the second scan signal SC2. When the fourth switching transistor T4 is turned on, the reference voltage Vref is applied to the second node N2. The fourth switching transistor T4 is formed as an N-type transistor and turns on when the voltage of the second scan signal SC2 is the gate high voltage.

[0066] The fifth switching transistor T5 is connected between the reset voltage line to which the reset voltage VAR is applied and the fourth node N4, and is turned on in response to the first light emission signal EM1. When the fifth switching transistor T5 is turned on, the reset voltage VAR is applied to the fourth node N4. The fifth switching transistor T5 is formed as an N-type transistor and turns on when the voltage of the first light emission signal EM1 is the gate high voltage.

[0067] The sixth switching transistor T6 is connected between a reference voltage line to which a reference voltage Vref is applied and the second capacitor CA, and is turned on in response to the third scan signal SC3. When the sixth switching transistor T6 is turned on, the reference voltage Vref charges the second capacitor CA. The sixth switching transistor T6 is formed as an N-type transistor and turns on when the voltage of the third scan signal SC3 is the gate high voltage.

[0068] Such a subpixel circuit may operate in the following sequence: initialization period, sensing period, data writing period, anode reset period, and emission period.

[0069] As described above, in the subpixel circuit according to the embodiment of the present disclosure, the first switching transistor T1 is a P-type transistor, and the second switching transistors T2 to the sixth switching transistor T6 and the drive transistor DRT may be N-type transistors.

[0070] When the first switching transistor T1 is a P-type transistor, the third node N3 can be fixed to the pixel high potential voltage EVDD, which has the advantage that the light-emitting current flowing through the light-emitting element ED does not fluctuate due to the storage capacitor Cst. Therefore, the light-emitting current is more easily supplied stably.

[0071] A P-type transistor can be a silicon transistor formed from a semiconductor such as silicon (for example, a transistor having a polysilicon channel formed using a low-temperature process called LTPS or low-temperature polysilicon).

[0072] On the other hand, N-type transistors can consist of oxide transistors formed using oxide semiconductors (for example, transistors having channels formed from oxide semiconductors such as indium, gallium, zinc oxide, IGZO, or IGZTO). Oxide transistors have the characteristic of having relatively lower leakage current than silicon transistors.

[0073] Therefore, the drive transistor DRT and at least some of the switching transistors T2 to T6 that constitute the subpixel circuit can be made of oxide transistors. When oxide transistors are used to realize the drive transistor DRT and switching transistors, there is an effect of reducing image quality defects such as flicker by suppressing current leakage from the drive transistor DRT.

[0074] In this case, to detect the flicker characteristics of oxide transistors DRT, T2 to T6, a test transistor can be used that can accurately detect the interface characteristics of the buffer layer via the lower gate electrode and the interface characteristics of the gate insulating film via the upper gate electrode.

[0075] Here, the driving transistor DRT and the switching transistors T1 to T6 that constitute the subpixel circuit are sometimes referred to as subpixel transistors.

[0076] Thus, a subpixel SP consisting of seven transistors DRT, T1 to T6, and two storage capacitors Cst, CA, is sometimes called a 7T2C structure.

[0077] Here, among various subpixel SP circuits, the 7T2C structure is shown as an example, and the structure and number of transistors and capacitors constituting the subpixel SP can be varied in many ways. On the other hand, each of the multiple subpixel SPs may have the same structure, or some of the multiple subpixel SPs may have different structures.

[0078] Figure 3 is a diagram illustrating an exemplary cross-section of a display panel according to an embodiment of the present disclosure.

[0079] Referring to Figure 3, the display panel 110 according to the embodiment of the present disclosure may include a first buffer layer BUF1 formed on a substrate SUB.

[0080] A light shield layer (LS) may be formed on the first buffer layer BUF1 to block light.

[0081] A second buffer layer BUF2 may be positioned to cover the light shield layer LS.

[0082] A first active layer ACT1, which constitutes the first transistor TR1, may be placed on the second buffer layer BUF2.

[0083] The first transistor TR1 can include a low-temperature polysilicon transistor among the switching transistors that make up the subpixel SP. For example, the subpixel in Figure 2 can include the first switching transistor T1.

[0084] A first gate insulating film GI1 may be placed on top of the first active layer ACT1.

[0085] A first gate electrode GE1 made of a gate material can be formed on a first gate insulating film GI1. As the gate material, opaque conductive materials with low resistance such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), and tantalum (Ta) can be used. Alternatively, transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO), along with opaque conductive materials, can be used as the gate material. The first gate electrode GE1 can be formed to have a multilayer structure in which these materials are stacked.

[0086] The first gate electrode GE1 corresponds to the gate electrode of the first transistor TR1 and can also correspond to the lower gate electrode of the second transistor TR2, which is formed at a position separated from the first transistor TR1. Furthermore, the first gate electrode GE1 can correspond to one electrode forming capacitors Cst and CA.

[0087] For example, the second transistor TR2 may be a switching transistor consisting of an oxide transistor within the subpixel. In the subpixel of Figure 2, the second transistor TR2 can correspond to the second switching transistor T2 to the sixth switching transistor T6.

[0088] In this case, the second transistor TR2 may be formed as a dual-gate structure including an upper gate electrode and a lower gate electrode. In this case, the first gate electrode GE1 can correspond to the lower gate electrode of the second transistor TR2.

[0089] The first interlayer insulating film ILD1 may be positioned to cover the first gate electrode GE1.

[0090] On the other hand, a first gate electrode GE1 and a second gate electrode GE2 that forms capacitance can be formed on the first interlayer insulating film ILD1. The second gate electrode GE2 is formed of the same gate material as the first gate electrode GE1, and the first gate electrode GE1 and the second gate electrode GE2 can form capacitors Cst and CA of the subpixel circuit.

[0091] A third buffer layer BUF3 can be formed on the first interlayer insulating film ILD1.

[0092] A third gate electrode GE3, made of gate material, can be formed on the third buffer layer BUF3.

[0093] The third gate electrode GE3 can correspond to the lower gate electrode of the third transistor TR3, which is formed at a position separated from the second transistor TR2.

[0094] For example, the third transistor TR3 may be a drive transistor DRT consisting of an oxide transistor within a subpixel.

[0095] In this case, the third transistor TR3 may be formed to have a dual-gate structure including an upper gate electrode and a lower gate electrode. In this case, the third gate electrode GE3 can correspond to the lower gate electrode of the third transistor TR3.

[0096] Thus, the second transistor TR2 and the third transistor TR3, both made of oxide transistors, can include lower gate electrodes GE1 and GE3 located in different layers in the vertical direction.

[0097] The fourth buffer layer BUF4 may be positioned to cover the third gate electrode GE3 on the third buffer layer BUF3.

[0098] On the fourth buffer layer BUF4, a second active layer ACT2, which constitutes the second transistor TR2, and a third active layer ACT3, which constitutes the third transistor TR3, may be arranged.

[0099] The second active layer ACT2 can constitute the active layer of a switching transistor made of an oxide transistor, and the third active layer ACT3 can constitute the active layer of a driving transistor made of an oxide transistor.

[0100] The second gate insulating film GI2 may be positioned to cover the second active layer ACT2 and the third active layer ACT3.

[0101] Two or more fourth gate electrodes GE4, made of gate material, can be formed on the second gate insulating film GI2.

[0102] The fourth gate electrode GE4 can correspond to the upper gate electrode of the second transistor TR2 and the upper gate electrode of the third transistor TR3.

[0103] The second interlayer insulating film ILD2 may be positioned to cover the fourth gate electrode GE4.

[0104] Multiple first source-drain electrode patterns SD1 can be arranged on the second interlayer insulating film ILD2.

[0105] As the first source-drain electrode pattern SD1, any of the following can be used: molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), and alloys formed from combinations thereof.

[0106] One of the first source-drain electrode patterns SD1 corresponds to the first source electrode SE1 and the first drain electrode DE1 of the first transistor TR1. Another of the first source-drain electrode patterns SD1 corresponds to the second source electrode SE2 and the second drain electrode DE2 of the second transistor TR2. Yet another of the first source-drain electrode patterns SD1 corresponds to the third source electrode SE3 and the third drain electrode DE3 of the third transistor TR3.

[0107] A portion of the first source-drain electrode pattern SD1 can be electrically connected to the second active layer ACT2 of the second transistor TR2 and the third active layer ACT3 of the third transistor TR3, respectively, via contact holes in the second interlayer insulating film ILD2 and the second gate insulating film GI2.

[0108] Furthermore, another portion of the first source-drain electrode pattern SD1 can be electrically connected to the first active layer ACT1 of the first transistor TR1 via the contact holes of the second interlayer insulating film ILD2, the second gate insulating film GI2, the fourth buffer layer BUF4, the third buffer layer BUF3, the first interlayer insulating film ILD1, and the first gate insulating film GI1.

[0109] The first planarization layer PLN1 may be positioned to cover the first source-drain electrode pattern SD1. The first planarization layer PLN1 may be composed of an organic insulating material such as an acrylic resin. In this case, the drive transistor DRT constituting the subpixel SP and some switching transistors (e.g., T2-T6) may have a dual-gate structure including an upper gate electrode and a lower gate electrode to improve current characteristics in the turn-on state and ensure reliability.

[0110] A second source-drain electrode pattern SD2 may be placed on the first planarization layer PLN1. The second source-drain electrode pattern SD2 may be connected to one of the first source-drain electrode patterns SD1 via a contact hole in the first planarization layer PLN1.

[0111] A second planarization layer PLN2 may be positioned to cover the second source-drain electrode pattern SD2. A light-emitting element ED may be positioned on the second planarization layer PLN2.

[0112] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE.

[0113] The anode electrode AE ​​may be placed on the second planarization layer PLN2. The anode electrode AE ​​may be electrically connected to the second source-drain electrode pattern SD2 through contact holes in the second planarization layer PLN2.

[0114] The bank may be positioned to cover a portion of the anode electrode AE. The bank may have an opening (open portion) in at least a portion of the region corresponding to the light-emitting region EA of the subpixel SP.

[0115] A portion of the anode electrode AE ​​may be exposed through an opening (open portion) in the bank.

[0116] The light-emitting layer (EL) may be placed on the sides of the bank and in the openings (open portions) of the bank. All or part of the light-emitting layer (EL) may be placed between adjacent banks. The light-emitting layer (EL) may include an organic film.

[0117] At the opening of the bank, the light-emitting layer EL can come into contact with the anode electrode AE. A cathode electrode CE may be placed on the light-emitting layer EL.

[0118] A sealing layer ENCAP may be placed on the light-emitting element ED.

[0119] The ENCAP sealing layer may have a single-layer or multi-layer structure. For example, the ENCAP sealing layer may include a first sealing layer PAS1, a second sealing layer PCL, and a third sealing layer PAS2.

[0120] For example, the first sealing layer PAS1 and the third sealing layer PAS2 may be inorganic films, and the second sealing layer PCL may be an organic film. Of the first sealing layer PAS1, the second sealing layer PCL, and the third sealing layer PAS2, the second sealing layer PCL may be the thickest. With this configuration, the second sealing layer PCL can function as a planarization layer.

[0121] The first sealing layer PAS1 is also called the first inorganic sealing layer, the second sealing layer PCL is also called the organic sealing layer, and the third sealing layer PAS2 is also called the second inorganic sealing layer.

[0122] The first encapsulation layer PAS1 is positioned on the cathode electrode CE and can be positioned as close as possible to the light-emitting element ED. The first encapsulation layer PAS1 can be formed from an inorganic insulating material that can be deposited at low temperatures. For example, the first encapsulation layer PAS1 may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere, during the deposition process, the first encapsulation layer PAS1 can prevent damage to the light-emitting layer EL, which contains organic materials that are vulnerable to high-temperature atmospheres.

[0123] The second sealing layer PCL may be formed with a smaller area than the first sealing layer PAS1. In this case, the second sealing layer PCL may be formed so as to expose both ends of the first sealing layer PAS1. The second sealing layer PCL can also play a role in relieving stress between each layer that occurs when the display device 100 is bent, and can enhance the planarization performance.

[0124] For example, the second sealing layer PCL may be an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). For example, the second sealing layer PCL may be formed by an inkjet method.

[0125] The third sealing layer PAS2 may be formed on the second sealing layer PCL so as to cover the upper and side surfaces of both the second sealing layer PCL and the first sealing layer PAS1. The third sealing layer PAS2 can minimize or block the penetration of external moisture or oxygen into the first sealing layer PAS1 and the second sealing layer PCL.

[0126] For example, the third sealing layer PAS2 may be formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0127] On the other hand, the display device 100 of this disclosure may have a touch sensor TS formed on the sealing layer ENCAP for detecting touches from a user's finger or pen.

[0128] If the touch sensor TS is of a type that is integrated into the display panel 110, the touch sensor TS may be placed on the sealing layer ENCAP. The structure of the touch sensor is described in detail below.

[0129] A touch buffer film T-BUF may be placed on the sealing layer ENCAP.

[0130] A touch sensor TS may be placed on a touch buffer film T-BUF.

[0131] The touch sensor TS may include touch sensor metal TSM located in different layers and bridge metal BRG.

[0132] The touch sensor metal TSM and bridge metal BRG may have a triple structure of Ti / Al / Ti.

[0133] A touch interlayer insulating film (T-ILD) may be placed between the touch sensor metal (TSM) and the bridge metal (BRG).

[0134] The touch interlayer insulating film (T-ILD) can be composed of inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiOx). In this case, the touch interlayer insulating film (T-ILD) may be formed using inorganic materials such as silicon oxide (SiOx) to improve touch performance.

[0135] For example, the touch sensor TS may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal arranged adjacent to each other.

[0136] If a third touch sensor metal is positioned between a first touch sensor metal and a second touch sensor metal, and the first and second touch sensor metals need to be electrically connected to each other, the first and second touch sensor metals may be electrically connected via a bridge metal BRG of different layers.

[0137] The bridge metal (BRG) can be isolated from the third touch sensor metal by the touch interlayer insulating film (T-ILD).

[0138] When a touch sensor TS is formed on the display panel 110, moisture or other substances may be generated from chemicals used in the process (such as a developer or etching solution) or from an external source.

[0139] By placing the touch sensor TS on the touch buffer film T-BUF, it is possible to prevent chemicals, moisture, etc. from penetrating the light-emitting layer EL, which contains organic matter, during the manufacturing process of the touch sensor TS.

[0140] This configuration allows for the use of a touch buffer film (T-BUF) to prevent damage to the light-emitting layer (EL), which is vulnerable to chemicals or moisture.

[0141] The touch buffer film (T-BUF) can be formed using an organic insulating material with a low dielectric constant that can be formed at a low temperature (e.g., below 100°C) to prevent damage to the light-emitting layer (EL) which contains organic materials that are vulnerable to high temperatures. For example, the touch buffer film (T-BUF) can be formed using acrylic, epoxy, or siloxane-based materials.

[0142] In the display device 100, bending may damage the sealing layer ENCAP and potentially damage the touch sensor metal TSM located on the touch buffer film T-BUF. However, even if the display device 100 is bent, the touch buffer film T-BUF, which is made of an organic insulating material and has planarization properties, can prevent damage to the sealing layer ENCAP and damage to the touch sensor metal TSM or bridge metal BRG.

[0143] The protective layer PAC may be positioned to cover the touch sensor TS. The protective layer PAC may also be an organic insulating film.

[0144] Figure 4 is a diagram illustrating an exemplary plan view of a display device according to an embodiment of the present disclosure.

[0145] Referring to Figure 4, the display device 100 according to the embodiment of the present disclosure includes at least one display area DA, and the display area DA has a plurality of subpixels SP arranged therein.

[0146] A non-display area (NDA) may be placed around the display area DA that encloses the display area DA. The non-display area NDA is adjacent to one or more sides of the display area DA and encloses the rectangular display area DA. However, the form of the display area DA and the form and arrangement of the non-display area NDA adjacent to the display area DA are not limited thereto.

[0147] A gate drive circuit 120 may be placed in the side non-display area NDA of the display panel 110, and a data drive circuit 130 may be placed in the upper non-display area NDA.

[0148] In the display area DA, multiple subpixels SP connected to multiple data lines DL and multiple gate lines GL may be arranged at the intersections of multiple data lines DL and multiple gate lines GL.

[0149] The non-display area (NDA) may include a pad area (PA) and a link area (LA) where the data drive circuit 130 and the display panel 110 come into contact.

[0150] Pads connected to various signal lines and data drive circuits 130 are arranged in the pad area PA. Pads for applying external signals to the panel may be arranged in the pad area PA, such as probe pads for lighting inspection and pads for adhesion.

[0151] In the link area LA, various connection wires and drive voltage lines such as EVDDL and EVSSL are arranged between the pad area PA and the display area DA.

[0152] The drive voltage line may include a pixel high-potential voltage line EVDDL that applies a high-level pixel high-potential voltage EVDD to the subpixel SP, and a pixel low-potential voltage line EVSSL that applies a low-level pixel low-potential voltage EVSS.

[0153] The drive voltage lines EVDDL and EVSSL can be formed using a first source-drain electrode pattern SD1 or a second source-drain electrode pattern SD2.

[0154] The pixel low-voltage line EVSSL applies a common voltage to the subpixel SP and can be positioned between the gate drive circuit 120 and the edge of the display panel 110 to surround three sides of the display area DA.

[0155] Furthermore, an initialization line IL for applying an initialization voltage to the subpixel SP may be placed between the display area DA and the gate drive circuit 120.

[0156] The data drive circuit 130 may be mounted on a printed circuit board and connected to the display panel 110 via a pad area PA, or it may be mounted in the form of a COP (Chip On Panel) in the link area LA between the pad area PA and the display area DA.

[0157] The subpixel SP of the display area DA may include subpixel circuits connected to the gate line GL and data line DL, and operating in response to the data voltage. The subpixel circuits may be positioned to overlap with either the data line DL or the gate line GL.

[0158] The subpixel SP may be configured to include an organic light-emitting element, depending on the configuration of the subpixel circuit. When the subpixel SP includes an organic light-emitting element, the display panel 110 may be configured using a top emission method, a bottom emission method, or a dual emission method.

[0159] In this case, the outer region of the display panel 110 can be extended from the display region DA by the first inorganic sealing layer PAS1 and the second inorganic sealing layer PAS2 that constitute the sealing layer ENCAP, in order to realize a narrow bezel and prevent moisture permeability.

[0160] Figure 5 is a diagram illustrating a plan view of a display panel in which a first inorganic sealing layer and a second inorganic sealing layer are formed in a display device according to an embodiment of the present disclosure.

[0161] Referring to Figure 5, the display device 100 according to the embodiment of the present disclosure may have inorganic sealing layers PAS1 and PAS2 formed from the display area of ​​the display panel 110 to the outer bezel area in order to minimize or block the penetration of moisture and oxygen from the outside.

[0162] In the display area, the first inorganic encapsulation layer PAS1, the organic encapsulation layer PCL, and the second inorganic encapsulation layer PAS2 may be formed in a laminated structure, while in the bezel area, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be extended.

[0163] In this case, the end of the second inorganic encapsulation layer PAS2 may be located outside the end of the first inorganic encapsulation layer PAS1, or the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 may be formed at the same position.

[0164] For example, the bezel region opposite the pad region PA to which the data driving circuit 130 is coupled to the display panel 110, and the left and right bezel regions of the display panel 110 may also be called the first inorganic layer region CVA1. In the first inorganic layer region CVA1, the end of the second inorganic encapsulation layer PAS2 extends further than the end of the first inorganic encapsulation layer PAS1.

[0165] On the other hand, the portion adjacent to the pad region PA can also be called the third inorganic layer region CVA3. In the third inorganic layer region CVA3, the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 are formed at the same position.

[0166] On the other hand, the portion where the first inorganic layer region CVA1 and the third inorganic layer region CVA3 are in contact may correspond to a second inorganic layer region CVA2 where the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 gradually approach each other. In this case, the second inorganic layer region CVA2 may be located on both outer sides of the pad region PA.

[0167] Thus, because the positions of the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 differ for each inorganic layer region CVA1, CVA2, and CVA3, the separation distances of the drive voltage lines EVDDL and EVSSL that extend along the inorganic layer regions CVA1, CVA2, and CVA3 may differ.

[0168] In this case, if the distance between the first inorganic encapsulation layer PAS1 and the drive voltage lines EVDDL and EVSSL is small, moisture flowing in from the end or seam region of the first inorganic encapsulation layer PAS1 is likely to be transmitted to the drive voltage lines EVDDL and EVSSL in the link region, increasing the likelihood of malfunction.

[0169] Accordingly, in the display device 100 of this disclosure, the ends of the drive voltage lines EVDDL and EVSSL are positioned below the insulating film inside the dam formed in the inorganic layer regions CVA1, CVA2, and CVA3, thereby maintaining a certain separation distance from the ends of the first inorganic sealing layer PAS1 and preventing defects due to moisture permeability.

[0170] In this case, the end positions of the drive voltage lines EVDDL and EVSSL may be the same for each inorganic layer region CVA1, CVA2, and CVA3, or they may differ depending on the end position of the first inorganic sealing layer PAS1 in each of the inorganic layer regions CVA1, CVA2, and CVA3.

[0171] Figure 6 is a diagram illustrating an exemplary cross-section of the first inorganic layer region in a display device according to an embodiment of the present disclosure.

[0172] Here, the first inorganic layer region CVA1 shows a cross-section obtained by cutting through section AB in Figure 5.

[0173] Referring to Figure 6, in the display device 100 according to the embodiment of the present disclosure, in the first inorganic layer region CVA1, the end of the second inorganic encapsulation layer PAS2 can be extended further outward than the end of the first inorganic encapsulation layer PAS1.

[0174] When a liquid organic encapsulation layer (PCL) is formed in the display area DA, one or more dams may be formed in the first inorganic layer area CVA1 to prevent the liquid organic encapsulation layer (PCL) from collapsing in the direction of the bezel area.

[0175] This section illustrates the case where a primary dam (DAM1), a secondary dam (DAM2), and a tertiary dam (DAM3) are formed.

[0176] The primary dam DAM1 is the outermost dam and may have a structure in which the second flattening layer PLN2, the bank BANK, the spacer SPACER, the first inorganic sealing layer PAS1, and the second inorganic sealing layer PAS2 are sequentially stacked.

[0177] At this time, the end of the second source-drain electrode pattern SD2, which forms the drive voltage line, can be located at the bottom of the second flattening layer PLN2 inside the primary dam DAM. Here, the pixel low-potential voltage line EVSSL, which transmits the pixel low-potential voltage EVSS, is shown exemplarily among the drive voltage lines. That is, the pixel low-potential voltage line EVSSL extends only to the interior of the primary dam DAM1, which is located at the outermost edge of the first inorganic layer region CVA1, and does not extend outside the primary dam DAM1.

[0178] This increases the separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic sealing layer PAS1. Since no other metal wiring other than the pixel low-voltage line EVSSL is located within the separation distance Dsp, the thickness of the first inorganic sealing layer PAS1 extending beyond the primary dam DAM1 can be increased. This effectively prevents moisture flowing in from the top of the inorganic sealing layers PAS1 and PAS2 from reaching the pixel low-voltage line EVSSL in the link region.

[0179] For example, the separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic sealing layer PAS1 can be maintained at 60 μm or more, but is not limited to this.

[0180] In this configuration, the end of the pixel low-voltage line EVSSL is positioned to be covered by the second flattening layer PLN2 inside the primary dam DAM1, thereby effectively blocking the inflow of moisture from the link region.

[0181] The secondary dam DAM2 is positioned inward of the display device 100 so as to be adjacent to the primary dam DAM1, and may have a structure in which a bank, a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked.

[0182] Furthermore, the tertiary dam DAM3 may be configured to have a structure in which a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked on top of a bank BANK that is positioned inward of the display device 100 so as to be adjacent to the secondary dam DAM2.

[0183] Figure 7 is an enlarged plan view of the second inorganic layer region in a display device according to an embodiment of the present disclosure, in which the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer gradually approach each other. Figure 8 is a diagram illustrating a cross-section obtained by cutting the CD section of the second inorganic layer region in a display device according to an embodiment of the present disclosure.

[0184] Referring to Figures 7 and 8, in the display device 100 according to the embodiment of the present disclosure, a constant distance can be maintained between the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 in the first inorganic layer region CVA1, but in the second inorganic layer region CVA2, the end of the first inorganic encapsulation layer PAS1 can gradually approach the end of the second inorganic encapsulation layer PAS2.

[0185] Such a second inorganic layer region CVA2 can correspond to the outer edges on both sides of the pad region PA to which the data driving circuit 130 is coupled to the display panel 110.

[0186] Depending on its position on the second inorganic layer region CVA2, the end of the first inorganic encapsulation layer PAS1 may be located inside the end of the second inorganic encapsulation layer PAS2, or the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 may be formed at the same position.

[0187] In the portion where the end of the first inorganic encapsulation layer PAS1 is located inside the end of the second inorganic encapsulation layer PAS2, the separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic encapsulation layer PAS1 may be narrower, similar to the first inorganic layer region CVA1.

[0188] As a result, moisture that has entered the link region through the end or seam of the first inorganic sealing layer PAS1 may reach the drive voltage lines EVDDL and EVSSL, potentially causing malfunctions.

[0189] Therefore, in the second inorganic layer region CVA2, in the portion where the end of the first inorganic sealing layer PAS1 is located inward from the end of the second inorganic sealing layer PAS2, the ends of the drive voltage lines EVDDL and EVSSL are formed inside the primary dam DAM1, thereby increasing the separation distance Dsp between the ends of the drive voltage lines EVDDL and EVSSL and the end of the first inorganic sealing layer PAS1, and effectively blocking moisture from flowing into the link region from the upper part of the inorganic sealing layers PAS1 and PAS2.

[0190] When a liquid organic encapsulation layer PCL is formed in the display area DA within the second inorganic layer region CVA2, one or more dams may be formed to prevent the liquid organic encapsulation layer PCL from collapsing in the direction of the bezel region.

[0191] This section illustrates the case where a primary dam (DAM1), a secondary dam (DAM2), and a tertiary dam (DAM3) are formed.

[0192] The primary dam DAM1 is the outermost dam and may have a structure in which the second flattening layer PLN2, the bank BANK, the spacer SPACER, the first inorganic sealing layer PAS1, and the second inorganic sealing layer PAS2 are sequentially stacked.

[0193] At this time, the end of the second source-drain electrode pattern SD2, which forms the drive voltage line, can be located below the second planarization layer PLN2 inside the primary dam DAM. Here, among the drive voltage lines EVDDL and EVSSL, the pixel low-potential voltage line EVSSL, which transmits the pixel low-potential voltage EVSS, is shown exemplarily.

[0194] In other words, the pixel low-potential voltage line EVSSL formed from the second source-drain electrode pattern SD2 can be formed to extend only into the interior of the primary dam DAM1 located at the outermost edge of the second inorganic layer region CVA2, and not extend outside the primary dam DAM1.

[0195] This increases the separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic sealing layer PAS1, effectively blocking moisture flowing in from the top of the inorganic sealing layers PAS1 and PAS2 from reaching the pixel low-voltage line EVSSL in the link region.

[0196] In this case, the separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic sealing layer PAS1 can be maintained at 60 μm or more.

[0197] Furthermore, by positioning the end of the pixel low-voltage line EVSSL to be covered by the second flattening layer PLN2 inside the primary dam DAM1, the inflow of moisture into the link region can be effectively blocked.

[0198] The secondary dam DAM2 is positioned inward of the display device 100 so as to be adjacent to the primary dam DAM1, and may have a structure in which a bank, a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked.

[0199] Furthermore, the tertiary dam DAM3 may be configured to have a structure in which a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked on top of a bank BANK that is positioned inward of the display device 100 so as to be adjacent to the secondary dam DAM2.

[0200] Figure 9 is an enlarged plan view of a third inorganic layer region in a display device according to an embodiment of the present disclosure, in which the end positions of the first inorganic encapsulation layer and the end positions of the second inorganic encapsulation layer are the same. Figure 10 is a diagram illustrating an exemplary cross-section of the EF section of the third inorganic layer region in a display device according to an embodiment of the present disclosure.

[0201] Referring to Figures 9 and 10, according to the display device 100 of the embodiment of the present disclosure, the end positions of the first inorganic encapsulation layer PAS1 and the end positions of the second inorganic encapsulation layer PAS2 can be located on the same line in the third inorganic layer region CVA3.

[0202] Such a third inorganic layer region CVA3 can correspond to a pad region PA to which the data driving circuit 130 is coupled to the display panel 110.

[0203] Therefore, in the third inorganic layer region CVA3, the end of the first inorganic encapsulation layer PAS1 extends to the end of the second inorganic encapsulation layer PAS2, so that a sufficient separation distance Dsp can be secured between the end of the pixel low-voltage line EVSSL and the end of the first inorganic encapsulation layer PAS1.

[0204] Therefore, even if the ends of the drive voltage lines EVDDL and EVSSL protrude outside the primary dam DAM1, if the separation distance Dsp between the ends of the drive voltage lines EVDDL and EVSSL and the ends of the first inorganic sealing layer PAS1 is greater than the distance between the ends of the first inorganic sealing layer PAS1 and the outermost primary dam DAM1, then moisture flowing into the link region from the top of the inorganic sealing layers PAS1 and PAS2 can be blocked.

[0205] In addition, since the separation distance Dsp between the ends of the drive voltage lines EVDDL and EVSSL and the ends of the first inorganic sealing layer PAS1 is formed to be greater than the distance between the ends of the first inorganic sealing layer PAS1 and the outermost primary dam DAM1, the ends of the drive voltage lines EVDL and EVSSL can be formed inside the primary dam DAM1.

[0206] When a liquid organic encapsulation layer PCL is formed in the display area DA within the third inorganic layer region CVA3, one or more dams may be formed to prevent the liquid organic encapsulation layer PCL from collapsing in the direction of the bezel region.

[0207] This section illustrates the case where a primary dam (DAM1), a secondary dam (DAM2), and a tertiary dam (DAM3) are formed.

[0208] The primary dam DAM1 is the outermost dam and may have a structure in which the second flattening layer PLN2, the bank BANK, the spacer SPACER, the first inorganic sealing layer PAS1, and the second inorganic sealing layer PAS2 are sequentially stacked.

[0209] At this time, the end of the second source-drain electrode pattern SD2, which forms the drive voltage line, can be located below the second planarization layer PLN2 inside the primary dam DAM. Here, among the drive voltage lines EVDDL and EVSSL, the pixel low-potential voltage line EVSSL, which transmits the pixel low-potential voltage EVSS, is shown exemplarily.

[0210] In other words, the pixel low-voltage line EVSSL formed from the second source-drain electrode pattern SD2 can protrude outside the primary dam DAM1 located at the outermost edge of the third inorganic layer region CVA3. Alternatively, the end of the pixel low-voltage line EVSSL may be located inside the primary dam DAM1.

[0211] Thus, by considering the end position of the first inorganic encapsulation layer PAS1 and forming a separation distance Dsp between the end of the pixel low potential voltage line EVSSL and the end of the first inorganic encapsulation layer PAS1, it is possible to effectively block moisture flowing from the top of the inorganic encapsulation layers PAS1 and PAS2 into the link region from reaching the pixel low potential voltage line EVSSL.

[0212] The separation distance Dsp between the end of the pixel low-voltage line EVSSL and the end of the first inorganic sealing layer PAS1 can be maintained at 60 μm or more.

[0213] Furthermore, if the end of the pixel low-voltage line EVSSL is located inside the primary dam DAM1, the end of the pixel low-voltage line EVSSL can be positioned so that it is covered by the second flattening layer PLN2, thereby effectively blocking the inflow of moisture into the link region.

[0214] The secondary dam DAM2 is located inward of the display device 100 so as to be adjacent to the primary dam DAM1, and may have a structure in which a bank, a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked.

[0215] Furthermore, the tertiary dam DAM3 may be configured to have a structure in which a spacer, a first inorganic sealing layer PAS1, and a second inorganic sealing layer PAS2 are sequentially stacked on top of a bank BANK that is positioned inward from the display device 100 so as to be adjacent to the secondary dam DAM2.

[0216] On the other hand, the display device 100 of this disclosure can also prevent the distance between the end of the first inorganic encapsulation layer PAS1 and the drive voltage lines EVDDL and EVSSL from becoming too close in the link region by moving the position of the point where the end of the first inorganic encapsulation layer PAS1 and the end of the second inorganic encapsulation layer PAS2 contact each other outside the link region in the second inorganic layer region CVA2.

[0217] Figure 11 is a diagram illustrating a plan view of a display device according to an embodiment of the present disclosure, in which the position of the point where the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer contact is moved to the outside of the link region.

[0218] Referring to Figure 11, in the second inorganic layer region CVA2, the end of the first inorganic encapsulation layer PAS1 gradually approaches the end of the second inorganic encapsulation layer PAS2. The second inorganic layer region CVA2 can be superimposed on the link region LA, through the pad region, to which the drive voltage lines EVDDL and EVSSL are extended.

[0219] Thus, when the second inorganic layer region CVA2 overlaps with the link region LA, the separation distance Dsp between the end of the first inorganic encapsulation layer PAS1 and the ends of the drive voltage lines EVDDL and EVSSL in the second inorganic layer region CVA2 may become narrower. In this case, moisture flowing into the link region from the top of the inorganic encapsulation layers PAS1 and PAS2 may reach the drive voltage lines EVDDL and EVSSL.

[0220] However, if the position of the second inorganic layer region CVA2, where the end of the first inorganic encapsulation layer PAS1 gradually approaches the end of the second inorganic encapsulation layer PAS2, is moved outside the link region LA, the separation distance Dsp between the end of the first inorganic encapsulation layer PAS1 and the end of the pixel low-voltage line EVSSL in the link region LA can be made sufficiently large.

[0221] As a result, in the link region LA, the separation distance Dsp between the end of the pixel low-potential voltage line EVSSL and the end of the first inorganic sealing layer PAS1 is formed to be greater than the distance between the end of the first inorganic sealing layer PAS1 and the inner primary dam DAM1, thereby effectively blocking moisture flowing into the link region from the top of the inorganic sealing layers PAS1 and PAS2 from reaching the pixel low-potential voltage line EVSSL.

[0222] Here, the explanation was based on the case where the pixel low-voltage line EVSSL is located outside the pixel high-voltage line EVDDL in the link region LA. However, when the pixel high-voltage line EVDDL is located outside the pixel low-voltage line EVSSL, the effect of moisture inflow can be determined based on the separation distance between the end of the pixel high-voltage line EVDDL and the end of the first inorganic sealing layer PAS1.

[0223] A display device according to an embodiment of the present disclosure can be described as follows.

[0224] The display device of the present disclosure includes a display panel including a display area on which a plurality of subpixels are formed and a non-display area divided into a plurality of inorganic layer areas on the outer edge of the display area according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer; a data driving circuit coupled to a pad area of ​​the display panel; and a timing controller for controlling the data driving circuit. The separation distance between the end of a driving voltage line that transmits a driving voltage to the plurality of subpixels and the end of the first inorganic sealing layer in a link area adjacent to the pad area may be configured to be greater than the distance between the end of the first inorganic sealing layer and the outermost primary dam.

[0225] The multiple inorganic layer regions may include a first inorganic layer region where the end of the second inorganic encapsulation layer is located, which is an extension of a certain distance from the end of the first inorganic encapsulation layer; a second inorganic layer region where the end of the first inorganic encapsulation layer gradually approaches the end of the second inorganic encapsulation layer; and a third inorganic layer region where the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer coincide.

[0226] The third inorganic layer region is located in the pad region, the second inorganic layer region is located on both sides of the third inorganic layer region, and the first inorganic layer region may be located in a region other than the second inorganic layer region and the third inorganic layer region.

[0227] In the first inorganic layer region, a primary dam is formed between the display region and the end of the first inorganic sealing layer, and the end of the drive voltage line may be formed inside the primary dam.

[0228] The primary dam has a structure in which a flattening layer, a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked, and the end of the drive voltage line can be located below the flattening layer.

[0229] The first inorganic layer region further includes a secondary dam and a tertiary dam formed between the display region and the primary dam, wherein the secondary dam is arranged inward adjacent to the primary dam and has a structure in which a bank, a spacer, the first inorganic sealing layer and the second inorganic sealing layer are sequentially stacked, and the tertiary dam is configured to have a structure in which a spacer, the first inorganic sealing layer and the second inorganic sealing layer are sequentially stacked on top of a bank arranged inward adjacent to the secondary dam, and the drive voltage line can be located below the secondary dam and the tertiary dam.

[0230] In the second inorganic layer region, at least one dam is formed between the display region and the end of the first inorganic sealing layer, and the end of the drive voltage line may be formed inside the dam.

[0231] In the third inorganic layer region, at least one dam is formed between the display region and the end of the first inorganic sealing layer, the dam having a structure in which a planarization layer, a bank, a spacer, the first inorganic sealing layer and the second inorganic sealing layer are sequentially stacked, and the end of the drive voltage line can be extended to the outside of the planarization layer.

[0232] The drive voltage line includes a pixel low-voltage line that transmits a pixel low-voltage to the plurality of subpixels, and a pixel high-voltage line that transmits a pixel high-voltage to the plurality of subpixels, wherein the pixel low-voltage line may be located outside the pixel high-voltage line.

[0233] The plurality of subpixels may include a substrate, a first transistor disposed on the upper part of the substrate and made of a low-temperature polysilicon transistor, a second transistor disposed on the upper part of the substrate and made of an oxide transistor, a drive transistor disposed on the upper part of the substrate and made of an oxide transistor, the first transistor, the second transistor, and a first source-drain electrode pattern forming the source electrode and drain electrode of the drive transistor, a first planarization layer formed to cover the first source-drain electrode pattern, a second source-drain electrode pattern electrically connected to the first source-drain electrode pattern through contact holes in the first planarization layer, a second planarization layer formed to cover the second source-drain electrode pattern, a light-emitting element formed on the upper part of the second planarization layer, and a sealing layer formed on the upper part of the light-emitting element by sequentially stacking the first inorganic sealing layer, an organic sealing layer, and the second inorganic sealing layer.

[0234] The drive voltage line can be formed by the second source-drain electrode pattern.

[0235] The second inorganic layer region may be formed outside the link region.

[0236] Furthermore, the display panel of this disclosure includes a display area on which a plurality of subpixels are formed, a non-display area divided into a plurality of inorganic layer areas on the outer edge of the display area according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer, a pad area on which a data driving circuit is coupled, and a link area on which a driving voltage line that transmits a driving voltage to the plurality of subpixels extends through the pad area, wherein the separation distance between the end of the driving voltage line and the end of the first inorganic sealing layer may be formed to be greater than the distance between the end of the first inorganic sealing layer and the outermost primary dam.

[0237] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only, and not to limit the technical concept of this disclosure, and such embodiments do not limit the scope of the technical concept of this disclosure.

Claims

1. A display panel comprising a display area in which multiple subpixels are formed, and a non-display area divided into multiple inorganic layer areas according to the arrangement of a first inorganic sealing layer and a second inorganic sealing layer on the outer edge of the display area, wherein the non-display area has multiple dams arranged on it. A data driving circuit coupled to the pad area of ​​the display panel, and Includes a timing controller that controls the data drive circuit, In the link region adjacent to the pad region, the end of the drive voltage line that transmits the drive voltage to the plurality of subpixels is formed to be located inside the primary dam, which is the outermost of the plurality of dams. Display device.

2. The plurality of inorganic layer regions are The first inorganic layer region where the end of the second inorganic sealing layer, which is extended by a certain distance from the end of the first inorganic sealing layer, is located, The end of the first inorganic sealing layer gradually approaches the end of the second inorganic sealing layer in a second inorganic layer region, and A third inorganic layer region where the end of the first inorganic encapsulation layer and the end of the second inorganic encapsulation layer coincide. The display device according to claim 1, including the following:

3. The third inorganic layer region is located in the pad region, The second inorganic layer region is located on the outer edges on both sides of the third inorganic layer region. The first inorganic layer region is located in a region other than the second inorganic layer region and the third inorganic layer region. The display device according to claim 2.

4. In the first inorganic layer region, the primary dam is formed between the display region and the end of the first inorganic sealing layer. The end of the aforementioned drive voltage line is formed inside the primary dam. The display device according to claim 2.

5. The primary dam has a structure in which a flattening layer, a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The end of the drive voltage line is located below the flattening layer. The display device according to claim 4.

6. The first inorganic layer region further includes secondary and tertiary dams formed between the display region and the primary dam, The secondary dam is positioned inward so as to be adjacent to the primary dam, and has a structure in which a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The tertiary dam is configured such that, in the upper part of a bank arranged inward adjacent to the secondary dam, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The drive voltage line is located below the secondary dam and the tertiary dam. The display device according to claim 4.

7. In the second inorganic layer region, the primary dam is formed between the display region and the end of the first inorganic sealing layer. The end of the aforementioned drive voltage line is formed inside the primary dam. The display device according to claim 2.

8. The primary dam has a structure in which a flattening layer, a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The end of the drive voltage line is located below the flattening layer. The display device according to claim 7.

9. The second inorganic layer region further includes secondary and tertiary dams formed between the display region and the primary dam, The secondary dam is positioned inward so as to be adjacent to the primary dam, and has a structure in which a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The tertiary dam is configured such that, in the upper part of a bank arranged inward adjacent to the secondary dam, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The drive voltage line is located below the secondary dam and the tertiary dam. The display device according to claim 8.

10. In the third inorganic layer region, the primary dam is formed between the display region and the end of the first inorganic sealing layer. The primary dam has a structure in which a flattening layer, a bank, a spacer, the first inorganic sealing layer, and the second inorganic sealing layer are sequentially stacked. The end of the drive voltage line extends to the outside of the planarization layer. The display device according to claim 2.

11. The aforementioned drive voltage line is A pixel low voltage line that transmits a pixel low voltage to the plurality of subpixels, and Pixel high potential voltage line that transmits pixel high potential voltage to the plurality of subpixels Includes, The aforementioned pixel low voltage line is located outside the aforementioned pixel high voltage line. The display device according to claim 1.

12. The aforementioned subpixels are substrate, A first transistor, which is a low-temperature polysilicon transistor, is located on the upper part of the substrate. A second transistor, which is an oxide transistor, is located on the upper part of the aforementioned substrate. A drive transistor, which is made of an oxide transistor, is located on the upper part of the aforementioned substrate. A first source-drain electrode pattern forming the source electrode and drain electrode of the first transistor, the second transistor, and the drive transistor, A first planarization layer formed to cover the first source-drain electrode pattern, A second source-drain electrode pattern is electrically connected to the first source-drain electrode pattern via the contact holes of the first planarization layer. A second planarization layer formed to cover the second source-drain electrode pattern, A light-emitting element formed on the upper part of the second planarization layer, and A sealing layer is formed on the upper part of the light-emitting element by sequentially laminating the first inorganic sealing layer, the organic sealing layer, and the second inorganic sealing layer. The display device according to claim 1, including the following:

13. The display device according to claim 12, wherein the drive voltage line is formed by the second source-drain electrode pattern.

14. The display device according to claim 2, wherein the second inorganic layer region is formed outside the link region.

15. A display area in which multiple subpixels are formed, The outer edge of the display area is divided into multiple inorganic layer areas according to the arrangement of the first inorganic sealing layer and the second inorganic sealing layer, and a non-display area in which multiple dams are arranged. A pad area to which a data drive circuit is coupled, and The pad region includes a link region to which a drive voltage line that transmits a drive voltage to the plurality of subpixels is extended, The end of the drive voltage line is formed to be located inside the primary dam, which is the outermost of the multiple dams. Display device.

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