Printed circuit board

Abstract

The present invention provides a printed circuit board that offers excellent integration density and reliability, and eliminates the need for cavity processing and filling processes by incorporating via capacitors. [Solution] A printed circuit board according to one embodiment of the present disclosure includes a capacitor comprising a first insulating layer, a through hole penetrating at least a portion of the first insulating layer, a first electrode layer disposed on the side surface of the through hole, a second electrode layer disposed on the side surface of the first electrode layer, and a first wiring layer comprising a first metal layer covering the upper surface of the first electrode layer and a second metal layer covering the upper surface of the second electrode layer, wherein the first metal layer and the second metal layer may each have a first incision and a second incision.

Description

[Technical Field]

[0001] The present disclosure relates to a printed circuit board. [Background Art]

[0002] Conventionally, structures have been adopted in which passive elements such as chip capacitors and silicon capacitors are mounted outside a printed circuit board (PCB), or the passive elements are embedded after a cavity is formed in the core of the PCB.

[0003] However, when a large number of passive elements are mounted outside the PCB, the large number of passive elements occupies the external area of the PCB, which may reduce the space efficiency of the PCB.

[0004] In addition, when forming a cavity for embedding a passive element in the core of the PCB, there is a disadvantage that a separate cavitation processing space must be secured, and the passive element can only be built in the limited space of the PCB. Further, the cavity asymmetrically occupying the internal volume of the PCB may cause variation in insulation thickness. [Summary of the Invention] [Problem to be Solved by the Invention]

[0005] One of the various objects of the present disclosure is to provide a printed circuit board with excellent integration density.

[0006] One of the various objects of the present disclosure is to provide a printed circuit board with excellent reliability.

[0007] One of the various objects of the present disclosure is to provide a printed circuit board in which via capacitors are introduced to eliminate the need for cavity processing and embedding processes.

[0008] However, the objects of the present disclosure are not limited to the above description, and can be more easily understood in the process of describing specific embodiments of the present disclosure. [Means for solving the problem]

[0009] A printed circuit board according to one embodiment of the present disclosure includes a capacitor comprising a first insulating layer, a through hole penetrating at least a portion of the first insulating layer, a first electrode layer disposed on the side surface of the through hole, a second electrode layer disposed on the side surface of the first electrode layer, and a first wiring layer comprising a first electrode layer covering the upper surface of the first electrode layer and a second metal layer covering the upper surface of the second metal layer, wherein the first metal layer and the second metal layer may each have a first cut portion and a second cut portion.

[0010] A printed circuit board according to one embodiment of the present disclosure includes a capacitor comprising a first insulating layer having through holes, a first electrode layer, a first dielectric layer, and a second electrode layer sequentially arranged on the side surface of the through holes, and a first metal layer and a second metal layer disposed above the through holes and connected to the first and second electrode layers, respectively, wherein, when viewed from above the metal layers, the first and second electrode layers each have shapes corresponding to the first and second electrode layers, and the first and second metal layers each include a first incision and a second incision that are open in different directions from each other. [Effects of the Invention]

[0011] One of the various effects of this disclosure is that it can provide a printed circuit board with excellent integration density.

[0012] One of the various benefits of this disclosure is the ability to provide a highly reliable printed circuit board.

[0013] One of the various effects of this disclosure is the ability to provide a printed circuit board that eliminates the cavity processing and filling processes by introducing via capacitors. [Brief explanation of the drawing]

[0014] [Figure 1]This is a block diagram illustrating a schematic example of an electronic equipment system. [Figure 2] This is a perspective view showing a schematic example of an electronic device. [Figure 3] This is a schematic top plan view showing a printed circuit board according to one embodiment of the present disclosure. [Figure 4] This is a schematic cross-sectional view showing a section along the line I-I' in Figure 3. [Figure 5] This is a schematic cross-sectional view showing a section along the line II-II' in Figure 3. [Figure 6] This is a schematic cross-sectional view showing a section along the line III-III' in Figure 4. [Figure 7] This is a schematic perspective view showing the first wiring layer of a printed circuit board according to one embodiment of the present disclosure. [Figure 8a] Figures 3 to 5 are cross-sectional views corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8b] Figures 3 to 5 are cross-sectional views corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8c] Figures 3 to 5 are cross-sectional views corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8d] Figures 3 to 5 are cross-sectional views corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8e] Figures 3 to 5 show a cross-sectional view and a top plan view corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8f] Figures 3 to 5 show a cross-sectional view and a top plan view corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8g] Figures 3 to 5 show a cross-sectional view and a top plan view corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 8h] Figures 3 to 5 show a cross-sectional view and a top plan view corresponding to Figure 5, illustrating an example of a manufacturing method for printed circuit boards. [Figure 9]FIG. 1 is a schematic top plan view showing a printed circuit board according to another embodiment of the present disclosure. [Figure 10] It is a cross-sectional view schematically showing a cut cross-section taken along line IV-IV' of FIG. 9. [Figure 11] It is a cross-sectional view schematically showing a cut cross-section taken along line V-V' of FIG. 9. [Figure 12a] It is a cross-sectional view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12b] It is a cross-sectional view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12c] It is a cross-sectional view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12d] It is a cross-sectional view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12e] They are a cross-sectional view and a top plan view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12f] They are a cross-sectional view and a top plan view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. [Figure 12g] They are a cross-sectional view and a top plan view corresponding to FIG. 11 for explaining an example of a method of manufacturing the printed circuit board of FIGS. 9 to 11. MODE FOR CARRYING OUT THE INVENTION

[0015] Embodiments of the present disclosure will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present disclosure can be modified into several other forms, and the scope of the present disclosure is not limited to the embodiments described below. Furthermore, embodiments of the present disclosure are provided to give a more complete explanation of the present disclosure to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer explanation, and elements indicated by the same reference numeral in the drawings are the same element.

[0016] Furthermore, in order to clearly illustrate this disclosure, parts unrelated to the explanation have been omitted in the drawings, and the size and thickness of each illustrated component are shown arbitrarily for the convenience of explanation; therefore, this disclosure is not necessarily limited by the illustrations. Also, components with the same function within the scope of the same idea are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a component, it does not mean that other components are excluded, but rather that other components may be included, unless otherwise stated to the contrary.

[0017] electronic equipment Figure 1 is a block diagram illustrating a schematic example of an electronic equipment system.

[0018] Referring to Figure 1, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0019] Chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. Chip-related components 1020 can also be in the form of a package containing the aforementioned chips and electronic components.

[0020] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi® (IEEE 802.11 family, etc.), WiMAX® (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It may also include any other numerous wireless or wired standards or protocols. Furthermore, network-related component 1030 can be combined with chip-related component 1020.

[0021] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0022] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include the camera 1050, antenna 1060, display 1070, and battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components used for various purposes.

[0023] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, etc. However, it is not limited to these, and can also be any other electronic device that processes data.

[0024] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0025] Referring to Figure 2, the electronic device could be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Furthermore, other components, such as a camera module 1130 and / or a speaker 1140, are housed inside, either physically and / or electrically connected to or not connected to the motherboard 1110. Some of the components 1120 can be the chip-related components described above, and can be, for example, a component package 1121, but are not limited to this. The component package 1121 can be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on the surface. Alternatively, the component package 1121 can be in the form of a printed circuit board with active and / or passive components embedded within it. On the other hand, the electronic device is not necessarily limited to a smartphone 1100, and as described above, it can be other electronic devices.

[0026] Printed circuit board Figure 3 is a schematic top plan view of a printed circuit board according to one embodiment of the present disclosure; Figure 4 is a schematic cross-sectional view of a cross section along line I-I' in Figure 3; Figure 5 is a schematic cross-sectional view of a cross section along line II-II' in Figure 3; Figure 6 is a schematic cross-sectional view of a cross section along line III-III' in Figure 4; and Figure 7 is a schematic perspective view of the first wiring layer of a printed circuit board according to one embodiment of the present disclosure.

[0027] Referring to Figures 3 to 7, the printed circuit board 100 may include a first insulating layer 101 having through holes TH1, a capacitor 110, and a first wiring layer 120.

[0028] The first insulating layer 101 may have a structure in which one or more insulating layers are laminated. The through-hole TH1 may penetrate at least a portion of the first insulating layer 101. For example, the through-hole TH1 may penetrate between the upper and lower surfaces of the first insulating layer 101. Although the drawings show a structure in which the first insulating layer 101 has one through-hole TH1, the disclosure is not limited thereto. The first insulating layer 101 may have a plurality of through-holes TH1.

[0029] The capacitor 110 may include, for example, a first electrode layer 111 disposed on the side surface of the through hole TH1, a second electrode layer 112 disposed on the side surface of the first electrode layer 111, and a first dielectric layer 115 disposed between the first electrode layer 111 and the second electrode layer 112. The capacitor 110 may also include, for example, a first electrode layer 111, a first dielectric layer 115, and a second electrode layer 112 sequentially disposed on the side surface of the through hole TH1.

[0030] The first electrode layer 111 and the second electrode layer 112 are arranged facing each other with the first dielectric layer 115 in between to form a capacitance. The capacitor 110 can function as an electronic element that generates voltage and outputs current by utilizing its characteristic of repeated charging and discharging. This can fix an unstable power supply and remove noise. It can also block DC and allow AC to pass through. Furthermore, it can be used for the stable operation of semiconductor chips.

[0031] Other methods for placing capacitors on a printed circuit board include mounting chip capacitors such as MLCCs on the surface of the printed circuit board, or creating a separate cavity in the printed circuit board and embedding the chip capacitors in that cavity.

[0032] However, when numerous chip capacitors are mounted on the surface of a printed circuit board, the numerous chip capacitors occupy an external area of ​​the printed circuit board, potentially reducing the spatial efficiency of the printed circuit board. Furthermore, when chip capacitors are mounted on the surface of a printed circuit board via soldering, the surface tension of the soldering may cause cracks in the chip capacitors or cause them to detach, potentially increasing parasitic inductance due to soldering. On the other hand, a printed circuit board 100 according to one embodiment of this disclosure includes a capacitor 110 placed inside a through-hole TH1, thereby reducing the number of chip capacitors mounted on the surface of the printed circuit board 100 and improving the integration density of the printed circuit board 100. In addition, the capacitor 110, being placed inside the through-hole TH1, offers excellent reliability, is directly connected within the signal path of the printed circuit board 100, improves SI (Signal Integrity) characteristics, and reduces parasitic inductance.

[0033] On the other hand, when embedding chip capacitors in the cavities of a printed circuit board, a separate cavity processing and embedding process must be performed, and the cavity occupies the internal volume of the printed circuit board asymmetrically, reducing the distribution of the insulation thickness of the printed circuit board. Furthermore, since the chip capacitors embedded in the cavities must be connected to other components via wiring layers formed inside the printed circuit board, parasitic inductance may occur, and they can only be housed within the limited space of the cavity. On the other hand, the printed circuit board 100 according to one embodiment of this disclosure can omit the separate cavity processing and embedding process, and the reliability characteristics such as the distribution of insulation thickness and warping characteristics of the printed circuit board 100 can be improved by omitting the cavity. In addition, the capacitor 110 of the printed circuit board 100 according to one embodiment of this disclosure can be directly connected in the signal path to reduce parasitic inductance, and the integration density of the printed circuit board 100 can be improved by forming multiple through holes TH1 as needed in the printed circuit board 100 and arranging the capacitor 110 inside them.

[0034] The first wiring layer 120 may include, for example, a first metal layer 121 covering the upper surface of the first electrode layer 111 and a second metal layer 122 covering the upper surface of the second electrode layer 112. For example, the first metal layer 121 and the second metal layer 122 may be positioned above the through hole TH1 and connected to the first electrode layer 111 and the second electrode layer 112, respectively.

[0035] The first metal layer 121 and the second metal layer 122 may each include a first incision 121a and a second incision 122a. For example, when viewed from above the through hole TH1, the first metal layer 121 and the second metal layer 122 may each have shapes corresponding to the first electrode layer 111 and the second electrode layer 112, and the first metal layer 121 and the second metal layer 122 may each include a first incision and a second incision that are open in different directions from each other. That is, the first metal layer 121 and the second metal layer 122 may each have a ring shape in which a portion is cut out by the first incision 121a and the second incision 122a.

[0036] For example, the first incision 121a can be opened in a first direction, and the second incision 122a can be opened in a second direction different from the first direction. The first and second directions are not particularly limited and may be opposite to each other. For example, the first direction may be to the right in Figure 3, and the second direction may be to the left in Figure 3.

[0037] The first incision 121a and the second incision 122a may be configured to connect the first metal layer 121 and the second metal layer 122, which have different polarities, to the signal patterns of the first wiring layer 120, which also have different polarities. For example, the first wiring layer 120 may include a first conductor layer 125 that penetrates the second incision 122a and is connected to the first metal layer 121, and a second conductor layer 126 that penetrates the first incision 121a and is connected to the second metal layer 122. That is, the first conductor layer 125 and the second conductor layer 126 can be arranged at a distance from the second metal layer 122 and the first metal layer 121, respectively, via the first incision 121a and the second incision 122a.

[0038] In one embodiment, the capacitor 110 may further include a third electrode layer 113 disposed on the side surface of the second electrode layer 112, a second dielectric layer 116 disposed between the second electrode layer 112 and the third electrode layer 113, a fourth electrode layer 114 disposed on the side surface of the third electrode layer 113, and a third dielectric layer 117 disposed between the third electrode layer 113 and the fourth electrode layer 114. That is, the capacitor 110 may include a first electrode layer 111, a first dielectric layer 115, a second electrode layer 112, a second dielectric layer 116, a third electrode layer 113, and a third dielectric layer 117 sequentially disposed on the side surface of the through hole TH1, and may include a fourth electrode layer 114 disposed on the side surface of the third dielectric layer 117 and filling the center of the through hole TH1. The electrode layers 111, 112, 113, 114 and the dielectric layers 115, 116, 117 may be arranged alternately with respect to each other in the direction toward the side surface of the through hole TH1 at the center of the through hole TH1. The first to third electrode layers 111, 112, and 113 and the first to third dielectric layers 115, 116, and 117 are hollow columnar structures, and the fourth electrode layer 114 may also be columnar.

[0039] The first wiring layer 120 may include a third metal layer 123 covering the upper surface of the third electrode layer 113 and a fourth metal layer 124 covering the upper surface of the fourth electrode layer 114. For example, the third metal layer 123 and the fourth metal layer 124 may be positioned above the through hole TH1 and connected to the third electrode layer 113 and the fourth electrode layer 114, respectively.

[0040] The third metal layer 123 may have a third incision 123a. For example, when viewed from above the through hole TH1, the third metal layer 123 may have a shape corresponding to the third electrode layer 113 and may include a third incision 123a. That is, the third metal layer 123 may have a ring shape with a portion cut out by the third incision 123a. For example, the first incision 121a and the third incision 123a may each be open in the first direction, and the second incision 122a may be open in the second direction, which is different from the first direction.

[0041] The first wiring layer 120 may include, for example, a first conductor layer 125 that penetrates the second incision 122a and is connected to the first metal layer 121 and the third metal layer 123, respectively; a second conductor layer 126 that penetrates the first incision 121a and is connected to the second metal layer 122; and a third conductor layer 127 that penetrates the third incision 123a and is connected to the second metal layer 122 and the fourth metal layer 124, respectively.

[0042] The first conductor layer 125 can be connected to the first metal layer 121 and the third metal layer 123 via the second incision 122a, and the first conductor layer 125 can be positioned at a distance from the second metal layer 122. In addition, the third conductor layer 127 can be connected to the second metal layer 122 and the fourth metal layer 124 via the third incision 123a, and the third conductor layer 127 can be positioned at a distance from the first metal layer 121.

[0043] In one embodiment, the first wiring layer 120 may further include a fourth conductor layer 128 connected to the outer surface of the first metal layer 121. The first conductor layer 125 and the fourth conductor layer 128 may be arranged side by side, and the second conductor layer 126 and the third conductor layer 127 may be arranged side by side, but the disclosure is not limited thereto. The first conductor layer 125 and the fourth conductor layer 128 can form first traces connected to the first metal layer 121 and the third metal layer 123, respectively, and the second conductor layer 126 and the third conductor layer 127 can form second traces connected to the second metal layer 122 and the fourth metal layer 122, respectively. The first electrode layer 111 and the third electrode layer 113, which have the same polarity, can be connected in parallel via the first conductor layer 125 and the fourth conductor layer 128, and the second electrode layer 112 and the fourth electrode layer 114, which have the same polarity, can be connected in parallel via the second conductor layer 126 and the third conductor layer 127.

[0044] In one embodiment, a first insulating film 104 may be further disposed between the first incision 121a and the first electrode layer 111, and between the second incision 122a and the second electrode layer 112. The first insulating film 104 may also be disposed between the third incision 123a and the third electrode layer 113. The first insulating film 104 can electrically isolate the first conductor layer 125 and the second electrode layer 112, which have different polarities from each other, the second conductor layer 126 and the first electrode layer 111, and the third conductor layer 127 and the third electrode layer 113. The first insulating film 104 may contain the same insulating material as the first insulating layer 101, or it may contain an insulating material different from the first insulating layer 101.

[0045] The printed circuit board 100 may further include a second insulating layer 102 disposed on the upper surface of the first insulating layer 101. The second insulating layer 102 may contain the same insulating material as the first insulating layer 101, or it may contain a different insulating material than the first insulating layer 101.

[0046] In one embodiment, at least a portion of the first wiring layer 120 can be embedded in the second insulating layer 102. The upper surface of the first wiring layer 120 and the upper surface of the second insulating layer 102 may be substantially coplanar, and the lower surface of the first wiring layer 120 and the lower surface of the second insulating layer 102 may be substantially coplanar, but the disclosure is not limited thereto. By embedding the first wiring layer 120 in the second insulating layer 102, the overall thickness of the printed circuit board 100 can be easily reduced.

[0047] The printed circuit board 100 may further include a second wiring layer 130 which includes a fifth metal layer 131 covering the underside of the first electrode layer 111 and a sixth metal layer 132 covering the underside of the second electrode layer 112. The second wiring layer 130 may further include, for example, a seventh metal layer 133 covering the underside of the third electrode layer 113 and an eighth metal layer 134 covering the underside of the fourth electrode layer 114.

[0048] The second wiring layer 130 may have a shape that is symmetrical to the first wiring layer 120 in the thickness direction of the printed circuit board 100. That is, although not shown in the figures, the fifth to seventh metal layers 131, 132, and 133 may each include fourth to sixth incisions. The second wiring layer 130 may include, for example, a fifth conductor layer 135 that penetrates the fifth incision and is connected to the fifth and seventh metal layers 131 and 133, respectively; a sixth conductor layer 136 that penetrates the fourth incision and is connected to the sixth metal layer 132; and a seventh conductor layer 137 that penetrates the sixth incision and is connected to the sixth and eighth metal layers 132 and 134, respectively. The second wiring layer 130 may further include an eighth conductor layer 138 that is connected to the outer surface of the fifth metal layer 131. The fifth conductor layer 135 and the eighth conductor layer 138 can form a third trace connected to the fifth metal layer 131 and the seventh metal layer 133, respectively, and the sixth conductor layer 136 and the seventh conductor layer 137 can form a fourth trace connected to the sixth metal layer 132 and the eighth metal layer 134, respectively.

[0049] Furthermore, a second insulating film 105 can be further arranged between the fourth incision and the first electrode layer 111, and between the fifth incision and the second electrode layer 112. The second insulating film 105 can also be arranged between the sixth incision and the third electrode layer 113. The second insulating film 105 may contain the same insulating material as the first insulating layer 101, or it may contain a different insulating material than the first insulating layer 101.

[0050] The printed circuit board 100 may further include a third insulating layer 103 disposed on the underside of the first insulating layer 101. The third insulating layer 103 may contain the same insulating material as the first insulating layer 101, or it may contain a different insulating material than the first insulating layer 101.

[0051] In one embodiment, at least a portion of the second wiring layer 130 can be embedded in the third insulating layer 103. The upper surface of the second wiring layer 130 and the upper surface of the third insulating layer 103 may be substantially coplanar, and the lower surface of the second wiring layer 130 and the lower surface of the third insulating layer 103 may be substantially coplanar, but the disclosure is not limited thereto. By embedding the second wiring layer 130 in the third insulating layer 103, the overall thickness of the printed circuit board 100 can be easily reduced.

[0052] The following describes in more detail each component included in the printed circuit board 100.

[0053] The first, second, and third insulating layers 101, 102, and 103 can each contain an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may include inorganic fillers, organic fillers, and / or glass fibers (glass fiber, glass cloth, and / or glass fabric) together with such a resin. The insulating material may include photosensitive and / or non-photosensitive materials. For example, as the insulating material for the first, second, and third insulating layers 101, 102, and 103, insulating materials such as PPG (Prepreg) and RCC (Resin Coated Copper) can be used, but are not limited to these, and ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), etc., can also be used. In addition, other polymer materials with excellent rigidity can be used as the insulating material for the first, second, and third insulating layers 101, 102, and 103.

[0054] The first to fourth electrode layers 111, 112, 113, and 114 can each contain a metallic substance. The metallic substance contained in the first to fourth electrode layers 111, 112, 113, and 114 can include, for example, one or more of Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof. The first to fourth electrode layers 111, 112, 113, and 114 can each contain an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but the disclosure is not limited thereto. A sputtering layer can also be formed as a seed layer instead of an electroless plating layer.

[0055] The first to third dielectric layers 115, 116, and 117 may contain dielectric materials different from the insulating material contained in the first insulating layer 101. For example, the first to third dielectric layers 115, 116, and 117 may each contain a mixture of dielectric particles and resin. The first to third dielectric layers 115, 116, and 117 may each have a form in which the dielectric particles are dispersed in the resin, but this disclosure is not limited thereto. The dielectric particles may include one or more of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate particles from the viewpoint of insulating properties and non-dielectric constant. The resin contained in the first to third dielectric layers 115, 116, and 117 may include organic polymer insulating materials, but this disclosure is not limited thereto.

[0056] The first wiring layer 120 and the second wiring layer 130 may each contain a metallic substance. The metallic substance contained in the first wiring layer 120 and the second wiring layer 130 may include, for example, one or more of Cu, Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof. The first wiring layer 120 and the second wiring layer 130 may each include an electroless plating layer (or chemical copper) as a seed layer and an electroplating layer (or electrolytic copper) as a plating layer, but the disclosure is not limited thereto. A sputtering layer may be formed instead of an electroless plating layer as a seed layer. Copper foil may be further included as needed.

[0057] The first wiring layer 120 and the second wiring layer 130 can each perform various functions depending on the design. For example, the first wiring layer 120 and the second wiring layer 130 can each include signal patterns, power patterns, ground patterns, etc., and these patterns can each have various forms such as lines (or traces), planes (or plates), pads (or lands), etc.

[0058] Figures 8a to 8h are cross-sectional and / or top plan views corresponding to Figure 5, illustrating an example of the manufacturing method of the printed circuit board shown in Figures 3 to 5.

[0059] An example of a method for manufacturing a printed circuit board 100 will be described below with reference to Figures 8a to 8h, but this disclosure is not limited thereto.

[0060] Referring to Figure 8a, after preparing the first insulating layer 101, a first metal thin film layer M1 and a second metal thin film layer M2 can be formed on the upper and lower surfaces of the first insulating layer 101, respectively. The metal thin film layers M1 and M2 can be formed, for example, by electroless plating, such as chemical copper plating. If necessary, the metal thin film layers M1 and M2 can also be formed by sputtering.

[0061] Referring to Figure 8b, through-holes TH1 can be formed in the first insulating layer 101 on which metal thin film layers M1 and M2 are formed. The through-holes TH1 can be formed by methods such as mechanical drilling.

[0062] Referring to Figure 8c, a first electrode layer 111 can be formed on the side surface of the through hole TH1 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering, and then the inside of the through hole TH1 can be filled with dielectric material D1.

[0063] Referring to Figure 8d, a portion of the dielectric material D1 can be removed by methods such as drilling to form the first dielectric layer 115. Next, a second electrode layer 112 can be formed on the side surface of the first dielectric layer 115 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering.

[0064] Referring to Figure 8e, the second dielectric layer 116, the third electrode layer 113, and the third dielectric layer 117 can be sequentially formed on the second electrode layer 112 by repeating the steps shown in Figures 8c and 8d. Finally, a fourth electrode layer 114 can be formed in the center of the through hole TH1 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering. This allows a capacitor 110 to be formed inside the through hole TH1.

[0065] Referring to Figure 8f, an etching process can be performed on the edges of the metal thin film layers M1 and M2 and the first to third electrode layers 111, 112, and 113. Referring to Figure 8g, a first insulating film 104 and a second insulating film 105 can be formed on the edges of the first to third electrode layers 111, 112, and 113.

[0066] Referring to Figure 8h, the second insulating layer 102 and the first wiring layer 120 can be formed on the upper surface of the first insulating layer 101, and the third insulating layer 103 and the second wiring layer 130 can be formed on the lower surface of the first insulating layer 101. The method for forming the second insulating layer 102 and the third insulating layer 103 and the first wiring layer 120 and the second wiring layer 130 is not particularly limited. For example, the second insulating layer 102 and the third insulating layer 103 can be formed on the upper and lower surfaces of the first insulating layer 101, respectively. Next, pattern grooves with the same shape as the first wiring layer 120 and the second wiring layer 130 can be formed in the second insulating layer 102 and the third insulating layer 103 by an etching process using a mask. Finally, the pattern grooves can be filled in a plating process to form the first wiring layer 120 and the second wiring layer 130.

[0067] Figure 9 is a schematic top plan view of a printed circuit board according to another embodiment of the present disclosure, Figure 10 is a schematic cross-sectional view showing a cross section along the line IV-IV' in Figure 9, and Figure 11 is a schematic cross-sectional view showing a cross section along the line V-V' in Figure 9.

[0068] Hereinafter, a printed circuit board 200 according to another embodiment of the present disclosure will be described with reference to Figures 9 to 11. For components identical or similar to those of the printed circuit board 100 described in Figures 3 to 7, the same or similar reference numerals will be used, and redundant explanations will be omitted.

[0069] Referring to Figures 9 to 11, the printed circuit board 200 may include a first insulating layer 201 having through holes TH2, a capacitor 210, and a first wiring layer 220.

[0070] In one embodiment of the present disclosure, the through-hole TH2 of the printed circuit board 200 may have a tapered shape such that the width of the upper end is greater than the width of the lower end in cross-section.

[0071] The capacitor 210 may include, for example, a first electrode layer 211 disposed on the side surface of the through hole TH2, a second electrode layer 212 disposed on the side surface of the first electrode layer 211, and a first dielectric layer 215 disposed between the first electrode layer 211 and the second electrode layer 212. The capacitor 210 may further include a third electrode layer 213 disposed on the side surface of the second electrode layer 212, a second dielectric layer 216 disposed between the second electrode layer 212 and the third electrode layer 213, a fourth electrode layer 214 disposed on the side surface of the third electrode layer 213, and a third dielectric layer 217 disposed between the third electrode layer 213 and the fourth electrode layer 214.

[0072] The first wiring layer 220 may include, for example, a first metal layer 221 covering the upper surface of the first electrode layer 211 and a second metal layer 222 covering the upper surface of the second electrode layer 212. The first metal layer 221 and the second metal layer 222 may each include a first incision 221a and a second incision 222a. The first wiring layer 220 may also include a third metal layer 223 covering the upper surface of the third electrode layer 213 and a fourth metal layer 224 covering the upper surface of the fourth electrode layer 214. The third metal layer 223 may have a third incision 223a.

[0073] The first wiring layer 220 may include a first conductor layer 225 that penetrates the second incision 222a and is connected to the first metal layer 221 and the third metal layer 223, respectively; a second conductor layer 226 that penetrates the first incision 221a and is connected to the second metal layer 222; and a third conductor layer 227 that penetrates the third incision 223a and is connected to the second metal layer and the fourth metal layers 222 and 224, respectively. The first wiring layer 220 may further include a fourth conductor layer 228 that is connected to the outer surface of the first metal layer 221.

[0074] The printed circuit board 200 may further include a second wiring layer 230 that covers the lower surface of the through hole TH2. In one embodiment, the first dielectric layer 215 can be continuously arranged on the side surface of the first electrode layer 211 and the upper surface of the second wiring layer 230. The second electrode layer 212 can be continuously arranged on the side surface and bottom surface of the first dielectric layer 215, the second dielectric layer 216 can be continuously arranged on the side surface and bottom surface of the second electrode layer 212, the third electrode layer 213 can be continuously arranged on the side surface and bottom surface of the second dielectric layer 216, and the third dielectric layer 217 can be continuously arranged on the side surface and bottom surface of the third electrode layer 213. The fourth electrode layer 214 may have a tapered shape such that the width of the upper end is greater than the width of the lower end in cross-section.

[0075] The printed circuit board 200 may further include a second insulating layer 202 and a third insulating layer 203, which are disposed on the upper and lower surfaces of the first insulating layer 201, respectively. In one embodiment, at least a portion of the first wiring layer 220 can be embedded in the second insulating layer 202, and at least a portion of the second wiring layer 230 can be embedded in the third insulating layer 203. Furthermore, a first insulating film 204 may be disposed between the first incision 221a and the first electrode layer 211, and between the second incision 222a and the second electrode layer 212. The first insulating film 204 may also be disposed between the third incision 223a and the third electrode layer 213.

[0076] Figures 12a to 12g are cross-sectional and / or top plan views corresponding to Figure 11, illustrating an example of the manufacturing method of the printed circuit board shown in Figures 9 to 11.

[0077] The following describes an example of a method for manufacturing the printed circuit board 200, with reference to Figures 12a to 12g. For components identical or similar to those described in Figures 8a to 8h for the example of the method for manufacturing the printed circuit board 100, the same or similar reference numerals are used, and redundant explanations are omitted.

[0078] Referring to Figure 12a, through-holes TH2 can be formed in the first insulating layer 201 on which the first metal thin film layer M1 and the second metal thin film layer M2 are formed. The through-holes TH2 can be formed by methods such as laser processing. The through-holes TH2 may have a tapered shape.

[0079] Referring to Figure 12b, a first electrode layer 211 can be formed on the side surface of the through hole TH2 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering. At this time, the holes formed in the second metal thin film layer M2 by plating, etc., can be filled. Next, referring to Figure 12c, the inside of the through hole TH2 can be filled with dielectric material D1.

[0080] Referring to Figure 12d, a first dielectric layer 215 can be formed by removing a portion of the dielectric material D1 using methods such as laser processing. Next, a second electrode layer 212 can be formed on the side and bottom surfaces of the first dielectric layer 215 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering.

[0081] Referring to Figure 12e, by repeating the above process, a second dielectric layer 216 can be formed on the sides and bottom of the second electrode layer 212, a third electrode layer 213 can be formed on the sides and bottom of the second dielectric layer 216, and a third dielectric layer 217 can be formed on the sides and bottom of the third electrode layer 213. Finally, a fourth electrode layer 214 can be formed in the center of the through hole TH2 using electroless plating (chemical copper), electrolytic plating (electrolytic copper), and / or sputtering. This allows a capacitor 210 to be formed inside the through hole TH2.

[0082] Referring to Figure 12f, etching can be performed on the edges of the metal thin film layers M1 and M2 and the first to third electrode layers 211, 212, and 213. After etching the second metal thin film layer M2, a second insulating layer 203 can be formed in the etched region to form a second wiring layer 230, but the disclosure is not limited thereto.

[0083] Referring to Figure 12g, a first insulating film 204 can be formed at the edges of the first to third electrode layers 211, 212, and 213. Next, a second insulating layer 202 and a first wiring layer 220 can be formed on the upper surface of the first insulating layer 201. The second insulating layer 202 and the first wiring layer 220 can be formed by etching and plating processes using the mask described above, but this disclosure is not limited thereto.

[0084] This disclosure is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims attached. Therefore, within the scope of the technical idea of ​​this disclosure as described in the claims, various forms of substitution, modification, and alteration are possible by a person with ordinary skill in the art, and these also fall within the scope of this disclosure.

[0085] Furthermore, the expression "one embodiment" does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their implementation in combination with the features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or inconsists with that matter.

[0086] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. The terms "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of Symbols]

[0087] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related parts 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 Battery 1100 Smartphone 1110 Motherboard 1020 Parts 1121 Component Package 1130 Camera Module 1140 speakers 100, 200 through-holes for printed circuit boards TH1, TH2 101, 102, 103, 201, 202, 203 Insulating layer 104, 105, 204 Insulating film; 110, 210 Capacitor 111, 112, 113, 114, 211, 212, 213, 214 metal layer 115, 116, 117, 215, 216, 217 Dielectric layers 120, 130, 220, 230 wiring layers 121, 122, 123, 124, 131, 132, 133, 134, 221, 222, 223, 224 Metal layer 125, 126, 127, 128, 135, 136, 137, 138, 225, 226, 227, 228 Conductor layer

Claims

1. The first insulating layer and A through hole penetrating at least a portion of the first insulating layer, A capacitor comprising a first electrode layer disposed on the side surface of the through hole, a second electrode layer disposed on the side surface of the first electrode layer, and a first dielectric layer disposed between the first electrode layer and the second electrode layer, A first wiring layer including a first metal layer covering the upper surface of the first electrode layer and a second metal layer covering the upper surface of the second electrode layer, A printed circuit board in which the first metal layer and the second metal layer each have a first incision and a second incision, respectively.

2. The first incision is open in the first direction, The printed circuit board according to claim 1, wherein the second incision is open in a second direction different from the first direction.

3. The printed circuit board according to claim 1, wherein the first wiring layer further includes a first conductor layer that penetrates the second incision and is connected to the first metal layer, and a second conductor layer that penetrates the first incision and is connected to the second metal layer.

4. The capacitor further includes a third electrode layer disposed on the side surface of the second electrode layer, a second dielectric layer disposed between the second electrode layer and the third electrode layer, a fourth electrode layer disposed on the side surface of the third electrode layer, and a third dielectric layer disposed between the third electrode layer and the fourth electrode layer. The first wiring layer further includes a third metal layer covering the upper surface of the third electrode layer, and a fourth metal layer covering the upper surface of the fourth electrode layer. The printed circuit board according to claim 1, wherein the third metal layer has a third incision.

5. The first incision and the third incision are each open in the first direction, The printed circuit board according to claim 4, wherein the second incision is open in a second direction different from the first direction.

6. The printed circuit board according to claim 4, wherein the first wiring layer further includes a first conductor layer that penetrates the second incision and is connected to the first metal layer and the third metal layer, respectively; a second conductor layer that penetrates the first incision and is connected to the second metal layer; and a third conductor layer that penetrates the third incision and is connected to the second metal layer and the fourth metal layer, respectively.

7. The printed circuit board according to claim 1, wherein the first wiring layer further includes a fourth conductor layer connected to the outer surface of the first metal layer.

8. The printed circuit board according to claim 1, wherein the first metal layer and the second metal layer each have a ring shape, with a portion of them cut out by the first and second cut portions, respectively.

9. The printed circuit board according to claim 1, wherein an insulating film is further disposed between the first incision and the first electrode layer, and between the second incision and the second electrode layer.

10. The invention further includes a second insulating layer disposed on the upper surface of the first insulating layer, The printed circuit board according to claim 1, wherein at least a portion of the first wiring layer is embedded in the second insulating layer.

11. The printed circuit board according to claim 1, further comprising a second wiring layer including a fifth metal layer covering the lower surface of the first electrode layer and a sixth metal layer covering the lower surface of the second electrode layer.

12. The printed circuit board according to any one of claims 1 to 11, wherein the through hole has a tapered shape such that the width of the upper end is greater than the width of the lower end in cross-section.

13. The wiring further includes a second wiring layer covering the lower surface of the through hole, The printed circuit board according to claim 12, wherein the first dielectric layer is continuously arranged on the side surface of the first electrode layer and on the upper surface of the second wiring layer.

14. A first insulating layer having through holes, A capacitor including a first electrode layer, a first dielectric layer, and a second electrode layer sequentially arranged on the side surface of the through hole, It includes a first metal layer and a second metal layer, which are positioned above the through hole and connected to the first electrode layer and the second electrode layer, respectively. A printed circuit board in which, when viewed from above the through hole, the first metal layer and the second metal layer each have a shape corresponding to the first electrode layer and the second electrode layer, and the first metal layer and the second metal layer each include a first incision and a second incision that are open in different directions from each other.

15. A first conductive layer that penetrates the second incision and is connected to the first metal layer, The printed circuit board according to claim 14, further comprising a second conductive layer that penetrates the first incision and is connected to the second metal layer.

16. The printed circuit board according to claim 14, wherein the capacitor further comprises a third electrode layer disposed on the side surface of the second electrode layer, a second dielectric layer disposed between the second electrode layer and the third electrode layer, a fourth electrode layer disposed on the side surface of the third electrode layer, and a third dielectric layer disposed between the third electrode layer and the fourth electrode layer.

17. Displaced above the through hole, connected to the third electrode layer, and comprising a third metal layer including a third incision, A fourth metal layer is positioned above the through hole and connected to the fourth electrode layer, The present invention further includes a third conductive layer that penetrates the third incision and is connected to the second and fourth metal layers, respectively. The printed circuit board according to claim 16, wherein, when viewed from above the through hole, the third metal layer and the fourth metal layer each have a shape corresponding to the third electrode layer and the fourth electrode layer.

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