Wiring circuit board, and method for manufacturing a wiring circuit board

Abstract

To provide a wiring circuit board that allows for narrower wiring pitches and greater flexibility in wiring design. [Solution] A wiring circuit board comprising a first insulating layer 1, a first conductor layer 2 disposed on the first insulating layer, a second conductor layer 3 disposed on the first conductor layer, and a second insulating layer 4 covering a part of the first conductor layer and having a through hole 4a, wherein the first conductor layer has a first conductor terminal portion, the second conductor layer has a second conductor terminal portion, the second conductor terminal portion is formed on the first conductor terminal portion, the second conductor terminal portion is formed in the through hole, and the surface of the second conductor terminal portion opposite to the first conductor terminal portion is not in contact with the second insulating layer.

Description

[Technical Field]

[0001] The present invention relates to a wired circuit board, a method for manufacturing a wired circuit board, a semiconductor package including the wired circuit board, and an electronic device. [Background Art]

[0002] A wired circuit board on which a semiconductor chip is mounted is manufactured by, for example, laminating and forming conductive parts such as wires and various insulating layers on a base material. The conductive parts and the insulating layers are patterned by, for example, photolithography.

[0003] Along with the increase in the number of connection terminals of semiconductor chips and the reduction of pitch due to the higher performance of semiconductor chips, narrow pitch is also required for pads of wired circuit boards. For example, as a wiring board that can easily cope with narrow pitch of pads, a wiring board has been proposed, which includes an uppermost first wiring layer, a protective insulating layer covering the first wiring layer, and a first through hole penetrating the protective insulating layer in a thickness direction and exposing a part of an upper surface of the first wiring layer, wherein the first through hole is formed by communicating a recess formed on an upper surface of the protective insulating layer with an inner wall surface formed into a curved surface, and an opening formed at a bottom of the recess and having a smaller planar shape than the recess (see Patent Document 1). [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-118067 [Summary of Invention] [Problem to be Solved by the Invention]

[0005] Furthermore, along with the narrow pitch of pads of wired circuit boards, more complicated wiring designs have come to be performed.

[0006] Here, we will explain an example of a conventional wiring circuit board. The wiring circuit board 2000 shown in Figure 8 has a first insulating layer 101, a first conductor layer 102, a second conductor layer 103, and a second insulating layer 104. The first conductor layer 102 is arranged on the first insulating layer 101. The second conductor layer 103 is arranged on the first conductor layer 102. The second insulating layer 104 covers a part of the first conductor layer 102. The second insulating layer 104 has a through hole 104a. The first conductor layer 102 has a first conductor terminal portion 121 and a wiring portion 122. The second conductor layer 103 has a second conductor terminal portion 131. The second conductor terminal portion 131 is formed on the first conductor terminal portion 121. The second conductor terminal portion 131 is formed within the through hole 104a of the second insulating layer 104. The end of the second conductor terminal portion 131 is covered by the second insulating layer 104. The wiring circuit board 2000 shown in Figure 8 further includes a metal core layer 105, a third insulating layer 106, a third conductor layer 107, a fourth insulating layer 108, a fourth conductor layer 109, a fifth insulating layer 110, and an interlayer connection portion 111. The third conductor layer 107 is located on the side of the first insulating layer 101 opposite to the first conductor layer 102. The third insulating layer 106 is located on the side of the third conductor layer 107 opposite to the first insulating layer 101. The metal core layer 105 is located between the first insulating layer 101 and the third insulating layer 106. The metal core layer 105 has through holes. The interlayer connection portion 111 is formed within the through holes of the metal core layer 105. The interlayer connection portion 111 electrically connects the first conductor layer 102 and the third conductor layer 107. The fourth insulating layer 108 covers the third conductor layer 107. The fourth conductor layer 109 is located on the side of the fourth insulating layer 108 opposite to the third conductor layer 107. The fifth insulating layer 110 covers the fourth conductor layer 109. In the case of the wiring circuit board 2000 shown in Figure 8, the ends of the second conductor terminal portion 131, which serve as pads for connecting to terminals (e.g., bumps) of other electronic components (e.g., semiconductor chips), are covered by the second insulating layer 104. Therefore, the area of ​​the second conductor terminal portion 131 used for connection is smaller than the actual area of ​​the second conductor terminal portion 131. In other words, the actual area of ​​the second conductor terminal portion 131 is larger than the area of ​​the second conductor terminal portion 131 used for connection, and the second conductor terminal portion 131 has an extra area at its ends that is not effective for connection. Consequently, the first conductor terminal portion 121 located below the second conductor terminal portion 131 also needs to be made larger. As a result, the degree of freedom in the wiring design of the first conductor layer 102 is reduced.

[0007] The present invention aims to provide a wiring circuit board that enables narrow wiring pitch and allows for greater freedom in wiring design, a method for manufacturing the wiring circuit board, a semiconductor package including the wiring circuit board, and an electronic device. [Means for solving the problem]

[0008] The inventors of the present invention conducted diligent research to solve the above problems and, as a result, found that they could solve the above problems, and completed the present invention having the following gist. In other words, the present invention encompasses the following:

[0009] [1] First insulating layer and A first conductor layer is disposed on the first insulating layer, A second conductor layer is arranged on the first conductor layer, A second insulating layer that covers a portion of the first conductor layer and has through holes, A wiring circuit board having, The first conductor layer has a first conductor terminal portion, The second conductor layer has a second conductor terminal portion, The second conductor terminal portion is formed on the first conductor terminal portion, The second conductor terminal portion is formed within the through hole, The surface of the second conductor terminal portion opposite to the first conductor terminal portion is not in contact with the second insulating layer. Wiring circuit board. [2] The wiring circuit board according to [1], wherein the shape of the through hole is tapered, with the opening area increasing from the opening end of the through hole on the first insulating layer side toward the opening end of the through hole on the opposite side of the first insulating layer side. [3] The wiring circuit board according to [2], wherein the gradient angle in the tapered shape is 11.3° to 63.4°. [4] The wiring circuit board according to any one of [1] to [3], wherein the ratio (T / L) of the thickness (T) of the second conductor layer to the length (L) from the surface of the first conductor layer on the side of the second insulating layer to the surface of the second insulating layer on the side opposite to the first conductor layer is 0.1 or more and 0.9 or less. [5] A third conductor layer disposed on the side of the first insulating layer opposite to the first conductor layer, An interlayer connection portion electrically connects the first conductor layer and the third conductor layer, A wiring circuit board according to any one of [1] to [4], further comprising: [6] The third insulating layer is disposed on the side of the third conductor layer to the first insulating layer, A metal core layer disposed between the first insulating layer and the third insulating layer, It further possesses, The metal core layer has through holes, The interlayer connection portion is formed within the through-hole of the metal core layer. [5] The wiring circuit board described. [7] The wiring circuit board according to any one of [1] to [6], wherein the first conductor terminal portion and the second conductor terminal portion each have a protrusion in approximately the center. [8] A wiring circuit board according to any one of [1] to [7], wherein the first conductor layer has a wiring portion. [9] A semiconductor package including a wiring circuit board as described in any of [1] to [8]. Electronic equipment including the semiconductor package described in

[10] [9]. A method for manufacturing a wiring circuit board, which manufactures the wiring circuit board according to any one of [1] to [8], a step of forming the second insulating layer having a through-hole on the patterned first conductor layer such that a part of the first conductor terminal portion in the first conductor layer is exposed; a step of forming the second conductor layer such that the second conductor terminal portion is formed in the through-hole of the second insulating layer and on the first conductor terminal portion; A method for manufacturing a wiring circuit board, comprising: Effects of the Invention

[0010] According to the present invention, it is possible to provide a wiring circuit board that enables narrow pitch of wiring and increases the degree of freedom in wiring design, a method for manufacturing the wiring circuit board, a semiconductor package including the wiring circuit board, and an electronic device. Brief Description of Drawings

[0011] [Figure 1] FIG. 1A is a schematic diagram of an embodiment of a wiring circuit board. [Figure 2A] FIG. 2A is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 1). [Figure 2B] FIG. 2B is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 2). [Figure 2C] FIG. 2C is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 3). [Figure 2D] FIG. 2D is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 4). [Figure 2E] FIG. 2E is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 5). [Figure 2F] FIG. 2F is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 6). [Figure 2G] FIG. 2G is a schematic diagram for explaining an example of a method for manufacturing a wiring circuit board (Part 7). [Figure 2H] Figure 2H is a schematic diagram illustrating an example of a manufacturing method for a wiring circuit board (Part 8). [Figure 2I] Figure 2I is a schematic diagram illustrating an example of a method for manufacturing a wiring circuit board (Part 9). [Figure 3A] Figure 3A is a schematic diagram of one embodiment of a wiring circuit board. [Figure 3B] Figure 3B is an enlarged view of region X of the wiring circuit board shown in Figure 3A. [Figure 4A] Figure 4A is a schematic diagram illustrating the relationship between the positional accuracy of the photomask and the position of the exposure area and the shape of the second conductor terminal (Part 1). [Figure 4B] Figure 4B is a schematic diagram illustrating the relationship between the positional accuracy of the photomask and the position of the exposure area and the shape of the second conductor terminal (part 2). [Figure 5] Figure 5 is a diagram illustrating the preferred relationship between the thickness (L) of the second insulating layer on the first conductor terminal and the thickness (T) of the second conductor layer. [Figure 6A] Figure 6A is a schematic diagram illustrating the relationship between the positional accuracy of the photomask and the gradient angle (Part 1). [Figure 6B] Figure 6B is a schematic diagram illustrating the relationship between the positional accuracy of the photomask and the gradient angle (part 2). [Figure 6C] Figure 6C is a schematic diagram illustrating the relationship between the positional accuracy of the photomask and the gradient angle (part 3). [Figure 7] Figure 7 is a schematic diagram of another embodiment of a wiring circuit board. [Figure 8] Figure 8 is a schematic diagram of one embodiment of a conventional wiring circuit board. [Modes for carrying out the invention]

[0012] (Wiring circuit board, and method for manufacturing a wiring circuit board) The wiring circuit board of the present invention comprises a first insulating layer, a first conductor layer, a second conductor layer, and a second insulating layer. The first conductor layer is placed on the first insulating layer. The second conductor layer is placed on top of the first conductor layer. The second insulating layer covers a portion of the first conductor layer. The second insulating layer has through holes. The first conductor layer has a first conductor terminal portion. The second conductor layer has a second conductor terminal portion. The second conductor terminal is formed on the first conductor terminal. The second conductor terminal is formed within a through-hole in the second insulating layer. The surface of the second conductor terminal opposite to the first conductor terminal is not in contact with the second insulating layer.

[0013] The wiring circuit board may further include a metal core layer, a third insulating layer, a third conductor layer, a fourth insulating layer, a fourth conductor layer, a fifth insulating layer, interlayer connections, and the like. By having a metal core layer in the wiring circuit board, warping of the wiring circuit board can be reduced. Furthermore, the handling of the wiring circuit board is improved, and the overall thickness of the wiring circuit board can be reduced.

[0014] An example of the wiring circuit board of the present invention will be described below with reference to Figure 1. Figure 1 is a schematic cross-sectional view of an example of a wiring circuit board 1000. The wiring circuit board 1000 has a first insulating layer 1, a first conductor layer 2, a second conductor layer 3, and a second insulating layer 4. The first conductor layer 2 is arranged on the first insulating layer 1. The second conductor layer 3 is arranged on top of the first conductor layer 2. The second insulating layer 4 covers a portion of the first conductor layer 2. The second insulating layer 4 has through holes 4a. The first conductor layer 2 has a first conductor terminal portion 21 and a wiring portion 22. The second conductor layer 3 has a second conductor terminal portion 31. The second conductor terminal portion 31 is formed on the first conductor terminal portion 21. The second conductor terminal portion 31 is formed within the through-hole of the second insulating layer 4. The surface of the second conductor terminal portion 31 opposite to the first conductor terminal portion 21 is not in contact with the second insulating layer 4. The wiring circuit board 1000 further includes a metal core layer 5, a third insulating layer 6, a third conductor layer 7, a fourth insulating layer 8, a fourth conductor layer 9, a fifth insulating layer 10, and an interlayer connection portion 11. The third conductor layer 7 is located on the side of the first insulating layer 1 opposite to the first conductor layer 2. The third insulating layer 6 is located on the side of the third conductor layer 7 that is on the first insulating layer 1 side. The metal core layer 5 is positioned between the first insulating layer 1 and the third insulating layer 6. The metal core layer 5 has through holes. The interlayer connection portion 11 is formed within the through-hole of the metal core layer 5. The interlayer connection section 11 electrically connects the first conductor layer 2 and the third conductor layer 7. The fourth insulating layer 8 covers the third conductor layer 7. The fourth conductor layer 9 is located on the side of the fourth insulating layer 8 opposite to the third conductor layer 7. The fifth insulating layer 10 covers the fourth conductor layer 9.

[0015] In Figure 1, the first conductor terminal portion 21 is in contact with and integrated with the interlayer connection portion 11, but the first conductor terminal portion 21 does not necessarily have to be in contact with the interlayer connection portion 11.

[0016] In the case of the wiring circuit board 2000 shown in Figure 8, the end of the second conductor terminal portion 131 is covered by the second insulating layer 104. In this case, since the end of the second conductor terminal portion 131, which will become a pad to be connected to the terminals (e.g., bumps, etc.) of other electronic components (e.g., semiconductor chips), is covered by the second insulating layer 104, the area of ​​the second conductor terminal portion 131 used for connection becomes smaller than the actual area of ​​the second conductor terminal portion 131. In other words, the actual area of ​​the second conductor terminal portion 131 is larger than the area of ​​the second conductor terminal portion 131 used for connection, and the second conductor terminal portion 131 has an extra area at its end that is not effective for connection. Consequently, the first conductor terminal portion 121 located below the second conductor terminal portion 131 also needs to be made larger. As a result, the degree of freedom in the wiring design of the first conductor layer 102 is reduced. On the other hand, in the case of the wiring circuit board 1000 shown in Figure 1, the surface of the second conductor terminal portion 31 opposite to the first conductor terminal portion 21 is not in contact with the second insulating layer 4. In other words, the end of the second conductor terminal portion 31 is not covered by the second insulating layer 4. In this case, since the end of the second conductor terminal portion 31, which becomes a pad to be connected to the terminals (e.g., bumps, etc.) of other electronic components (e.g., semiconductor chips), is not covered by the second insulating layer 4, the area of ​​the second conductor terminal portion 31 used for connection is the same as the actual area of ​​the second conductor terminal portion 31. In other words, there is no extra area in the second conductor terminal portion 31 that is not effective for connection. Also, since there is no extra area in the second conductor terminal portion 31, the first conductor terminal portion 21 located below the second conductor terminal portion 31 can be the minimum necessary size. As a result, it is possible to narrow the wiring pitch of the first conductor layer 2 and to greatly increase the freedom of the wiring design of the first conductor layer 2.

[0017] In the wiring circuit board shown in Figure 1, the shape of the through-hole in the second insulating layer is tapered (hereinafter sometimes referred to as "reverse tapered shape"), where the opening area widens from the opening end on the first insulating layer side of the through-hole to the opening end on the opposite side of the first insulating layer side. In this case, the shape of the second conductor terminal portion is also reverse tapered, and the second conductor terminal portion is larger on the side that contacts the terminals of other electronic components than on the side that contacts the first conductor terminal portion. Therefore, the second conductor terminal portion can be made larger as needed, while the first conductor terminal portion located below the second conductor terminal portion can be made smaller.

[0018] The first conductor layer preferably has wiring sections. Having wiring sections in the first conductor layer enables high-density wiring. Furthermore, it improves the flatness of the wiring circuit board. Additionally, it increases the mechanical strength of the wiring circuit board. There are no particular restrictions on the wiring density of the wiring section.

[0019] The ratio (T / L) of the thickness (T) of the second conductor layer to the length (L) from the surface of the first conductor layer on the second insulating layer side to the surface of the second insulating layer on the opposite side is not particularly limited, but is preferably 0.1 or more and 0.9 or less. A ratio (T / L) of 0.3 or higher is more preferable, and 0.4 or higher is particularly preferable. Furthermore, a ratio (T / L) of 0.8 or less is more preferable, and 0.6 or less is particularly preferable.

[0020] In a wiring circuit board, the surface of the second conductor terminal opposite to the first conductor terminal is not in contact with the second insulating layer. One way to achieve this is to form the second insulating layer first, and then form the second conductor layer, as explained using Figures 2A to 2I.

[0021] Therefore, the method for manufacturing a wiring circuit board of the present invention includes, for example, a second insulating layer formation step and a second conductor layer formation step in this order. The second insulating layer formation step is a step of forming a second insulating layer having through holes on a patterned first conductor layer such that a portion of the first conductor terminal portion of the first conductor layer is exposed. The second conductor layer formation step is a step of forming a second conductor layer such that the second conductor terminal portion is formed within the through-hole of the second insulating layer and on the first conductor terminal portion. By doing so, it is possible to manufacture a wiring circuit board in which the surface of the second conductor terminal opposite to the first conductor terminal is not in contact with the second insulating layer. Furthermore, by doing so, no residue of the second insulating layer is generated on the surface of the second conductor terminal opposite to the first conductor terminal, thus simplifying the cleaning of that surface.

[0022] An example of a manufacturing method for the wiring circuit board shown in Figure 1 will be explained using Figures 2A to 2I. First, prepare the laminate shown in Figure 2A. The laminate shown in Figure 2A has a metal core layer 5, a third insulating layer 6, a third conductor layer 7, a fourth insulating layer 8, a fourth conductor layer 9, and a fifth insulating layer 10. The laminate shown in Figure 2A can be manufactured, for example, by the following method. First, prepare the metal core layer 5. Next, a third insulating layer 6 having through holes is formed on one surface of the metal core layer 5. The third insulating layer 6 having through holes can be formed, for example, as follows. • Coating and drying of a photosensitive resin composition containing photosensitive polyimide onto the metal core layer 5. • Selective exposure and development of the formed photosensitive polyimide film Next, a patterned third conductor layer 7 is formed on the third insulating layer 6 and within the through-holes. The third conductor layer 7 can be formed, for example, as follows. Formation of a seed layer (not shown) on the third insulating layer 6 • Formation of a photoresist film (not shown) on the seed layer • Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electroplating of the exposed seed layer • Removal of photoresist film and removal of unnecessary seed layer The formed patterned electroplated layer becomes the third conductive layer 7. As a result, a patterned third conductor layer 7 is formed. Note that a portion of the third conductor layer 7 is formed along the inner wall of the through-hole in the third insulating layer 6. Next, a fourth insulating layer 8 having through holes is formed on the third conductor layer 7. The fourth insulating layer 8 covers the patterned third conductor layer 7. The fourth insulating layer 8 can be formed, for example, by coating and drying a photosensitive resin composition containing photosensitive polyimide, and then selectively exposing and developing the formed photosensitive polyimide film. Next, a patterned fourth conductor layer 9 is formed on the fourth insulating layer 8 and within the through-holes. The fourth conductor layer 9 can be formed, for example, as follows. Formation of a seed layer (not shown) on the fourth insulating layer 8 • Formation of a photoresist film (not shown) on the seed layer • Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electroplating of the exposed seed layer • Removal of photoresist film and removal of unnecessary seed layer The formed patterned electroplated layer becomes the fourth conductive layer 9. As a result, a patterned fourth conductor layer 9 is formed. A portion of the fourth conductor layer 9 is electrically connected to the third conductor layer 7. Next, a fifth insulating layer 10 having through holes is formed on the fourth conductor layer 9. The fifth insulating layer 10 covers the patterned fourth conductor layer 9. The fifth insulating layer 10 can be formed, for example, by coating and drying a photosensitive resin composition containing photosensitive polyimide, and then selectively exposing and developing the formed photosensitive polyimide film. Next, a through-hole 5a is formed in the metal core layer 5 from the side opposite to the third insulating layer 6. The through-hole 5a can be formed, for example, as follows. Formation of a photoresist film (not shown) on the surface of the metal core layer 5 opposite to the third insulating layer 6 side. • Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the metal core layer) • Wet etching of the exposed metal core layer 5 (for example, wet etching using ferric chloride) • Removal of photoresist film As a result, through holes 5a are formed in the metal core layer 5. As a result, the laminate shown in Figure 2A is obtained.

[0023] Next, a first insulating layer 1 is formed on the metal core layer 5 and so as to fill the through holes 5a of the metal core layer 5. Then, through holes 1a are formed in the first insulating layer 1 within the through holes 5a of the metal core layer 5 (Figure 2B). This step can be performed, for example, by selective exposure and development of a photosensitive resin film, which will later become the first insulating layer 1, after it has been attached to the metal core layer 5.

[0024] Next, a patterned conductive layer is formed on the first insulating layer 1 and within the through-holes 1a of the first insulating layer 1. The patterned conductive layer can be formed, for example, as follows. Formation of a seed layer (not shown) on the first insulating layer 1 • Formation of a photoresist film (not shown) on the seed layer • Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electroplating of the exposed seed layer • Removal of photoresist film and removal of unnecessary seed layer As a result, a patterned conductor layer is formed. Of the patterned conductor layer, the portion that fills the through-hole 1a of the first insulating layer 1 becomes the interlayer connection portion 11. The other portion of the patterned conductor layer becomes the first conductor layer 2 having the first conductor terminal portion 21 and the wiring portion 22.

[0025] Next, a second insulating layer 4 having through holes 4a is formed on the patterned first conductive layer 2 (Figure 2D). The second insulating layer 4 can be formed, for example, by attaching a photosensitive resin film, which will later become the second insulating layer 4, to the first conductive layer 2, and then selectively exposing and developing the film.

[0026] Next, a photoresist film 15 (negative type dry film resist) is attached to the second insulating layer 4 having through holes 4a (Figure 2E). Before attaching the photoresist film 15, a seed layer (not shown) is formed on the second insulating layer 4. The seed layer is a layer for forming the second conductive layer 3 by electroplating. Next, the photoresist film 15 is selectively exposed such that the photoresist film located in the through-hole 4a of the second insulating layer 4 becomes the unexposed portion 15a, and the other portions become the exposed portion 15b (Figure 2F). At this time, the light is irradiated to the area above the center of the inclined portion of the inner wall of the through-hole 4a of the second insulating layer 4. Next, the unexposed portion 15a is developed to expose the through-hole 4a of the second insulating layer 4 (Figure 2G).

[0027] Next, a second conductor terminal portion 31 is formed in the through-hole 4a of the exposed second insulating layer 4, and a second conductor layer 3 is formed (Figure 2H). The second conductor layer 3 can be formed, for example, by electroplating using a seed layer.

[0028] Next, the exposed portion 15b of the photoresist film is removed (Figure 2I). Unnecessary seed layers (not shown) are also removed. The seed layers can be removed, for example, by soft etching. As a result, the wiring circuit board shown in Figure 2I (Figure 1) is obtained. In this manufacturing method, by forming the second insulating layer and then forming the second conductor layer, it is possible to ensure that the surface of the second conductor terminal opposite to the first conductor terminal is not in contact with the second insulating layer.

[0029] Here, we will explain the shift in exposure position when forming the second conductor terminal. Figure 3A is the wiring circuit board shown in Figure 1. Figure 3B is an enlarged view of region X in Figure 3A. Note that both Figure 3A and Figure 3B are schematic diagrams, and the aspect ratios of the structures differ between Figure 3A and Figure 3B. The method for forming the second conductor terminal in region X of Figure 3A is as described above using Figures 2E to 2I. When selectively exposing a photoresist film, a photomask with a light-shielding section is typically used. The positional accuracy of the photomask is usually a few micrometers. Therefore, if the gradient angle of the reverse taper shape is too small, a portion of the second conductor terminal will protrude from the through-hole in the second insulating layer. This can lead to defects such as short circuits. Here, Figure 4A shows the position of the exposure area 15b and the shape of the second conductor terminal 31 when the positional accuracy of the photomask is high and the photomask is placed in an ideal position. Figure 4B shows the position of the exposure area 15b and the shape of the second conductor terminal 31 when the position of the photomask is deviated from the ideal position. In Figure 4A, the second conductor terminal portion 31 is formed without being misaligned from the through-hole 4a of the second insulating layer 4. In Figure 4B, the end of the second conductor terminal portion 31 is formed up to the upper part of the inner wall of the through-hole 4a of the second insulating layer 4. Furthermore, if the position of the photomask is shifted, a part of the second conductor terminal portion 31 will protrude from the through-hole 4a.

[0030] Based on the above, a suitable gradient angle for the inverse taper shape of the through-hole in the second insulating layer will be described. Figure 5 is an enlarged view of region X in Figure 3A. This figure shows a cross-sectional view where the cross-sectional area of ​​the through-hole in the second insulating layer is maximized. Herein, we define the following: a: Width of the first conductor terminal portion 21 b: Width of the opening on the first insulating layer 1 side of the through hole 4a of the second insulating layer 4. c: Width of the opening of the through hole 4a of the second insulating layer 4 on the side opposite to the first insulating layer 1. f: Width of the inclined portion of the second conductor terminal 31 B: Thickness of the second insulating layer 4 on the first conductor terminal portion 21 D: Thickness of the second conductor terminal portion 31 X: Width of the surface of the second conductor terminal portion 31 opposite to the first conductor terminal portion 21. θ: Gradient angle of the inverse taper shape of the through hole 4a Note that B (thickness of the second insulating layer on the first conductor terminal) is synonymous with the length (L) from the surface of the first conductor layer on the side of the second insulating layer to the surface of the second insulating layer on the opposite side of the first conductor layer. D (thickness of the second conductor terminal) is synonymous with the thickness (T) of the second conductor layer. Furthermore, X needs to be of a certain size to connect the second conductor terminal to the terminals (e.g., bumps) of other electronic components (e.g., semiconductor chips), and there is usually a set value for this. Furthermore, the gradient angle (θ) refers to the angle at which the inner wall of the through-hole in the second insulating layer is inclined with respect to the thickness direction of the second insulating layer. Here, let "E" be the positional accuracy of the photomask during exposure. Therefore, regarding the constraints when manufacturing a wiring circuit board, for example, the following equation can be derived. Formula (1): a≧b+2E Formula (1) is the condition for ensuring that the second conductor terminal does not protrude above the first conductor terminal. Formula (2): X = b + 2f Formula (3): f = D / tan(90° - θ) Formula (4): tan(90°-θ)=2B / (cb) Then, from equations (1) and (2), the following equation (1') can be obtained. Formula (1'): a≧X+2E-2f Then, from equations (1'), (3), and (4), the following equation (1'') can be obtained. Formula (1''):a≧X+2E-(cb)×(D / B) Here, since both X and E are predetermined values, in equation (1'') (X+2E) is a constant, and the term that changes is [-(cb)×(D / B)]. Furthermore, from the standpoint of narrowing the wiring pitch and increasing the freedom of wiring design, it is preferable that "a" be as small as possible. Therefore, it is preferable that "a" be minimized in equation (1''). Therefore, it is preferable that [(cb) × (D / B)] in formula (1'') be large. For this reason, it is preferable that (cb) > 0. That is, it is preferable that c > b. In other words, it is preferable that the through-hole of the second insulating layer has an inverse tapered shape. Furthermore, regarding (D / B), (D / B) > 0 is preferable. Also, considering the connection between the terminals (e.g., bumps) of other electronic components (e.g., semiconductor chips) and the second conductor terminal portion, if (D / B) is close to 1, when the terminals of other electronic components are connected to the second conductor terminal portion, the connection structure between the terminals of other electronic components and the second conductor terminal portion tends to protrude from the through-holes of the second insulating layer, resulting in a higher likelihood of short circuits between adjacent connection structures. On the other hand, if (D / B) is small (e.g., less than 0.1), the second conductor terminal portion is located deep inside the through-holes of the second insulating layer, which may result in insufficient connection between the terminals of other electronic components and the second conductor terminal portion. From these viewpoints, (D / B) [synonymous with (T / L)] is preferably 0.1 or more and 0.9 or less. Furthermore, (D / B) is more preferably 0.3 or more, and particularly preferably 0.4 or more. (D / B) is more preferably 0.8 or less, and particularly preferably 0.6 or less.

[0031] Here, we will explain the preferred range of the gradient angle (θ) for the inverse taper shape. Figure 6A corresponds to an enlarged view of region X in Figure 3A. However, the gradient angle (θ) of the inverse taper shape is different from that in Figure 3A. Figure 6A is a diagram where the allowable positional accuracy (E) of the photomask during exposure is ±10 μm. If E is ±10 μm, then [(cb) / 2] is 20 μm. If "B" is 10 μm, then tan(90°-θ) is 0.5 as follows. tan(90°-θ)=B / [(cb) / 2]=10μm / 20μm=0.5 In that case, (90°-θ)=26.6°, and the slope angle (θ)=63.4°.

[0032] Figure 6B corresponds to an enlarged view of region X in Figure 3A. However, the gradient angle (θ) of the inverse taper shape is different from that in Figure 3A. Figure 6B shows the case where the allowable positional accuracy (E) of the photomask during exposure is ±5 μm. If E is ±5 μm, then [(cb) / 2] is 10 μm. If "B" is 10 μm, then tan(90°-θ) is 1 as follows. tan(90°-θ)=B / [(cb) / 2]=10μm / 10μm=1 In that case, (90°-θ)=45°, and the gradient angle (θ)=45°.

[0033] Figure 6C corresponds to an enlarged view of region X in Figure 3A. However, the gradient angle (θ) of the inverse taper shape is different from that in Figure 3A. Figure 6C is a diagram showing the case where the allowable positional accuracy (E) of the photomask during exposure is ±1.0 μm. If E is ±1.0 μm, then [(cb) / 2] is 2 μm. If "B" is 10 μm, then tan(90°-θ) is 5 as follows. tan(90°-θ)=B / [(cb) / 2]=10μm / 2μm=5 In that case, (90°-θ)=78.7°, and the slope angle (θ)=11.3°.

[0034] From the above explanation using Figures 6A to 6C, (90°-θ) is preferably between 26.6° and 78.7°. That is, the gradient angle (θ) is preferably between 11.3° and 63.4°.

[0035] The first conductor terminal portion of the wiring circuit board may have a protrusion approximately in the center. The second conductor terminal portion of the wiring circuit board may have a protrusion approximately in the center. The wiring circuit board 1000 shown in Figure 7 is an embodiment of a wiring circuit board in which the first conductor terminal portion 21 and the second conductor terminal portion 31 have a protrusion approximately in the center. The other structures are the same as the wiring circuit board 1000 shown in Figure 1. The first conductor terminal portion 21 and the second conductor terminal portion 31 have a protrusion approximately in the center, which improves the reliability of connections with terminals (e.g., solder bumps) of other electronic components (e.g., semiconductor chips). One method for forming a protrusion approximately in the center of the first conductor terminal and the second conductor terminal is to appropriately change the plating conditions when forming the first conductor layer and the second conductor layer by electroplating.

[0036] The following describes the materials and thicknesses of the metal core layer, conductor layers (first conductor layer, second conductor layer, third conductor layer, fourth conductor layer), insulating layers (first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer), and interlayer connections.

[0037] A metal core layer is, for example, an element used to ensure the rigidity of a wiring circuit board. The material of the metal core layer is not particularly limited and includes, for example, Cu, Cu alloys, Al, stainless steel, FeNi alloys such as 42 alloy, and combinations thereof. Among these, Cu, Cu alloys, Al, and stainless steel are preferred from the viewpoint of thermal conductivity and electrical conductivity. The thickness of the metal core layer is not particularly limited, and is, for example, 10 μm or more, preferably 15 μm or more, and also, for example, 500 μm or less, preferably 300 μm or less.

[0038] The material of the insulating layers in a wiring circuit board (e.g., first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer) is not particularly limited, and examples include synthetic resins. Examples of synthetic resins include polyimide resin, epoxy resin, polyethernitrile, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, and polyvinyl chloride. Polyimide resin and epoxy resin are preferred because they have excellent heat resistance, low coefficient of linear expansion, and dielectric strength. The insulating layer may or may not contain fillers, but if it does not contain fillers, it has excellent insulating properties and excellent suppression of electrical leakage. The insulating layer may or may not contain glass fibers. An insulating layer containing glass fibers may be made by impregnating a glass fiber cloth with a synthetic resin, such as a glass epoxy represented by FR4 (Flame Retardant Type 4). The thickness of the insulating layer is not particularly limited, but is, for example, 1 μm or more, preferably 3 μm or more, and also, for example, 35 μm or less, preferably 20 μm or less.

[0039] Examples of materials for the conductor layers (e.g., first conductor layer, second conductor layer, third conductor layer, fourth conductor layer) and interlayer connections in a wiring circuit board include metallic materials. Examples of metallic materials include copper, nickel, gold, solder, and alloys thereof. The thickness of the conductor layer is not particularly limited, and is, for example, 3 μm or more, preferably 5 μm or more, and also, for example, 50 μm or less, preferably 30 μm or less.

[0040] The wiring circuit board may have a seed layer (not shown). The seed layer is used as a conductive layer for electroplating. Examples of materials for the seed layer include copper, chromium, nickel, and alloys thereof.

[0041] (Semiconductor package) The semiconductor package of the present invention includes the wiring circuit board of the present invention. A semiconductor package includes, for example, a semiconductor chip connected to a wiring circuit board. A semiconductor package includes, for example, a sealing resin that encloses a semiconductor chip. Examples of semiconductor packages include FC-CSP (Flip Chip-Chip Scale Package), MIS-BGA (Molded Interconnect Substrate-Ball Grid Array) packages, ETS-BGA (Embedded Trace Substrate-Ball Grid Array) packages, Fan-out WLP (Wafer Level Package), Fan-in WLP, Fan-out PLP (Panel Level Package), Fan-in PLP, FC-BGA (Flip Chip-Ball Grid Array), and high-end 2.5D and 3D packages.

[0042] (electronic equipment) The electronic device of the present invention includes the semiconductor package of the present invention. Examples of electronic devices are not particularly limited and include, for example, ICT infrastructure equipment such as servers, routers, supercomputers, mainframes, and workstations; antennas such as GPS antennas, base station antennas, millimeter-wave antennas, and RFID antennas; communication devices such as mobile phones, smartphones, PHS phones, PDAs, and tablet terminals; digital devices such as personal computers, televisions, digital cameras, digital video cameras, POS terminals, wearable devices, and digital media players; in-vehicle electronic devices such as electronic control systems, in-vehicle communication equipment, car navigation equipment, millimeter-wave radar, and in-vehicle camera modules; semiconductor testing equipment, high-frequency measuring equipment, etc. [Explanation of symbols]

[0043] 1. First insulating layer 1a Through hole 2. First Conductor Layer 3. Second Conductor Layer 4. Second insulating layer 4a through hole 5. Metal core layer 5a through hole 6. Third insulating layer 7. Third conductor layer 8. Fourth insulating layer 9. Fourth Conductor Layer 10. Fifth insulating layer 11 Interlayer connection 15 Photoresist film 15a Unexposed area 15b Exposed area 21 First conductor terminal section 22 Wiring section 31 Second conductor terminal section 101 First insulating layer 102 First Conductor Layer 103 Second Conductor Layer 104 Second insulating layer 104a Through hole 105 Metal core layer 106 Third insulating layer 107 Third Conductor Layer 108 Fourth insulating layer 109 Fourth Conductor Layer 110 Fifth insulating layer 111 Interlayer connection 121 First conductor terminal section 122 Wiring section 131 Second conductor terminal section 1000 Wiring Circuit Boards 2000 Wiring Circuit Board

Claims

1. The first insulating layer, A first conductor layer is disposed on the first insulating layer, A second conductor layer is arranged on the first conductor layer, A second insulating layer that covers a portion of the first conductor layer and has through holes, A wiring circuit board having, The first conductor layer has a first conductor terminal portion, The second conductor layer has a second conductor terminal portion, The second conductor terminal portion is formed on the first conductor terminal portion, The second conductor terminal portion is formed within the through hole, The surface of the second conductor terminal portion opposite to the first conductor terminal portion is not in contact with the second insulating layer. Wiring circuit board.

2. The wiring circuit board according to claim 1, wherein the shape of the through hole is tapered, with the opening area increasing from the opening end of the through hole on the first insulating layer side toward the opening end of the through hole on the opposite side of the first insulating layer side.

3. The wiring circuit board according to claim 2, wherein the gradient angle in the tapered shape is 11.3° to 63.4°.

4. The wiring circuit board according to claim 1, wherein the ratio (T / L) of the thickness (T) of the second conductor layer to the length (L) from the surface of the first conductor layer on the second insulating layer side to the surface of the second insulating layer on the opposite side to the first conductor layer side is 0.1 or more and 0.9 or less.

5. A third conductor layer is disposed on the side of the first insulating layer opposite to the first conductor layer, An interlayer connection portion electrically connects the first conductor layer and the third conductor layer, The wiring circuit board according to claim 1, further comprising the following:

6. The third insulating layer is disposed on the side of the third conductor layer to the first insulating layer, A metal core layer disposed between the first insulating layer and the third insulating layer, It further possesses, The metal core layer has through holes, The interlayer connection portion is formed within the through-hole of the metal core layer. The wiring circuit board according to claim 5.

7. The wiring circuit board according to claim 1, wherein the first conductor terminal portion and the second conductor terminal portion each have a protrusion approximately in the center.

8. The wiring circuit board according to claim 1, wherein the first conductor layer has a wiring portion.

9. A semiconductor package comprising a wiring circuit board according to any one of claims 1 to 8.

10. An electronic device comprising the semiconductor package described in claim 9.

11. A method for manufacturing a wiring circuit board according to any one of claims 1 to 8, A step of forming a second insulating layer having through holes on the patterned first conductor layer such that a portion of the first conductor terminal portion of the first conductor layer is exposed, A step of forming the second conductor layer such that the second conductor terminal portion is formed within the through hole of the second insulating layer and on the first conductor terminal portion, A method for manufacturing a wiring circuit board, including the method described above.

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