LED drive control device and control circuit

Abstract

Even if the control clock pulse fluctuates, variations in the brightness of the LED device can be suppressed. We provide an LED drive control device. [Solution] The system includes a clock setting unit that sets a first number of clock pulses corresponding to the maximum number of bits in the dimming data; a clock generation unit that generates control clock pulses such that the number of clock pulses within a predetermined period is smaller than the first number of clock pulses; a dimming correction unit that corrects the dimming data based on the first and second number of clock pulses and outputs dimming correction data; and a drive unit that supplies drive current to the LED device during a period in which the control clock pulses are counted by the number of clock pulses in the dimming correction data at predetermined intervals.

Description

[Technical Field]

[0001] The present disclosure relates to an LED drive control device that drives an LED (Light-Emitting Diode) device and a control circuit for driving an LED device. [Background Art]

[0002] Recently, LED devices have been used in display units of display devices and backlights of liquid crystal display devices, and the luminance of a plurality of LED devices is individually controlled.

[0003] For example, examples of the above display device include a self-luminous display using an LED device as a display element, and a liquid crystal display device employing local dimming that individually controls an LED backlight.

[0004] As a driving device for conventional LED devices, the PWM (Pulse Width Modulation) type is widely used. In a PWM-type LED drive control device, as disclosed in Patent Document 1, for example, a drive signal (PWM pulse) subjected to pulse width modulation corresponding to the luminance value of a video signal is generated for each one-frame period of the video signal. Applying a voltage to the LED device in accordance with the generated drive signal creates a light-emitting period and a non-light-emitting period for the LED device within one frame period. As a result, the emission luminance of the LED device for each frame can be made to correspond to the luminance value of the video signal. [Prior Art Literature] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Laid-open No. 2013-156326 [Patent Document 2] International Publication No. 2015 / 186171

[0006] [Summary] In conventional PWM-type LED drive control devices, an oscillator is provided, and a PWM clock pulse CLK is generated based on the base clock output from the oscillator circuit. The pulse width of the drive signal is set by counting the PWM clock pulse CLK in order to generate a pulse width modulated drive signal corresponding to the dimming data.

[0007] However, the oscillation frequency of the oscillator circuit fluctuates due to manufacturing variations as well as voltage and temperature fluctuations. Consequently, the frequency of the PWM clock pulse CLK deviates from the expected value, degrading the accuracy of the PWM clock pulse CLK. This manifests as a deviation in the pulse width of the drive signal, resulting in a problem of brightness variations in the LED device.

[0008] Therefore, the object of this disclosure is to provide an LED drive control device and a control circuit that can suppress variations in the brightness of an LED device even when the clock pulse CLK for PWM fluctuates due to fluctuations in the oscillation frequency of the oscillation circuit that forms the basis of the clock pulse CLK for PWM.

[0009] The LED drive control device of this disclosure is an LED drive control device that controls the brightness of an LED device at predetermined intervals based on dimming data, and comprises: an ideal clock setting unit that sets a first number of clock pulses corresponding to the maximum value that the dimming data can take; a clock generation unit that generates a control clock pulse in which the number of clocks within the predetermined period is smaller than the first number of clock pulses; a dimming correction unit that corrects the dimming data based on the first number of clock pulses supplied from the ideal clock setting unit and the second number of clock pulses extracted from the control clock pulse in the predetermined period and outputs dimming correction data; and a drive unit that receives the control clock pulse and the dimming correction data and supplies a drive current to the LED device for a period in which the control clock pulse is counted by the number of clock pulses in the dimming correction data at predetermined intervals.

[0010] The control circuit of the present disclosure is a control circuit for controlling a drive unit of an LED driver that drives a display panel that displays an image using an LED device, and includes: a clock generation unit that receives M-bit dimming data that controls the brightness of the LED device at predetermined intervals and generates a control clock pulse set so that the number of clock pulses within the predetermined interval is less than the maximum number of bits of the M-bit; and a dimming correction unit that corrects the M-bit dimming data based on a first number of clock pulses extracted from the control clock pulses in the predetermined interval and a second number of clock pulses corresponding to the maximum number of bits of the M-bit, and outputs the dimming correction data, and causes the drive unit to supply a drive current to the LED device for a period during which the control clock pulses are counted by the number of clock pulses of the dimming correction data at predetermined intervals. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a block diagram showing the LED drive control device of Example 1. [Figure 2] Figure 2 shows multiple display areas of a display. [Figure 3] Figure 3 shows the relationship between each of the multiple display areas stored in the host device of the LED drive control device in Figure 1 and the dimming data. [Figure 4] Figure 4 is a time chart showing the dimming compensation operation of the LED drive control device shown in Figure 1. [Figure 5] Figure 5 is a time chart showing the drive signal generation operation of the LED drive control device shown in Figure 1. [Figure 6] Figure 6 shows the duty cycle characteristics of the light emission period for dimming data when the frequency of the clock pulse PWMCLK is the ideal frequency and when it is 10% lower than the ideal frequency. [Figure 7] Figure 7 shows the emission period for the set dimming data 128 when the frequency of the clock pulse PWMCLK is the ideal frequency and when it is 10% lower than the ideal frequency. [Figure 8]Figure 8 is a block diagram of the LED drive control device of Example 2. [Figure 9A] Figure 9A is a block diagram showing the clock generation unit of the LED drive control device shown in Figure 8. [Figure 9B] Figure 9B shows the switching operation of the frequency switching section of the clock generation section in Figure 9A. [Figure 10] Figure 10 is a block diagram showing the LED drive control device of Example 3. [Figure 11] Figure 11 is a block diagram showing the LED drive control device of Example 4. [Figure 12] Figure 12 is a block diagram showing the LED drive control device of Example 5. [Figure 13] Figure 13 is a time chart showing a comparison of the operation of SCAN count = 1 and SCAN count = 8 in Example 5. [Figure 14] Figure 14 is a block diagram showing the detailed internal configuration of the dimming compensation unit 24 in Embodiment 5. [Figure 15] Figure 15 is a block diagram showing the detailed internal configuration of the dimming compensation unit 24 in Embodiment 6.

[0012] [Detailed explanation] The LED drive control device of this disclosure will be described in detail below with reference to the drawings.

[0013] [Example 1] FIG. 1 shows the LED drive control apparatus of Embodiment 1. This LED drive control apparatus includes a control circuit 11 and an LED driver 12. The control circuit 11 is connected to the LED driver 12. The LED driver 12, which serves as a driving unit, drives an LED device 13 for a display backlight. As shown in FIG. 2, the LED device 13 includes N LEDs (not shown) corresponding to the plurality of display regions 1 to N of the liquid crystal display panel 14 of the aforementioned display. A host device 15 is connected to the control circuit 11 and the LED driver 12, and a vertical synchronization signal VSYNC of a video signal is supplied from the host device 15 to the control circuit 11 and the LED driver 12. It should be noted that the LED device 13 is not limited to a method in which the LEDs in each display region are individually dimmed by dividing the entire display area into the plurality of display regions 1 to N, and may also employ a method in which the entire display region is controlled to single dimming by one or more LEDs. Furthermore, the LED device 13 may be used not only for a backlight of a liquid crystal display unit but also for a self-luminous display using an LED device as a display element.

[0014] As shown in FIG. 3, the host device 15 has a memory (not shown) that stores dimming data DV indicating dimming values set for each of the plurality of display regions 1 to N of the aforementioned liquid crystal display panel 14. The dimming data DV for each of the display regions 1 to N is read out for each frame period by a read control unit (not shown). Each piece of dimming data DV is an M-bit value representing the light emission period of each LED of the LED device 13 in one frame period, which corresponds to the emission luminance in one frame period. In the first Embodiment, each piece of dimming data DV is an 8-bit value, which is an integer value in a range from 0 to 255. For example, dimming data DV=128 is set for the display region K. In the host device 15, the dimming data DV for each of the display regions 1 to N can be changed and set, for example, for each frame period. Furthermore, the dimming data DV for each of the display regions 1 to N may be read out not for each one frame period but for a plurality of frame periods, for example, for each two frame periods.

[0015] The control circuit 11 is formed of a control IC (integrated circuit) and controls the driving operation of the LED driver 12. The control circuit 11 includes a clock generation unit 21, a clock pulse number extraction unit 22 (clock extraction unit), an ideal clock pulse number setting unit 23 (ideal clock setting unit), and a dimming correction unit 24.

[0016] The clock generation unit 21 generates a clock pulse PWMCLK. The clock generation unit 21 includes an oscillation circuit 25 and a clock adjustment unit 26. The oscillation circuit 25 generates an oscillation signal in accordance with an oscillation command Adj from the outside. The clock adjustment unit 26 receives the oscillation signal from the oscillation circuit 25 and generates the clock pulse PWMCLK based on the oscillation signal. The clock pulse PWMCLK is a pulse signal of a constant period (constant frequency), and in the present embodiment, the ideal number of the clock pulses PWMCLK in one frame period of a video signal is 255, which is the maximum luminance level among luminance levels of 0 to 255 expressed when M bits are 8 bits, for example. The clock adjustment unit 26 may include a frequency divider and be configured to frequency-divide the oscillation signal supplied from the oscillation circuit 25 to generate the clock pulse PWMCLK.

[0017] The clock generation unit 21 is connected to the clock pulse number extraction unit 22 and supplies the clock pulse PWMCLK to the clock pulse number extraction unit 22. The clock generation unit 21 also supplies the clock pulse PWMCLK to the LED driver 12.

[0018] A vertical synchronization signal VSYNC is supplied to the clock pulse number extraction unit 22. The clock pulse number extraction unit 22 counts the clock pulses PWMCLK for each one frame period of the video signal and extracts the number of clock pulses Npa in one frame period. The numerical value of the number of clock pulses Npa is an actual count value of the clock pulses PWMCLK generated in one frame period, and corresponds to an actual frequency that is the actual frequency of the clock pulse PWMCLK.

[0019] The ideal clock pulse count setting unit 23 holds and outputs the ideal clock pulse count Npr, which is the count value of the clock pulse PWMCLK that should be generated in one frame period. The value of the ideal clock pulse count Npr corresponds to a given reference frequency of the clock pulse PWMCLK. In this embodiment, the ideal clock pulse count Npr is a predetermined fixed value of 255. The clock pulse count Npa is made smaller than the ideal clock pulse count Npr. That is, the greater than / less than relationship is Npa <Nprである。

[0020] The dimming correction unit 24 has input terminals A, B, and C, and output terminal Y. The output terminal of the clock pulse count extraction unit 22 is connected to input terminal A, and the clock pulse count Npa is supplied. The output terminal of the ideal clock pulse count setting unit 23 is connected to input terminal B, and the ideal clock pulse count Npr is supplied. Dimming data DV is supplied to input terminal C from the host device 15. The dimming correction unit 24 performs the calculation Y value = A value / B value × C value, where the values ​​of input terminals A, B, C, and output terminal Y are A value, B value, C value, and Y value, respectively. That is, the actual clock pulse count / ideal clock pulse count is multiplied by the dimming data DV as a correction amount CA, and the corrected dimming data ADV (dimming correction data) is output from output terminal Y.

[0021] Next, the operation of the LED drive control device with this configuration will be explained using the time charts in Figures 4 and 5. For the sake of simplicity, only one of the multiple display areas 1 to N described above will be explained, but the same operation will be performed in all of the display areas 1 to N.

[0022] As shown in Figure 4, the vertical synchronization signal VSYNC is a pulse signal representing one frame period. The count value of the clock pulse PWMCLK by the clock pulse count extraction unit 22 increases from 0 to 1 during one frame period. In this embodiment, the clock pulse PWMCLK should ideally be generated 255 times during its one frame period, but in reality, due to the frequency error of the oscillation signal of the oscillation circuit 25, it is assumed to be 10% lower than the ideal frequency of the clock pulse PWMCLK, so it is generated 229 times during one frame period.

[0023] Therefore, the clock pulse count Npa = 229 is output from the clock pulse count extraction unit 22 to the input terminal A of the dimming correction unit 24. The ideal clock pulse count Npr = 255 is output from the ideal clock pulse count setting unit 23 to the input terminal B of the dimming correction unit 24. The correction amount CA for the dimming data DV is the clock pulse count Npa / ideal clock pulse count Npr, so CA = 229 / 255 = 89.8%.

[0024] Here, if the dimming data DV supplied to the input terminal C of the dimming correction unit 24 is 128, then taking into account the correction amount CA = 89.8%, the corrected dimming data ADV becomes ADV = 128 × 89.8% = 115. Note that the correction amount CA is determined from the number of clock pulses Npa and the ideal number of clock pulses Npr, but it can also be determined from the actual frequency and ideal frequency (given reference frequency) of the clock pulse PWMCLK.

[0025] As shown in Figure 5, the corrected dimming data ADV=115 is output from the output terminal Y of the dimming correction unit 24, and this 115 is supplied directly to the LED driver 12. In the LED driver 12, the LED of one of the multiple display areas 1 to N corresponding to the LED of the display area is driven to light up during the light emission period from the start of one frame period until the number of clock pulses PWMCLK reaches 115. This light emission drive is performed with a duty cycle of 115 / 229=50.2%, and a drive current (constant current) flows to the corresponding LED during this light emission drive period. That is, as shown in Figure 4, the light emission drive is performed with a duty cycle of 50.2% for the actual number of clock pulses Npa=229, which is 26 less than the ideal number of clock pulses Npr=255 for one frame period. This makes it possible to suppress the increase in the light emission period to less than 1%. This drive signal generation operation is performed for each of the multiple display areas 1 to N during one frame period.

[0026] Incidentally, as shown by the solid line X in Figure 6, if the frequency of the clock pulse PWMCLK is the ideal frequency and the number of clock pulses in the clock pulse PWMCLK during one frame period is 255, which is the ideal number of clock pulses Npr, then light emission drive with a duty cycle of 0 to 100% is possible for dimming data 0 to 255, thus enabling normal dimming control. However, as shown by the solid line Y in Figure 6, if the actual frequency of the clock pulse PWMCLK is 10% lower than the ideal frequency, light emission drive with a duty cycle of 0 to 100% is possible for dimming data 0 to 229. Furthermore, as shown by the dashed line Y' in Figure 6, for dimming data in the range where the value exceeds 229, it becomes the next frame period, and dimming itself becomes impossible.

[0027] In the LED drive control device that does not include the dimming correction unit 24 shown in Example 1, for example, as shown in Figure 7, if the dimming data DV for one frame period is set to 128, and the number of clock pulses Npa of the clock pulse PWMCLK for one frame period is in a state where the ideal number of clock pulses Npr = 255, then the light emission period will be 50% of the duty cycle for one frame period. On the other hand, if the number of clock pulses Npa of the clock pulse PWMCLK for one frame period is 229, which is 10% lower than the ideal number of clock pulses Npr, then the light emission period will be 55.9% of the duty cycle for one frame period.

[0028] Thus, if the actual frequency of the clock pulse PWMCLK is lower than the ideal frequency, the illumination period for the same dimming data value will increase, making normal dimming control impossible. Conversely, if the actual frequency of the clock pulse PWMCLK is higher than the ideal frequency, the illumination period for the same dimming data value will decrease, similarly making normal dimming control impossible.

[0029] In contrast, according to the LED drive control apparatus including the dimming correction unit 24 as in the present embodiment 1, dimming data DV=128 becomes corrected dimming data ADV=115 in the dimming correction unit 24, so the corrected dimming data ADV=115 is supplied to the LED driver 12. Therefore, in the LED driver 12, for example, as shown in FIG. 5, the LEDs in the corresponding one display region among the plurality of display regions 1 to N are driven to emit light during the light emission period from the start of one frame period until the number of clock pulses Npa of the clock pulse PWMCLK reaches 115. The light emission drive is performed at a duty ratio of 115 / 229=50.2%, and a drive current flows through the corresponding LED during the light emission period. As a result, when the number of clock pulses Npa of the clock pulse PWMCLK in one frame period in FIG. 7 is in a state where the ideal number of clock pulses Npr=255, the light emission period has a duty ratio of 50% which is substantially the same as that in this state, so that the emission luminance corresponding to preset dimming data can be obtained from the LEDs of the LED device 13, and the frequency error (deviation) of the oscillation signal of the oscillation circuit 25 from the ideal frequency (given reference frequency) can be compensated.

[0030] Conversely, this frequency error compensation for the oscillation signal of the oscillation circuit 25 from the ideal frequency means that the frequency accuracy of the oscillation signal of the oscillation circuit 25 does not need to be high. In addition, in the clock generation unit 21, there is no need to perform frequency compensation using a PLL (Phase Locked Loop) circuit or the like for generating the clock pulse PWMCLK. As a result, advantages are obtained in that the manufacturing cost of the clock generation unit 21 including the oscillation circuit 25 can be reduced and the circuit scale can be suppressed.

[0031] [Embodiment 2] FIG. 8 shows the LED drive control apparatus of Embodiment 2. In the LED drive control apparatus shown in FIG. 8, a comparison unit 31 that compares the number of clock pulses Npa with the ideal number of clock pulses Npr is provided, and the frequency of the oscillation signal of the oscillation circuit 25 of the clock generation unit 21 is controlled to decrease in accordance with the comparison result signal AdjDWN from the comparison unit 31, whereby the frequency of the clock pulse PWMCLK is controlled such that Npa<Npr.

[0032] In the clock generation unit 21 of the LED drive control device shown in FIG. 8, as shown in FIG. 9A, the frequency switching unit 32 is provided upstream of the oscillation circuit 25. A plurality of set values Adj=0 to Adj=5 are prepared for the frequency switching unit 32 to set the frequency of the oscillation signal. Any one of the plurality of set values Adj=0 to Adj=5 is selected, and the selected set value is supplied to the oscillation circuit 25. The order of Adj=0 to Adj=5 for the plurality of set values is an order that increases the frequency of the oscillation signal of the oscillation circuit 25, and conversely, the order of Adj=5 to Adj=0 is an order that decreases the frequency of the oscillation signal. That is, when the set value Adj=0 is selected, the frequency of the oscillation signal of the oscillation circuit 25 is the lowest, and when the set value Adj=5 is selected, the frequency of the oscillation signal of the oscillation circuit 25 is the highest.

[0033] FIG. 9A shows a selection state in an initial state. As indicated by a broken line A1 in FIG. 9A, the frequency switching unit 32 outputs the initially set set value Adj=4 (predetermined set value) to the oscillation circuit 25 in accordance with an oscillation command Adj from the outside.

[0034] Further, the comparison result signal AdjDWN from the comparison unit 31 is supplied to the frequency switching unit 32. When the number of clock pulses Npa exceeds the ideal number of clock pulses Npr, that is, when the magnitude relationship satisfies Npa>Npr, the frequency switching unit 32 switches the set value Adj=0 to Adj=5 in response to the comparison result signal AdjDWN, and outputs the switched set value to the oscillation circuit 25. The switching of the set values Adj=0 to Adj=5 is performed so as to lower the oscillation frequency of the oscillation circuit 25. For example, as indicated by a broken line A2 in FIG. 9B, the set value Adj=1 is output to the oscillation circuit 25. As a result, the oscillation frequency of the oscillation circuit 25 is lowered, and the frequency of the clock pulse PWMCLK is also lowered. A decrease in the frequency of the clock pulse PWMCLK reduces the number of clock pulses Npa of the clock pulse PWMCLK in one frame period, so the number of clock pulses Npa obtained from the clock pulse number extraction unit 22 becomes lower than the ideal number of clock pulses Npr. That is, as shown in FIG. 9B, the magnitude relationship returns to Npa<Npr.

[0035] Note that the other components of the LED drive control device in Example 2 are the same as those of the LED drive control device in Example 1 shown in Figure 1, so their explanation is omitted here.

[0036] [Example 3] Figure 10 shows an LED drive control device of Embodiment 3. In the LED drive control device shown in Figure 10, the LED driver 16 includes a control circuit 11 and an LED drive unit 17. A host device 15 is connected to the LED driver 16. The control circuit 11 of the LED drive control device shown in Figure 10 is the same as that of the LED drive control device shown in Figure 1, and the LED drive unit 17 corresponds to the LED driver 12 portion of the LED drive control device shown in Figure 1. The LED driver 16 can be configured as a semiconductor circuit integrating the control circuit 11 and the LED drive unit 17.

[0037] Note that the other configurations and operations of the LED drive control device shown in Figure 10 are the same as those of the LED drive control device of Embodiment 1 shown in Figure 1, so their explanation here is omitted.

[0038] [Example 4] Figure 11 shows an LED drive control device of Embodiment 4. In the LED drive control device shown in Figure 11, the host device 18 includes a control circuit 11, a period generation unit 19, and a dimming data generation unit 20. The host device 18 is connected to the LED driver 12. The control circuit 11 of the LED drive control device shown in Figure 11 is the same as that of the LED drive control device shown in Figure 1. The period generation unit 19 and the dimming data generation unit 20 are included in the host device 15 shown in Figure 1. The period generation unit 19 generates a vertical synchronization signal VSYNC for the video signal. The dimming data generation unit 20 generates dimming data DV indicating the dimming value. The host device 18 can be configured as a device that incorporates the control circuit 11, the period generation unit 19, and the dimming data generation unit 20.

[0039] Note that the other configurations and operations of the LED drive control device shown in Figure 11 are the same as those of the LED drive control device of Embodiment 1 shown in Figure 1, so their explanation is omitted here.

[0040] [Assumptions and challenges for further implementations] In controlling LED backlights, in addition to the brightness variation problem caused by the oscillation frequency deviation mentioned above, there is a known problem of "flicker" specific to PWM dimming. As a method to reduce flicker, for example, a method of devising the lighting order of multiple backlight blocks has been proposed (see, for example, Patent Document 2). Another promising method is "double-speed driving (multi-scan)," which increases the number of times the LED lights up (number of scans) within one frame period. However, if one simply tries to perform double-speed driving by increasing the number of scans (for example, to 8 times), the frequency of the base clock pulse PWMCLK must also be increased by the multiplier (8 times) in order to maintain the resolution of one lighting period. If increasing the clock frequency is not permissible due to the performance constraints of the LED driver or power consumption, it has been difficult to increase the number of scans. Furthermore, when dimming data is divided and controlled by digital calculation, if the "fractions" resulting from the division occur at the same timing every frame, this appears as a visual beat (low-frequency noise), which degrades image quality. Examples 5 and 6 below describe configurations that address these issues.

[0041] [Example 5] Figure 12 is a block diagram showing the LED drive control device of Example 5. In previous examples, brightness correction for frequency fluctuations of the clock pulse PWMCLK has been described, but in Example 5, in order to reduce flicker, the number of times the LED device 13 is lit up and down within one frame period (hereinafter referred to as the number of scans) is variably controlled.

[0042] As shown in Figure 12, the LED drive control device of this embodiment includes a SCAN count setting unit 40 in the host device 18, in addition to the configuration of Embodiment 4 shown in Figure 11. The SCAN count setting unit 40 sets the SCAN count, which is an integer value (e.g., 1, 2, 4, 8, etc.) that defines how many subframes one frame period (e.g., 1 / 60 second) is divided into for driving, and supplies the SCAN count to the period generation unit 19 and the dimming correction unit 24 in the control circuit 11.

[0043] The period generation unit 19 changes the generation period of the vertical synchronization signal VSYNC based on the number of scans supplied from the scan count setting unit 40. Specifically, if the reference frame period is Tf and the number of scans is M, the period generation unit 19 generates the vertical synchronization signal VSYNC with a period of Tf / M and supplies it to the LED driver 12 and the control circuit 11. Conventionally, when increasing the number of scans to perform double-speed driving, it was necessary to increase the frequency of the clock pulse PWMCLK to the number of scans (for example, 8 times) in order to maintain the number of gradations within one subframe. However, due to performance constraints of the LED driver 12 and power consumption, it is sometimes difficult to increase the clock frequency. Therefore, in this embodiment, the frequency of the clock pulse PWMCLK generated by the clock generation unit 21 is not changed (maintained at a low speed), and instead, multiple scans are achieved by compressing the dimming data.

[0044] The dimming correction unit 24 has input terminals A (actual clock pulse count Npa), B (ideal clock pulse count Npr), and C (original dimming data DV), as well as a newly added input terminal D, to which the number of scans from the scan count setting unit 40 is input. The dimming correction unit 24 corrects the dimming data DV according to the input number of scans. Specifically, it uses the value obtained by dividing the original dimming data DV by the number of scans as a reference, and further takes into account the correction due to the deviation in the number of clock pulses (Npa / Npr) to generate the final dimming data ADV. As a result, the LED driver 12 performs multiple lighting operations with shortened lighting times within a short period (subframe), effectively reducing flicker while maintaining the total lighting time.

[0045] Figure 13 is a time chart showing a comparison of operation with SCAN count = 1 and SCAN count = 8 in Example 5. The upper part of the figure shows the case with SCAN count = 1 (normal operation), and the lower part shows the case with SCAN count = 8 (8x speed operation). It is important to note that the frequency of the clock pulse PWMCLK is fixed to, for example, 10MHz in both the upper and lower parts and is not changed.

[0046] First, let's explain the case where the number of scans in the upper section is 1. The vertical synchronization signal VSYNC is generated at the start of a predetermined 1-frame period (for example, 16.7 ms). At this time, it is assumed that the PWM width is set to 128 as a setting value (SETTING) based on the dimming data from the host device 18. Based on this setting value, the LED driver 12 sets the output signal OUT-K to a high level (on state) for a period of 128 counts of the clock pulse PWMCLK from the rising edge of the vertical synchronization signal VSYNC. As a result, one relatively long period of illumination occurs within the 1-frame period.

[0047] Next, we will explain the case where the number of scans in the lower section is 8. Based on the setting of the number of scans = 8, the period generation unit 19 generates a total of 8 vertical synchronization signals VSYNC at a period (subframe period) obtained by dividing the 1 frame period in the upper section into 8 equal parts. In response to this, the dimming correction unit 24 supplies the LED driver 12 with a new setting value (SETTING) of the value obtained by dividing the original PWM width = 128 by the number of scans = 8, i.e., PWM width = 16 (128 / 8).

[0048] The LED driver 12 sets the output signal OUT-K to a high level only for the duration of each subframe period, which is shortened to 1 / 8, when the clock pulse PWMCLK is counted 16 times. Since this operation is repeated 8 times within one frame period, the output signal OUT-K is output intermittently 8 times with a short pulse width. The total illumination time over the entire frame period is the same for the upper case (128 clock cycles) and the lower case (16 clock cycles × 8 times = 128 clock cycles), so the average brightness of the LED device 13 is maintained. On the other hand, because the illumination period is dispersed, the effect of reduced flicker (flickering) is obtained, making it easier for the human eye to perceive. Furthermore, since it is not necessary to increase the PWMCLK frequency (10MHz) to 80MHz or the like to achieve this operation, high image quality can be achieved without increasing the load on the circuit.

[0049] Figure 14 is a block diagram showing the detailed internal configuration of the dimming correction unit 24 in Embodiment 5. The dimming correction unit 24 includes a pulse count counter 41, an actual pulse count holding unit 42, an ideal pulse count holding unit 43, and a calculation circuit 44.

[0050] The pulse counter 41 is supplied with a clock pulse PWMCLK from the clock generation unit 21 and a vertical synchronization signal VSYNC from the period generation unit 19. The pulse counter 41 counts the clock pulse PWMCLK for each period (1 subframe period) of the vertical synchronization signal VSYNC and outputs the count value sequentially.

[0051] The actual pulse count holding unit 42 acquires and holds the count value of the pulse count counter 41 at the timing when the vertical synchronization signal VSYNC is input. This held value is the actual number of clock pulses (actual pulse count Npa) that occurred in the previous period (subframe period), and is supplied to the input terminal A of the arithmetic circuit 44. The ideal pulse count holding unit 43 holds the ideal number of clock pulses that should be present in that period (for example, 255), and supplies that value (ideal pulse count Npr) to the input terminal B of the arithmetic circuit 44.

[0052] The arithmetic circuit 44 receives dimming data DV from the host device 18 as input terminal C, and the number of scans from the scan count setting unit 40 as input terminal D. The arithmetic circuit 44 uses the four input values ​​(A, B, C, D) to perform calculations based on the aforementioned equation (1). Specifically, the arithmetic circuit 44 divides the actual number of pulses (A) by the ideal number of pulses (B) to determine the frequency error correction ratio, and divides the dimming data (C) by the number of scans (D) to determine the length of one lighting period. The result of multiplying these (Y) is then output from the output terminal Out as the corrected dimming data ADV. This makes it possible to correct the variation in oscillation frequency while enabling appropriate pulse width modulation control according to the number of scans.

[0053] [Example 6] Figure 15 is a block diagram showing the detailed internal configuration of the dimming correction unit 24 in Example 6. This configuration is basically the same as that of Example 5 shown in Figure 14, but the arithmetic processing in the arithmetic circuit 44, particularly the handling of the input terminal D which is the divisor, is different. Note that the operation of the pulse count counter 41, the actual pulse count holding unit 42, and the ideal pulse count holding unit 43 is the same as in Example 5, so a detailed explanation is omitted.

[0054] The arithmetic circuit 44 of Embodiment 6 has the function of performing calculations by adding a small perturbation value δ1[n] that fluctuates at predetermined timings (e.g., frames or subframes) to the number of scans input to the input terminal D. In the illustrated example, as indicated by "D+δ1[n]" inside the input terminal D of the arithmetic circuit 44, the perturbation value δ1[n] is added to the number of scans (D), and the result of the addition is used as the divisor. Here, δ1[n] is a random integer or fixed-point number generated by, for example, a random number generator (not shown), and its value changes with the passage of time n.

[0055] The arithmetic circuit 44 performs a process that includes dividing the dimming data (C) by the sum of the number of scans (D) and the perturbation value (δ1[n]), as shown in equation (2) below. Y=(A / B)×(C / (D+δ1[n]))···(2) As a result, the pattern of fractional (remainder) generated by division changes randomly from frame to frame, influenced by the perturbation value δ1[n].

[0056] By slightly varying the divisor in this way, quantization errors caused by rounding down or up fractions are dispersed over time (dithering). As a result, visual noise such as beats and flicker caused by fluctuations in brightness at a specific period are reduced, enabling smoother gradation expression.

[0057] Furthermore, by controlling the added perturbation value δ1[n] to become zero over a long period of time (Σδ1[n]=0), it is possible to remove only the flicker component without changing the average brightness of the entire image. Although not shown in the diagram, a similar configuration may also be used to add a perturbation value to the input terminal B (ideal pulse number Npr) which serves as the divisor.

[0058] This disclosure is not limited to the embodiments described above, and various improvements and design modifications are possible without departing from the spirit of this disclosure.

[0059] [Note] This specification discloses the following configuration:

[0060] (Composition 1) An LED drive control device for controlling the brightness of an LED device at predetermined intervals based on dimming data, comprising: an ideal clock setting unit that sets a first number of clock pulses corresponding to the maximum value that the dimming data can take; a clock generation unit that generates control clock pulses such that the number of clock pulses within the predetermined period is smaller than the first number of clock pulses; a dimming correction unit that corrects the dimming data based on the first number of clock pulses supplied from the ideal clock setting unit and the second number of clock pulses extracted from the control clock pulses in the predetermined period and outputs dimming correction data; and a drive unit that receives the control clock pulses and the dimming correction data and supplies drive current to the LED device for a period in which the control clock pulses are counted by the number of clock pulses in the dimming correction data at predetermined intervals.

[0061] (Configuration 2) The LED drive control device according to claim 1, further comprising a clock extraction unit that receives the control clock pulses generated by the clock generation unit and supplies the number of clock pulses extracted from the control clock pulses in the predetermined period as the second number of clock pulses to the dimming correction unit.

[0062] (Composition 3) The LED drive control device according to configuration 1 or 2, wherein the dimming correction unit calculates a correction amount by dividing the number of second clock pulses by the number of first clock pulses, and calculates the dimming correction data by multiplying the dimming data by the correction amount.

[0063] (Composition 4) The LED drive control device according to any one of configurations 1 to 3, wherein the clock generation unit includes an oscillation circuit that generates a base clock having a frequency based on a predetermined set value, and a clock adjustment unit that generates the control clock pulses based on the generated base clock, and the predetermined set value is set such that the number of second clock pulses is smaller than the number of first clock pulses corresponding to the maximum value that the dimming data can take.

[0064] (Composition 5) The LED drive control device according to configuration 4, wherein the clock generation unit has a plurality of setting values ​​including the predetermined setting value, and is equipped with a switching means for switching between the plurality of setting values, and further comprises a comparison unit for comparing the number of first clock pulses with the number of second clock pulses, and when the number of second clock pulses fluctuates and becomes greater than the number of first clock pulses, the comparison unit supplies a signal to the clock generation unit instructing it to switch to a setting value different from the predetermined setting value among the plurality of setting values ​​that makes the number of second clock pulses less than the number of first clock pulses.

[0065] (Composition 6) The drive unit is an LED drive control device according to any one of configurations 1 to 5, which drives the LED device using a pulse width modulation method.

[0066] (Composition 7) An LED drive control device according to any one of configurations 1 to 6, wherein the predetermined period is set to a frame period corresponding to the rewriting time of one screen of video data in the display device.

[0067] (Composition 8) An LED drive control device according to any one of configurations 1 to 7, comprising a plurality of the LED devices, wherein dimming data corresponding to each of the plurality of LED devices is supplied, the dimming correction unit outputs dimming correction data for each of the dimming data corresponding to each of the plurality of LED devices, and the drive unit supplies current to each of the plurality of LED devices for a period during which the control clock pulses are counted for the number of clock pulses of the dimming correction data corresponding to each of the plurality of LED devices at a predetermined period.

[0068] (Composition 9) The LED drive control device according to configuration 8, which drives a display panel that includes the aforementioned plurality of LED devices as light-emitting units for displaying images.

[0069] (Composition 10) An LED drive control device according to any one of configurations 1 to 9, comprising: a scan count setting unit that sets a scan count that defines the number of times the image is rewritten within a predetermined period; and a synchronization signal generation unit that generates multiple vertical synchronization signals within the predetermined period based on the scan count, wherein the dimming correction unit corrects the dimming data based on the first clock pulse count, the second clock pulse count, and the scan count.

[0070] (Composition 11) The LED drive control device according to configuration 10, wherein the dimming correction unit calculates a correction amount by multiplying the value obtained by dividing the second clock pulse number by the first clock pulse number by the reciprocal of the scan number, and calculates the dimming correction data by multiplying the dimming data by the correction amount.

[0071] (Composition 12) The LED drive control device according to configuration 10 or 11, wherein the dimming correction unit adds a perturbation value that changes at predetermined timings to the divisor used in the correction calculation of the dimming data.

[0072] (Composition 13) The LED drive control device according to configuration 12, wherein the perturbation value is a random value and is set such that the sum of the perturbation values ​​over multiple cycles of the vertical synchronization signal is zero.

[0073] (Composition 14) A control circuit for controlling the drive unit of an LED driver that drives a panel equipped with an LED device whose brightness is controlled at predetermined intervals based on dimming data, comprising: an ideal clock setting unit that sets a first number of clock pulses corresponding to the maximum value that the dimming data can take; a clock generation unit that generates control clock pulses such that the number of clock pulses within the predetermined period is smaller than the first number of clock pulses; and a dimming correction unit that corrects the dimming data based on the first number of clock pulses supplied from the ideal clock setting unit and the second number of clock pulses extracted from the control clock pulses in the predetermined period and outputs dimming correction data, wherein the control circuit causes the drive unit to supply drive current to the LED device for a period during which the control clock pulses are counted by the number of clock pulses in the dimming correction data at predetermined intervals.

[0074] This application claims domestic priority based on the Japanese patent application "Title of Prior Application" (Patent Application No. 2025-030187) filed on February 27, 2025. The entire description, claims, and drawings of said patent application are incorporated herein by reference. [Explanation of Symbols]

[0075] 11 Control circuit, 12, 16 LED driver, 13 LED device, 14 LCD display panel, 15, 18 Host device, 17 LED drive unit, 19 Period generation unit, 20 Dimming data generation unit, 21 Clock generation unit, 22 Clock pulse count extraction unit, 23 Ideal clock pulse count setting unit, 24 Dimming correction unit, 25 Oscillation circuit, 26 Clock adjustment unit, 31 Comparison unit, 32 Frequency switching unit, 40 SCAN count setting unit, 41 Pulse count counter, 42 Actual pulse count holding unit, 43 Ideal pulse count holding unit, 44 Arithmetic circuit, 1~N Display area.

Claims

1. An LED drive control device that controls the brightness of an LED device at predetermined intervals based on dimming data, An ideal clock setting unit sets a first number of clock pulses corresponding to the maximum value that the dimming data can take, A clock generation unit that generates control clock pulses such that the number of clock pulses within a predetermined period is smaller than the number of first clock pulses, A dimming correction unit corrects the dimming data based on the number of first clock pulses supplied from the ideal clock setting unit and the number of second clock pulses extracted from the control clock pulses in the predetermined period, and outputs dimming correction data. An LED drive control device comprising: a drive unit that receives the control clock pulse and the dimming correction data, and supplies drive current to the LED device for a period in which the control clock pulse is counted by the number of clock pulses of the dimming correction data at predetermined intervals.

2. The LED drive control device according to claim 1, further comprising a clock extraction unit that receives the control clock pulses generated by the clock generation unit and supplies the number of clock pulses extracted from the control clock pulses in the predetermined period as the second number of clock pulses to the dimming correction unit.

3. The LED drive control device according to claim 1, wherein the dimming correction unit calculates the dimming correction data by dividing the number of second clock pulses by the number of first clock pulses to obtain a correction amount, and multiplying the dimming data by the correction amount.

4. The clock generation unit includes an oscillation circuit that generates a base clock having a frequency based on a predetermined set value, and a clock adjustment unit that generates the control clock pulse based on the generated base clock. The LED drive control device according to claim 1, wherein the predetermined setting value is set such that the second number of clock pulses is smaller than the first number of clock pulses corresponding to the maximum value that the dimming data can take.

5. The clock generation unit has a plurality of setting values ​​including the predetermined setting value, and is equipped with switching means for switching between the plurality of setting values, The system further includes a comparison unit that compares the number of first clock pulses with the number of second clock pulses, The LED drive control device according to claim 4, wherein the comparison unit supplies a signal to the clock generation unit to instruct it to switch to a setting value different from the predetermined setting value among the plurality of setting values ​​that results in the second clock pulse number being smaller than the first clock pulse number when the second clock pulse number fluctuates and becomes larger than the first clock pulse number.

6. The LED drive control device according to claim 1, wherein the drive unit drives the LED device using a pulse width modulation method.

7. The LED drive control device according to any one of claims 1 to 6, wherein the predetermined period is one frame period corresponding to the rewriting time of one screen of video data in the display device.

8. The system is equipped with multiple LED devices, and each of the multiple LED devices is supplied with the dimming data corresponding to it. The dimming correction unit outputs dimming correction data for each of the dimming data corresponding to each of the plurality of LED devices. The LED drive control device according to claim 1, wherein the drive unit supplies current to each of the plurality of LED devices for a period during which the control clock pulse is counted for the number of clock pulses of the dimming correction data corresponding to each of the plurality of LED devices at a predetermined period.

9. The LED drive control device according to claim 8, which drives a display panel that includes the plurality of LED devices as light-emitting units for displaying images.

10. A scan count setting unit sets a scan count that defines the number of times the image is rewritten within the predetermined period, A synchronization signal generation unit that generates multiple vertical synchronization signals within a predetermined period based on the number of scans, Equipped with, The LED drive control device according to claim 1, wherein the dimming correction unit corrects the dimming data based on the first number of clock pulses, the second number of clock pulses, and the scan count.

11. The LED drive control device according to claim 10, wherein the dimming correction unit calculates a correction amount by multiplying the value obtained by dividing the second clock pulse number by the first clock pulse number by the reciprocal of the scan number, and calculates the dimming correction data by multiplying the dimming data by the correction amount.

12. The LED drive control device according to claim 10 or 11, wherein the dimming correction unit adds a perturbation value that changes at predetermined timings to the divisor used in the correction calculation of the dimming data.

13. The LED drive control device according to claim 12, wherein the perturbation value is a random value and is set such that the sum of the perturbation values ​​over multiple cycles of the vertical synchronization signal is zero.

14. A control circuit for controlling the drive unit of an LED driver that drives a panel equipped with an LED device whose brightness is controlled at predetermined intervals based on dimming data, An ideal clock setting unit sets a first number of clock pulses corresponding to the maximum value that the dimming data can take, A clock generation unit that generates control clock pulses such that the number of clock pulses within a predetermined period is smaller than the number of first clock pulses, The system includes a dimming correction unit that corrects the dimming data based on the number of first clock pulses supplied from the ideal clock setting unit and the number of second clock pulses extracted from the control clock pulses in a predetermined period, and outputs dimming correction data. A control circuit that causes the drive unit to supply drive current to the LED device for a period of time during which the control clock pulse is counted for the number of clock pulses of the dimming correction data at predetermined intervals.

Images