Method for manufacturing a packaging substrate and a packaging substrate using the same.

Abstract

The present invention provides a method for manufacturing a packaging substrate that drastically reduces warping even after the formation of an insulating layer, thereby greatly improving the yield and quality of the packaging substrate, and a packaging substrate using the same. [Solution] The method includes the steps of: generating a glass structure consisting of core vias 23, cavity portions 28, or all of these on a glass core 21 including a first surface 213 and a second surface 214 facing each other; forming an upper insulating layer 253 on the first surface or the second surface using an insulating film; and forming an upper layer 26 on top of the upper insulating layer, including an upper distribution layer 25 and an upper connection layer 27. The step of forming the upper insulating layer includes a primary curing step of laminating a first insulating film on the first surface and then curing it, and a secondary curing step of laminating a second insulating film on the primary cured first insulating film and then curing it. Through this, warping can be improved and detachment of electronic elements can be prevented.

Description

[Technical Field]

[0001] This embodiment relates to a method for manufacturing a semiconductor packaging substrate, specifically a method for manufacturing a packaging substrate including a glass core and an insulating layer, and a technology relating to a packaging substrate using the same. [Background technology]

[0002] In the manufacturing of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers into a state where they can be used in actual products is called the back-end process (BE), and the packaging process is included in this back-end process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as line widths in the nanoscale (below the micron), cells exceeding 10 million, high-speed operation, and significant heat dissipation, but relatively speaking, the technology to perfectly package these is not yet supported. Therefore, the electrical performance of a semiconductor is sometimes determined more by the packaging technology and the resulting electrical connections than by the performance of the semiconductor technology itself.

[0004] While ceramics or resins are commonly used as packaging substrate materials, recent research has focused on applying silicon and glass to high-end packaging substrates. In particular, packaging substrates with a cavity structure have been developed using glass cores.

[0005] Relevant prior art includes U.S. Patent Publication US2022 / 0293560A1 and Korean Patent Publication No. 10-2018-0142742. [Overview of the project] [Problems that the invention aims to solve]

[0006] The objective of this embodiment is to provide a method for manufacturing a packaging substrate that can improve the warping phenomenon that can occur in a packaging substrate using a glass core and an insulating film due to differences in the degree of thermal expansion and the resulting stress, and to provide a packaging substrate using this method.

[0007] Furthermore, the purpose of this embodiment is to provide a method for manufacturing a packaging substrate that can prevent the separation or detachment of electronic elements arranged in the cavity of a glass core, and a packaging substrate using the same. [Means for solving the problem]

[0008] To achieve the above objective, a method for manufacturing a packaging substrate according to one embodiment includes the steps of: generating a glass structure comprising core vias, cavity portions, or all of these in a glass core including a first surface and a second surface facing each other; forming an insulating layer on the first surface or the second surface using an insulating film; and forming an upper layer including an upper distribution layer and an upper connection layer on top of the insulating layer.

[0009] The step of forming the insulating layer may include a primary curing step of laminating the first insulating film on the first surface and then curing it, and a secondary curing step of laminating the second insulating film on the primary cured first insulating film and then curing it.

[0010] The cavity portion is recessed by opening in the direction of the first or second surface of the glass core, or has a space through the first and second surfaces in which an electronic element is arranged.

[0011] The method for manufacturing the packaging substrate may further include the step of arranging electronic elements in the cavity portion.

[0012] In one embodiment, the step of arranging the electronic elements may be performed between the step of generating the glass structure and the step of generating the insulating layer.

[0013] In one embodiment, the first insulating film may be laminated over the entire first surface or in the cavity portion in which the electronic elements are arranged.

[0014] In one embodiment, when the first insulating film is laminated to the cavity portion, the first insulating film may be cut based on the shape and size of the cavity portion.

[0015] In one embodiment, the thickness of the first insulating film and the thickness of the second insulating film may be different from each other.

[0016] In one embodiment, a reduced-pressure lamination method may be applied to the primary curing step and the secondary curing step, respectively. The pressure and temperature applied in the secondary curing step may be higher than the pressure and temperature applied in the primary curing step.

[0017] The method for manufacturing the packaging substrate may further include a final curing step after the secondary curing step.

[0018] The aforementioned final curing step is a step in which the first insulating film and the second insulating film are further cured to achieve final curing.

[0019] In one embodiment, the electronic element may include a passive element or an active element.

[0020] On the other hand, in order to achieve the above objective, a packaging substrate according to one embodiment includes a core layer and an upper layer located on the core layer, the core layer includes a glass core including a first surface and a second surface facing each other, a number of core vias and cavity portions penetrating in the thickness direction of the glass core, an electrically conductive layer disposed on the surface of the glass core, electronic elements arranged in the cavity portions, and an insulating layer filling the core vias and the cavity portions.

[0021] The cavity portion is recessed with an opening toward the first surface or the second surface of the glass core, or has a space penetrating through the first surface and the second surface, and the insulating layer may include a first insulating layer obtained by laminating and curing a first insulating film on the first surface, and a second insulating layer obtained by laminating and curing a second insulating film on the first insulating layer.

[0022] In one embodiment, the first insulating layer may be formed on the entire first surface or in the cavity portion where the electronic elements are arranged.

[0023] In one embodiment, the insulating layer may further include a third insulating layer obtained by laminating and curing a third insulating film on the second surface. The third insulating layer may be formed embedded in the direction toward the first surface on the second surface.

[0024] In one embodiment, a first boundary where the first insulating film and the second insulating film are in contact may be formed between the first insulating layer and the second insulating layer.

[0025] In one embodiment, a second boundary where the first insulating film and the third insulating film are in contact may be formed between the first insulating layer and the third insulating layer.

[0026] The second boundary may be formed inside the core via and the cavity portion.

[0027] In one embodiment, the color of the first insulating layer and the color of the third insulating layer may be distinguished from each other. That is, they may be different from each other.

[0028] In one embodiment, the thickness of the first insulating layer and the thickness of the second insulating layer may be different from each other.

[0029] In one embodiment, the glass core may be a rectangular sheet glass.

[0030] In one embodiment, the thickness of the glass core may be 300 μm to 1,500 μm.

[0031] In one embodiment, the height difference between the corner of the packaging substrate and the floor on which the packaging substrate is placed may be 12 mm or less.

[0032] The electronic element may include passive or active elements. [Effects of the Invention]

[0033] The manufacturing method for packaging substrates described in this example, and the packaging substrates using this method, exhibit a rapid reduction in warping even after the formation of the insulating layer, thereby significantly improving the yield and quality of the packaging substrates.

[0034] Furthermore, by improving the warping phenomenon, it is possible to prevent the separation or detachment of electronic elements located in the cavity of the glass core. [Brief explanation of the drawing]

[0035] [Figure 1] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in a real-world example. [Figure 2] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate related to other concrete examples. [Figure 3] (a) and (b) are conceptual diagrams illustrating a portion of a packaging substrate related to an actual example in cross-section. [Figure 4] This flowchart shows a cross-sectional view of the process of generating the core distribution layer, which is part of the manufacturing process of a packaging substrate related to a concrete example. [Figure 5] This flowchart shows a cross-sectional view of the process of generating the insulating layer in the manufacturing process of a packaging substrate, as illustrated in the example. [Figure 6] This diagram illustrates the warping phenomenon that occurs in the packaging substrate when an insulating layer is formed in the conventional manner. [Figure 7]This is a cross-section illustrating the concept of a manufacturing method for a packaging substrate related to a concrete example. [Figure 8] This flowchart illustrates the manufacturing process of a packaging substrate in a cross-sectional view, where P1 represents the first pre-cure step, P2 represents the second pre-cure step, L1 represents the first predicted boundary line, and L2 represents the second predicted boundary line. [Figure 9A] Figure 9A is a photograph showing the boundaries of the insulating layers produced by the manufacturing of a packaging substrate according to an embodiment example. In Figure 9A, a sample is applied in which an insulating film with a thickness of 70 μm is used as the first insulating film, and an insulating film with a thickness of 60 μm and an insulating film with a thickness of 80 μm are used as the second and third insulating films, respectively. [Figure 9B] Figure 9B is a photograph showing the boundaries of the insulating layers produced by the manufacturing of a packaging substrate according to an embodiment example. From left to right, the samples are an insulating film with a thickness of 60 μm, an insulating film with a thickness of 70 μm, and an insulating film with a thickness of 80 μm applied as the second insulating film. [Figure 10] This photograph illustrates the warping (warpage) of a packaging substrate produced during the manufacturing process of a packaging substrate as described in the example. [Figure 11] This is a flowchart illustrating the manufacturing process of packaging substrates related to other concrete examples. [Figure 12] This is a conceptual diagram illustrating the structure of a packaging substrate in cross-section, relating to other concrete examples. [Modes for carrying out the invention]

[0036] The embodiments are described below in detail with reference to the accompanying drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the embodiments belong. However, the embodiments can be realized in a variety of different forms and are not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0037] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0038] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0040] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0041] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0042] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0043] In the process of developing a semiconductor device that is more integrated, thinner, and capable of high performance, the inventors recognized that not only the element itself but also the packaging is a crucial factor in improving performance. While researching this, they discovered that, unlike conventional methods that applied two or more core layers as a packaging substrate on a motherboard, such as interposers and organic substrates, they could apply a single layer of glass core and a cavity structure to make the packaging substrate even thinner and improve the electrical characteristics of the semiconductor device. This led to the completion of their invention.

[0044] The formation process of RDL involves the curing of an insulating layer such as ABF (Ajinomoto Build-up Film), but sometimes the packaging substrate would warp during this process. The inventors determined that this phenomenon was caused by the difference in the degree of thermal expansion (coefficient of thermal expansion) between the internal components of the substrate and the ABF, resulting in thermal stress, and recognized the need to improve the warping phenomenon.

[0045] As a result of further research, we confirmed that by performing pre-curing of the insulating film multiple times instead of once when creating an insulating layer in the core via and cavity structure, we can improve the phenomenon of warping of the glass core due to differences in CTE (Coefficient of Thermal Expansion) between the insulating film and the glass core, and thus completed the invention.

[0046] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in an example; Figure 2 shows a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in another example; and Figures 3(a) and 3(b) are conceptual diagrams illustrating a cross-sectional portion of a packaging substrate in an example, respectively.

[0047] To achieve the above objective, the semiconductor device 100 according to the embodiment includes a semiconductor element section 30 on which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to the semiconductor elements 32, 34, and 36 and connects them to each other.

[0048] A packaging substrate 20 according to one example includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity portion 28 in which an electronic element 40 can be positioned.

[0049] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connecting electrodes or the like. Specifically, the semiconductor element portion 30 may be, for example, a computing element such as a CPU or GPU (first element: 32, second element: 34), a memory element such as a memory chip (third element: 36), etc., but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0050] The motherboard 10 may be a printed circuit board, a printed wiring board, or the like.

[0051] The packaging substrate 20 may further include a lower layer 38 that is selectively located below the core layer.

[0052] The core layer 22 may include: a glass core 21 comprising a first region 221 having a first thickness 211, and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first region; a number of core vias 23 penetrating the glass core 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23, which electrically connects a first surface 213 of the glass core 21 and a second surface 214 facing the first surface via the core vias 23. That is, the core layer 22 may refer to a glass structure comprising a glass core 21 comprising a first surface 213 and a second surface 214 facing each other, core vias 23, a cavity 28, or all of these.

[0053] The second region 222 of the core layer 22 can function as a cavity structure.

[0054] Within the same area, the glass core 21 has a first surface 213 and a second surface 214 that face each other, and since these two surfaces are generally parallel to each other, the glass core 21 has a constant thickness throughout.

[0055] The internal space 281 formed by the difference in thickness between the first area 221 and the second area 222 serves to accommodate part or all of the electronic element 40.

[0056] The glass core 21 may include core vias 23 that penetrate the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222 and may be formed with an intended pitch and pattern.

[0057] Conventionally, packaging substrates for semiconductor devices have been applied in a form where silicon substrates and organic substrates are stacked. In the case of silicon substrates, due to their semiconductor properties, there is a risk of parasitic elements occurring when applied to high-speed circuits, which is a disadvantage as it results in relatively large power losses. In the case of organic substrates, a large area is required to form even more complex distribution patterns, which does not fit with the trend towards manufacturing ultra-miniaturized electronic devices. In order to form complex distribution patterns within a given size, it is practically necessary to miniaturize the pattern, but due to the properties of materials such as polymers used in organic substrates, there are practical limitations to the miniaturization of the pattern.

[0058] In this concrete example, a glass core 21 is used as a support for the core layer 22 to solve these problems. Furthermore, by applying core vias 23 formed through the glass core 21 together with the glass core 21, the length of the electrical current is further shortened, resulting in a more compact packaging substrate 20 with faster response and lower loss characteristics.

[0059] The glass core 21 is preferably made of plate glass used in semiconductors, and may, but is not limited to, borosilicate plate glass or alkali-free plate glass.

[0060] The core via 23 penetrates the glass core 21. The core via 23 may be formed by removing a predetermined area of ​​the glass core 21, specifically by etching a plate of glass by physical and / or chemical methods.

[0061] Specifically, the formation of the core via 23 may involve forming defects (grooves) on the surface of the glass core using a laser or the like, followed by chemical etching, laser etching, or other similar methods, but is not limited to these.

[0062] The core vias 23 may be positioned in a number of 100 to 3,000, 100 to 2,500, or 225 to 1,024 locations per unit area (1 cm × 1 cm) of the glass core 21. When these pitch conditions are met, the formation of electrically conductive layers and the performance of the packaging substrate can be improved.

[0063] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core via through vias, and a core insulating layer 223 surrounding the core distribution pattern. The core layer 22, having an electrically conductive layer formed inside it via core vias, acts as an electrical passage across the glass core 21, connecting the upper and lower parts of the glass core over a relatively short distance, thereby enabling faster electrical signal transmission and lower loss characteristics. The electrically conductive layer may, for example, be a copper plating layer, but is not limited thereto.

[0064] The cavity portion 28 is not limited in shape, and can be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, or any other shape.

[0065] The electronic element 40 may have a shape that is generally cylindrical, rectangular, or polygonal.

[0066] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the electronic element 40 and the core distribution layer 24, and an insulating layer surrounding the cavity distribution pattern.

[0067] On the other hand, the cavity portion according to other embodiments may be embodied in a form that penetrates the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the core via 23 formation process, and the area and shape that penetrate the glass core 21 may differ from those of the core via 23.

[0068] In such an embodiment, an insulating layer may be formed after the electronic elements 40 are arranged in the cavity. That is, an insulating layer may also be formed in the cavity through the process by which the core insulating layer 223 described above is formed.

[0069] The core distribution pattern 241 may be formed in such a way that it can be electrically connected to the electronic element 40.

[0070] The electronic element 40 may include an active element such as a transistor, or a power transfer element such as a multilayer ceramic capacitor (MLCC), i.e., a passive element.

[0071] When an element such as a transistor, which plays a role in converting electrical signals between the motherboard and the semiconductor element section to an appropriate level, is used as the electronic element 40, the transistor and the like are applied to the passages of the packaging substrate 20, which makes it possible to provide a semiconductor device 100 that is more efficient and has a higher speed.

[0072] Furthermore, power transfer elements such as multilayer ceramic capacitors (MLCCs) play a crucial role in the performance of semiconductor devices. These passive power transfer elements are typically applied in quantities of at least 200 to a semiconductor device, and their performance is influenced by the characteristics of the electrical conductive layer surrounding the element. In one example, non-circular core vias can be applied where a low-resistance electrical conductive layer is required, such as in these power transfer elements.

[0073] On the other hand, the electronic element 40 may be applied by individually inserting passive elements such as capacitors, or a group of elements containing numerous passive elements embedded between insulating layers (cavity insulating layers) may be formed so that the electrodes are exposed and then inserted into the electronic element. In the latter case, the workability of manufacturing the packaging substrate can be further streamlined and it is even more advantageous to ensure that the insulating layer is positioned sufficiently and with high reliability in the complex spaces between elements.

[0074] The glass core 21 plays an intermediate or mediating role in connecting the semiconductor element section 30 and the motherboard 10 to its upper and lower parts, respectively, and the core via 23 acts as a passage for transmitting these electrical signals, thereby ensuring smooth signal transmission.

[0075] The upper layer 26 is located on the first surface 213.

[0076] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the uppermost surface of the upper layer 26 may be protected by a cover layer 60 having openings formed therein that allow the connection electrodes of the semiconductor element to make direct contact.

[0077] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface and an upper distribution pattern 251 embedded in the upper insulating layer 253, which is an electrically conductive layer having a predetermined pattern and to which the core distribution layer 24 and at least a portion thereof are electrically connected.

[0078] The upper insulating layer 253 can be any material that is applied as an insulating layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler may be used, but it is not limited to this.

[0079] The insulating layer may be formed by forming a coating layer and curing it, or by laminating an in-cured or semi-cured insulating film onto the core layer 22 and curing it. In this case, if a vacuum lamination method or the like is applied, the insulating material can be embedded into the space inside the core via 23, enabling efficient process execution.

[0080] In one embodiment, even when multiple insulating layers are laminated and applied, it may be difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case their boundary is not substantially distinguished. Alternatively, in other embodiments, the boundary between the insulating layers can be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0081] The upper distribution pattern 251 refers to an electrically conductive layer located within the upper insulating layer 253 in a predetermined configuration, and may be formed, for example, by a build-up layer method. Specifically, by forming an insulating layer, removing unnecessary portions of the insulating layer, forming an electrically conductive layer by a method such as copper plating, selectively removing unnecessary portions of the electrically conductive layer, forming another insulating layer on this electrically conductive layer, removing unnecessary portions again, and then forming another electrically conductive layer by a method such as plating, an upper distribution pattern 251 can be formed in which electrically conductive layers are formed vertically or horizontally in the desired pattern.

[0082] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, it is formed to include a fine pattern in at least a part of it so that electrical signals can be transmitted smoothly with the semiconductor element portion 30 and the intended complex pattern can be adequately accommodated. In this case, the fine pattern may have a width and spacing of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm, respectively (the description of the fine pattern is the same hereafter).

[0083] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253, to which the upper distribution pattern 251 and at least a portion thereof are electrically connected, and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion thereof may be embedded while being exposed on the upper insulating layer. For example, if the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating, and if the upper connection pattern is embedded while a portion thereof is exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or electrically conductive layer may be removed by methods such as surface polishing or surface etching.

[0084] The top connection pattern 272, like the top distribution pattern 251 described above, can include a fine pattern in at least part of its structure. A top connection pattern 272 including such a fine pattern allows even more elements to be electrically connected in a small area, making the connection of electrical signals between elements or to the outside smoother and enabling more integrated packaging.

[0085] The upper connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or it may be connected via an element connection portion 51 such as a solder ball.

[0086] The cavity portion 28 is located above and / or below the second area 222 and includes an internal space 281 in which a cavity distribution layer 282 and an electronic element 40 are located, which are electrically connected to the core distribution pattern 241.

[0087] Specifically, the glass core 21 in the second region 222 is even thinner than that in the first region 221, and the internal space 281 formed by this difference in thickness allows for the placement of electronic elements 40. Furthermore, the core vias 23 and core distribution layer 24 formed in the glass core 21 serve as electrical connection structures that connect the electronic elements 40 to external elements.

[0088] Furthermore, as described above, a cavity portion may be generated not in the second region 222, but in the first region 221, that is, a cavity portion that penetrates the first surface 213 and the second surface 214 of the glass core 1, and electronic elements 40 may be arranged in the cavity portion.

[0089] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the terminals of the motherboard 10 by the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or it may be electrically connected via a board connection part 52 such as a solder ball. Alternatively, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via the lower layer 38 located below the core layer 22.

[0090] For example, the packaging substrate 20 located between the semiconductor element section 30 and the motherboard 10 may not have any substantially additional substrates applied other than the glass core 21.

[0091] Conventionally, when connecting elements to a motherboard, an interposer and an organic substrate were stacked together between them. This multi-layered configuration was applied for at least two reasons: firstly, there were scaling issues when directly bonding the fine patterns of the elements to the motherboard; and secondly, the difference in thermal expansion coefficients could cause damage to the wiring during the bonding process or the operation of the semiconductor device. In this concrete example, these problems were solved by applying a glass core with a thermal expansion coefficient similar to that of the semiconductor element, and by forming a fine pattern with a scale small enough to support the element on the first surface of the glass core and the upper layer thereof.

[0092] The following describes a method for manufacturing a packaging substrate according to an embodiment of the present invention.

[0093] Figures 4 and 5 are flowcharts illustrating the manufacturing process of a packaging substrate in a cross-sectional view, based on an actual example.

[0094] First, a glass core 21a having a flat first surface and a flat second surface is prepared as shown in Figure 4(a), and defects (grooves) 21b are formed on the glass surface at predetermined positions for the formation of core vias. The glass can be a glass core used for substrates of electronic devices, etc., and may, for example, an alkali-free glass core, but is not limited to this. Commercial products manufactured by companies such as Corning, Schott, and AGC may be used. Methods such as mechanical etching and laser irradiation may be used to form the defects (grooves).

[0095] As shown in Figure 4(b), the glass core 21a on which the defect (groove) 21b is formed undergoes an etching step to form core vias 23 through a physical or chemical etching process. During the etching process, the glass core forms vias in the defective area, and at the same time, the surface of the glass core 21a may also be etched. To prevent such etching of the glass surface, a masking film or the like can be applied, but considering the hassle of applying and removing the masking film, the defective glass core itself can be etched, in which case the thickness of the glass core with core vias may be slightly thinner than the thickness of the original glass core.

[0096] Subsequently, as shown in Figures 4(c) and 4(d), the core layer manufacturing step can be carried out by forming an electrically conductive layer 21d on the glass core. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited to this.

[0097] The adhesion between the glass surface (including the glass core surface and core via surface) and the copper metal surface is inferior due to their differing properties. In practical applications, the adhesion between the glass surface and the metal can be improved using two methods: a dry method and a wet method.

[0098] The dry method is a method that applies sputtering, that is, a method that forms a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper, etc. In such cases, the adhesion between the glass and the metal can be improved by an anchoring effect caused by the interaction between the surface morphology of the glass and the metal particles.

[0099] The wet method is a method of priming, in which a primer layer 21c is formed by pretreatment with a compound having a functional group such as an amine. Depending on the desired degree of adhesion, pretreatment with a silane coupling agent can be performed, followed by priming with a compound or particles having an amine functional group. As mentioned above, the support substrate in the embodiment needs to be high-performance enough to form a fine pattern, and this must be maintained even after priming. Therefore, when such a primer contains nanoparticles, it is preferable to use nanoparticles having an average diameter of 150 nm or less, and for example, it is preferable to use nanoparticles for particles having an amine group. The primer layer may, as an example, be formed by applying an adhesion improver manufactured by MEC's ​​CZ series or the like.

[0100] The seed layer / primer layer 21c can selectively form a metal layer with or without removing portions where the formation of an electrical conductive layer is unnecessary. Furthermore, the seed layer / primer layer 21c can be treated in a state where the formation of an electrical conductive layer is necessary or unnecessary, either by activating or deactivating it with metal plating, before proceeding to subsequent steps. For example, the activation or deactivation treatment may include light irradiation treatment such as a laser of a certain wavelength, or chemical treatment. For the formation of the metal layer, copper plating methods used in the manufacture of semiconductor devices may be used, but are not limited to these.

[0101] As shown in Figure 4(e), if a portion of the core distribution layer is unnecessary, it may be removed, or the etching layer 21e of the core distribution layer may be formed by partially removing or deactivating the seed layer and then performing metal plating to form an electrically conductive layer in a predetermined pattern.

[0102] Figure 5 illustrates the manufacturing steps for forming the insulating layer and the upper distribution pattern using an example.

[0103] As shown in Figure 5(a), the core via can undergo an insulating layer formation step in which the void space is filled with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. At this time, the insulating layer to be applied may be one manufactured in the form of a film, for example, by laminating an insulating layer in the form of a film under reduced pressure. By performing lamination under reduced pressure in this way, the insulating layer is sufficiently embedded into the void space inside the core via, thereby forming a core insulating layer without void formation.

[0104] Figures 5(b) to (e) illustrate the upper layer manufacturing steps.

[0105] The upper layer manufacturing step involves forming an upper distribution layer, which includes an upper insulating layer and an upper distribution pattern, on the core layer. The upper insulating layer may be formed by coating with a resin composition that forms the insulating layer 23a, or by laminating an insulating film. For simplicity, the lamination of an insulating film is preferred. The lamination of the insulating film can be carried out by laminating and curing the insulating film. In this case, if a reduced-pressure lamination method is applied, the insulating resin can be sufficiently embedded even in layers where an electrically conductive layer has not been formed inside the core vias. The upper insulating layer also comes into direct contact with the glass core at least in part, and therefore, one with sufficient adhesion is used. Specifically, it is preferable that the glass core and the upper insulating layer have characteristics that satisfy an adhesion test value of 4B or higher according to ASTM D3359.

[0106] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching away unnecessary parts to form an etched layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with the insulating layer in between, the pattern can be formed by forming blind vias 23b in the insulating layer and then performing a plating process. Blind vias can be formed using dry etching methods such as laser etching or plasma etching, or wet etching methods using a masking layer and etching solution.

[0107] Subsequently, although not shown in the diagram, an upper connecting layer and a cover layer may be formed.

[0108] The top connection pattern and top connection electrodes can also be formed by a process similar to that of the top distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, then forming an electrically conductive layer thereon, and then forming an etching layer of the electrically conductive layer. Alternatively, a method may be applied that selectively forms only the electrically conductive layer without applying the etching method. The cover layer may be formed so that openings (not shown) are formed at positions corresponding to the top connection electrodes, exposing the top connection electrodes and allowing direct connection to the element connection portion or the terminals of the element.

[0109] Once the upper layer is generated, the process of forming the lower connecting layer and cover layer to generate the lower layer can be carried out. The lower distribution layer and / or lower connecting layer, and selectively a cover layer (not shown) can be formed in a manner similar to the upper connecting layer and cover layer formation steps described above.

[0110] Figure 6 is a diagram illustrating the warping phenomenon that occurred in the substrate when an insulating layer was formed in the conventional manner.

[0111] Electronic elements can be formed so as to be inserted into an insulating layer. This is called the embedding process, and at this time, if a thick insulating film, such as ABF (Ajinomoto Build-up Film), is used to fill the space remaining after the placement of electronic elements in the cavity area, i.e., the cavity region, all at once, asymmetrical shrinkage may occur on one side of the substrate after curing, as shown in Figure 6.

[0112] The step of curing the insulating layer may include a pre-curing step, in which the insulating film is partially cured without being completely hardened, and an additional curing step, in which the insulating film is completely hardened.

[0113] During pre-curing, significant shrinkage forces may occur in specific directions due to chemical reactions between insulating films such as ABF and their components, deviations in the CTE (Coefficient of Thermal Expansion) of the glass core, and residual thermal stress. This stress can cause warping.

[0114] As shown in Figure 6, the glass core may bulge due to warping in the direction of the insulating film, which can result in defects in the packaging substrate. As will be described later, the manufacturing process of the packaging substrate is as follows: After fixing the position of the electronic elements with an adhesive film in a through-cavity, an insulating film is placed on the surface opposite to the adhesive film. Then, pre-curing is performed along with vacuum lamination, and the adhesive film is removed in order to proceed to the next step. At this time, shrinkage force is likely to occur in the insulating layer due to residual stress in the insulating layer, and it is thought that warping occurs in the glass core for various reasons, including this.

[0115] In this case, problems may arise where elements placed in the cavity region detach, move, or separate from their original positions. Furthermore, in the case of pre-curing, the insulating film is not completely solidified, making element separation relatively easy.

[0116] Warpage can be measured by placing the packaging substrate (or glass core) on a flat floor and measuring the height at which the corners of the packaging substrate (or glass core) are lifted from the floor. As shown in Figure 6, due to shrinkage during pre-curing, one vertex of the packaging substrate (or glass core) was lifted approximately 20 mm, or about 2 cm, from the floor. This can act as a fatal defect in the production of the packaging substrate.

[0117] The packaging substrate in the example may have a gap of 12 mm or less between the corners. This represents a superior characteristic compared to the existing example in Figure 6, where the gap is approximately 2 cm.

[0118] The packaging substrate in the example is placed on a flat floor, and the height difference between the corners of the packaging substrate and the floor on which it is placed may be 10 mm or less, 8 mm or less, 6 mm or less, or 4 mm or less. The aforementioned height difference may be 0 mm or more, or 1 mm or more. Since such a packaging substrate has a relatively small degree of warping, a stable manufacturing process for the packaging substrate can proceed, and the defect rate can be reduced.

[0119] The height difference between the corners is measured by placing the packaging substrate on a flat floor and measuring the height of the corners away from the floor without applying any other external force. For example, in the case of a rectangular packaging substrate, the highest value among the four corners is taken and presented as the height difference between the corners.

[0120] Therefore, in one embodiment of the present invention, it is proposed that the pre-curing process of the insulating film be performed multiple times instead of just once.

[0121] Figure 7 is a cross-sectional view illustrating the concept of a manufacturing method for a packaging substrate in a concrete example.

[0122] The packaging substrate in Figure 7 is a conceptually simplified diagram to illustrate the formation of the insulating layer, and the concepts described with reference to Figures 1 to 3 can be applied.

[0123] The cavity portion 29 shown in Figure 7 is formed by penetrating both the first and second surfaces of the glass core 21, and the electronic element 40 is arranged inside the cavity portion 29. The cavity portion 29 may be formed simultaneously through the same formation stage as the core vias, or it may be formed independently after or before the core vias are formed.

[0124] Unlike in Figure 7, the cavity 29 may be formed in the form of a recessed surface with only one of the first and second surfaces open. In this case, the cavity 29 may also be formed simultaneously through the same formation steps as the core vias, or it may be formed independently after or before the core vias are formed.

[0125] As described above, the electronic element 40 may include passive elements and / or active elements.

[0126] As shown in Figure 7, a relatively thin insulating film is used instead of the existing thick insulating film to fill the core vias and cavity portions 29 of the glass core 21 that constitute the core layer, and an insulating layer can be generated on at least one surface of the glass core through two or more steps.

[0127] In other words, the insulating film is laminated in two or more stages, and pre-curing is performed after each lamination. Through this process, warpage can be minimized, and the detachment of electronic components from the substrate can be substantially prevented.

[0128] More specifically, the first insulating film 61 can be laminated from the first surface to the second surface (including cases where reduced-pressure lamination is applied to embed components of the insulating film in the spaces of holes or cavities) and cured, thereby forming the first insulating layer.

[0129] Subsequently, a second insulating layer can be formed by laminating a second insulating film 63 onto the first insulating layer and curing it. At the same time, or through a separate process, a third insulating layer can be generated by laminating a third insulating film 64 from the second surface towards the first surface and curing it.

[0130] In other words, a first insulating layer can be formed through lamination of a first insulating film and a primary curing step (pre-cure), and a second insulating layer can be formed on the upper part of the glass core (upper part of the first insulating layer) through lamination of a second insulating film and a secondary curing step (pre-cure).

[0131] Furthermore, lamination in the secondary curing step allows for the lamination of the third insulating film not only on the upper part of the glass core (upper part of the first insulating layer) but also on the lower part of the glass core (second surface), and through the secondary curing step (pre-cure), the second and third insulating layers can be formed simultaneously. In this case, the same insulating film as the second insulating film can be used for the third insulating film. Also, in this case, simultaneous curing on both sides of the glass core can distribute the stress generation, which may be even more advantageous in suppressing warping.

[0132] In this way, through a two-stage pre-curing treatment, it is possible to stably form an insulating layer inside the core via and cavity portion 29 while improving or substantially improving the warping phenomenon of the substrate.

[0133] Figure 8 is a flowchart illustrating the manufacturing process of a packaging substrate in a cross-sectional view, based on an actual example.

[0134] The steps for forming an insulating layer on a packaging substrate will be explained in more detail using Figure 8 as an example.

[0135] First, as shown in Figure 8(a), the glass core 21 is attached to an adhesive film 80 such as PI tape (Polyimide Tape), and the electronic elements 40 are selected and placed in the cavity portion 29 (specification of the position of the electronic elements).

[0136] Subsequently, as shown in (b), a first lamination process (1st Lamination on top) may be performed on the first surface. Once the first insulating film 61 is laminated over the entire first surface of the glass core 21 and a first pre-cure step is performed, the first insulating layer may be embedded so that the insulator extends into the internal space of the cavity portion 29, as shown in (c).

[0137] If necessary, the adhesive film 80 may be removed during a subsequent process. For example, the adhesive film 80 may be an adhesive film whose adhesive strength can be reduced by ultraviolet irradiation or the like. The adhesive film 80 can be easily removed from the glass core by reducing its adhesive strength, either by direct irradiation of the adhesive film or by irradiating it with ultraviolet light through the glass core.

[0138] Furthermore, the position of the electronic element 40 can be fixed by the first insulating layer that has been pre-cured by primary curing, and if the degree of warping is controlled to be below a certain level, subsequent processes can be applied without fixing the adhesive film 80.

[0139] Once the first insulating layer is formed, a secondary curing step may be performed in which the second insulating film 63 and / or the third insulating film 64 are laminated onto the primary cured first insulating film 61 and / or second surface, respectively, and then secondary curing (2nd Pre-cure) is carried out (2nd Lamination on top & bottom).

[0140] Once secondary curing is complete, an insulating layer separated by the boundary between the insulating films may be formed, as shown in (d). In other words, the insulating layer may include a first insulating layer formed by laminating and curing a first insulating film 61 from the first surface to the second surface, and a second insulating layer formed by laminating and curing a second insulating film 63 on the first insulating layer. Optionally, it may further include a third insulating layer formed by laminating and curing a third insulating film 64 from the second surface to the first surface. An expected boundary 1 (L1) may be formed between the first insulating layer and the second insulating layer where the first insulating film 61 and the second insulating film 63 are in contact, and an expected boundary 2 (L2) may be formed between the first insulating layer and the third insulating layer where the first insulating film 61 and the third insulating film 64 are in contact.

[0141] For example, the thickness of the first insulating film 61 to which primary curing is applied and the thickness of the second insulating film 63 to which secondary curing is applied may be different from each other.

[0142] The first insulating film 61 and the second insulating film 63 may be applied in a thickness ratio of 1:0.5 to 2, or a thickness ratio of 1:0.6 to 1.5. For example, if the total thickness of the first insulating film 61 and the second insulating film 63 is 80 μm, the thickness ratio of the first insulating film 61 / second insulating film 63 may be in the range of 30 / 50, 50 / 30, or 40 / 40. If the total thickness of the first insulating film 61 and the second insulating film 63 is 60 μm, the thickness ratio of the first insulating film 61 / second insulating film 63 may be in the range of 30 / 30, 20 / 40, or 40 / 20. Alternatively, if the total thickness of the first insulating film 61 and the second insulating film 63 is 30 μm, the thickness ratio of the first insulating film 61 / second insulating film may be in the range of 15 / 15, 10 / 20, or 20 / 10.

[0143] Of course, the pre-curing step may be performed more than twice. The thickness of the insulating film and the number of curing cycles can be optimally set according to the size of the cavity 29 and the height of the glass core 21.

[0144] Insulating films such as ABF may be manufactured using a thermosetting method that involves applying heat.

[0145] Specifically, the insulating film can be pre-cured by a thermosetting method after a portion of its components has been induced to be placed inside vias, cavities, etc., using a reduced-pressure lamination method. In this case, pre-curing means that the insulating film is not completely cured, but rather cured to an intermediate stage, and this can be controlled by adjusting the curing temperature, etc.

[0146] The temperature and pressure during primary and secondary curing are not the same. The pressure and temperature applied during the secondary curing step are higher than those applied during the primary curing step.

[0147] The primary curing step may be performed at a primary curing temperature of 60°C to 145°C.

[0148] The primary curing temperature may be 60°C or higher, or 65°C or higher. The primary curing temperature may be 145°C or lower, 140°C or lower, 130°C or lower, 120°C or lower, 110°C or lower, 100°C or lower, or 90°C or lower. In this case, the insulating layer may be cured to a pre-curing level without being completely cured.

[0149] The primary curing step is performed at 15 kgf / cm 2 or lower, 12 kgf / cm 2 or lower, or 10 kgf / cm 2 or lower under reduced pressure conditions. The reduced pressure condition may be 2 kgf / cm 2 or higher, or 5 kgf / cm 2 or higher.

[0150] The secondary curing step may be performed at a secondary curing temperature of 120°C to 180°C.

[0151] The secondary curing temperature may be 120°C or higher, 130°C or higher, 140°C or higher, 150°C or higher, or 160°C or higher. The secondary curing temperature may be 180°C or lower, 170°C or lower, or 165°C or lower. In this case, the insulating layer may be cured to a pre-curing level without being completely cured.

[0152] The secondary curing step is performed at 22 kgf / cm 2 or lower, 20 kgf / cm 2 or lower, or 18 kgf / cm 2 or lower under reduced pressure conditions. The reduced pressure condition may be 10 kgf / cm 2 or higher, or 13 kgf / cm 2 or higher.

[0153] The curing temperature in the primary curing step may be applied at a temperature higher than the curing temperature in the secondary curing step.

[0154] The heating to the primary curing temperature may be carried out over 20 to 120 minutes, or over 20 to 80 minutes. The primary curing temperature may be maintained for 20 to 120 minutes, or over 20 to 80 minutes.

[0155] The heating to the secondary curing temperature may be carried out for 20 to 100 minutes, or for 20 to 80 minutes. The secondary curing temperature may be maintained for 20 to 100 minutes, or for 20 to 80 minutes.

[0156] When curing is performed under these temperature and pressure conditions, a pre-cured or cured insulating layer can be obtained to the intended level.

[0157] After pre-curing steps such as primary and / or secondary curing are performed, the insulating film may undergo a final curing step to fully cure it. Between the pre-cure and cure steps, a step to planarize the substrate surface may be performed. That is, the upper surface of the insulating layer may be guided to be planarized. Exemplaryly, a method of positioning a planarizing film (e.g., PET film) on the insulating layer during a vacuum lamination process may be applied. However, the planarizing method is not limited to this.

[0158] For example, such planarization may be performed between the primary and secondary curing processes described above.

[0159] On the other hand, it will be apparent to those skilled in the art that the pre-curing step of the insulating film described with reference to Figure 8 can also be applied to a cavity portion that opens in either direction of the first or second surface of the glass core 21.

[0160] Figures 9A and 9B are microscope images of the boundaries of the insulating layers produced by the manufacturing of the packaging substrate according to the embodiment example, respectively.

[0161] After going through the process shown in Figure 8, an insulating layer like that shown in Figure 9A or Figure 9B is formed. Specifically, a first boundary L1 is formed between the first insulating layer and the second insulating layer, where the first insulating film 61 and the second insulating film 63 are in contact, and a second boundary L2 is formed between the first insulating layer and the third insulating layer, where the first insulating film 61 and the third insulating film 64 are in contact.

[0162] L2 in Figure 9B shows a second boundary (a line between two types of materials) formed between the first insulating layer and the third insulating layer inside the cavity 29. Such a boundary indicates that the insulating layers were generated through multiple curing steps rather than a single curing process, and the boundary can be observed because different temperatures and pressures are applied during curing.

[0163] For example, the boundary may be observed as a line where the difference in color is defined.

[0164] For example, the boundary may be observed as a band shape with a relatively constant thickness of color and a change in color (for example, a gradient-like color change). For example, the constant interval may be 2 μm to 30 μm, or 3 μm to 10 μm.

[0165] Furthermore, at the boundary, the colors of the insulating layers, for example, the first insulating layer and the third insulating layer, can be distinguished from each other.

[0166] As shown in Figures 9A and 9B, the thickness of the first insulating film 61 may be 60 μm, 70 μm, or 80 μm, and the position where the second boundary is formed may change depending on the thickness of the first insulating film 61.

[0167] Figure 10 is a photograph illustrating the warpage of a packaging substrate produced by the manufacturing process of a packaging substrate in a concrete example.

[0168] As described above, warpage can be measured as the average height of the corners of the glass core away from the floor on which the packaging substrate or glass core is placed. Figure 10 shows the warpage when the curing process for the insulating film is carried out in multiple stages according to an embodiment of the present invention.

[0169] The glass core can have a rectangular shape (in one example, the width and length of the glass core are approximately 53 cm), and in one example, its thickness may be 400 μm to 600 μm. When the curing process for the insulating film is performed in multiple stages on a glass core under these conditions, one vertex of the glass core is less than 0.1 mm away from the floor, as shown in Figure 10.

[0170] Compared to Figure 6, this degree of warping (WARPAGE) is very significant, and it can be evaluated as having almost completely disappeared.

[0171] Figure 11 is a flowchart illustrating the manufacturing process of a packaging substrate for another concrete example.

[0172] As shown in the figure, the cavity portion 29 in Figure 11 also has a structure that penetrates the first and second surfaces of the glass core 21, and a capacitor 41 is arranged as an example electronic element.

[0173] As described above, in addition to passive elements such as the capacitor 41, active elements may also be placed in the cavity 29 as electronic elements.

[0174] As shown in Figure 11(a), a glass core 21 is attached to an adhesive film 80 such as PI tape, and an electronic element such as a capacitor 41 is placed in the cavity portion 29.

[0175] According to this embodiment, the first insulating film can be laminated and cured not over the entire first surface, but in the cavity portion 29 where the capacitor 41 is located, or in the region including the cavity portion 29.

[0176] In other words, as shown in Figure 11, the first insulating layer 61a formed on the packaging substrate is not formed on the entire upper surface of the glass core 21, but rather is formed to fill all or part of the empty areas of the core vias and / or cavity portion 29. In such a case, the first insulating layer 61a can serve as an insulating layer surrounding an electronic element such as a capacitor 41.

[0177] In this case, the first insulating film can be cut based on the shape and size of the cavity 29 and laminated on top of the cavity 29. For example, the shape of the cut first insulating film may be substantially the same as or similar to the shape of the cavity 29 when viewed from above.

[0178] The size (area) of the first insulating film can be further adjusted to be larger or smaller, taking into consideration the volume to which the insulating layer should be embedded in the cavity portion 29, the thickness of the insulating layer, and so on. For example, the size of the first insulating film may be slightly smaller than the shape of the opening of the cavity portion 29, and its thickness may be thinner than the thickness of the cavity portion 29.

[0179] Through this process, a sufficient amount of insulating material can be embedded in the cavity while minimizing the formation of unnecessary insulating areas in regions other than the cavity 29. Furthermore, the occurrence of surface undulation that may occur between electronic elements and / or between electronic elements and the cavity can be minimized, resulting in a substantially flat insulating layer surface.

[0180] As described above, the step of forming the insulating layer may be performed in different numbers depending on the thickness of the glass core 21, the thickness of the insulating film, or the size and properties of the electronic elements. In addition, the region of the insulating layer to be cured in the primary stage can also be transformed into various structures depending on the arrangement of the cavity portions 29, the size and properties of the electronic elements.

[0181] Once the first insulating layer 61a is formed, the second insulating film can be laminated over the entire first and second surfaces of the glass core 21, as shown in Figure 8(c), and secondary curing can be performed.

[0182] After secondary curing, a second insulating layer 63a may be formed that completely surrounds the glass core 21 and the first insulating layer 61a, as shown in Figure 11(c).

[0183] Figure 12 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate related to another implementation example.

[0184] As shown in the figure, the packaging substrate is a glass structure having a glass core 21, core vias 23, a cavity 29, and electronic elements 40 arranged in the cavity 29, that is, it can include a core layer, an upper layer 26 located above the core layer, and a lower layer 38 located below the core layer. Cover layers 60 are formed on the upper layer 26 and the lower layer 38. The number of electronic elements 40 is not specified, and in this embodiment it is shown as 2.

[0185] A core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass core 21, is formed on the surface of the core via 23 and the cavity portion 29. In addition, an element electrically conductive layer 42 for electrically connecting the electronic element 40 and the upper distribution pattern 251 of the upper layer 26 is formed on a part of the upper surface, side surface, and lower surface of the electronic element 40.

[0186] On the other hand, as shown in the figure, the first insulating layer 61a fills the space between the two electronic elements 40 and the internal space of the cavity. The packaging substrate shown in Figure 12 is formed only in a limited area that can cover the cavity, rather than covering the entire first surface of the glass core 21, as described with reference to Figure 11. Furthermore, the first insulating layer 61a is not laminated on the upper surface of the cavity 29, but can fill the empty space on the side of the cavity 29, i.e., in the area where the electronic elements 40 are arranged.

[0187] In one embodiment, the electronic element 40 may be a capacitor, and when the capacitor is placed in a cavity 29 penetrating the glass core 21, one side of the capacitor, either the top or bottom, rather than both sides, may be connected to the upper distribution pattern 251. That is, the two electrodes 42a and 42b of the capacitor are electrically connected to the upper distribution pattern 251 formed in the upper layer 26, as shown in Figure 12, and current flows into the first electrode 42a and out through the second electrode 42b. The electrodes 42a and 42b may be formed as part of the element's electrically conductive layer 42, or they may be formed stepwise through a separate lamination process.

[0188] Of course, the two electrodes 42a and 42b of the capacitor may be formed in the direction of the second surface, which is the lower surface of the glass core 21, rather than the first surface, which is the upper surface.

[0189] An electrical conductive layer 42 is formed on the electronic element 40, and a first insulating layer 61a is formed surrounding it. After this, a second insulating layer 63a can be formed on the upper and lower parts of the first insulating layer 61a and the glass core 21. In other words, instead of filling the cavity region in one go as in the conventional method, a relatively thin insulating film can be used instead of the existing thick insulating film to fill the cavity portion 29, and an insulating layer can be generated on at least one surface of the glass core through two or more steps. That is, the insulating film is laminated in two or more stages, and pre-curing is performed after each lamination. Through this, warpage can be minimized and the electronic element can be prevented from detaching from the substrate.

[0190] An upper layer 26 is formed on top of the second insulating layer 63a formed on the first surface. The upper layer 26 may include an upper insulating layer 253 and an upper insulating layer 251 which is an electrically conductive layer having a predetermined pattern and to which the core distribution pattern 241 and the two electrodes 42a, 42b of the element electrically conductive layer 42 and at least a portion thereof are electrically connected, and which is embedded in the upper insulating layer 253.

[0191] The second insulating layer 63a and the upper insulating layer 253 may be made of the same insulating material, in which case their boundary may be substantially difficult to distinguish in cross-section. Alternatively, as in other embodiments, the boundary of the insulating layers may be relatively easily distinguished in cross-section by setting different pressures and temperatures for curing the multilayer insulating layers.

[0192] The second insulating layer 63a and the upper insulating layer 253 may be made of different insulating materials, in which case their boundary can be more easily demarcated.

[0193] Furthermore, as described above, the upper distribution pattern 251 refers to an electrically conductive layer located within the upper insulating layer 253 in a predetermined configuration, and may be formed, for example, by a build-up layer method. The method for manufacturing a packaging substrate according to the embodiments described above and the packaging substrate using the same can improve the warping phenomenon caused by differences in the degree of thermal expansion of the elements on the substrate, and can prevent separation or detachment of electronic elements.

[0194] The present invention described above has been explained with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person with ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present invention is not limited to the embodiments described above, and various modifications and improvements made by persons skilled in the art using the basic concepts of the embodiments as defined in the attached claims also fall within the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical idea of ​​the attached claims. [Explanation of Symbols]

[0195] 100 Semiconductor Devices 10 Motherboards 30 Semiconductor element section 32 First Semiconductor Element 34. Second Semiconductor Element 36 Third Semiconductor Device 20 Packaging substrates 21,21a Glass core 22 core layers 223 Core insulating layer 213 Page 1 214 2nd page 23 Corevia 24-core distribution layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 23b Blind Beer 253 Upper insulating layer 27 Top connecting layer 271 Top connecting electrode 272 Top connection pattern 28 Cavity section 281 Interior space 282 Cavity Distribution Layer 40 Electronic elements 50 Connection part 51 Element connection section 52 Board connection section 60 Cover layer

Claims

1. A packaging substrate, The aforementioned packaging substrate is The core layer, The upper layer located on the core layer, The aforementioned core layer is A glass core including a first surface and a second surface facing each other, The glass core comprises numerous core vias and cavity portions that penetrate in the thickness direction, An electrically conductive layer disposed on the surface of the glass core, The electronic elements arranged in the cavity portion, The core via and the insulating layer filling the cavity portion are included. The cavity portion is recessed by opening in the direction of the first or second surface of the glass core, or has a space that penetrates both the first and second surfaces. The insulating layer includes a first insulating layer formed by laminating and curing a first insulating film on the first surface, and a second insulating layer formed by laminating and curing a second insulating film on the first insulating layer. The first insulating layer is not formed on the entire upper surface of the first surface of the glass core, but is formed to fill all or part of the empty area of ​​the cavity portion in which the electronic elements are arranged. The second insulating layer is formed to completely surround the glass core and the first insulating layer. A packaging substrate in which the height difference between the corners of the packaging substrate and the floor on which the packaging substrate is placed is 12 mm or less.

2. The packaging substrate according to claim 1, wherein the insulating layer further comprises a third insulating layer formed by laminating and curing a third insulating film on the second surface.

3. A first boundary is formed between the first insulating layer and the second insulating layer, where the first insulating film and the second insulating film are in contact. A second boundary is formed between the first insulating layer and the third insulating layer, where the first insulating film and the third insulating film are in contact. The packaging substrate according to claim 2, wherein the second boundary is formed inside the core via and the cavity portion.

4. The packaging substrate according to claim 2, wherein the colors of the first insulating layer and the third insulating layer are different from each other.

5. The packaging substrate according to claim 1, wherein the thickness of the first insulating layer and the thickness of the second insulating layer are different from each other.

6. The packaging substrate according to claim 1, wherein the glass core is rectangular and the thickness of the glass core is 300 μm to 1,500 μm.

7. The packaging substrate according to claim 1, wherein the electronic elements include passive elements or active elements.

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