Memory device

Abstract

This invention provides a new semiconductor device with a structure that can retain stored data even when power is unavailable and has no limitations on the number of write cycles. [Solution] The semiconductor device includes a first transistor 160 having a channel forming region 116, a first gate insulating layer 108, a first gate electrode 110, and a first source electrode and first drain electrodes 130a, 130b; a second transistor 162 having an oxide semiconductor layer 140, a second source electrode and second drain electrodes 142a, 142b, and a second gate insulating layer 146, and a second gate electrode 148a; and a capacitive element 164 having one of the second source electrode or the second drain electrode, the second gate insulating layer, and an electrode provided on the second gate insulating layer so as to overlap with one of the second source electrode or the second drain electrode, wherein the first gate electrode and one of the second source electrode or the second drain electrode are electrically connected.

Description

[[TECHNICAL FIELD]]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the same . [[BACKGROUND ART]]

[0002] Memory devices using semiconductor elements are broadly classified into volatile memory devices, which lose stored data when power supply is interrupted , and non-volatile memory devices, which retain stored data even when power supply is interrupted .

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Ac cess Memory). DRAM stores information by selecting a transistor constituting a memory element and accumulating charge in a capacitor.

[0004] Based on the above principle, in DRAM, charge in the capacitor is lost when information is read out , so a rewrite operation is required each time data is read. Furthermore, in the memory element constituting transistors, leakage current exists, and even when the transistor is not selected , charge flows out or in, so the data retention period is short. For this reason, at predetermined intervals , a rewrite operation (refresh operation) is required, making it difficult to sufficiently reduce power consumption . In addition, stored data is lost when power supply is interrupted, so long-term data storage requires another storage device using a magnetic material or an optical material.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM retains stored content using a circuit such as a flip-flop Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Furthermore, in order to retain or remove charge from a floating gate, A high voltage is required, as well as a circuit to handle it. Furthermore, charge retention, Removing it takes a relatively long time, and speeding up writing and erasing is not easy. There are also problems. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 [Overview of the project] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of its objectives is to achieve this. [Means for solving the problem]

[0011] The disclosed invention constructs a semiconductor device using a highly purified oxide semiconductor. Transistors constructed using ionized oxide semiconductors have extremely low leakage current. It is possible to retain information over a long period of time.

[0012] One aspect of the disclosed invention comprises a channel-forming region and a portion provided to sandwich the channel-forming region. An impurity region, a first gate insulating layer provided on the channel formation region, and the first gate A first gate electrode is provided on the insulating layer, and a first source is electrically connected to the impurity region. A first transistor having an electrode and a first drain electrode, an oxide semiconductor layer, and an acid A second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer, and an oxide semiconductor A second conductor layer, a second source electrode, and a second drain electrode are provided to cover the conductor layer, the second source electrode, and the second drain electrode. A second gate insulating layer and a second oxide semiconductor layer are provided on top of the second gate insulating layer. A second transistor having a gate electrode and a second source electrode or second drain electrode One of the electrodes, a second gate insulating layer, and a second source electrode on the second gate insulating layer. A capacitive element having an electrode provided so as to overlap with one of the second drain electrodes, It has a first gate electrode and one of the second source electrode or the second drain electrode, and electricity is connected between them. It is a semiconductor device that is connected to a target.

[0013] Furthermore, one aspect of the disclosed invention comprises a channel-forming region and a portion sandwiching the channel-forming region. The impurity region, the first gate insulating layer provided on the channel formation region, and the first A first gate electrode provided on the gate insulating layer, and a first that electrically connects to the impurity region A first transistor having a source electrode and a first drain electrode, and an oxide semiconductor layer The oxide semiconductor layer is electrically connected to a second source electrode and a second drain electrode, and the An insulating layer in contact with the two source electrodes and the second drain electrode, an oxide semiconductor layer, and the second source A drain electrode, a second drain electrode, and a second gate insulating layer provided to cover the insulating layer. And, a second gate insulating layer is provided on the second gate insulating layer so as to be superimposed on the oxide semiconductor layer. A second transistor having a pole and a second source electrode or a second drain electrode A second gate insulating layer and a second source electrode or second gate insulating layer on the second gate insulating layer A capacitive element having an electrode provided so as to overlap with one of the rain electrodes, The gate electrode of electrode 1 is electrically connected to either the second source electrode or the second drain electrode. It is a semiconductor device.

[0014] In the above, the oxide semiconductor layer is located on the sides of the second source electrode and the second drain electrode. It is preferable that the upper surface makes contact. Also, in the above, the second transistor and The capacitive element is preferably located above the first transistor.

[0015] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, such as "directly above" or This does not necessarily mean "directly below". For example, "gate electrode on the gate insulating layer". If the expression is ", then exclude those that include other components between the gate insulating layer and the gate electrode. No. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation and do not require any special mention. This also includes the inverted versions, unless otherwise specified.

[0016] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0017] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It shall be done.

[0018] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0019] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0020] In one aspect of the present invention, a transistor using a material other than an oxide semiconductor and an oxide semiconductor A semiconductor device relating to the stacked structure of the transistors used is provided.

[0021] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0022] Furthermore, it does not require high voltage for writing information, and there are no problems with element degradation. Because it does not require the injection or extraction of electrons into or from the floating gate, as in non-volatile memory, No problems such as deterioration of the insulating layer occur. In other words, the semiconductor device according to this embodiment does not experience any degradation. Unlike conventional non-volatile memory, it does not have the limitation on the number of rewrite cycles, and its reliability is... It improves dramatically. Furthermore, the on and off states of the transistor allow for information to be written. Because this process is performed, high-speed operation can be easily achieved. Also, the operation to erase information is It also has the advantage of being unnecessary.

[0023] Furthermore, transistors using materials other than oxide semiconductors are capable of sufficiently high-speed operation, By using this method, it is possible to read the contents of memory at high speed.

[0024] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0025] [Figure 1] Cross-sectional and plan views of a semiconductor device. [Figure 2] Cross-sectional view of a semiconductor device [Figure 3] Circuit diagram of a semiconductor device [Figure 4] Cross-sectional view of the semiconductor device manufacturing process [Figure 5] Cross-sectional view of the semiconductor device manufacturing process [Figure 6] Cross-sectional and plan views of a semiconductor device. [Figure 7] Cross-sectional view of the semiconductor device manufacturing process [Figure 8] Circuit diagram of a semiconductor device [Figure 9] Cross-sectional and plan views of a semiconductor device. [Figure 10] Cross-sectional view of a semiconductor device [Figure 11] Cross-sectional view of the semiconductor device manufacturing process [Figure 12] Cross-sectional view of the semiconductor device manufacturing process [Figure 13] Cross-sectional view of the semiconductor device manufacturing process [Figure 14] Perspective view for explaining electronic equipment [Figure 15] Figure showing the results of the memory window width investigation. [Modes for carrying out the invention]

[0026] Embodiments of the invention will be described below with reference to the drawings. However, the invention is not limited to the following description. It is not fixed, and its form and details may be changed in various ways without deviating from its purpose and scope. It will be easily understood by those skilled in the art to obtain this. Therefore, the present invention is as shown in the embodiments below. The interpretation is not limited to the content stated herein.

[0027] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0028] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0029] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. The following will be explained with reference to Figures 1 to 5. Note that in the circuit diagrams, oxide semiconductors are used. Sometimes, the sign "OS" is added to indicate that it is a transistor.

[0030] <Planar and cross-sectional configurations of semiconductor devices> Figure 1 shows an example of the configuration of a semiconductor device. Figure 1(A) shows a cross-section of the semiconductor device. Figure B) shows the planes of the semiconductor device. Here, Figure 1(A) is the same as A in Figure 1(B). This corresponds to the cross-sections at 1-A2 and B1-B2, as shown in Figures 1(A) and 1(B). The semiconductor device has a transistor 160 made of a material other than an oxide semiconductor at its lower part. It has a transistor 162 and a capacitive element 164 made of oxide semiconductor at the top. Yes. Note that both transistor 160 and transistor 162 are n-channel type transistors. Although it will be explained as a transistor, a p-channel transistor can be used. It goes without saying that. Furthermore, the technical essence of the disclosed invention is that acid is used to retain information. The key point is that a synthetic semiconductor is used in transistor 162, so the specific configuration of the semiconductor device is... It is not necessary to limit the scope to what is shown here.

[0031] The transistor 160 is provided on a substrate 100 containing a semiconductor material (for example, silicon). A channel-forming region 116 and an impurity formed so as to sandwich the channel-forming region 116 Region 114 and high-concentration impurity region 120 (these are collectively also simply called the impurity region) The gate insulating layer 108 provided on the channel forming region 116, and the gate insulating layer 108 The gate electrode 110 provided above, and the source electrode or dove that is electrically connected to the impurity region. It has a rain electrode 130a and a source electrode or drain electrode 130b.

[0032] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Furthermore, in the area of ​​the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed in plan view, A region having a high-concentration impurity region 120, and a metal compound region 124 adjacent to the high-concentration impurity region 120 It exists. Also, on the substrate 100, there is an element isolation insulating layer 10 surrounding the transistor 160. 6 is provided, and the interlayer insulating layer 126 and interlayer insulating layer are provided so as to cover the transistor 160. An edge layer 128 is provided. Source electrode or drain electrode 130a, and source electrode The electrode or drain electrode 130b is formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the opening. In other words, the source electrode. Alternatively, the drain electrode 130a and the source electrode or drain electrode 130b are metallized. The compound region 124 is electrically connected to the high-concentration impurity region 120 and the impurity region 114. Furthermore, the electrode 130c is formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the gate electrode 110 through the opening. In some cases, such as due to the integration of 60 components, the sidewall insulating layer 118 may not be formed.

[0033] The transistor 162 has a source electrode or drain electrode 14 provided on the insulating layer 138. 2a, and source electrode or drain electrode 142b, and source electrode or drain electrode 142a, and the oxidizing electrode electrically connected to the source electrode or drain electrode 142b. A monocrystalline semiconductor layer 140, a source electrode or drain electrode 142a, and a source electrode or The drain electrode 142b, the insulating layer 144 in contact with the oxide semiconductor layer 140, and the source electrode The drain electrode 142a, the source electrode or drain electrode 142b, and the oxide semiconductor layer 14 0, a gate insulating layer 146 covering the insulating layer 144, and an oxide semiconductor layer on the gate insulating layer 146. It has a gate electrode 148a that is provided so as to overlap with 140. Here, the insulating layer 1 44 is provided to reduce capacitance caused by gate electrode 148a, etc. Furthermore, to simplify the process, the insulating layer 144 may be omitted.

[0034] Furthermore, as mentioned above, the transistor 162 shown in Figure 1 is a top-gate type, and Connection between the oxide semiconductor layer 140 and a source electrode or a drain electrode 142a or the like is formed in a region including the lower surface of the oxide semicon ductor layer 140, and thus the structure can be called a top-gate bottom-co ntact type.

[0035] Here, it is preferable that impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, or the oxide semiconductor layer 140 is highly purified by being supplied with sufficient oxygen. Specifically , for example, the hydrogen concentration of the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 or lower, preferab ly 5×10 18 atoms / cm 3 or lower, more preferably 5×10 17 atoms / cm 3 or lower. Note that the hydrogen concentration in the above-described oxide semiconductor layer 140 is measured by secondar y ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscop y). As described above, in the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced for high purification, and defect le vels in the energy gap caused by oxygen deficiency are reduced due to supply of sufficient oxygen, the carrier concentration is 1×10 / cm 12 / cm 3 or less, preferably 1 ×10 11 / cm 3 or less, more preferably 1.45×10 10 / cm 3 or less. For exa mple, in the case where the channel length is 10 μm and the film thickness of the oxide semiconductor layer is 30 nm, when the dr ain voltage is in the range of approximately 1 V to 10 V, the off-state current (drain current when the voltage between the gate and the source is 0 V or lower) is 1×10 -13 A or lower. Further, at room temperature The off-current density (off-current divided by the transistor's channel width) is 1 × 10⁻⁶ -20 A / μm (10 zA (zeptoampere) / μm) to 1 × 10 -19 A / μm (100 Hz A) The off-resistivity is approximately 1 × 10⁻¹⁶ / μm. 9 Ω·m or greater, preferably 1 × 10⁻⁶ 1 0 The coefficient of gravity becomes Ω·m or greater. Thus, the oxide is i-type (intrinsed) or substantially i-type. By using semiconductors, it is possible to obtain a transistor 162 with extremely excellent off-current characteristics. Cut.

[0036] Furthermore, the source electrode or drain electrode 142a is electrically connected to electrode 130c. In other words, the source electrode or drain electrode 142a is the gate electrode of transistor 160. It is electrically connected to electrode 110. Similarly, to source electrode or drain electrode 130a Electrode 142c is in contact with the source electrode or drain electrode 130b, and electrode 142d is in contact with the source electrode or drain electrode 130b. They are each formed in their own way.

[0037] The capacitive element 164 consists of a source electrode or drain electrode 142a, a gate insulating layer 146, and an electrode. It consists of 148b, that is, the source electrode or drain electrode 142a is a capacitive element Electrode 148b functions as one electrode of sub-electrode 164, and electrode 148b functions as the other electrode of capacitive element 164. It will function in that way.

[0038] Furthermore, a protective insulating layer 150 is provided on the transistor 162 and the capacitive element 164. Furthermore, an interlayer insulating layer 152 is provided on the protective insulating layer 150.

[0039] <Modified examples of the transistor and capacitive elements at the top> Next, Figure 2 shows a modified version of the upper transistor and capacitive element shown in Figure 1(A).

[0040] The transistor and capacitance elements shown in Figure 2(A) are located at the top of the semiconductor device shown in Figure 1. These are variations of static and capacitive elements.

[0041] The difference between the configuration shown in Figure 2(A) and the configuration shown in Figure 1(A) is that the insulating layer 144 is the source power Formed on the electrode or drain electrode 142a, and the source electrode or drain electrode 142b The oxide semiconductor layer 140 is located on the insulating layer 144, and the source electrode or drain electrode 14 2a and the point formed to cover the source electrode or drain electrode 142b Furthermore, the oxide semiconductor layer 140 allows the source electricity to pass through the openings provided in the insulating layer 144. It is provided in contact with the electrode or drain electrode 142a.

[0042] Furthermore, in the transistor and capacitive element shown in Figure 2, the source electrode or drain electrode 1 42a, the source electrode or drain electrode 142b, and the end of the insulating layer 144 are tapered - The shape is preferable. Here, the taper angle is, for example, 30° or more and 60° or less. It is preferable that it be present. Note that the taper angle refers to a layer having a tapered shape (for example, a source). The electrode or drain electrode 142a) is positioned perpendicular to its cross-section (the plane perpendicular to the surface of the substrate). This shows the inclination angle between the side and bottom surfaces of the layer when observed from the front. Source electrode or Dray The ends of the source electrode 142a, the source electrode, or the drain electrode 142b are tapered. This improves the coverage of the oxide semiconductor layer 140 and prevents step breaks.

[0043] Furthermore, in the configuration shown in Figure 2(A), the oxide semiconductor layer 140 is not processed, therefore, during processing... The etching process performed in this manner prevents contaminants from entering the oxide semiconductor layer 140. Furthermore, in the capacitive element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and electrode 148b is maintained. It is possible to ensure sufficient connection.

[0044] The transistor and capacitance element shown in Figure 2(B) are the same as the transistor and capacitance element in Figure 2(A). It has a slightly different structure.

[0045] The difference between the configuration shown in Figure 2(B) and the configuration shown in Figure 2(A) is that the oxide semiconductor layer is formed in an island-like shape. The point is that it is achieved. In other words, in the configuration shown in Figure 2(A), the oxide semiconductor layer 140 is an absolute Edge layer 144, source electrode or drain electrode 142a, and source electrode or drain In contrast to the configuration shown in Figure 2(B), which completely covers electrode 142b, the oxide semiconductor By making the layers island-like, the insulating layer 144, the source electrode or drain electrode 142a, and A portion of the source electrode or drain electrode 142b is covered. Here, island-shaped oxide hemispheres are present. The ends of the conductor layer 140 are preferably tapered. The taper angle is, for example, 3 It is preferable that the angle be between 0° and 60°.

[0046] Furthermore, in the capacitive element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and electrode 148b is This can be sufficiently secured.

[0047] The transistor and capacitance element shown in Figure 2(C) are the same as the transistor and capacitance element in Figure 2(A). It has a slightly different structure.

[0048] The difference between the configuration shown in Figure 2(C) and the configuration shown in Figure 2(A) is due to transistor 162 and capacity The key feature is that the element 164 does not have an insulating layer 144. (See the configuration in Figure 2(C)) Therefore, since the insulating layer 144 is not provided, it can be compared with the transistor and capacitive element shown in Figure 2(A). This simplifies the manufacturing process and reduces production costs.

[0049] Furthermore, in the configuration shown in Figure 2(C), the oxide semiconductor layer 140 is not processed, therefore, during processing... The etching process performed in this manner prevents contaminants from entering the oxide semiconductor layer 140. Furthermore, in the capacitive element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and electrode 148b is maintained. It is possible to ensure sufficient connection.

[0050] The transistor and capacitance elements shown in Figure 2(D) are the same as the transistor and capacitance elements shown in Figure 2(B). It has a slightly different configuration from the other components.

[0051] The difference between the configuration shown in Figure 2(D) and the configuration shown in Figure 2(B) is due to transistor 162 and capacity The key feature is that the element 164 does not have an insulating layer 144. By omitting the insulating layer 144 on the capacitance element 164, the configuration can be compared with that shown in Figure 2(B). This simplifies the manufacturing process and reduces production costs.

[0052] Furthermore, in the capacitive element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and electrode 148b is This can be sufficiently secured.

[0053] <Circuit configuration and operation of semiconductor devices> Next, we will describe an example of the circuit configuration of the above semiconductor device and its operation. Figure 3 (A-1 This is an example of a circuit configuration corresponding to the semiconductor device shown in Figure 1.

[0054] In the semiconductor device shown in Figure 3(A-1), the first line (also called the source line) The source electrode of transistor 160 is electrically connected to the second wiring (2nd The line (also called the bit line) and the drain electrode of transistor 160 are electrically connected. It is done. Also, the third wiring (3rd Line: also called the first signal line) and the transistor The source electrode or drain electrode of TA162 is electrically connected to the other, and the fourth wiring ( The 4th line (also called the second signal line) and the gate electrode of transistor 162 are connected by electricity. They are electrically connected. And the gate electrode of transistor 160 and transistor 16 One of the source or drain electrodes of the 2 is electrically connected to one of the electrodes of the capacitive element 164. Next, the fifth line (also called the word line) and the electrodes of the capacitive element 164 are connected. The other end is electrically connected.

[0055] Transistor 160, which uses materials other than oxide semiconductors, is capable of sufficiently high-speed operation, By using this, it is possible to perform tasks such as reading stored contents at high speed. Furthermore, The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, transistor 160 It is possible to maintain the potential of the gate electrode for an extremely long period of time. And the capacitance element Having child 164 helps retain the charge applied to the gate electrode of transistor 160. This makes it easier to retrieve stored data.

[0056] In the semiconductor device shown in this embodiment, the potential of the gate electrode of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: .

[0057] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential is set so that transistor 162 is turned on, thereby turning on transistor 162. As a result, the potential of the third wiring is controlled by the gate electrode of transistor 160 and the capacitive element 1 It is applied to one of the 64 electrodes. That is, the gate electrode of transistor 160 is given a predetermined A charge is given (written). Here, a charge that gives two different potential levels ( It shall give either a low-level charge or a high-level charge. Next, the potential of the fourth wire is set to the potential at which transistor 162 is in the off state, and the transistor By turning off transistor 162, the power supplied to the gate electrode of transistor 160 is reduced. The load is held (held).

[0058] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0059] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, when the appropriate potential (readout potential) is applied to the fifth wiring, the gate of transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then a High level will be applied to the gate electrode of transistor 160. Apparent threshold V when charge is given th_H The gate of 160 transistors Apparent threshold V when a low-level charge is applied to the electrode th_L Lower This is for the purpose of turning on transistor 160. Here, the apparent threshold voltage is the voltage that turns transistor 160 "on". This refers to the potential of the fifth wiring necessary to achieve the above. V th_H and V th_L By setting the potential V0 to the intermediate potential, the transistor 160 The charge applied to the gate electrode can be determined. For example, during writing, High level If a charge is applied, the potential of the fifth wire is V0 (>V th_H ) If that's the case, Lampistor 160 will be in the "on state". If a low-level charge is applied, The potential of the fifth wire is V0( <V th_L Even if this happens, transistor 160 remains in the "off state". It remains as is. Therefore, by looking at the potential of the second wire, the retained information can be read. It can be released.

[0060] Note that if information is not read, the state of the gate electrode of transistor 160 is irrelevant. The potential at which transistor 160 is in the "off state" is, that is, V th_H smaller You just need to apply potential to the fifth wire. Alternatively, you can apply potential to the gate electrode of transistor 160. The potential at which transistor 160 remains "on" is, that is, V th_L twist A large potential should be applied to the fifth wire.

[0061] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. The potential is set to such a state, and transistor 162 is turned on. This changes the potential of the third wiring. (The potential related to new information) is applied to the gate electrode of transistor 160 and the capacitive element 164. It is applied to one electrode. Then, the potential of the fourth wire is applied when transistor 162 is in the off state. By setting the potential to such a state and turning off transistor 162, transistor 16 The gate electrode with a value of 0 becomes a state where it is given a charge related to new information.

[0062] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0063] Note that the source or drain electrode of transistor 162 is connected to the gate of transistor 160. By being electrically connected to the electrode, it is used as a non-volatile memory element. It performs the same function as the floating gate of a ting-gate transistor. In the figure, the source electrode or drain electrode of transistor 162 and the gate of transistor 160. The part where the electrode is electrically connected is sometimes called the floating gate section (FG). When the transistor 162 is off, the floating gate section FG is embedded in the insulator. It can be seen that charge is retained in the floating gate portion FG. In transistor 162 using a conductor, the off-current is generated by the silicon semiconductor and other materials that form the transistor. Because it is less than 1 / 100,000th of the leakage of transistor 162, It is possible to ignore the dissipation of charge accumulated in the floating gate section FG. By using an oxide semiconductor transistor 162, a non-volatile memory device can be realized. This is possible.

[0064] For example, the off-current density of transistor 162 at room temperature is 10 zA / μm(1 zA(Zepto Amperes are 1 x 10 -21 A) The capacitance value of the capacitive element 164 is approximately 1pF. In that case, at least 10 6 Data can be retained for more than a second. Needless to say, this will vary depending on the transistor characteristics and capacitance values.

[0065] Furthermore, in this case, the gate issue that has been pointed out in conventional floating-gate transistors This avoids the problem of degradation of the tunnel insulating film. This solves the problem of gate insulating film degradation when injecting the child into the floating gate. This makes it possible. And, as a result, in the semiconductor device shown in this embodiment, the principle of writing There is no limit to the number of times it can be used. Also, in conventional floating-gate transistors The high voltage previously required for writing and erasing data is no longer necessary.

[0066] The semiconductor device shown in Figure 3(A-1) consists of elements such as transistors that make up the semiconductor device. It can be replaced with a circuit like the one shown in Figure 3(A-2), which includes resistance and capacitance. It is possible. In other words, in Figure 3(A-2), transistor 160 and capacitive element 164, Each of these is thought to consist of a resistor and a capacitor. R1 and C1 These are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the same as that of the capacitive element 164. This corresponds to the resistance value of the insulating layer that makes up 64. Also, R2 and C2 are, respectively, These are the resistance and capacitance values ​​of transistor 160, where resistance R2 is when transistor 160 is ON. This corresponds to the resistance value due to the gate insulating layer in the current state, and the capacitance value C2 is the so-called gate capacitance (gate This corresponds to the capacitance value formed between the source electrode or drain electrode. The resistance value R2 is the resistance value between the gate electrode of transistor 160 and the channel formation region. Since this is merely an illustration, some of the connections are shown with dotted lines to clarify this point.

[0067] The resistance between the source and drain electrodes when transistor 162 is in the off state (actual) If R1 and R2 are R1≧ROS and R2≧ROS, then R1≧ROS and R2≧ROS. If the conditions are met, the charge retention period (which can also be called the information retention period) is primarily determined by This will be determined by the off-current of the transistor 162.

[0068] Conversely, if the above conditions are not met, the off-current of transistor 162 will be sufficiently small. However, it becomes difficult to ensure a sufficient retention period. This occurs in transistors other than transistor 162. This is because the leakage is large. For this reason, the semiconductor device disclosed in this embodiment It is desirable that the above-mentioned relationship is satisfied.

[0069] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2. Therefore, when controlling the potential of the floating gate section FG by the fifth wiring (for example, read This is because it allows the potential of the fifth wiring to be kept low (when the wiring is disconnected).

[0070] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. In this configuration, R1 and R2 are provided by gate insulating layer 108 and gate insulating layer 146, etc. It is controlled in this way. The same applies to C1 and C2. Therefore, the material of the gate insulating layer and It is desirable to set the thickness and other parameters appropriately so that the above relationship is satisfied.

[0071] Figure 3(B) shows a semiconductor device whose configuration differs in some respects from the semiconductor device described above. In the semiconductor device shown in ), the gate electrode of transistor 160 and transistor 166 One of the source or drain electrodes of the capacitor and one of the electrodes of the capacitive element 164 are electrically connected. They are connected. Also, the first wiring and the source electrode of transistor 160 are electrically connected. The second wiring is then electrically connected to the drain electrode of transistor 160. And the third wire and the other of the source or drain electrode of transistor 166 The fourth wire and the first gate electrode of transistor 166 are electrically connected. They are connected. Also, the fifth wiring and the other electrode of the capacitive element 164 are electrically connected. The sixth wire and the second gate electrode of transistor 166 are electrically connected. The sixth wire may be given the same potential as the fourth wire, or a different potential from the fourth wire. A potential may be applied, and it may be controlled independently of the fourth wiring.

[0072] In other words, the semiconductor device shown in Figure 3(B) is a semiconductor device with a transistor that is the same as the semiconductor device shown in Figure 3(A-1). This configuration replaces transistor 162 with transistor 166, which has a second gate electrode. Therefore, in the semiconductor device shown in Figure 3(B), in the semiconductor device shown in Figure 3(A-1) In addition to the effects obtained, the electrical characteristics of transistor 166 (e.g., threshold voltage) can be adjusted. This has the effect of making it easier. For example, by applying a negative potential to the sixth wire, It is possible to easily turn off the 166 inverter.

[0073] Note that the above explanation refers to an n-type transistor (n-channel transistor) that uses electrons as the majority carrier. This concerns the case where a st(s) is used, but instead of an n-type transistor, a large number of holes are used. It goes without saying that a p-type transistor can be used as the carrier.

[0074] <Methods for fabricating semiconductor devices> Next, an example of a method for manufacturing the semiconductor device shown in Figures 1 and 3(A-1) will be described. Below, we will first explain the method for fabricating transistor 160 at the bottom, referring to Figure 4. Next, refer to Figure 5 for the method of fabricating the upper transistor 162 and the capacitive element 164. I will explain by referring to it.

[0075] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 4(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. An example will be shown. Generally speaking, an "SOI substrate" is a substrate with silicon semiconductor on an insulating surface. This refers to a substrate having a conductive layer, but in this specification, it refers to a substrate having a silicon on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The plate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. It shall include the following.

[0076] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 4(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxide nitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0077] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 4(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0078] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0079] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0080] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment can be performed using, for example, He, Ar, Kr, X This process is carried out using a mixture of gases such as noble gases (e), oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen. This is possible. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm to 100 nm. It can be less than or equal to m.

[0081] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using [a specific method]. Furthermore, using semiconductor materials such as polycrystalline silicon, conductive [a specific method] can be used. A layer containing the material may be formed. The formation method is not particularly limited and may include vapor deposition, CVD, and sputtering. Various film deposition methods such as taring and spin coating can be used. The example shown illustrates a case where a layer containing a conductive material is formed using a metallic material. Let's assume that.

[0082] Subsequently, the layers containing the insulating layer and conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 4(C)).

[0083] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see Figure 4(C)). Then, half By adding phosphorus (P) or arsenic (As) to the conductive region 104, an impurity region with a shallow junction depth is created. Form 114 (see Figure 4(C)). Note that here an n-type transistor is formed. Although phosphorus and arsenic are added, when forming a p-type transistor, boron (B) and arsenic are used. To form the above impurity region 114, impurity elements such as luminium (Al) should be added. As a result, a channel formation region 116 is formed below the gate insulating layer 108 of the semiconductor region 104. This is done (see Figure 4(C)). Here, the concentration of the added impurities can be set as appropriate. However, when semiconductor devices are miniaturized to a high degree, it is desirable to increase the concentration. In this case, a process is employed in which an impurity region 114 is formed after the insulating layer 112 is formed. However, the process may also involve forming the insulating layer 112 after forming the impurity region 114.

[0084] Next, the sidewall insulating layer 118 is formed (see Figure 4(D)). Layer 118 is formed to cover the insulating layer 112, and then an anisotropic high layer is added to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110 and the impurity region 1 It's best to expose the top surface of part 14.

[0085] Next, to cover the gate electrode 110, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed in the region in contact with the impurity region 114. Adding substances such as As (see Figure 4(E)) creates a high-concentration impurity region 120. The above insulating layer is removed, and the gate electrode 110, sidewall insulating layer 118, high concentration impurities A metal layer 122 is formed to cover region 120, etc. (see Figure 4(E)). 2 is formed using various film deposition methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 reacts with the semiconductor material constituting the semiconductor region 104. It is desirable to form it using a metal material that forms a low-resistance metal compound. Examples of materials include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc. be.

[0086] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 4(F)). Furthermore, when using polycrystalline silicon or the like as the gate electrode 110, A metal compound region will also be formed in the area that comes into contact with the metal layer 122.

[0087] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that can achieve heat treatment in a very short time. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0088] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 4(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnitex oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic resin. It has a two-layer structure consisting of an interlayer insulating layer 126 and an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is as follows Not limited. After the formation of the interlayer insulating layer 128, its surface may be treated with CMP or etching. It is desirable to flatten it out by doing so.

[0089] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening Then, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected. Form (see Figure 4(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed using methods such as etching or CMP. It can be formed by removing [something].

[0090] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the formation surface (such as the native oxide film) is reduced, and the lower electrode (here, the metal compound region 124) It has the function of reducing contact resistance with ). Furthermore, the titanium nitride film formed thereafter is It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by a plating method.

[0091] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. It removes essential elements such as tungsten, titanium, and titanium nitride, while also improving the flatness of the surface. This can be done. In this way, the source electrode or drain electrode 130a, source electrode Alternatively, by planarizing the surface including the drain electrode 130b, a good result can be obtained in a later process. This makes it possible to form suitable electrodes, wiring, insulating layers, semiconductor layers, and so on.

[0092] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, An electrode 130c that comes into contact with the source electrode 110 can be formed together. It can be used as an electrode or drain electrode 130a, or a source electrode or drain electrode 130b. There are no particular limitations on the materials that can be used; various conductive materials can be used. For example, Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Conductive materials such as scandium can be used. Furthermore, the subsequent heat treatment must be taken into consideration. Then, source electrode or drain electrode 130a, source electrode or drain electrode 130b It is desirable to form it using a material that has sufficient heat resistance to withstand subsequent heat treatment. It seems so.

[0093] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material (Figure See 4(H). Furthermore, electrodes, wiring, insulating layers, etc., may be formed after the above process. Good. The wiring structure employs a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers. This makes it possible to provide highly integrated semiconductor devices.

[0094] <Method for fabricating the upper transistor> Next, using Figure 5, we will describe the process of fabricating the transistor 162 on the interlayer insulating layer 128. Let me explain. Figure 5 shows various electrodes on the interlayer insulating layer 128, and transistors such as 162. This shows the manufacturing process, so transistor 16 is located below transistor 162. Details regarding the 0th grade are omitted.

[0095] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 138 is formed on the rain electrode 130b and electrode 130c. The insulating layer 138 is PVD It can be formed using methods such as the CVD method. Also, silicon oxide, silicon oxide nitride Inorganic insulating materials such as silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide. It can be formed using a material containing the above. Note that the insulating layer 138 is of the transistor 162 It functions as a base layer. An insulating layer 138 does not need to be provided.

[0096] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c (see Figure 5(A)). The opening can be formed by methods such as etching using a mask. The mask is It can be formed by exposure using a photomask, etc., as etching. Either wet etching or dry etching can be used, but from the perspective of microfabrication... Dry etching is preferable in this case. Therefore, this step can be omitted.

[0097] Next, source electrode or drain electrode 142a, source electrode or drain electrode 142b , form electrodes 142c and 142d (see Figure 5(B)). Source electrode or Dray electrode 142a, source electrode or drain electrode 142b, electrode 142c, electrode 142d This involves forming a conductive layer to cover the insulating layer 138, and then selectively etching the conductive layer. It can be formed by doing so.

[0098] The conductive layer is created using PVD methods such as sputtering, and CVD methods such as plasma CVD. It can be formed using the method. Furthermore, aluminum and chromium can be used as materials for the conductive layer. Elements selected from copper, tantalum, titanium, molybdenum, and tungsten, as mentioned above. Alloys and the like containing elements can be used. Examples include manganese, magnesium, and zirconium. Materials selected from beryllium and thorium, one or more of the above, may be used. In addition to aluminum, titanium, tantalum, tungsten, molybdenum, chromium, and neodymium are also used. Alternatively, materials consisting of one or more elements selected from scandium may be used. The conductive layer may be a single layer or a laminated structure of two or more layers. For example, sil A single-layer structure of an aluminum film containing condensate, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked.

[0099] Furthermore, the conductive layer may be formed using a conductive metal oxide. These include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and oxide Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxidation Indium zinc oxide alloy (In2O3-ZnO), or these metal oxide materials Products containing lycon or silicon oxide can be used.

[0100] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance from the lower end of the source electrode or drain electrode 142b. If the length (L) is less than 25 nm, then the wavelength is ultra-ultraviolet (Ex) from a few nm to a few tens of nm. It is recommended to form the etching mask using treme ultraviolet. . Exposure with extreme ultraviolet has high resolution and a large depth of focus. Therefore, a pa ttern of less than 25 nm can be formed, and the channel length (L) of a transistor can be set to 1 nm or more and 1 000 nm or less. Transistors with such a small channel length are preferable because they achieve high circuit operation speed and reduced power consumption.

[0101] Further, it is preferable that the end portions of the source or drain electrode 142a and the source or drain electrode 1 42b are formed to have a tapered shape. This is because by making the end portions of the source or drain electrode 142a and the source or drain electrode 142b have a tapered shape, the coverage of an oxide semiconductor layer to be formed later can be improved, and disconnection can be prevented. Here, the taper angle is preferably, for example, 30° or more and 60° or less. Note that the taper angle refers to an inclination angle formed by a side surface and a bottom surface of a layer having a tapered shape (e.g., the source or drain electrode 142a) when the layer is observed from a direction perpendicular to its cross section (a plane perpendicular to the surface of a substrate).

[0102] Next, after an oxide semiconductor layer is formed to cover the source or drain electrode 142a, the source or drain electrode 142b and the like by a method such as etching using a mask, the oxide semiconductor layer is processed to form an island-shaped oxide semiconductor layer 140 (see FIG. 5 (C )).

[0103] The oxide semiconductor layer is preferably formed by a sputtering method. The oxide semiconductor layer is an In-Sn-Ga-Zn-O-based quaternary metal oxide or a ternary metal oxide ​​In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O systems, Al-Ga-Zn-O systems, Sn-Al-Zn-O systems, and binary metal oxides The materials are In-Zn-O, Sn-Zn-O, Al-Zn-O, and Zn-Mg-O. Gold systems such as Sn-Mg-O, In-Mg-O, In-O, Sn-O, and Zn-O. It can be formed using metal oxides. Note that silicon can also be added to the metal oxide. Good. For example, using a target containing 2% to 10% by weight of SiO2, an oxide semi-oxide A conductive layer may be formed.

[0104] In particular, by using In-Ga-Zn-O metal oxides, the resistance in the absence of an electric field is sufficiently high. To form a semiconductor device with high (sufficiently small) off-current and high field-effect mobility. This is possible. In this respect, In-Ga-Zn-O metal oxides are semiconductors used in semiconductor devices. It is suitable as a material.

[0105] A typical example of an In-Ga-Zn-O metal oxide is InGaO3(ZnO). m (m Some are represented as >0). Also, M is used instead of Ga, such as InMO3(ZnO). m There are metal oxides that are expressed as (m>0). Here, M is gallium (Ga), and Aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (C) o) indicates one or more metallic elements selected from the above. For example, M is: Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co and other elements can be applied. Note that the above composition is derived from the crystal structure. Yes, but I must add that this is merely one example.

[0106] In this embodiment, the oxide semiconductor layer is an In-Ga-Zn-O-based metal oxide target. The formation will be carried out by a sputtering method using [specific technology / method].

[0107] The formation of the oxide semiconductor layer involves holding the substrate in a processing chamber under reduced pressure and controlling the substrate temperature. Preferably, 100°C to 600°C, more preferably 200°C to 400°C. This is done. Here, by forming an oxide semiconductor layer while heating the substrate, the oxide semiconductor The concentration of impurities in the layer can be reduced, and the oxide semiconductor layer produced by sputtering can be reduced. Damage can be reduced.

[0108] The formation atmosphere for the oxide semiconductor layer is designed to sufficiently reduce impurities such as hydrogen, water, hydroxyl groups, and hydrides. A noble gas atmosphere (typically argon), an oxygen atmosphere, or a noble gas atmosphere (typically A mixed atmosphere of argon and oxygen is preferred. Specifically, for example, hydrogen and water Impurities such as hydroxyl groups and hydrides are present at a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high-purity gas atmosphere in which impurities have been removed to the level of )

[0109] In this case, it is preferable to use an adsorption-type vacuum pump to remove residual moisture from the processing chamber. For example, using cryopumps, ion pumps, and titanium sublimation pumps. This can be done. Furthermore, as an exhaust method, a cold trap can be added to the turbomolecular pump. It may also be made of a cryopump. The deposition chamber, which has been evacuated using a cryopump, for example, contains hydrogen atoms, Water (H2O) and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Since the gas is exhausted, the concentration of impurities contained in the oxide semiconductor layer formed in the film forming chamber can be reduced .

[0110] The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that an appropriate thickness differs depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material to be used.

[0111] Further, by using a pulsed direct current (DC) power supply when forming the oxide semiconductor layer, particles (powdery or flaky substances formed during film formation) can be reduced, and the film thickness distribution can also be made uniform .

[0112] Note that, as sputtering film formation conditions for the oxide semiconductor layer, for example, for the distance between the substrate and the target of 170 mm, a pressure of 0.4 Pa, a direct current (DC) power of 0.5 kW, and an atmosphere of oxygen (oxygen flow rate ratio: 100%) atmosphere, such conditions can be applied.

[0113] Note that before forming the oxide semiconductor layer by a sputtering method, argon gas is introduced to perform reverse sputtering that generates plasma, and particles adhering to the surface of the insulating layer 138 are removed , which is preferable. Here, reverse sputtering refers to that in normal sputtering, ions are caused to collide with a sputtering target, and conversely, ions are caused to collide with the surface to be treated to modify the surface by such collision. As a method for causing ions to collide with the treatment surface , there is a method of applying a high-frequency voltage to the treatment surface side in an argon atmosphere to generate plasma in the vicinity of the substrate. Note that nitrogen, helium, oxygen or the like may be used instead of the argon atmosphere. ​

[0114] The above oxide semiconductor layer can be etched using either dry etching or wet etching. You may also use this. Of course, you can also use both in combination. To create the desired shape... To enable etching, etching conditions (etching gas, etching solution, etc.) can be adjusted according to the material. You can set the timing time, temperature, etc. as appropriate.

[0115] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), and carbon tetrachloride. Examples include fluorine (CCl4, etc.). Also, fluorine-containing gases (fluorinated gases, for example, tetrafluorine) Carbon dioxide (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and helium (H) in these gases. e) or gases to which noble gases such as argon (Ar) have been added may also be used.

[0116] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0117] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there.

[0118] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the removal of impurities such as hydrogen from the oxide semiconductor layer. If performed after etching, even when using wet etching, etching One advantage is that the time required can be reduced. The temperature of the first heat treatment is 30 The temperature should be between 0°C and 750°C, preferably between 400°C and 700°C. For example, resistance heating A substrate is introduced into an electric furnace using a body, and the oxide semiconductor layer 140 is subjected to a nitrogen atmosphere 45 A heat treatment is performed at 0°C for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the atmosphere. In addition, the first heat treatment temperature is set to prevent the re-introduction of hydrogen (including water, etc.). The degree should preferably be determined considering the heat resistance of the electrodes and wiring of the lower-layer transistor 160. It's nice.

[0119] Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, or It may also be a device that heats the object to be processed by thermal radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) for Thermal Anneal devices, etc. A device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp such as a silver lamp. Yes, there is. A GRTA device is a device that performs heat treatment using high-temperature gas. As for the gas, Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment. A gas is used.

[0120] For example, as a first heat treatment, a substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C. After adding the inert gas and heating for several minutes, the substrate is removed from the inert gas in a GRTA treatment. It is also possible to use GRTA treatment, which allows for high-temperature heat treatment in a short time. Because it is a heat treatment, when using substrates with low heat resistance such as glass substrates, the substrate distortion It can be applied even under temperature conditions exceeding the 3°C point.

[0121] Furthermore, the first heat treatment mainly uses nitrogen or noble gases (helium, neon, argon, etc.) It is desirable to carry out the procedure in an atmosphere that does not contain hydrogen, water, etc. For example The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the heat treatment apparatus, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0122] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may result in a semiconductor layer containing crystalline components. Also, depending on the conditions of the first heat treatment, or oxidation Depending on the material of the semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. be.

[0123] Furthermore, by providing a crystalline layer on the amorphous surface, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to form a crystal layer in which electrically anisotropic crystal grains are oriented. This allows us to change the electrical properties of the oxide semiconductor layer.

[0124] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0125] Furthermore, is the above heat treatment effective in dehydrogenating (dehydrating) the oxide semiconductor layer 140? This can also be called dehydrogenation treatment (dehydration treatment). Such treatments are used for oxide semiconductors. After forming the conductive layer, an insulating layer (such as a gate insulating layer) is laminated on the oxide semiconductor layer 140. This can be done at any point, such as after the gate electrode has been formed. Furthermore, this process can be performed multiple times, not just once.

[0126] Furthermore, by controlling the atmosphere involved in the formation of the oxide semiconductor layer, hydrogen can be sufficiently supplied. In cases where a reduced oxide semiconductor layer can be obtained, the first heat treatment can be omitted. It is also possible.

[0127] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. This may be done. The plasma treatment causes adhesion to the surface of the exposed oxide semiconductor layer. It can remove water and other substances. It can also remove oxygen-containing gases such as mixed gases of oxygen and argon. Plasma treatment using a gas may be performed. This supplies oxygen to the oxide semiconductor layer. By supplying oxygen, it is possible to reduce defect levels in the energy gap caused by oxygen deficiency. .

[0128] Next, source electrode or drain electrode 142a, source electrode or drain electrode 142b An insulating layer 144 is formed above the oxide semiconductor layer 140, and the area where the gate electrode is formed An opening is formed in a part of the region, and in a part of the region where the electrodes of the capacitive element are formed. After forming the gate insulating layer 146 to cover the region including the opening, the gate electrode 148a and electrode 148b is formed (see Figure 5(D)). The opening of the insulating layer 144 is made using a mask. It can be formed by methods such as etching. Electrode gate 148a and electrode After forming a conductive layer over the gate insulating layer 146, pole 148b selects the conductive layer. It can be formed by etching the target.

[0129] The insulating layer 144 and the gate insulating layer 146 are formed using methods such as CVD or sputtering. It is possible to do so. In addition, the insulating layer 144 and the gate insulating layer 146 are made of silicon oxide, nitrogen Silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. It is preferable to form it to include the following: The insulating layer 144 and the gate insulating layer 146 are single layers It is good as a structural element, and it is also good as a laminated structure. Furthermore, its thickness is not particularly limited, but for example... For example, it can be between 10 nm and 500 nm. Note that the insulating layer 144 is of the electrode It is provided to reduce capacitance caused by overlapping, etc. For example, the insulating layer 144 is formed By doing so, the source electrode or drain electrode 142a and the gate electrode 148a This reduces the capacity.

[0130] The insulating layer 144 and the gate insulating layer 146 are constructed using a method that makes it difficult for impurities such as hydrogen and water to be mixed in. It is preferable to form it using the following: The insulating layer 144 and the gate insulating layer 146 contain hydrogen. This involves the penetration of hydrogen into the oxide semiconductor layer and the extraction of oxygen from the oxide semiconductor layer by hydrogen. This is because such problems may occur.

[0131] For example, when the insulating layer 144 and the gate insulating layer 146 are formed by sputtering. The sputtering gas contains impurities such as hydrogen, water, hydroxyl groups, or hydrides, at a concentration of 1 pp. A high-purity gas, which has been removed to approximately m (preferably to a concentration of approximately 10 ppb), is used. It is desirable to remove any residual moisture from the processing room.

[0132] Furthermore, as shown in this embodiment, the oxide semiconductor is intrinsically purified by the removal of impurities. Conductors (highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, when using such an oxide semiconductor in the oxide semiconductor layer, the boundary with the gate insulating layer The surface becomes important. For this reason, the gate insulating layer 146 in contact with the highly purified oxide semiconductor layer This will require a high level of quality.

[0133] For example, high-density plasma CVD using μ-waves (frequency 2.45 GHz) produces dense and insulating materials. It is preferable in that it can form a high-quality gate insulating layer 146 with high voltage resistance. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can improve sexual performance.

[0134] Of course, if a good insulating layer can be formed as a gate insulating layer, then highly purified acid Even when using a synthetic semiconductor layer, other methods such as sputtering and plasma CVD are used. The law can be applied. Furthermore, the film quality and interface properties can be modified by heat treatment after formation. An insulating layer may be applied. In any case, the film quality is good, and the oxide semiconductor layer A gate insulating layer 146 can be formed to reduce the interface state density.

[0135] In this embodiment, the insulating layer 144 and the gate insulating layer 146 contain silicon oxide. The insulating layer will be formed by the sputtering method.

[0136] After forming the insulating layer 144, or after forming the gate insulating layer 146, an inert gas atmosphere A second heat treatment (preferably between 200°C and 400°C) is performed under ambient air or an oxygen gas atmosphere. It is desirable to perform the procedure at a temperature of, for example, between 250°C and 350°C. For example, under a nitrogen atmosphere at 25 A second heat treatment is performed at 0°C for 1 hour. After the second heat treatment, the electrical characteristics of the transistor are improved. This can reduce variations. In addition, the second heat treatment removes the oxygen-containing insulating layer. Oxygen is supplied to the oxide semiconductor layer, and defect levels in the energy gap caused by oxygen deficiency It is also possible to reduce this. Note that the heat treatment atmosphere is not limited to the above; it can also be an atmospheric atmosphere, etc. This is also acceptable. However, in that case, hydrogen must not be mixed into the oxide semiconductor layer. It is desirable to create an atmosphere from which water and other substances have been removed. Also, the second heat treatment is an essential step. It's not there, so you can omit it.

[0137] The conductive layers that form the gate electrode 148a and electrode 148b are formed by sputtering, among other methods. It can be formed using PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) methods such as plasma CVD. For details, see below. This is the same as in the case of source electrode or drain electrode 142a, and these descriptions should be taken into consideration. can.

[0138] Etching to form openings in the insulating layer 144, and forming gate electrode 148a, etc. For etching, either dry etching or wet etching can be used. Of course, both can be used in combination. Etching conditions (etching gas, etching solution, etching time, temperature) are determined according to the material. You can set the degree, etc., as appropriate.

[0139] Next, a protective insulating layer 150 and an interlayer insulating layer 152 are formed (see Figure 5(E)).

[0140] The protective insulating layer 150 and the interlayer insulating layer 152 are formed using methods such as PVD or CVD. It can also be made from silicon oxide, silicon oxide nitride, silicon nitride, hafnium oxide, acid It can be formed using materials containing inorganic insulating materials such as aluminum oxide and tantalum oxide. ru.

[0141] Furthermore, the protective insulating layer 150 is located relatively close to the oxide semiconductor layer 140. Therefore, it is formed using methods that are less likely to introduce impurities such as hydrogen and water, such as sputtering. It is preferable to do so.

[0142] Furthermore, it is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that it becomes flat, electrodes and This is because it allows for the formation of wiring and other components in a suitable manner.

[0143] Note that the protective insulating layer 150 and the interlayer insulating layer 152 are not essential components and can be omitted as needed. It's okay to abbreviate it.

[0144] With the above steps, the transistor 162 and the capacitive element 164 using oxide semiconductors are completed. (See Figure 5(E)).

[0145] The transistor 162 made using an oxide semiconductor by the method described above has an off-current of It is characterized by being extremely small. For example, a sufficiently intrinsically carbonated (type i) oxide semiconductor. In the body, the carrier density is, for example, 1 × 10⁻⁶. 12 / cm 3 Less than, preferably 1.45 × 10 10 / cm 3 The off-current of the transistor is less than, for example, the drain voltage Vd is In the case of +1V or +10V, and when the gate voltage Vg is in the range of -5V to -20V , 1 x 10 -13 The result will be A or less. Therefore, a sufficient information retention period must be ensured for semiconductor devices. This is possible. Furthermore, when using a sufficiently intrinsically purified oxide semiconductor, at room temperature... Leakage current is 1 × 10 -20 From approximately A (10 zA (zeptamperes)) to 1 × 10 -19 It can be reduced to A (100 Hz). In other words, the leakage current can be made virtually zero. It is also possible to do so. By using such oxide semiconductors, the information retention period can be extended. We can provide semiconductor devices with sufficient capacity.

[0146] Furthermore, by forming a capacitive element 164 together, the gate electrode of the transistor 160 is formed This makes it easier to retain the given charge and easier to read the stored contents. In particular, in this implementation In the method shown in the form, it is not necessary to increase the number of steps in order to form the capacitive element 164. Therefore, it is suitable from the standpoint of cost reduction, etc.

[0147] In this embodiment, a transistor using a material other than an oxide semiconductor and an oxide semiconductor are used. We have described a semiconductor device relating to a stacked structure (2 layers) with a transistor using a body, but The structures that can be used in the invention described are not limited to the laminated structure. That's fine, and a laminated structure of three or more layers is also fine.

[0148] Furthermore, the arrangement and connection relationships of electrodes (wiring), insulating layer, semiconductor layer, wiring width, channel width, etc. Channel length and other parameters, as well as other conditions, are required for semiconductor integrated circuits. It is possible to change it as appropriate depending on the function. For example, forming a semiconductor device with a single-layer structure The configuration of electrodes and wiring in this case differs significantly from that in the case of a laminated structure.

[0149] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0150] (Embodiment 2) In this embodiment, a semiconductor device with a configuration different from that of the semiconductor device shown in the previous embodiment is used. The placement and manufacturing method will be explained with reference to Figures 6 and 7. The configuration and manufacturing process of the semiconductor device are largely the same as in Embodiment 1. Therefore, in the following, we will omit explanations of overlapping parts and explain the differences in detail. ru.

[0151] <Planar and cross-sectional configurations of semiconductor devices> Figure 6 shows an example of the configuration of a semiconductor device. Figure 6(A) shows a cross-section of the semiconductor device, and Figure 6( Figure B) shows the planes of the semiconductor device. Here, Figure 6(A) is the same as A in Figure 6(B). This corresponds to the cross-sections at 3-A4 and B3-B4, as shown in Figures 6(A) and 6(B). The semiconductor device, as in Figures 1(A) and 1(B), has a lower section made of a material other than an oxide semiconductor. It has a transistor 160 made of a material, and a transistor 16 made of an oxide semiconductor on top. The semiconductor device shown in this embodiment has an insulating layer 2 and a capacitive element 164. Because the structure does not include 144, the manufacturing process is different compared to the semiconductor device shown in Figure 1(A). The process is simplified, and manufacturing costs are reduced. To reduce the amount, an insulating layer 144 may be provided.

[0152] The transistor 162 shown in Figure 6(A) has an oxide semiconductor layer 1 provided on the insulating layer 138. 40 and the source electrode or drain electrode electrically connected to the oxide semiconductor layer 140. 142a, and source electrode or drain electrode 142b, and source electrode or drain Electrode 142a, and source electrode or drain electrode 142b, oxide semiconductor layer 140 The gate insulating layer 146 covers the gate, and the oxide semiconductor layer 140 is superimposed on the gate insulating layer 146. It has a gate electrode 148a provided therein. Note that the transistor shown in Figure 6(A) 162 is a top-gate type, and the oxide semiconductor layer 140 and the source electrode or drain The connection with the in electrode 142a, etc., is made in a region including the upper surface of the oxide semiconductor layer 140. Because it is designed this way, it can be called a top-gate, top-contact type.

[0153] <Methods for fabricating semiconductor devices> Next, an example of a method for manufacturing the above semiconductor device will be described. In the following, the upper transistor The method for manufacturing transistor 162 will be explained with reference to Figure 7. Note that the lower transistor 16 The method for producing 0 is the same as the method shown in Figure 4, so it will be omitted.

[0154] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 138 is formed on the rain electrode 130b and electrode 130c, and relative to the insulating layer 138, Source electrode or drain electrode 130a, source electrode or drain electrode 130b, electrode An opening reaching 130c is formed (see Figure 7(A)). Material and formation method of insulating layer 138 The method can be seen in Figure 5(A), so the explanation will be omitted. Also, the above-mentioned opening is It can be formed by methods such as etching using a squeegee.

[0155] Next, an oxide semiconductor layer is formed on the insulating layer 138, and etching is performed using a mask. By this method, the oxide semiconductor layer is processed to form island-shaped oxide semiconductor layers 140. See Figure 7(B). The material and formation method of the island-shaped oxide semiconductor layer 140 are shown in Figure 5(C). Since it can be referenced, the explanation will be omitted.

[0156] Next, the insulating layer 138, the openings provided in the insulating layer 138, and the island-shaped oxide semiconductor layer 1 A conductive layer is formed to cover 40, and the conductive layer is then processed by methods such as etching using a mask. The electrode layer is processed to form a source electrode or drain electrode 142a that contacts the oxide semiconductor layer 140. , forming source electrode or drain electrode 142b, electrode 142c and electrode 142d And, source electrode or drain electrode 142a, source electrode or drain electrode 14 2b, form a gate insulating layer 146 so as to cover electrode 142c and electrode 142d. See Figure 7(C). Source electrode or drain electrode 142a, source electrode or drain The materials and forming methods for electrodes 142b, 142c, and 142d are shown in Figure 5(B). Since it can be referenced, the explanation will be omitted. Also, the material and shape of the gate insulating layer 146. The method can be seen in Figure 5(D), so the explanation will be omitted.

[0157] Next, a conductive layer is formed on the gate insulating layer 146, and etching using a mask is performed. The conductive layer is processed according to the method to form the gate electrode 148a and the electrode 148b (Figure 7). (See (D)). The materials and formation methods of the gate electrode 148a and electrode 148b are shown in Figure 5(D). Since you can refer to [the relevant source], I will omit the explanation.

[0158] Next, protective insulation covering the gate insulating layer 146, gate electrode 148a, and electrode 148b. An edge layer 150 and an interlayer insulating layer 152 are formed (see Figure 7(E)). Protective insulating layer 150 and The material and formation method of the interlayer insulating layer 152 can be found in Figure 5(E). The "Akira" part will be omitted.

[0159] Based on the above, the semiconductor device shown in Figure 6 can be fabricated.

[0160] (Embodiment 3) In this embodiment, a semiconductor device is formed using multiple semiconductor devices shown in Embodiment 1. An example of the circuit configuration and operation will be explained using Figures 8 and 9.

[0161] <Circuit configuration and operation of semiconductor devices> Figures 8(A) and 8(B) show the semiconductor device (hereinafter referred to as memory cell 19) shown in Figure 3(A-1). This is a circuit diagram of a semiconductor device formed using multiple (also written as 0). Figure 8(A) is This is a circuit diagram of a NAND-type semiconductor device in which memory cells 190 are connected in series, as shown in Figure 8(B). This is a circuit diagram of a NOR-type semiconductor device in which memory cells 190 are connected in parallel.

[0162] The semiconductor device shown in Figure 8(A) has a source line SL, a bit line BL, a first signal line S1, and a second signal line. It has line S2, word line WL, and multiple memory cells 190. The gate electrode of transistor 160 and the source electrode or drain electrode of transistor 162 One electrode of the 164 and one electrode of the capacitive element 164 are electrically connected. 1. The signal line S1 and the other of the source or drain electrode of transistor 162 are electrically connected. The second signal line S2 and the gate electrode of transistor 162 are electrically connected. And the word line WL and the other electrode of the capacitive element 164 are electrically connected. Yes, they are.

[0163] Furthermore, the source electrode of the transistor 160 of the memory cell 190 is adjacent to the memory cell The drain electrode of transistor 160 is electrically connected to the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. It is electrically connected to 160 source electrodes. However, it is connected in series to multiple memory cells. Of these, the drain of the transistor 160 of the memory cell 190 located at one end The electrodes are electrically connected to the bit lines. Also, multiple memory cells connected in series... The source electrode of the transistor 160 of the memory cell 190 located at the other end is It is electrically connected to the source line. Note that in Figure 8(A), the source line SL and the bit line B are shown. The configuration has one L each, but is not limited to this, and source lines SL and B A configuration with multiple BL wires is also possible.

[0164] The semiconductor device shown in Figure 8(A) performs line-by-line writing and reading operations. The operation is performed as follows: Transistor 16 is connected to the second signal line S2 of the line to be written. By applying a potential that turns on transistor 2, the transistor 162 of the row to be written is turned on. This allows the first signal line S1 to be transmitted to the gate electrode of transistor 160 in the specified row. A position is given, and a predetermined charge is applied to the gate electrode. In this way, the specified row Data can be written to the memory cell.

[0165] Furthermore, the reading operation is performed as follows: First, the word lines WL other than the line to be read. Regardless of the charge of the gate electrode of transistor 160, transistor 160 is in the ON state. By applying a suitable potential, the transistors 160 other than those in the row being read are turned ON. Then, a constant potential is applied to the source line SL, and the bit line BL is read out by a circuit (not shown in the diagram). Connect to the following. Here, multiple transistors 160 between the source line SL and the bit line BL are read. Except for the lines where the output is performed, the conduction between the source line SL and the bit line BL is on. The state is determined by the state of transistor 160 of the row being read. The charge on the gate electrode of transistor 160 in the row that performs the output causes the readout circuit The potential of the bit line BL being read is different. In this way, data is obtained from the memory cell of the specified row. The data can be read.

[0166] Next, the semiconductor device shown in Figure 8(B) has a source line SL, a bit line BL, and a first signal line S1. It has multiple second signal lines S2 and multiple word lines WL, and multiple memory cells 190. The gate electrode of each transistor 160 and the source electrode or dot of transistor 162. One of the rain electrodes and one of the electrodes of the capacitive element 164 are electrically connected. The source line SL and the source electrode of transistor 160 are electrically connected, and the bit line B L and the drain electrode of transistor 160 are electrically connected. Also, the first signal The wire S1 is electrically connected to the other of the source or drain electrode of transistor 162. Furthermore, the second signal line S2 and the gate electrode of transistor 162 are electrically connected. Furthermore, the word line WL and the other electrode of the capacitive element 164 are electrically connected.

[0167] The semiconductor device shown in Figure 8(B) performs line-by-line writing and reading operations. The reading operation is performed in the same manner as the semiconductor device shown in Figure 8(A) above. The process is as follows: First, the word line WL of the row to be read is connected to transistor 160. The ON or OFF state of transistor 160 is selected based on the charge present in the gate electrode. Apply a potential such that the following occurs. Then, apply a constant potential to the source line SL and read the bit line BL. It is connected to the output circuit (not shown). Also, transistor 160 in the unselected row is in the OFF state. This is the state. Here, the conductance between the source line SL and the bit line BL is read out. This is determined by the state of transistor 160 in the row. In other words, the state of the transistor in the row being read. The potential of the gate electrode of ZISTA 160 determines the potential of the bit line BL read by the read circuit. They are different. In this way, data can be read from the memory cell of the specified row. .

[0168] The semiconductor devices shown in Figures 8(A) and 8(B) use transistors made of materials other than oxide semiconductors. Because the ZISTA 160 is capable of sufficiently high-speed operation, it can perform tasks such as reading stored data at high speed. This is possible. Furthermore, the oxide semiconductor transistor 162 has an extremely small off-current. It has the characteristic of being such. Therefore, by turning off transistor 162, It is possible to maintain the potential of the gate electrode of transistor 160 for an extremely long period of time. It is present. And, by having a capacitive element 164, the gate electrode of transistor 160 This makes it easier to retain the given charge and to read the stored contents.

[0169] By the way, in a semiconductor device composed of multiple memory cells as described above, the storage capacity per In order to reduce the unit cost, the challenge is to reduce the area occupied by each memory cell. To solve this problem, for example, in the NAND type semiconductor device shown in Figure 8(A) The transistors 160 connected in series are configured as shown in the cross-sectional view in Figure 9(A). This reduces the area occupied by each memory cell. Note that Figure 9(A) is shown in Figure 9 This corresponds to the cross-sections C1-C2 and D1-D2 in (B).

[0170] The semiconductor device shown in Figure 9(A) has a transistor 160 provided on a substrate 100 that is high concentration The impurity region 120 (also simply called the impurity region) and the metal compound region 124 are adjacent to each other. The configuration is such that it is connected to transistor 160. The high-concentration impurity region 120 and the metal compound region 124 are the source of one of the transistors 160. It functions as both a region and the drain region of the other transistor 160.

[0171] Furthermore, interlayer insulating layers 126 and 128 are formed to cover the transistor 160. It is also done. At the ends of multiple transistors 160 connected in series, the interlayer insulating layer 12 Through the openings formed in 6 and the interlayer insulating layer 128, the metal compound region 124 is electrically connected. The connected electrode 192 is formed.

[0172] Here, transistor 160 is almost the same as transistor 160 shown in Figure 1 of Embodiment 1. Since it will take this form, you can refer to that for details. However, the form of this implementation In this configuration, in order to achieve high integration of transistor 160, the sidewall insulating layer 1 shown in Figure 1 is used. The configuration does not include 18.

[0173] Furthermore, the configuration shown in Figure 9(A) is not limited to the NAND type semiconductor device shown in Figure 8(A), It can also be used in NOR-type semiconductor devices as shown in Figure 8(B). For example, in Figure 8(B) In this configuration, the memory cells of adjacent columns are arranged symmetrically, and the memory cells of adjacent columns Transistor 160 of the r is connected via a high-concentration impurity region 120 and a metal compound region 124. The configuration should be such that they are connected. In this case, at least two transistors 160 These will be connected via a high-concentration impurity region 120 and a metal compound region 124.

[0174] By connecting multiple transistors 160 in the configuration described above, transistor 16 This allows for high integration of 0 and memory cells 190. This enables the storage of semiconductor devices. This allows us to reduce the cost per unit volume.

[0175] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0176] (Embodiment 4) Next, Figure 10 shows a modified example of the configuration of a semiconductor device.

[0177] The semiconductor device shown in Figure 10(A) is a modified example of the semiconductor device shown in Figure 1(A).

[0178] The difference between the configuration shown in Figure 10(A) and the configuration shown in Figure 1(A) is that the electrode 130c is on the substrate 10 The point is that it is electrically connected to the metal compound region located at 0. In other words, Figure 1(A) In the configuration shown, the source electrode or drain electrode 142a and the gate electrode 110 are electrically connected. In contrast to being connected to the source electrode or drain, in the configuration shown in Figure 10(A), the source electrode or drain is connected to the drain. Electrode 142a and the metal compound region are electrically connected.

[0179] By adopting the configuration shown in Figure 10(A), the semiconductor device shown in the previous embodiment is different from the semiconductor device shown in Figure 10(A). This enables the realization of semiconductor devices with different circuit configurations.

[0180] The semiconductor device shown in Figure 10(B) is a modified version of the semiconductor device shown in Figure 6(A).

[0181] The difference between the configuration shown in Figure 10(B) and the configuration shown in Figure 6(A) is that the electrode 130c is on the substrate 10 The point of electrical connection is the metal compound region located at 0. In other words, Figure 6(A) In the configuration shown, the source electrode or drain electrode 142a and the gate electrode 110 are electrically connected. In contrast to being connected to the source electrode or drain, in the configuration shown in Figure 10(B), the source electrode or drain is connected to the drain. Electrode 142a and the metal compound region are electrically connected.

[0182] By adopting the configuration shown in Figure 10(B), the semiconductor device shown in the previous embodiment is different from the one shown in Figure 10(B). This enables the realization of semiconductor devices with different circuit configurations.

[0183] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0184] (Embodiment 5) Next, the transistor 162, etc., used in the previous embodiment (Embodiment 1, etc.) Another example of a method for fabricating transistors using oxide semiconductors is shown in Figure Refer to Section 11 for further explanation. In this embodiment, highly purified oxide semiconductors (especially amorphous) The following will explain in detail the case where the structure is used. I will explain using transistors as an example, but it is not necessary to limit the transistor configuration to the top-gate type. stomach.

[0185] First, an insulating layer 202 is formed on the lower substrate 200. Then, an oxide layer is formed on the insulating layer 202. A semiconductor layer 206 is formed (see Figure 11(A)).

[0186] For example, the lower substrate 200 is in the semiconductor device of the previous embodiment (Figure 1 or Figure 6, etc.) This can be a structure located below the interlayer insulating layer 128. For details, see the previous example. The form of the installation can be taken into consideration. Furthermore, the surface of the lower substrate 200 is as flat as possible. This is desirable. For example, by chemical mechanical polishing (CMP) or the like, the difference in surface height can be reduced. It should be 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness. The (RMS) should be 2 nm or less, preferably 0.4 nm or less.

[0187] The insulating layer 202 functions as a base layer, and the insulating layer 138 in the previous embodiment and It can be formed in the same manner as the insulating layer 144, etc. For details, please refer to the previous embodiment. Just pour it in. Furthermore, the insulating layer 202 should be formed in such a way that it contains as little hydrogen and water as possible. That would be preferable.

[0188] The oxide semiconductor layer 206 is made of a quaternary metal oxide such as the In-Sn-Ga-Zn-O system, or a three-component system. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system It can be formed using oxide semiconductors such as Zn-O systems.

[0189] In particular, In-Ga-Zn-O oxide semiconductor materials have sufficiently high resistance in the absence of an electric field. Because the current can be made sufficiently small, and the field effect mobility is also high, semiconductors It is suitable as a semiconductor material for use in the device.

[0190] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m Some are expressed as (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are expressed as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), This indicates one or more metallic elements selected from cobalt (Co), etc. For example, For M, we have Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn Ga and Co can be applied. Note that the above composition is derived from the crystal structure. It should be noted that this is merely one example, and not the only possible outcome.

[0191] For fabricating the oxide semiconductor layer 206 by sputtering, the target is: A compound represented by the empirical formula Ga:Zn=1:x:y (where x is greater than or equal to 0, and y is greater than or equal to 0.5 and less than or equal to 5). You can use this. For example, In:Ga:Zn=1:1:1 [atom ratio] (x=1, y= 1) (i.e., In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio]) Targets with specific composition ratios may also be used. Also, In:Ga:Zn = 1:1:0.5 Targets with a composition ratio of [atom ratio] (x=1, y=0.5), or In:Ga:Z Targets having a composition ratio of n=1:1:2 [atom ratio] (x=1, y=2), or In A target having a composition ratio of :Ga:Zn=1:0:1 [atom ratio] (x=0, y=1) You can also use "t".

[0192] The relative density of metal oxides in the metal oxide target is 80% or more, preferably 95% or more. More preferably, it is 99.9% or higher. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer 206 with a dense structure.

[0193] In this embodiment, the amorphous oxide semiconductor layer 206 is made of an In-Ga-Zn-O gold The material will be formed by sputtering using an oxide target.

[0194] The formation atmosphere for the oxide semiconductor layer 206 is a noble gas atmosphere (typically argon), an oxygen atmosphere. A gaseous atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen, is preferable. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides must be present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the gas has been removed to a concentration of 10 ppb or less (preferably). That is the case.

[0195] When forming the oxide semiconductor layer 206, for example, the substrate is placed in a processing chamber held under reduced pressure. Maintain the substrate temperature between 100°C and less than 550°C, preferably between 200°C and 400°C. The substrate is heated in such a way. Then, moisture is removed from the processing chamber, along with hydrogen and water. The sputtered gas is introduced, and the oxide semiconductor layer 206 is formed using the target described above. By forming the oxide semiconductor layer 206 while heating the substrate, the oxide semiconductor layer 206 It can reduce the amount of impurities contained in the material. It can also reduce damage caused by sputtering. This can be done. To remove moisture from the processing chamber, an adsorption-type vacuum pump can be used. Preferred. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. It can be used. In addition, a turbomolecular pump with a cold trap added can be used. Alternatively, by using a cryopump to evacuate, hydrogen and water can be removed from the treatment chamber. Therefore, the impurity concentration in the oxide semiconductor layer 206 can be reduced.

[0196] For example, the formation conditions for the oxide semiconductor layer 206 include a distance of 1 between the substrate and the target. 70mm, pressure 0.4Pa, DC power 0.5kW, atmosphere oxygen (oxygen 10 0% atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon Conditions such as a suitable atmosphere can be applied. Furthermore, a pulsed DC power supply is used. This reduces dust (such as powdery substances formed during film formation) and also results in a more uniform film thickness distribution. Preferably, the thickness of the oxide semiconductor layer 206 is 2 nm or more and 200 nm or less, preferably 5 nm. The wavelength shall be between 30 nm and 30 nm. However, this depends on the oxide semiconductor material to be applied and the application of the semiconductor device. The appropriate thickness varies depending on factors such as the material used and its application. That's all you need to do.

[0197] Furthermore, before forming the oxide semiconductor layer 206 by sputtering, argon gas was used. Inverted sputtering is performed by introducing a plasma to generate deposits on the surface of the insulating layer 202. It is preferable to remove it. Here, reverse sputtering refers to the process of removing the odor of normal sputtering. Instead of colliding ions with the sputtering target, we can instead collide ions with the processing surface. This refers to a method of modifying a surface by causing ions to collide with it. One method involves applying a high-frequency voltage to the surface being treated under an argon atmosphere, and then applying a plate near the substrate. Methods for generating rasma include those using nitrogen, helium, and oxygen instead of an argon atmosphere. You may also apply an atmosphere created by, for example, [this].

[0198] Next, the oxide semiconductor layer 206 is processed by methods such as etching using a mask. Island-shaped oxide semiconductor layers 206a are formed.

[0199] For etching the oxide semiconductor layer 206, dry etching and wet etching are both possible. You may use this. Of course, you can also use both in combination. Oxide semiconductors Etching conditions (etching) can be adjusted according to the material so that the body layers can be etched into the desired shape. The gas, etching solution, etching time, temperature, etc. should be set as appropriate. Oxide semiconductor layer 206 The etching is performed in the same manner as the etching of the oxide semiconductor layer in the previous embodiment. This can be done. For details regarding etching conditions, etc., please refer to the previous embodiment.

[0200] Subsequently, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer 206a. i. This first heat treatment removes excess hydrogen (water and hydroxyl groups) from the oxide semiconductor layer 206a. (including) removes and arranges the structure of the oxide semiconductor layer, and the energy in the oxide semiconductor layer 206a The defect levels in the gap can be reduced. The temperature of the first heat treatment is, for example, 300°C. The temperature shall be between 5°C and 550°C, or between 400°C and 500°C. If performed after the initial etching, even if wet etching is used, the etching process will take time. One advantage is that it can save time.

[0201] The heat treatment involves, for example, introducing the lower substrate 200 into an electric furnace using a resistance heating element, and in a nitrogen atmosphere. This can be carried out under the conditions of gas, 450°C, and 1 hour. During this time, the oxide semiconductor layer 206a Prevent exposure to the atmosphere and avoid contamination with water or hydrogen.

[0202] The heat treatment device does not have to be limited to an electric furnace; it can also be a medium such as a heated gas that conducts heat, or A device that heats the object to be processed by thermal radiation may also be used. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) for Thermal Anneal devices, etc. A device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats an object to be processed by radiating light (electromagnetic waves) from a lamp such as a silver lamp. Yes, there is. A GRTA device is a device that performs heat treatment using high-temperature gas. As for the gas, Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment. A gas is used.

[0203] For example, as a first heat treatment, the substrate is placed in a heated inert gas atmosphere and heated for several minutes. Afterward, a GRTA treatment may be performed to remove the substrate from the inert gas atmosphere. Using treatment A allows for high-temperature heat treatment in a short time. Also, because it is a short-time heat treatment... This makes it possible to apply the treatment even under temperature conditions that exceed the heat resistance temperature of the substrate. The heat treatment may be switched to an oxygen-containing gas. The first heat treatment is performed in an oxygen-containing atmosphere. By doing so, it is possible to reduce the defect levels in the energy gap caused by oxygen deficiency. This is for the purpose of cutting.

[0204] The inert gas atmosphere can be nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to apply an atmosphere whose main component is ( ) and which does not contain water, hydrogen, etc. For example, nitrogen, helium, neon, argon, and other noble gases introduced into heat treatment equipment. The purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher. That is, the impurity concentration should be 1 ppm or less, preferably 0.1 ppm or less.

[0205] In any case, the first heat treatment reduces impurities and makes it i-type or substantially i-type. By forming the oxide semiconductor layer 206a, a transistor with extremely excellent characteristics is realized. It is possible.

[0206] The first heat treatment is performed on the oxide semiconductor layer 2 before it is processed into an island-shaped oxide semiconductor layer 206a. It can also be done in 06. In that case, after the first heat treatment, the lower substrate 20 is removed from the heating device. The zeros will be extracted, and the photolithography process will be performed.

[0207] The first heat treatment has the effect of removing hydrogen and water, therefore the first heat treatment is called a dehydration treatment, dehydration treatment. This can also be called a hydrogenation treatment. This dehydration treatment and dehydrogenation treatment are performed on an oxide semiconductor layer. After the formation of the oxide semiconductor layer 206a, or after the source electrode or drain electrode is stacked on the oxide semiconductor layer 206a, It is also possible to perform such dehydration and dehydrogenation treatments at these times. The chemical treatment can be performed multiple times, not just once.

[0208] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. Then, the conductive layer is selected. Etched to target source electrode or drain electrode 208a, source electrode or drain Form electrode 208b (see Figure 11(B)). This step is the same as the previous embodiment. This process is similar to the process related to the electrode or drain electrode 142a, etc. For details, see the previous section. Embodiments can be considered.

[0209] Next, a gate insulating layer 212 is formed in contact with a portion of the oxide semiconductor layer 206a. (Figure 11) (See (C)). For further details, please refer to the description of the insulating layer 138 in the previous embodiment. It is possible.

[0210] After the formation of the gate insulating layer 212, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The heat treatment temperature should be between 200°C and 450°C, preferably 25°C. The temperature range is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour under a nitrogen atmosphere. Yes, that's fine. By performing a second heat treatment, variations in the electrical characteristics of the transistors are reduced. This is possible. Also, if the gate insulating layer 212 contains oxygen, the oxide semiconductor layer 206 By supplying oxygen to a, the oxygen vacancies in the oxide semiconductor layer 206a are filled, resulting in an i-type (intrinsic semiconductor) ) Or, it is also possible to form an oxide semiconductor layer that is very close to type i.

[0211] In this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 212. The timing of the second heat treatment is not particularly limited to this.

[0212] Next, in the region on the gate insulating layer 212 that overlaps with the oxide semiconductor layer 206a, the gate electric A electrode 214 is formed (see Figure 11(D)). The gate electrode 214 is on the gate insulating layer 212. This is formed by first forming a conductive layer and then selectively patterning the conductive layer. This is possible. For details, please refer to the description of the gate electrode 148a in the previous embodiment. It is possible to pour drinks.

[0213] Next, an interlayer insulating layer 216 and an interlayer insulating layer are placed on the gate insulating layer 212 and the gate electrode 214. An edge layer 218 is formed (see Figure 11(E)). Interlayer insulating layer 216 and interlayer insulating layer 218 These can be formed using methods such as PVD and CVD. Also, silicon oxide, oxide Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It can be formed using a material containing an insulating material. In this embodiment, interlayer insulating The invention has a laminated structure of an edge layer 216 and an interlayer insulating layer 218, but one aspect of the disclosed invention is as follows It is not limited to a single layer, or it can be a laminated structure of three or more layers.

[0214] Furthermore, it is desirable that the interlayer insulating layer 218 be formed so that its surface is flat. By forming the interlayer insulating layer 218 so that the surface is flat, electricity is deposited on the interlayer insulating layer 218. This is because it allows for the formation of electrodes, wiring, and other components in a suitable manner.

[0215] As a result, the transistor 250 using the highly purified oxide semiconductor layer 206a is completed. (See Figure 11(E)).

[0216] The transistor 250 shown in Figure 11(E) is provided on the lower substrate 200 via an insulating layer 202. The oxide semiconductor layer 206a is cut, and a source electrically connected to the oxide semiconductor layer 206a. Electrode or drain electrode 208a, source electrode or drain electrode 208b, and oxide semiconductor Conductor layer 206a, source electrode or drain electrode 208a, source electrode or drain electrode A gate insulating layer 212 covering electrode 208b, and a gate electrode 214 on the gate insulating layer 212, The interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214, and on the interlayer insulating layer 216 It has an interlayer insulating layer 218.

[0217] In the transistor 250 shown in this embodiment, the oxide semiconductor layer 206a is made highly pure. Therefore, its hydrogen concentration is 5 × 10 19 atoms / cm 3 The following are preferable: ×10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 atoms / cm 3 Below The result is as follows. Furthermore, the carrier density of the oxide semiconductor layer 206a is as follows in a typical silicon wafer. Carrier density (1 × 10) 14 / cm 3 A sufficiently small value (for example) , 1 x 10 12 / cm 3 Less than, more preferably 1.45 × 10 10 / cm 3 (less than) And this makes the off-current sufficiently small. For example, if the channel length is 10 μm Therefore, when the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1V to 10V. If it is within a certain range, the off-current (the voltage between the gate and source when it is less than 0V) The current is 1 × 10 -13 It will be less than or equal to A. Or, the off-current density at room temperature (off-current (The value obtained by dividing by the transistor's channel width) is 1 × 10 -20 A / μm (10 zA / μm) From 1 x 10 -19 The amplitude will be approximately A / μm (100 Hz A / μm).

[0218] Furthermore, the characteristics of the transistor mentioned above include not only the off-current and off-current density, but also the off-resistance (transistor The resistance value when the transistor is off, or the off-resistivity (resistivity when the transistor is off) It can be expressed using the following. Here, the off-resistance R is expressed using the off-current and drain voltage. This value can be obtained from Ohm's law. Furthermore, the off-resistivity ρ is the value obtained from the channel formation region. This value can be obtained using the formula ρ = RA / L, where A is the area and L is the channel length. Specifically, In the case described above, the off-resistivity is 1 × 10⁻⁶. 9Ω·m or greater (or 1 × 10⁻⁶) 10 (greater than Ω·m) The cross-sectional area A is expressed as A = dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. It will be done.

[0219] By using the highly purified and intrinsically purified oxide semiconductor layer 206a in this way, The off-current of the zista can be significantly reduced.

[0220] In this embodiment, instead of the transistor 162 shown in the previous embodiment, Although the case using Sta250 has been explained, it is not necessary to interpret the disclosed invention as being limited to this. For example, by sufficiently improving the electrical properties of oxide semiconductors, the transistors that make up an integrated circuit can be improved. It is also possible to use oxide semiconductors for all transistors, including zistas. In such cases, it is not necessary to have a laminated structure as shown in the previous embodiment. However, To achieve good circuit operation, the field-effect mobility μ of the oxide semiconductor should be μ > 100 cm 2 It is desirable that the coefficient of flux be / V·s. In this case, a semiconductor substrate such as a glass substrate is used. It is possible to form a body device.

[0221] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0222] (Embodiment 6) Next, the transistor 162, etc., used in the previous embodiment (Embodiment 1, etc.) Another example of a method for fabricating transistors using oxide semiconductors, which is possible, is shown in Figure This will be explained with reference to 12. In this embodiment, the oxide semiconductor layer has a crystalline region. A first oxide semiconductor layer and a second acid grown from the crystalline region of the first oxide semiconductor layer The case using a synthetic semiconductor layer will be explained in detail below. I will explain using a transistor as an example, but it is not necessary to limit the transistor configuration to a top-gate type. It's not necessary.

[0223] First, an insulating layer 302 is formed on the lower substrate 300. Then, the first layer is formed on the insulating layer 302. An oxide semiconductor layer is formed, and at least the surface of the first oxide semiconductor layer is subjected to a first heat treatment. The region containing the element is crystallized to form the first oxide semiconductor layer 304 (see Figure 12(A)). ).

[0224] For example, the lower substrate 300 is in the semiconductor device of the previous embodiment (Figure 1 or Figure 6, etc.) This can be a structure located below the interlayer insulating layer 128. For details, see the previous example. The form of the installation can be taken into consideration. Furthermore, the surface of the lower substrate 300 is as flat as possible. This is desirable. For example, by chemical mechanical polishing (CMP) or the like, the difference in surface height can be reduced. It should be 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness. The (RMS) should be 2 nm or less, preferably 0.4 nm or less.

[0225] The insulating layer 302 functions as a base layer, and the insulating layer 138 in the previous embodiment and It can be formed in the same manner as the insulating layer 144, etc. For details, please refer to the previous embodiment. Just pour it in. Furthermore, the insulating layer 302 should be formed in such a way that it contains as little hydrogen and water as possible. That would be preferable.

[0226] The first oxide semiconductor layer is formed in the same manner as the oxide semiconductor layer 206 in the previous embodiment. This is possible. Details of the first oxide semiconductor layer and the method for forming the film therein can be found in the previous implementation. The form should be taken into consideration. However, in this embodiment, the first oxide is produced by the first heat treatment. In order to intentionally crystallize the semiconductor layer, an oxide semiconductor that is prone to crystallization is used as the first It is desirable to form an oxide semiconductor layer. Examples of such oxide semiconductors include: Examples include ZnO. Furthermore, even in the case of In-Ga-Zn-O oxide semiconductors, for example... For example, substances with a high concentration of Zn tend to crystallize easily, and Zn is a metallic element (In, Ga, Zn). Materials with a proportion of 60% or more are desirable for this purpose. Also, the first oxide The thickness of the semiconductor layer is preferably between 3 nm and 15 nm. This embodiment is an example. The thickness will be 5 nm. However, this depends on the oxide semiconductor material to be applied and the application of the semiconductor device. The appropriate thickness varies depending on the material and application, so the thickness should be selected according to the material and application. good.

[0227] The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The following applies. Furthermore, the heat treatment time should preferably be between 1 minute and 24 hours. The heat treatment temperature and time vary depending on the type of oxide semiconductor, etc. The atmosphere used for heat treatment should preferably be free of hydrogen, water, and other elements. For example, water In an atmosphere of nitrogen, oxygen, and noble gases (helium, neon, argon, etc.) from which all other elements have been thoroughly removed. It is possible.

[0228] Heat treatment devices utilize not only electric furnaces but also heat conduction from heated gases or other media, or heat radiation. Therefore, a device that heats the object to be processed can be used. For example, GRTA (Gas Ra pid Thermal Anneal) device, LRTA (Lamp Rapid Th RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment l) A device can be used. The LRTA device uses halogen lamps, metal halide lamps. Xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) from lamps such as lamps. The GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is Argonaut. Noble gases such as nitrates, or inert gases such as nitrogen, that do not react with the material being treated by heat treatment. This is used.

[0229] As a result of the first heat treatment described above, a region including at least the surface of the first oxide semiconductor layer becomes crystallized. The crystalline region extends from the surface of the first oxide semiconductor layer to the interior of the first oxide semiconductor layer. This is a region formed by the progression of crystal growth toward the surface. Furthermore, this crystalline region is... It may contain plate-like crystals with an average thickness of 2 nm to 10 nm. Furthermore, the crystalline region is The oxide semiconductor layer has an ab plane substantially parallel to the surface, and the c axis is in a direction substantially perpendicular to the surface. It may contain oriented crystals. Here, "approximately parallel" means within ±10° of the parallel direction. This refers to a state within ±10° of the vertical, and "approximately vertical" refers to a state within ±10° of the vertical direction.

[0230] Furthermore, the first heat treatment forms a crystalline region, and the hydrogen in the first oxide semiconductor layer It is desirable to remove (water and hydroxyl groups, etc.). When removing hydrogen, etc., Nitrogen and acid with a purity of 6N (99.9999%) or higher (i.e., impurity concentration of 1 ppm or less). The first heat treatment should be performed in an atmosphere of a noble gas (helium, neon, argon, etc.). More preferably, the purity should be 7N (99.99999%) or higher (i.e., the concentration of impurities should be 0.1%). The atmosphere is less than ppm. Furthermore, it is preferable to have an ultra-dry air with H2O at 20 ppm or less. Alternatively, the first heat treatment may be performed in ultra-dry air containing 1 ppm or less of H2O.

[0231] Furthermore, the first heat treatment forms a crystalline region and supplies oxygen to the first oxide semiconductor layer. It is desirable to supply oxygen. For example, by changing the heat treatment atmosphere to an oxygen atmosphere, Oxygen can be supplied to the oxide semiconductor layer 1.

[0232] In this embodiment, the first heat treatment is performed at 700°C for 1 hour under a nitrogen atmosphere. By removing hydrogen and other elements from the oxide semiconductor layer and then switching the atmosphere to an oxygen atmosphere... This supplies oxygen to the interior of the first oxide semiconductor layer. The main purpose of the first heat treatment is crystallization. Since this is for forming a region, processes aimed at removing hydrogen and supplying oxygen should be carried out separately. It is also possible to perform heat treatment to remove hydrogen, etc., or oxygen supply treatment beforehand. It is possible to perform heat treatment for crystallization.

[0233] This first heat treatment removes crystalline regions and hydrogen (including water and hydroxyl groups). A first oxide semiconductor layer is obtained, which is then treated and supplied with oxygen.

[0234] Next, on the first oxide semiconductor layer 304 having a crystalline region in at least the surface region, A second oxide semiconductor layer 305 is formed (see Figure 12(B)).

[0235] The second oxide semiconductor layer 305 is similar to the oxide semiconductor layer 206 in the previous embodiment. It can be formed. Details of the second oxide semiconductor layer 305 and the method for forming the film therein The above embodiment should be considered. However, the second oxide semiconductor layer 305 is the first acid It is desirable to form the first oxide semiconductor layer 304 thicker than the first oxide semiconductor layer 30 The sum of the thicknesses of 4 and the second oxide semiconductor layer 305 is between 3 nm and 50 nm. It is desirable to form the oxide semiconductor layer 305 of 2. The appropriate thickness varies depending on the application of the semiconductor device, so the thickness depends on the materials used and the application. You can choose according to your needs and circumstances.

[0236] The second oxide semiconductor layer 305 is made of a material with the same main components as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with closely spaced lattice constants after crystallization (mismatch of 1% or less). When using such materials, in the crystallization of the second oxide semiconductor layer 305 This is because crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed is more likely to proceed. Furthermore, if the main component material is the same, the interfacial properties and electrical properties will also be good.

[0237] Furthermore, if the desired film quality can be obtained by crystallization, a second method using materials with different main components may be used. An oxide semiconductor layer 305 may be formed.

[0238] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystal region is used as a seed to grow a crystal, forming a second oxide semiconductor layer 306 (Figure 12). (C))).

[0239] The temperature for the second heat treatment is 550°C to 850°C, preferably 600°C to 750°C. The following applies. The heating time for the second heat treatment shall be 1 minute or more and 100 hours or less, preferably 5 hours or less. The maximum treatment time is 20 hours or less, typically 10 hours. Furthermore, in the second heat treatment, Ideally, the atmosphere should not contain hydrogen, water, or other similar substances.

[0240] The details of the atmosphere and the effects of the heat treatment are the same as in the first heat treatment. The heat treatment apparatus capable of performing this is the same as in the case of the first heat treatment. For example, the heating of the second heat treatment Sometimes the inside of the furnace is filled with a nitrogen atmosphere, and during cooling, the inside of the furnace is filled with an oxygen atmosphere, Hydrogen and other substances can be removed using an atmospheric environment, while oxygen can be supplied using an oxygen atmosphere.

[0241] By performing the second heat treatment described above, the first oxide semiconductor layer 304 is formed Crystal growth is advanced from the crystalline region to the entire second oxide semiconductor layer 305, and the second oxide semiconductor A conductive layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like can be removed. This allows for the formation of a second oxide semiconductor layer 306 to which oxygen is supplied. Heat treatment makes it possible to increase the orientation of the crystalline regions of the first oxide semiconductor layer 304. be.

[0242] For example, an In-Ga-Zn-O based oxide semiconductor material is used for the second oxide semiconductor layer 306. If present, the second oxide semiconductor layer 306 is InGaO3(ZnO) m (m: integer) The crystals are represented as In2Ga2ZnO7 (In:Ga:Zn:O=2:2:1:7) It may contain crystals such as the following. Such crystals, by a second heat treatment, have their c-axis, second It is oriented in a direction approximately perpendicular to the surface of the oxide semiconductor layer 306a.

[0243] Here, the crystal described above contains either In, Ga, or Zn, and the a-axis is It can be understood as a stacked structure of layers parallel to the b-axis. In terms of the above crystal, it consists of a layer containing In and a layer that does not contain In (Ga). It has a structure in which layers (or layers containing Zn) are stacked in the c-axis direction.

[0244] In an In-Ga-Zn-O oxide semiconductor crystal, the in-plane direction of the In-containing layer, In other words, conductivity is good in the directions parallel to the a-axis and b-axis. This is In-G In α-Zn-O oxide semiconductor crystals, electrical conductivity is primarily controlled by In. Furthermore, the 5s orbital of one In overlaps with the 5s orbital of an adjacent In. This is due to the formation of a career path.

[0245] Furthermore, the first oxide semiconductor layer 304 has an amorphous region at the interface with the insulating layer 302. In the case of the structure, a second heat treatment is performed to form on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer, and In some cases, crystallization may occur in the crystalline region. Furthermore, the materials constituting the insulating layer 302 and the heat treatment conditions... In some cases, the amorphous region may remain.

[0246] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 have the same main component oxide semiconductor When using a body material, as shown in Figure 12(C), the first oxide semiconductor layer 304 and the second The oxide semiconductor layer 306 may have the same crystal structure. Therefore, Figure 12( In C), as shown by the dotted line, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 The boundary becomes indistinguishable, and the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 They can sometimes be considered to belong to the same layer.

[0247] Next, the first oxide semiconductor layer 304 and The oxide semiconductor layer 306 is processed to form island-shaped first oxide semiconductor layer 304a and second An oxide semiconductor layer 306a is formed (see Figure 12(D)). Note that here, a second thermal treatment is performed. After the initial processing, the island-shaped oxide semiconductor is processed, but the processing of the island-shaped oxide semiconductor layer Later, a second heat treatment may be performed. In this case, wet etching is used. However, it has the advantage of reducing the etching time.

[0248] For etching the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306, dry Either etching or wet etching can be used. Of course, both can be combined. They can also be used in combination. The material allows the oxide semiconductor layer to be etched into the desired shape. Etching conditions (etching gas, etching solution, etching time, temperature, etc.) should be adjusted accordingly. This is set as appropriate. Etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306. The etching can be performed in the same manner as etching the oxide semiconductor layer in the previous embodiment. For further details, please refer to the previously described embodiment.

[0249] Furthermore, the region within the oxide semiconductor layer that forms the channel has a flat surface. This is desirable. For example, the height difference on the surface of the second oxide semiconductor layer 306 is greater than that of the gate electrode. In the region where the layers are laid (channel formation region), the size is 1 nm or less (preferably 0.2 nm or less). It is preferable to have it.

[0250] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. The electrode layer is selectively etched to remove the source electrode or drain electrode 308a, and the source electrode Alternatively, the drain electrode 308b is formed (see Figure 12(D)). Source electrode or drain Electrode 308a, source electrode or drain electrode 308b is a source electrode in the previous embodiment. The source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and similar shapes This can be achieved. For details, please refer to the previously described embodiment.

[0251] Furthermore, in the process shown in Figure 12(D), the first oxide semiconductor layer 304a and the second oxide semiconductor layer On the side surface of the conductor layer 306a, the source electrode or drain electrode 308a, the source electrode Alternatively, the crystalline layer in contact with the drain electrode 308b may become amorphous. Therefore, All regions of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are crystallized. It's not necessarily a structure.

[0252] Next, a gate insulating layer 312 is formed in contact with a portion of the second oxide semiconductor layer 306a. The insulating layer 312 can be formed using methods such as CVD or sputtering. Subsequently, the first oxide semiconductor layer 304a and the second oxide semiconductor layer on the gate insulating layer 312 A gate electrode 314 is formed in the region overlapping with layer 306a. Then, a gate insulating layer 312 And interlayer insulating layers 316 and 318 are formed on the gate electrode 314 (Figure See 12(E). Gate insulating layer 312, gate electrode 314, interlayer insulating layer 316 and layer The interlayer insulating layer 318 is the insulating layer 138, gate electrode 148a, and interlayer insulating layer in the previous embodiment. The edge layer 216, interlayer insulating layer 218, etc., can be formed in the same manner. For details, see below. You may refer to the embodiment described above.

[0253] After the formation of the gate insulating layer 312, a third heat is applied under an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The temperature for the third heat treatment is preferably between 200°C and 450°C. The temperature range is between 250°C and 350°C. For example, 250°C for 1 hour in an oxygen-containing atmosphere. Heat treatment can be performed. By performing a third heat treatment, the electrical characteristics of the transistor can be improved. This can reduce rattling. Also, if the gate insulating layer 312 is an insulating layer containing oxygen... In addition, oxygen is supplied to the second oxide semiconductor layer 306a, and the acid of the second oxide semiconductor layer 306a By filling in elementary defects, an i-type (intrinsic semiconductor) or an oxide semiconductor layer very close to i-type is formed. It is also possible.

[0254] In this embodiment, the third heat treatment is performed after the formation of the gate insulating layer 312. The timing of the third heat treatment is not limited to this. Also, the timing of other treatments such as the second heat treatment may vary. Therefore, if oxygen is supplied to the second oxide semiconductor layer, the third heat treatment can be omitted. good.

[0255] As described above, the first oxide semiconductor layer 304a and the first oxide semiconductor layer 304a A transistor 350 using a second oxide semiconductor layer 306a grown from a crystalline region. This is completed (see Figure 12(E)).

[0256] The transistor 350 shown in Figure 12(E) is provided on the lower substrate 300 via an insulating layer 302. A first oxide semiconductor layer 304a is provided on the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306a and the second oxide semiconductor layer 306a are electrically connected Source electrode or drain electrode 308a, source electrode or drain electrode 308b, and 2 oxide semiconductor layer 306a, source electrode or drain electrode 308a, source electrode or This consists of a gate insulating layer 312 covering the drain electrode 308b, and the gate electrode on the gate insulating layer 312. The pole 314, the gate insulating layer 312 and the interlayer insulating layer 316 on the gate electrode 314, and the interlayer insulating It has an interlayer insulating layer 318 on the edge layer 316.

[0257] In the transistor 350 shown in this embodiment, the first oxide semiconductor layer 304a and Furthermore, because the second oxide semiconductor layer 306a is highly purified, its hydrogen concentration is 5 × 10⁻⁶ 19 / cm 3 The following is preferable: 5 x 10 18 / cm 3 The following is more preferable: 5 x 10 17 / cm 3 The following applies. Furthermore, the carrier density of the oxide semiconductor layer 206a is typical of silico Carrier density on a wafer (1 × 10⁻¹⁰ 14 / cm 3 (in comparison to the degree) sufficiently small Value (for example, 1 × 10) 12 / cm 3 Less than, more preferably 1.45 × 10 10 / cm 3 Take a value less than . And this makes the off-current sufficiently small. For example, channel length When the thickness is 10 μm and the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1 In the range of approximately V to 10V, the off-current (gate-source voltage is set to 0V or less) The drain current at that time is 1 × 10⁻⁶. -13 It will be less than or equal to A. Or, the off-current density at room temperature. (The value obtained by dividing the off-current by the transistor's channel width) is 1 × 10⁻⁶ -20 A / μm(10z From A / μm) to 1 × 10 -19 The amplitude will be approximately A / μm (100 Hz A / μm).

[0258] Furthermore, the characteristics of the transistor mentioned above include not only the off-current and off-current density, but also the off-resistance (transistor The resistance value when the transistor is off, or the off-resistivity (resistivity when the transistor is off) It can be expressed using the following. Here, the off-resistance R is expressed using the off-current and drain voltage. This value can be obtained from Ohm's law. Furthermore, the off-resistivity ρ is the value obtained from the channel formation region. This value can be obtained using the formula ρ = RA / L, where A is the area and L is the channel length. Specifically, In the case described above, the off-resistivity is 1 × 10⁻⁶. 9 Ω·m or greater (or 1 × 10⁻⁶) 10 (greater than Ω·m) The cross-sectional area A is expressed as A = dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. It will be done.

[0259] Thus, the first oxide semiconductor layer 304a and the second oxide semiconductor layer are purified and intrinsically activated. By using the monocrystalline semiconductor layer 306a, the off-current of the transistor can be sufficiently reduced. Cut.

[0260] Furthermore, in this embodiment, the oxide semiconductor layer is a first oxide semiconductor having a crystalline region. Body layer 304a and a second acid grown from the crystalline region of the first oxide semiconductor layer 304a Because a synthetic semiconductor layer 306a is used, the field-effect mobility is improved, resulting in good electrical characteristics. It is possible to realize a transistor that possesses these properties.

[0261] In this embodiment, instead of the transistor 162 shown in the previous embodiment, Although the use of STA350 has been explained, it is not necessary to interpret the disclosed invention as being limited to this. For example, the transistor 350 shown in this embodiment is a first oxide having a crystalline region. Crystal growth was performed from the semiconductor layer 304a and the crystalline region of the first oxide semiconductor layer 304a. A second oxide semiconductor layer 306a is used, and it has good field-effect mobility, so integration Using oxide semiconductors for all transistors, including the transistors that make up the circuit. It is possible. And in such cases, the laminated structure is as shown in the previous embodiment. It is not necessary. However, in order to achieve good circuit operation, the field-effect mobility of the oxide semiconductor μ is greater than 100 cm 2 It is desirable that / V·s. And in this case, the glass substrate It is possible to form semiconductor devices using substrates such as these.

[0262] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0263] (Embodiment 7) This embodiment describes a manufacturing method different from the semiconductor device manufacturing method shown in Embodiment 1. This will be clarified. In this embodiment, the gate voltage of the lower transistor is determined by the so-called damascene method. In addition to forming electrodes, the electrode material is used to form the source electrode and the top electrode of the transistor. The invention is characterized by forming rain electrodes and the like.

[0264] First, the state shown in Figure 4(G) is obtained by the method described in Embodiment 1. This state is shown in Figure 13( As shown in A). Then, the interlayer insulating layer 126 and interlayer insulating layer 128 are polished by CMP method, etc. The upper surface of the gate electrode 110 is exposed. Then, using a selective etching method, the gate electrode The pole 110 is etched to form a void 127 (see Figure 13(B)).

[0265] Next, a film deposition method is used to completely fill the void 127, using a conductive material made of metal or metal nitride. A layer is formed. The conductive layer can be a single layer or multiple layers. Then, the conductive layer is etched to form the electrode layer. (Source electrode or drain electrode 142a and source electrode or drain electrode 142b ) is obtained (see Figure 13(C)). At this stage, the same as Figure 5(B) shown in Embodiment 1 is obtained. This will form the structure.

[0266] Subsequently, similar to Embodiment 1, island-shaped oxide semiconductor layer 140, gate insulating layer 146, Form the gate electrode 148a and electrode 148b (see Figure 13(D)). Note What needs to be done is that the electrode layer (source electrode or drain electrode 142a) is below the transistor It is the gate electrode, and at the same time, the source electrode or drain electrode of the upper transistor. This means that the lower transistor that was required in Embodiment 1 is no longer needed. The step of forming a contact hole in the gate electrode 110 can be omitted. In this embodiment, the island-shaped oxide semiconductor layer 140 is in contact with the interlayer insulating layer 128, so the island-shaped Before forming the oxide semiconductor layer 140, the surface of the interlayer insulating layer 128 is thoroughly dehydrogenated. It is desirable to do so.

[0267] (Embodiment 8) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, This will be explained using Figure 14. In this embodiment, a computer and a mobile phone (mobile Telephones (also called mobile phones), personal information terminals (including portable game consoles, audio playback devices, etc.) (mu), digital camera, digital video camera, electronic paper, television equipment (tele The above-mentioned semiconductor device is applied to electronic devices such as a radio or television receiver. Let me explain the cases in which this occurs.

[0268] Figure 14(A) shows a notebook-type personal computer, consisting of chassis 401, chassis 402, It consists of a display unit 403, a keyboard 404, etc., and enclosures 401 and 402. Inside, the semiconductor device shown in the previous embodiment is provided. Therefore, information writing Furthermore, it offers fast readout, long-term storage, and significantly reduced power consumption. A mobile-type personal computer will be realized.

[0269] Figure 14(B) shows a personal digital assistant (PDA), and the main unit 411 has a display unit 413 and an external A separate interface 415 and operation buttons 414, etc., are provided. It is equipped with a stylus 412 for operating the end. Inside the main body 411, as in the previous embodiment, A semiconductor device is provided. Therefore, information can be written and read at high speed, and long This will enable the creation of a portable information terminal that can retain data for a specified period while significantly reducing power consumption.

[0270] Figure 14(C) shows an e-reader 420 with electronic paper implemented, consisting of a casing 421 and a casing 42 It consists of two enclosures, 421 and 423, each containing a display unit 42 A 5 and a display unit 427 are provided. The housing 421 and housing 423 are connected by a shaft portion 437. The shaft portion 437 is connected and can be opened and closed using the shaft portion 437 as an axis. It is equipped with a power supply 431, operation keys 433, speaker 435, etc. Enclosure 421, housing At least one of the body 423 is provided with the semiconductor device shown in the previous embodiment. Therefore, it offers high-speed information writing and reading, long-term memory retention, and low power consumption. This will result in ebooks with significantly reduced noise levels.

[0271] Figure 14(D) shows a mobile phone, which consists of two casings, casing 440 and casing 441. Furthermore, the casings 440 and 441 slide and unfold as shown in Figure 14(D). It can be transformed from a separate state to an overlapping state, and can be miniaturized to suit portability. The enclosure 441 includes a display panel 442, a speaker 443, a microphone 444, and a poi It is equipped with a lighting device 446, a camera lens 447, an external connection terminal 448, and the like. Furthermore, the housing 440 includes a solar cell 449 for charging the mobile phone, and an external memory slot. It is equipped with a 450, etc. The antenna is also built into the housing 441. Housing 4 At least one of 40 and the housing 441 is provided with the semiconductor device shown in the previous embodiment. Therefore, information can be written and read at high speed, and long-term memory retention is possible. Mobile phones with significantly reduced power consumption will be realized.

[0272] Figure 14(E) shows a digital camera, consisting of a main unit 461, a display unit 467, an eyepiece unit 463, and a control panel. It consists of a power switch 464, a display unit 465, a battery 466, etc. Inside 461, the semiconductor device shown in the previous embodiment is provided. Therefore, the information book It offers high-speed writing and reading, long-term data retention, and significantly reduced power consumption. A digital camera that meets these standards will be realized.

[0273] Figure 14(F) shows a television device 470, consisting of a housing 471, a display unit 473, and a stand. It consists of 475 and other components. The television device 470 is operated by the casing 471. This can be done using the switch or the remote control unit 480. The housing 471 and the remote control unit The device 480 is equipped with the semiconductor device shown in the previous embodiment. Therefore, the information book It offers high-speed writing and reading, long-term data retention, and significantly reduced power consumption. A television system will be realized.

[0274] As described above, the electronic device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is included. Therefore, electronic devices with reduced power consumption can be realized. [Examples]

[0275] The number of rewriteable cycles of a semiconductor device according to one embodiment of the disclosed invention was investigated. This example Now, let's explain the results of this survey with reference to Figure 15.

[0276] The semiconductor device used in the investigation is the one with the circuit configuration shown in Figure 3(A-1). Furthermore, an oxide semiconductor was used for the transistor corresponding to transistor 162. A capacitance element with a capacitance value of 0.33 pF was used as the corresponding capacitor element for sub-element 164.

[0277] The investigation involved determining the initial memory window width and the number of times data was retained and written. This was done by comparing it with the memory window width after iteration. Data retention and Data is written by applying 0V to the wiring corresponding to the third wiring in Figure 3(A-1), or Apply either 5V, and apply either 0V or 5V to the wire corresponding to the fourth wire. This was done by doing so. If the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to TA162 is in the off state, the floating gate section FG The given potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, then Since the transistor corresponding to transistor 162 is in the ON state, the wiring corresponding to the third wiring The potential of the line is applied to the floating gate section FG.

[0278] Memory window width is one of the indicators that show the characteristics of a storage device. Here, different memory The potential Vcg of the wiring corresponding to the fifth wiring in between states, and the potential of the wiring corresponding to transistor 160 The shift of the curve (Vcg-Id curve) that shows the relationship with the drain current Id of a transistor. This refers to the quantity ΔVcg. A different memory state is when the floating gate FG is at 0V. When the voltage is set to 5V, (hereinafter referred to as the Low state) and the floating gate FG is set to 5V This refers to the given state (hereinafter referred to as the High state). In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in both the Low and High states.

[0279] Figure 15 shows the memory window width in the initial state and 1 × 10 9 After writing this post The results of the investigation into the memory window width are shown. Note that in Figure 15, the horizontal axis is Vcg(V). The vertical axis shows Id(A). From Figure 15, 1 × 10 9 Before and after the writing, It can be confirmed that the width of the Mori window has not changed. 1×10 9 Before and after each post The fact that the memory window width does not change means that, at least during this time, the semiconductor device This indicates that it will not deteriorate.

[0280] As described above, a semiconductor device according to one aspect of the disclosed invention performs holding and writing multiple times. The properties do not change even after repeated use. In other words, according to one aspect of the disclosed invention, it is extremely reliable. This means that highly efficient semiconductor devices will be realized. [Explanation of symbols]

[0281] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Guard Station 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130 electrodes 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 138 Insulating layer 140 Oxide semiconductor layer 140a Oxide Semiconductor Layer 140b Oxide Semiconductor Layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 142c electrode 142d electrode 144 Insulating layer 146 Gate Insulation Layer 148a Token 148b Electrode 150 Protective insulating layer 152 Interlayer insulating layer 160 transistors 162 transistors 164 Capacitive elements 166 transistors 190 memory cells 200 Lower substrate 202 Insulating layer 206 oxide semiconductor layer 206a Oxide Semiconductor Layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate Insulation Layer 214 Grid gate 216 Interlayer insulating layer 218 Interlayer insulating layer 250 transistors 300 Lower layer substrate 302 Insulating layer 304 oxide semiconductor layer 304a oxide semiconductor layer 305 Oxide Semiconductor Layer 306 oxide semiconductor layer 306a Oxide Semiconductor Layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate Insulation Layer 314 gate 316 Interlayer insulating layer 318 Interlayer insulating layer 350 transistors 401 cabinet 402 cabinets 403 Display section 404 Keyboard 411 Main Unit 412 Stylus 413 Display section 414 Operation buttons 415 External Interface 420 eBooks 421 cabinet 423 cabinets 425 Display section 427 Display section 431 Power supply 433 Operation Keys 435 Speaker 437 Shaft 440 cabinets 441 cabinets 442 Display Panel 443 Speakers 444 Microphone 446 Pointing Devices 447 Camera Lenses 448 External connection terminals 449 solar cells 450 external memory slots 461 Main Unit 463 Eyepiece 464 Operation Switches 465 Display section 466 Battery 467 Display section 470 Television equipment 471 cabinets 473 Display section 475 Stand 480 Remote Control Unit

Claims

[Claim 1] Having a first memory cell and a second memory cell, The first memory cell comprises a first transistor, a second transistor, and a first capacitive element. The second memory cell has a third transistor, a fourth transistor, and a second capacitive element. The source or drain of the first transistor and the source or drain of the third transistor are electrically connected to the first signal line. The source or drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the first capacitive element. The source or drain of the third transistor is electrically connected to the gate of the fourth transistor and one electrode of the second capacitive element. Either the source or the drain of the second transistor is electrically connected to the bit line. The source or drain of the second transistor is electrically connected to the source or drain of the fourth transistor. The source or drain of the fourth transistor, the other of which is electrically connected to the source line, The other electrode of the first capacitive element is electrically connected to the first word line. The other electrode of the second capacitive element is electrically connected to the second word line. storage device.

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