Silicon carbide semiconductor equipment

Abstract

The present invention provides a silicon carbide (SiC) semiconductor device that suppresses the expansion of basal plane dislocations into Shockley-type stacking faults. [Solution] The SiC semiconductor device comprises a SiC substrate 11 made of n-type SiC doped with n-type impurities, an n-type low-concentration layer 13 having a lower n-type impurity concentration than the SiC substrate, a p-type deep layer 15 formed on the low-concentration layer, a p-type base region 17 disposed on the deep layer, an n-type source region 18 formed on the surface of the base region, a trench gate structure having a gate insulating film 22 formed on the wall surface of a gate trench 21 penetrating the source region and base region, and a gate electrode 23 formed on the gate insulating film, a source electrode 25 electrically connected to the source region and base region, and a drain electrode 26 electrically connected to the SiC substrate, with the deep layer and low-concentration layer forming a built-in diode, and the SiC substrate having a concentration of 9.0 × 10 16 / cm 3 The above contains boron.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide (hereinafter referred to as SiC) semiconductor devices. [Background technology]

[0002] Due to its excellent semiconductor properties, SiC is increasingly being put into practical use as a material for various semiconductor devices, such as power devices for vehicles. However, SiC single crystal substrates contain wavy dislocations called basal plane dislocations (hereinafter referred to as BPDs), which have dislocation lines on the (0001) plane.

[0003] When an epitaxial film is grown on such a SiC single-crystal substrate to construct a SiC semiconductor device equipped with a switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an internal diode is formed. When this SiC semiconductor device is applied to an inverter circuit or the like, and the internal diode operates bipolar due to freewheeling during switching, the BPD may expand into a Shockley stacking fault (SSF). That is, holes passing near the BPD recombine with electrons in the n-type layer, generating a large recombination energy, causing the BPD to expand into an SSF. Since SSFs occupy a larger area than BPDs and are defects that easily degrade the electrical properties of SiC semiconductor devices, it is desirable to suppress the expansion of BPDs into SSFs.

[0004] On the other hand, a technique for suppressing the expansion of BPD to SSF is proposed in Patent Document 1. In this technique, when manufacturing a SiC semiconductor device in which an epitaxial film is placed on one surface of a SiC single crystal substrate, p-type impurities are introduced during the manufacturing of the ingot used to form the n-type SiC single crystal substrate. This improves the crystallinity within the SiC single crystal substrate, increasing the energy required for the BPD to expand to SSF, thereby suppressing the expansion of BPD to SSF. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-57381 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, while the inclusion of p-type impurities in the SiC single crystal substrate can suppress the expansion of the BPD to the SSF, this effect was not fully realized depending on the current flowing through the built-in diodes in the SiC semiconductor device.

[0007] This disclosure aims to provide a SiC semiconductor device that can suppress the extension of BPD to SSF. [Means for solving the problem]

[0008] One aspect of this disclosure is a SiC semiconductor device, A SiC substrate (11) composed of n-type SiC doped with n-type impurities, A low-concentration n-type impurity layer (13) is formed on the SiC substrate and has a lower n-type impurity concentration than the SiC substrate, A p-type deep layer (15) is formed on the low-concentration layer and has multiple linear portions with one direction in the planar direction of the substrate as the longitudinal direction, A p-type base region (17) is disposed on the JFET section and the deep layer, An n-type source region (18) formed on the surface of the base region, The trench gate structure includes a gate insulating film (22) formed on the wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film, A source electrode (25) electrically connected to the source region and the base region, The substrate is electrically connected to a drain electrode (26), The built-in diode (40) is formed by a pn junction including the deep layer and the low-concentration layer, The SiC substrate contains B, and the B concentration in the SiC substrate is 9.0 × 10⁻⁶ 16 / cm 3 That is what is stated.

[0009] Thus, the current density of the current flowing when the built-in diode performs freewheeling operation is 11.6 A / mm². 2 In the above-mentioned applications, the B concentration in the SiC substrate is set to 9.0 × 10⁻⁶ 16 / cm 3 This is the conclusion. This makes it possible to suppress the expansion of BPD into SSF.

[0010] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0011] [Figure 1] This is a perspective cross-sectional view of the SiC semiconductor device described in the first embodiment. [Figure 2] This is a diagram illustrating the current path in a SiC semiconductor device. [Figure 3A] This is an explanatory diagram showing the behavior of holes and electrons near the built-in diode. [Figure 3B] This is an explanatory diagram of defect growth caused by BPD near the built-in diode. [Figure 4] This is a binarized image of a photoluminescence (PL) image, obtained by non-destructive testing using the PL method to confirm the degree of SSF expansion. [Figure 5] This figure shows the relationship between B concentration, SSF area occupancy, and SiC wafer warpage. [Figure 6] This figure shows the change in hole density in various parts near the buffer layer when the B concentration in the SiC substrate is changed. [Figure 7]This figure shows the change in hole density at the interface between the SiC substrate and the buffer layer with respect to the B concentration. [Figure 8A] This figure shows the relationship between the B concentration at which the SSF (Stress Saturation Factor) is 3% when there is no decrease in the n-type impurity concentration, and the electrical stress. [Figure 8B] This figure shows the relationship between the B concentration at which the SSF (Stress Stress Factor) reaches 3% when there is a drop in the n-type impurity concentration, and the electrical stress. [Figure 9] This figure shows the nitrogen concentrations in the SiC substrate, buffer layer, and low-concentration layer. [Figure 10A] Figure 1 is a cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 10B] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 10A. [Figure 10C] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 10B. [Figure 10D] Figure 10C is a cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 10E] Figure 10D is a cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 10F] Figure 10E is a cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 10G] Figure 10F is a cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 11] This figure shows the amount of warpage of multiple SiC wafer samples before the device formation process and after the deep layer formation process. [Figure 12] This diagram schematically illustrates the process of slicing and cutting SiC wafers from a SiC ingot. [Figure 13A] This figure shows the relationship between B concentration and warpage in a 6-inch wafer. [Figure 13B] This figure shows the relationship between B concentration and warpage in an 8-inch wafer. [Figure 14] This is a perspective cross-sectional view of the SiC semiconductor device described in the second embodiment. [Figure 15A]Figure 14 is a cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 15B] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 15A. [Figure 15C] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 15B. [Figure 15D] Figure 15C is a cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 15E] Figure 15D is a cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 15F] Figure 15E is a cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 16] This is a cross-sectional view showing the process of growing a SiC ingot in a growth crucible. [Figure 17A] This graph shows the content of various impurity elements present in the SiC substrate. [Figure 17B] This graph shows the content of various impurity elements present in the raw material powder. [Figure 18A] This figure shows the relationship between the concentration of each p-type impurity in the raw material powder and the concentration of each p-type impurity in the SiC substrate. [Figure 18B] This diagram shows the relationship between the concentration of each p-type impurity in the raw material powder and the concentration, ratio RP / S, and magnification RS / P of each p-type impurity in the SiC substrate. [Figure 19] This figure shows the changes in the concentrations of p-type impurities in a standard crucible (without purification) and a high-purity crucible (with purification). [Modes for carrying out the invention]

[0012] The embodiments of this disclosure will be described below with reference to the drawings. In each embodiment, including the other embodiments described below, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First Embodiment) A first embodiment of the present disclosure will be described. First, the configuration of a SiC semiconductor device according to the present embodiment will be described with reference to FIG. 1.

[0014] [Configuration of SiC Semiconductor Device] The SiC semiconductor device according to the present embodiment has, as a semiconductor element, an inversion-type vertical MOSFET with a trench gate structure shown in FIG. 1 formed therein. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure so as to surround the cell region, but only the vertical MOSFET is illustrated herein. In the following description, as shown in FIG. 1, mutually orthogonal directions are respectively referred to as the X direction, the Y direction, and the Z direction. Specifically, the width direction of the vertical MOSFET is defined as the X direction, the depth direction of the vertical MOSFET intersecting the X direction is defined as the Y direction, and the thickness direction or depth direction of the vertical MOSFET, that is, the direction normal to the XY plane is defined as the Z direction.

[0015] As shown in FIG. 1, in the SiC semiconductor device, an n-type doped with n-type impurities n + -type SiC substrate 11 is used. The SiC substrate 11 is a portion that constitutes the drain region in the vertical MOSFET 30. For example, the SiC substrate 11 has an off angle of 0 to 8° with respect to the (0001) Si surface, and has an n-type impurity concentration of 1.0×10 19 / cm 3 and has a thickness of 350 μm specification or 500 μm specification. The 350 μm specification means that the thickness is in the range of 325 to 375 μm, and the 500 μm specification means that the thickness is in the range of 475 to 525 μm.

[0016] Further, although the SiC substrate 11 is n-type, it contains at least B (boron) as a p-type impurity. Although the reason will be described later, when assuming a forward current of 600 A or more and a current density of 11.6 A / mm 2 or more flowing through the built-in diode 40 of the vertical MOSFET 30 shown in the equivalent circuit of FIG. 2, the B concentration is set to 9×1016 / cm 3 The above specifications are as follows. In addition, the forward current flowing through the built-in diode 40 should be 800A or more, and the current density should be 15.0A / mm². 2 If the above is assumed, the B concentration should be 1.5 × 10 17 / cm 3 The above is the explanation. The forward current expected to flow through the built-in diode 40 is the current that can flow as a return current when a SiC semiconductor device is applied to an inverter circuit or the like and performs a return current operation. In other words, it represents the magnitude of the current stress applied to the built-in diode 40. Hereafter, this forward current expected to flow through the built-in diode 40 will also be referred to as current stress.

[0017] Preferably, when the thickness of the SiC substrate 11 is specified as 350 μm, the B concentration is 1.75 × 10 17 / cm 3 For the following cases where the specification is 500 μm, the B concentration is 7.2 × 10 17 / cm 3 The following would be good.

[0018] On the main surface of the SiC substrate 11, n is made of SiC which constitutes part of the drift layer. - A buffer layer 12 of type n is formed. The buffer layer 12 is formed by epitaxial growth on the surface of the SiC substrate 11, and the n-type impurity concentration is set to the impurity concentration between the SiC substrate 11 and the low-concentration layer 13 described later. The buffer layer 12 has a thickness of, for example, about 1 μm, and the n-type impurity concentration is 6.0 × 10⁻⁶. 17 ~1.5×10 18 / cm 3 It is stated that on the buffer layer 12, there is a part of the drift layer made of SiC, which has a lower concentration than the SiC substrate 11. - A low-concentration layer 13 of the type is formed.

[0019] In the cell region, an n-type JFET section 14, which constitutes part of the drift layer made of SiC, is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET section 14 on the side opposite to the SiC substrate 11. Furthermore, in addition to the JFET section 14, a p-type deep layer 15 is formed on the low-concentration layer 13.

[0020] The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and both extend in the X direction as their longitudinal direction, and are arranged in alternating repeating patterns in the Y direction. In other words, when viewed from the direction normal to the main surface of the SiC substrate 11, at least a portion of the JFET section 14 and the deep layer 15 are each arranged in multiple lines, or in other words, stripes, and are arranged in an alternating pattern.

[0021] In this embodiment, the JFET section 14 is formed below the deep layer 15. Therefore, the striped portions of the JFET section 14 are connected below the deep layer 15, but each of the striped portions is positioned between multiple deep layers 15.

[0022] The deep layer 15 is composed of an ion-implanted layer formed by ion implantation of p-type impurities. As described above, the deep layer 15 is striped, and each line of the striped deep layer 15 has a constant width and is arranged at equal intervals, and the concentration of p-type impurities is constant in the depth direction, for example, 5 × 10 17 / cm 3 The above is the specification. Furthermore, the deep layer 15 has a thickness of 1 μm or less, which is the Z-direction dimension from the top surface to the bottom surface.

[0023] Furthermore, an n-type current dispersion layer 16, which constitutes part of the drift layer made of SiC, is formed on the JFET section 14 and the deep layer 15. The current dispersion layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET 30 to diffuse in the Y direction, and is formed in contact with the leading edge in the depth direction of the gate trench 21, which will be described later. For example, the n-type impurity concentration of the current dispersion layer 16 is higher than that of the low-concentration layer 13. However, it is not essential that the impurity concentration of the current dispersion layer 16 be higher than that of the low-concentration layer 13; for example, it may be the same impurity concentration as the low-concentration layer 13.

[0024] In this embodiment, the drift layer is composed of a buffer layer 12, a low-concentration layer 13, a JFET section 14, and a current-dispersing layer 16. However, the configuration of the drift layer is arbitrary, and for example, a structure without a buffer layer is also possible.

[0025] A p-type base region 17 made of SiC is formed on the current dispersion layer 16. Furthermore, an n-type base region made of SiC is formed on the base region 17. + A source region 18 of type p is formed. The base region 17 has a lower p-type impurity concentration than the deep layer 15. In addition, the source region 18 has a higher n-type impurity concentration than the current dispersion layer 16.

[0026] Furthermore, the p-type impurity concentration is higher than that of the base region 17 so that it reaches from the surface of the source region 18 to the base region 17. + A p-shaped contact region 19 is formed. In this embodiment, the contact region 19 is configured in a linear shape with the Y direction as its longitudinal direction. Furthermore, below the contact region 19, a p-shaped connecting layer 20 is formed that connects the base region 17 and the deep layer 15. The connecting layer 20 is formed in a linear shape with the Y direction as its longitudinal direction together with the contact region 19, and is arranged on both sides of the current distribution layer 16.

[0027] The contact region 19 and the connecting layer 20 play a role in connecting the deep layer 15 and the base region 17 to the source electrode 25, which will be described later, in order to fix the deep layer 15 and the base region 17 to the source potential.

[0028] The spacing between the contact regions 19 and the connecting layers 20 is arbitrary, but in this embodiment, they are formed on both sides of the trench gate structure, which will be described later. The width of the contact regions 19 and the connecting layers 20 is also arbitrary, but here it is set to be less than or equal to the spacing between adjacent trench gate structures.

[0029] Furthermore, a gate trench 21 is formed with a predetermined width and depth so as to penetrate the source region 18 and the base region 17 and reach the current distribution layer 16. The base region 17 and source region 18 are formed so as to be in contact with the side surface of this gate trench 21, and the contact region 19 is positioned away from the gate trench 21. The gate trench 21 is formed in a linear layout with the X direction as the width direction, and the Y direction as the longitudinal direction and the Z direction as the depth direction, intersecting the longitudinal direction of the JFET section 14 and the deep layer 15. As shown in Figure 1, the gate trench 21 is arranged in a stripe shape with multiple trenches arranged at equal intervals in the X direction, and the base region 17, source region 18, contact region 19 and connecting layer 20 are positioned between each of them.

[0030] The portion of the base region 17 located on the side of the gate trench 21 is designated as a channel region connecting the source region 18 and the current dispersion layer 16 when the vertical MOSFET 30 is operating, and the inner wall surface of the gate trench 21, including the channel region, is covered with a gate insulating film 22. A gate electrode 23 made of doped poly-Si is formed on the surface of the gate insulating film 22, and the trench gate structure is formed by arranging these gate insulating film 22 and gate electrode 23 within the gate trench 21. Furthermore, an interlayer insulating film 24 is formed to cover the gate electrode 23.

[0031] As shown in Figure 1, the source electrode 25 and other components are formed on the surface of the source region 18 and the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is composed of multiple metals, such as Ni / Al. Of these multiple metals, at least n-type SiC, specifically the portion in contact with the source region 18 and the gate electrode 23 in the case of n-type doping, is composed of a metal capable of ohmic contact with n-type SiC. Furthermore, of these multiple metals, at least p-type SiC, specifically the portion in contact with the contact region 19, is composed of a metal capable of ohmic contact with p-type SiC. The source electrode 25 is electrically insulated from the SiC portion by being formed on the interlayer insulating film 24, but it is electrically in contact with the source region 18 and the contact region 19 through contact holes 24a formed in the interlayer insulating film 24.

[0032] On the other hand, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back side of the SiC substrate 11. This structure constitutes a vertical MOSFET 30 with an n-channel inverted trench gate structure. Multiple such vertical MOSFETs 30 are arranged to form a cell region. Although not shown in the figures, an outer peripheral breakdown voltage structure such as a guard ring is formed to surround the cell region, thereby forming a SiC semiconductor device.

[0033] In a SiC semiconductor device with this configuration, an internal diode 40 is formed within the vertical MOSFET 30 by a pn junction between a low-concentration layer 13, a JFET section 14, etc., and a deep layer 15, a connecting layer 20, etc.

[0034] The above is a basic configuration example of the SiC semiconductor device according to this embodiment. As will be described later, this SiC semiconductor device can be used, for example, in an inverter circuit for driving a three-phase motor that uses a vertical MOSFET 30 as a switching element.

[0035] [Defect growth caused by BPD] As described above, the SiC semiconductor device has a structure in which a trench gate vertical MOSFET 30 and an internal diode 40 composed of a pn junction are provided in the cell region. Furthermore, BPDs exist in the SiC substrate 11 and the drift layer including the buffer layer 12, and defects caused by these BPDs can occur in the SiC semiconductor device.

[0036] The equivalent circuit of the SiC semiconductor device is shown in Figure 2 as a circuit configuration having a MOSFET 30 and an internal diode 40, and when the vertical MOSFET 30 is ON, an ON current I flows from the drain electrode 26 to the source electrode 25. ON This occurs. In Figure 2, "S", "D", and "G" correspond to the source electrode 25, drain electrode 26, and gate electrode 23, respectively. Specifically, when a predetermined voltage such as 20V is applied to the gate electrode 23, a channel region is formed on the surface of the base region 17 that is in contact with the gate trench 21, and an on-current I is generated between the source electrode 25 and the drain electrode 26. ON It plays.

[0037] Subsequently, when the SiC semiconductor device is turned off, a reverse bias is applied, causing it to conduct in reverse. Therefore, the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I flows through the built-in diode 40. OFF Current flows. At this time, as shown in Figure 3A, holes that have diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode 40 recombine with electrons in the n-type layer. Because the recombination energy of these holes and electrons is large, as shown in Figure 3B, BPD50 expands and SSF60 is formed. Furthermore, this SSF60 expands as the current stress on the built-in diode 40 accumulates. Since SSF60 occupies a larger area than BPD50, the on current I ON and return current I OFF This hinders the process. Furthermore, because the SSF60 expands in response to the current stress on the built-in diode 40, the electrical characteristics after operation deteriorate compared to the electrical characteristics immediately after manufacturing, i.e., before the SSF60 is formed.

[0038] For example, when a reverse bias is applied to the SiC semiconductor device of this embodiment, a freewheel current I is generated for the built-in diode 40. OFF The current was passed through the SSF60, and its state after the current was observed. Figure 4 is a binarized image of the PL image obtained by non-destructive testing using the PL method, which confirmed the degree of SSF60 expansion. The multiple white areas in the vertical lines of the figure represent SSF60. As shown in this figure, it can be seen that the SSF60 expands in the active region of the SiC semiconductor device's cell area, that is, in the region where the source electrode 25 is located and current is applied. In this way, the expansion of the SSF60, which occupies a large area, causes the on-current I ON and return current I OFF This hinders the process and degrades the electrical properties.

[0039] To suppress this deterioration in electrical characteristics, it is necessary to create a SiC semiconductor device with excellent diode current degradation characteristics that can prevent BPD50 from expanding to SSF60 even when stress accumulates on the built-in diode 40.

[0040] In particular, when SiC semiconductor devices are used in applications such as automotive power cards, the amount of current flowing through a single chip becomes large, making it unavoidable that the built-in diode 40 will turn on even when current is supplied through the channel region. Furthermore, even when using high currents in the freewheel mode where freewheel current flows, it is important to have a SiC semiconductor device with excellent diode current degradation characteristics to suppress hole injection and prevent the SSF60 from expanding.

[0041] [B concentration in SiC substrates] As shown in Patent Document 1 above, by mixing p-type impurities into an n-type SiC single crystal substrate, it is possible to suppress the expansion of BPD50 to SSF60. However, it has been confirmed that simply mixing in p-type impurities does not sufficiently suppress the expansion of BPD50 to SSF60. After diligent research, it was found that n +It was found that by introducing p-type impurity B into a SiC substrate 11 and adjusting the B concentration to a predetermined level or higher, it is possible to suppress the expansion of the required BPD50 to SSF60. Furthermore, it was found that the B concentration required to achieve this effect varies depending on the magnitude of the freewheeling current flowing in the forward direction of the built-in diode 40 when the SiC semiconductor device is applied to an inverter or the like, and that the larger the current, the higher the required B concentration.

[0042] Specifically, when applying a SiC semiconductor device to an inverter, we assumed cases where the current stress exceeded 600A and cases where it exceeded 800A, and applied a reverse bias to the SiC semiconductor device to allow forward current to flow through the built-in diode 40. Then, by changing the B concentration in the SiC substrate 11, we investigated the change in SSF area occupancy (%) after energization, and obtained the results shown in Figure 5. A current stress of 600A or more means that the current density, calculated by dividing this current value by the area of ​​the active region where current actually flows within the cell region where the vertical MOSFET 30 is formed, is 11.6A / mm². 2 This means that the result will be greater than or equal to the stated value. In the experiment, assuming an electrical stress of 600A or more, the actual current that flowed was 656A. In this case, the current density was 12.66A / mm². 2 Furthermore, an electrical stress of 800A or more means that the current density of the current flowing in the active region is 14.6A / mm². 2 This means that the value will be greater than or equal to the above. In the experiment, the actual current that flowed was 900A, assuming an electrical stress of 800A or more. The current density in this case is 16.41A / mm². 2 That was the case.

[0043] As shown in this figure, in both cases where the current stress is 600A or more and 800A or more, the SSF area occupancy rate can be reduced by introducing B into the SiC substrate 11, but the B concentration is 9.0 × 10 16 / cm 3If the value is less than this, the SSF area occupancy is high. This indicates that the effect of suppressing the expansion of BPD50 to SSF60 is not sufficiently obtained. As a result, excellent diode current degradation characteristics cannot be obtained.

[0044] In contrast, when the recirculation current is 600A or higher, in this case 656A, the B concentration is at least 9.0 × 10 16 / cm 3 At this level, the SSF area occupancy rate can be reduced to 3% or less. Also, in the case of 800A or higher, and in this case even 900A, the B concentration is at least 1.5 × 10 17 / cm 3 With these results, the SSF area occupancy rate can be reduced to 3% or less. In other words, the effect of suppressing the expansion of BPD50 to SSF60 is sufficiently achieved.

[0045] Based on these results, in order to ensure the diode current degradation characteristics, when a SiC semiconductor device is applied in a configuration where the current stress on the built-in diode 40 is 600A or more, the B concentration in the SiC substrate 11 should be set to 9.0 × 10 16 / cm 3 The above is the standard. Furthermore, when a SiC semiconductor device is applied in a configuration where the current stress on the built-in diode 40 exceeds 800A, the B concentration in the SiC substrate 11 is set to 1.5 × 10⁻¹⁰ 17 / cm 3 The above is the result. This makes it possible to create a SiC semiconductor device that exhibits excellent diode current degradation characteristics. Note that the greater the current stress, the greater the B concentration in the SiC substrate 11 required to obtain excellent diode current degradation characteristics. In this experiment, which assumed a 600A specification, the actual current that flowed was 656A, and the B concentration required at that time was 9.0 × 10⁻¹⁶. 16 / cm 3 However, in the case of 600A, a lower B concentration is required, so at least 9.0 × 10 16 / cm 3 The above is sufficient. Similarly, in an experiment where an 800A specification was assumed, the actual current that flowed was 900A, and the required B concentration at that time was 1.5 × 10⁻⁶. 17 / cm 3 However, in the case of 800A, a lower B concentration is required, so at least 1.5 × 10 17 / cm 3 Anything above that is fine.

[0046] On the other hand, regarding the B concentration in the SiC substrate 11, the higher the concentration, the smaller the SSF area occupancy. However, it was found that if the B concentration in the SiC substrate 11 is too high, problems occur when the SiC substrate 11 is in wafer form.

[0047] The SiC substrate 11 is n + This is constructed by dicing a SiC wafer into chip units. Specifically, a device formation process is performed on a SiC wafer to form vertical MOSFETs 30 and other elements, and then the SiC semiconductor device is constructed by dicing it into chip units. The portion that was originally the SiC wafer is called the SiC substrate 11.

[0048] SiC wafers are typically of a specified size, such as 6-inch or 8-inch wafers, and are transported to various devices such as epitaxial growth systems and ion implantation systems for device formation. However, depending on the amount of warpage of the SiC wafer, the vacuum chucks in the equipment may fail to hold the wafer, or the wafer may move from its desired position during transport, preventing successful device formation. Therefore, it is necessary to keep the amount of warpage of the SiC wafer within a specified range.

[0049] However, increasing the B concentration in the SiC substrate 11 increased the amount of warping of the SiC wafer, making it impossible to keep it within the specified range and thus preventing a successful device formation process. The relationship between the amount of warping of the SiC wafer and the B concentration was investigated by conducting experiments using a 6-inch wafer with a thickness of 350 μm. The results are shown in Figure 5.

[0050] As shown in this figure, the amount of warpage increases as the B concentration in the SiC substrate 11 increases. For good transport during the device formation process and adsorption of the SiC wafer in the vacuum chuck, it is preferable that the amount of warpage be 300 μm or less. To satisfy this, when using a 6-inch SiC wafer with a 350 μm specification, the B concentration should be 1.75 × 10⁻¹⁶, as shown in Figure 5 and Figure 13A described later. 17 / cm 3 The following is preferable. Therefore, when using a 6-inch wafer with a thickness of 350 μm as the SiC wafer, the B concentration in the SiC substrate 11 should be 1.75 × 10 17 / cm 3 The following applies:

[0051] Furthermore, when using an 8-inch SiC wafer, similar experiments were conducted for both 350 μm and 500 μm thickness specifications. As a result, as shown in Figure 13B described later, the B concentration in the SiC substrate 11 was 1.8 × 10⁻¹⁰ when the thickness was 350 μm. 17 / cm 3 The following is preferable; if a 500 μm specification is used, then 7.2 × 10 17 / cm 3 The following was found to be preferable.

[0052] In other words, whether the SiC wafer is a 6-inch or 8-inch wafer, if the thickness is 350 μm, the B concentration in the SiC substrate 11 is 1.75 × 10⁻¹⁰ 17 / cm 3 The following measures can be used to reduce the amount of warping to a level that does not affect transport. Furthermore, when using an 8-inch SiC wafer, if the thickness is 500 μm, the B concentration within the SiC substrate 11 should be 7.2 × 10⁻⁶. 17 / cm 3 The amount of warping can be suppressed by following the conditions below. Therefore, the B concentration in the SiC substrate 11 is set to satisfy these conditions.

[0053] The term "warpage" here refers to the magnitude of warpage that occurs during the device formation process. "Warpage" is calculated as the difference in height between the highest and lowest points on one surface of the SiC wafer when it is placed on a flat surface. Normally, SiC wafers are not perfectly flat, but have some warpage even in their initial state before the device formation process. During transport, the SiC wafer will have not only the warpage generated during the device formation process, but also the initial warpage. However, it is difficult to completely eliminate the initial warpage, and even if the warpage is reduced, it may still occur in a range of, for example, 200 μm. Therefore, it is necessary to adjust the warpage to a level that does not interfere with the device formation process, even when the initial warpage is included. The B concentration in the SiC substrate 11 is specified so that the warpage remains within a range that does not interfere with the device formation process.

[0054] Furthermore, when the built-in diode 40 is made to operate bipolar by freewheeling, the hole density at the interface between the SiC substrate 11 and the buffer layer 12 is 1.2 × 10⁻¹⁰. 16 / cm 3 It has been confirmed that hole injection into the SiC substrate 11 can be suppressed if the following conditions are met. As in this embodiment, when the B concentration in the SiC substrate 11 is set to the above range, the hole density at the interface between the buffer layer 12 and the low-concentration layer 13 is 1.2 × 10⁻⁶. 16 / cm 3 It was also possible to satisfy the condition of keeping it below the following level.

[0055] Through simulation, when the current stress on the built-in diode was set to 600A or more, the change in hole density at each part was confirmed when trap sites were formed in the SiC substrate 11 by acceptors assuming B. Specifically, the B concentration in the SiC substrate 11 was set to 1.0 × 10⁻⁶. 15 / cm 3 , 1.0 × 10 17 / cm 3 , 1.0 × 10 19 / cm 3As an example, changes in hole density at each portion near the buffer layer 12 were investigated. FIG. 6 shows the results. Further, FIG. 7 is a diagram in which the hole density at the interface between the SiC substrate 11 and the buffer layer 12 at each B concentration used in the simulation is plotted and linearly approximated. The measurement conditions are as follows: gate voltage Vg=3.5V, source-drain current Isd=470A, gate-source voltage Vgs=-3.5V, temperature Tj=175°C.

[0056] As shown in FIG. 6 and FIG. 7, when the B concentration in the SiC substrate 11 is set to 1.0×10 15 / cm 3 , the hole density is 1.8×10 16 / cm 3 or higher. However, when the B concentration in the SiC substrate 11 is set to 1.0×10 17 / cm 3 , the hole density is 1.1×10 16 / cm 3 or lower, and when the B concentration is set to 1.0×10 19 / cm 3 , the hole density is 2.0×10 15 / cm 3 or lower. As shown in FIG. 7, when linear approximation is performed, when the B concentration is about 7.0×10 16 / cm 3 , the hole density becomes 1.2×10 16 / cm 3 .

[0057] For this reason, when the conduction stress of the built-in diode 40 is set to 600A or more, if the B concentration in the SiC substrate 11 is set to 7.0×10 16 / cm 3 or higher, it is possible to suppress hole current from flowing to the buffer layer 12 side. In the present embodiment, when the conduction stress of the built-in diode 40 is set to 600A or more, the B concentration in the SiC substrate 11 is set to 9.0×10 16 / cm 3 . Therefore, the hole density can be maintained at 1.2×10 16 / cm 3As described below, the flow of Hall current to the buffer layer 12 can be suppressed, making it possible to suppress the expansion of BPD50 in the SiC substrate 11 into SSF60.

[0058] Furthermore, a similar simulation was performed when the current stress on the built-in diode 40 was set to 800A or more. In this case as well, as described above, the B concentration was set to 1.5 × 10⁻⁶. 17 / cm 3 If the above is true, the hole density will be 1.2 × 10⁻⁶ 16 / cm 3 The following could be achieved. Therefore, in this case as well, the expansion of BPD50 in the SiC substrate 11 into SSF60 can be suppressed, similar to the above.

[0059] Here, as described above, in this embodiment, when the current stress of the built-in diode 40 is set to 600A or more, the B concentration in the SiC substrate 11 is set to 9.0 × 10 16 / cm 3 However, 7.0 × 10 16 / cm 3 The above effect can be obtained if the above is achieved. Also, if the current stress on the built-in diode 40 is 800A or more, the B concentration should be 1.5 × 10 17 / cm 3 The above effects can be obtained by doing the above. These represent the magnitude of the forward current flowing through the built-in diode 40, in other words, the magnitude of the current stress, as the B concentration of the SiC substrate 11 for two forms: 600A or more and 800A or more. However, it can be quantified as the B concentration in relation to the magnitude of the current stress. As shown in Figure 8A, the current stress is 12.66 A / mm 2 In this case, the B concentration is 7.0 × 10 16 / cm 3 The electrical stress is 16.41 A / mm². 2 In this case, the B concentration is 1.5 × 10 17 / cm 3A straight line L1 can be drawn connecting the two plotted points. This line L1 represents the boundary where the SSF area occupancy rate becomes 3% after applying electrical stress. Therefore, by setting the B concentration in the SiC substrate 11 for the expected electrical stress such that the relationship between the B concentration in the SiC substrate 11 and the magnitude of the electrical stress lies to the right of the line L1, the expansion of BPD50 to SSF60 can be suppressed.

[0060] Furthermore, while it is possible to suppress the expansion of BPD50 to SSF60 by adjusting the B concentration in the SiC substrate 11, it has been confirmed that the n-type impurity concentration in the buffer layer 12 can also have an effect. Specifically, as shown by the dashed line La in Figure 9, the concentration of N doped as an n-type impurity is gradually reduced in the SiC substrate 11, buffer layer 12, and low-concentration layer 13 in order from location to location. For the buffer layer 12, the n-type impurity concentration is 6.0 × 10⁻⁶. 17 ~1.5×10 18 / cm 3 This results in a concentration profile with a reduced concentration distribution in the thickness direction. For example, 1.0 × 10 18 / cm 3 With this as the target value, ±0.5 × 10 18 / cm 3 This is intended to be within this range. However, as shown by the solid line Lb, the n-type impurity concentration of the buffer layer 12 drops on the SiC substrate 11 side, reaching 6.0 × 10 17 / cm 3 It may fall below this value. In this case, the ratio of BPD50 expanding to SSF60 may be higher compared to the concentration profile of the dashed line La. For this reason, it is preferable to keep the n-type impurity concentration of the buffer layer 12 within a concentration range of ±50% of the target value, so as not to drop in the n-type impurity concentration. However, although it is preferable to avoid a drop, if a drop occurs, it is also possible to address this by defining a boundary line where the SSF area occupancy rate becomes 3% after applying electrical stress. For example, when the electrical stress is 11.6 A / mm 2 In this case, the B concentration is 9 × 10 16 / cm 3It was confirmed that the above is desirable. Furthermore, the electrical stress was 16.0 A / mm². 2 In the above case, the B concentration is 1.5 × 10 17 / cm 3 It was confirmed that the above is desirable. In this case, as shown in Figure 8B, the electrical stress is 11.6 A / mm². 2 B concentration 9.0 × 10 16 / cm 3 The electrical stress is 16.0 A / mm². 2 In this case, the B concentration is 1.5 × 10 17 / cm 3 A straight line L2 can be drawn connecting the two plotted points. This line L2 can then be used as the boundary line where the SSF area occupancy rate becomes 3% after applying electrical stress.

[0061] [Method for manufacturing SiC semiconductor devices] Next, the manufacturing method of the SiC semiconductor device according to this embodiment will be described with reference to Figures 10A to 10G. Figures 10A to 10G are cross-sectional perspective views showing the manufacturing process in progress for the part corresponding to Figure 1.

[0062] [Process shown in Figure 10A] First, n + A SiC wafer is prepared to constitute the type SiC substrate 11. For the SiC wafer prepared at this time, if the current stress is 600A or more, the B concentration is set to 9.0 × 10⁻⁶. 16 / cm 3 If the concentration is 800A or higher, the B concentration is 1.5 × 10 17 / cm 3 That concludes the explanation. Furthermore, regarding the SiC wafers to be prepared, if they are 350 μm thick, the B concentration should be 1.75 × 10⁻¹⁰, taking into account the amount of warpage. 17 / cm 3 The following is preferable: If the thickness is 500 μm, the B concentration should be 7.2 × 10, taking into account the amount of warping. 17 / cm 3 The following is preferable.

[0063] Next, an epitaxial film is grown on the surface of the SiC substrate 11 to form a buffer layer 12 and a low-concentration layer 13 made of SiC. Then, a mask (not shown) is formed on the surface of the low-concentration layer 13, and the mask is patterned by photolithography or the like so that the area where the JFET portion 14 is to be formed is open. Specifically, the mask is patterned so that only the cell region is open. Then, n-type impurities such as N or P are ion-implanted onto the mask and heat-treated to form the JFET portion 14. After that, the mask is removed. For example, an LTO (Low Temperature Oxide) film is used as the mask. In this embodiment, a mask is also used in the process described later, and for each mask, for example, an LTO film is used.

[0064] [Process shown in Figure 10B] A mask 31 is formed, and the mask 31 is patterned using photolithography or the like so that the area where the deep layer 15 is to be formed is open. Then, p-type impurities such as Al are ion-implanted onto the mask 31 and heat-treated to form the deep layer 15.

[0065] [Process shown in Figure 10C] A current-dispersing layer 16 made of SiC is epitaxially grown on the low-concentration layer 13, the JFET section 14, and the deep layer 15. This forms a drift layer consisting of the buffer layer 12, the low-concentration layer 13, the JFET section 14, and the current-dispersing layer 16.

[0066] Next, a mask (not shown) is formed, and the mask is patterned using photolithography or the like so that the area where the connecting layer 20 is to be formed is open. Then, the connecting layer 20 is formed by ion implanting p-type impurities such as Al onto the mask and then heat-treating it. At this time, the connecting layer 20 is extended in a direction intersecting the extension direction of the deep layer 15. Therefore, even if there is some misalignment when forming the connecting layer 20, it is possible to suppress the occurrence of a problem where the deep layer 15 and the connecting layer 20 do not connect.

[0067] [Process shown in Figure 10D] A base region 17 is formed by epitaxially growing a p-type impurity layer on the current dispersion layer 16 and the connecting layer 20. Subsequently, a source region 18 is formed by epitaxially growing an n-type impurity layer on the base region 17.

[0068] [Process shown in Figure 10E] A mask (not shown) is formed, and the mask is patterned using photolithography or the like so that the area where the contact region 19 is to be formed is open. Furthermore, the contact region 19 is formed by ion implanting p-type impurities such as Al onto the mask and then heat-treating it.

[0069] [Process shown in Figure 10F] After forming a mask (not shown), the mask is patterned so that the area where the gate trench 21 is to be formed is open. Then, anisotropic etching is performed, and isotropic etching or sacrificial layer oxidation is performed as needed to form the gate trench 21.

[0070] [Process shown in Figure 10G] A gate insulating film 22 is formed in the area including the gate trench 21 by thermal oxidation or CVD (chemical vapor deposition). Subsequently, a polysilicon layer doped with n-type impurities is deposited on the surface of the gate insulating film 22, and then an etch-back process or the like is performed so that the gate insulating film 22 and gate electrode 23 remain in the gate trench 21. This constitutes a trench gate structure.

[0071] Although not shown in the diagram, the subsequent steps include forming the interlayer insulating film 24, creating contact holes 24a, forming source electrodes 25 and gate wiring, and forming drain electrodes 26 on the back side of the SiC substrate 11. This completes the manufacturing of the SiC semiconductor device according to this embodiment.

[0072] Vertical devices, such as SiC power MOSFETs, allow for the creation of high-field-resistant devices with shorter vertical distances, i.e., shorter distances in the Z-axis direction (which is the thickness), compared to Si devices. Furthermore, in SiC, impurities do not diffuse as they do in Si, so there is a tendency to increase the ion implantation dose when forming the impurity layer to increase the impurity concentration. In addition, to improve the breakdown voltage of the gate insulating film 22, it is necessary to increase the ion implantation depth for forming the deep layer 15, and ion implantation is performed at a high acceleration energy. For example, in the ion implantation process for the deep layer 15 described above, ion implantation is performed to a relatively shallow depth of 1 μm or less, so although it is below 1 MeV, high-acceleration ion implantation at a high ion implantation energy is still performed.

[0073] When an ion implantation process is performed with a high impurity concentration and a deep implantation depth, it tends to cause significant warping in the SiC wafer used to construct the SiC substrate 11. However, after thorough investigation, it was found that the amount of warping itself does not depend on the impurity concentration or implantation depth in ion implantation, but rather on the B concentration in the SiC wafer, that is, the amount of B mixed in during the SiC ingot manufacturing process.

[0074] Figure 11 shows the results of measuring the amount of warpage of multiple SiC wafer samples before the device formation process and after the formation of the deep layer 15. The horizontal axis of Figure 11 shows the sample number, where the first A-J is the ingot number, and the following numbers 1-15 indicate the order in which the SiC wafers were cut. The same ingot number means that the SiC wafers were cut from the same SiC ingot. For example, A-1 indicates the first SiC wafer cut from the SiC ingot number "A". The order in which the SiC wafers were cut indicates the number when they were cut in order from the leading edge of the SiC ingot. For example, suppose a SiC ingot 100 as shown in Figure 12 was obtained. In this case, SiC wafers 102 are cut in order from the growth surface 101 side of the SiC ingot 100 toward the seed crystal 110 side, and the order of the cut SiC wafers 102 is represented by the numbers.

[0075] In Figure 11, when comparing SiC wafers 102 obtained from the same SiC ingot 100 in regions R1 and R2, respectively, the amount of warpage is similar both before the device formation process and after the formation of the deep layer 15. However, when comparing SiC wafer 102 in region R1 and SiC wafer 102 in region R2, although the amount of warpage before the device formation process is similar, the amount of warpage after the formation of the deep layer 15 is not similar. This is due to the B concentration in the SiC wafer 102. Since the B concentration is similar in the same SiC ingot 100, the amount of warpage after the formation of the deep layer 15 is similar, but if the B concentration is different, the amount of warpage after the formation of the deep layer 15 will not be similar.

[0076] Thus, it is clear that the amount of warpage of the SiC wafer 102 during the device formation process depends on the B concentration in the SiC wafer 102, that is, the amount of B mixed in during the manufacturing of the SiC ingot 100. Therefore, in order to control the amount of warpage, it is necessary to adjust the B concentration in the SiC wafer that makes up the SiC substrate 11 in advance.

[0077] When the relationship between the amount of warpage and the B concentration in the SiC substrate 11 was investigated, the results for the 6-inch wafer were as shown in Figure 13A, and the results for the 8-inch wafer were as shown in Figure 13B. For the 6-inch wafer, the investigation was conducted for a thickness of 350 μm. For the 8-inch wafer, the investigation was conducted for both a thickness of 350 μm and a thickness of 500 μm. This relationship was basically obtained through actual measurements, but for parts where there was a gap between plots of multiple measured values, values ​​calculated by interpolation and extrapolation were used.

[0078] As shown in Figures 13A and 13B, for any size of SiC wafer 102, the amount of warpage increased as the B concentration in the SiC substrate 11 increased. For a 6-inch wafer, the B concentration at which the warpage was 300 μm was 1.75 × 10⁻¹⁶. 17 / cm3 Similarly, for an 8-inch wafer, if the warpage is 300 μm, the B concentration for a 350 μm specification is 1.8 × 10 17 / cm 3 For the 500μm specification, it is 7.2 × 10 17 / cm 3 That was the case.

[0079] Therefore, as explained in the process shown in Figure 10A, when the thickness is 350 μm, the B concentration is preferably 1.75 × 10 17 / cm 3 The following applies: If the thickness is 500 μm, preferably the B concentration is 7.2 × 10 17 / cm 3 The following is stated. This makes it possible to create SiC semiconductor devices with excellent diode current conduction characteristics, and also makes it possible to keep the amount of warping of the SiC wafer 102 during the device formation process within a specified range. Therefore, it becomes possible to perform transport and adsorption of the SiC wafer 102 in the vacuum chuck during the device formation process smoothly, enabling the device formation process to proceed smoothly.

[0080] (Second Embodiment) A second embodiment will now be described. This embodiment is a modification of the configuration of the vertical MOSFET 30 provided in the SiC semiconductor device compared to the first embodiment. Since the other aspects are the same as the first embodiment, only the differences from the first embodiment will be described.

[0081] In the first embodiment, the deep layer 15 was connected to the base region 17 via a connecting layer 20. However, as shown in Figure 14, in this embodiment, the connecting layer 20 is eliminated, and the deep layer 15 is directly connected to the base region 17.

[0082] In this embodiment, the current dispersion layer 16 is formed to be in contact with the leading edge in the depth direction of the gate trench 21, but it may be omitted. Also, since the current dispersion layer 16 is provided on the portion of the JFET section 14 located between the deep layers 15, the n-type impurity concentration in the surface layer of the JFET section 14 may be made higher than in the portion located below it, and this may be used as the current dispersion layer 16.

[0083] Furthermore, a p-type field relaxation layer 27 is provided along the bottom surface of the gate trench 21. The field relaxation layer 27 is composed of a p-type layer with a lower impurity concentration than, for example, the deep layer 15. Specifically, the field relaxation layer 27 is formed along the longitudinal direction of the gate trench 21. In other words, the field relaxation layer 27 extends along the Y-axis direction that intersects with the deep layer 15. In addition, although the field relaxation layer 27 in this embodiment is formed shallower than the JFET section 14 and the deep layer 15, it may also be formed so that its bottom surface penetrates the JFET section 14 and the deep layer 15 and reaches the low-concentration layer 13.

[0084] Thus, the deep layer 15 can also be directly connected to the base region 17. In this SiC semiconductor device structure as well, by setting the B concentration in the SiC substrate 11 to the concentration described in the first embodiment, the expansion of BPD50 to SSF60 can be suppressed. Furthermore, by setting the B concentration to take into account the amount of warpage, it becomes possible to keep the amount of warpage of the SiC wafer 102 during the device formation process within a specified range.

[0085] Furthermore, in the structure of this embodiment, the distance from the bottom of the deep layer 15 to the bottom of the gate insulating film 22 is shorter compared to the first embodiment, raising concerns about electric field penetration into the gate insulating film 22. However, since the electric field relaxation layer 27 is provided along the bottom surface of the gate trench 21, the penetration of electric field into the gate insulating film 22 located at the bottom of the gate trench 21 can be suppressed, thereby suppressing gate insulating film breakdown. In addition, by forming the electric field relaxation layer 27 in contact with the bottom surface of the gate trench 21, the capacitance between the gate electrode 23 and the drain electrode 26, i.e., the feedback capacitance, can be reduced, improving the switching speed. Moreover, by providing the electric field relaxation layer 27, the creeping of electric field to the JFET section 14 arranged between the electric field relaxation layers 27 is suppressed, improving the breakdown voltage.

[0086] The electric field relaxation layer 27 may be formed by dividing it into multiple sections along the Y-axis. However, the electric field relaxation layer 27 is formed to be electrically connected to the base region 17 via the deep layer 15.

[0087] Next, the manufacturing method of the SiC semiconductor device according to this embodiment will be described with reference to Figures 15A to 15F.

[0088] [Process shown in Figure 15A] After preparing a SiC wafer to constitute a SiC substrate 11 with a desired B concentration by performing the same steps as shown in Figure 10A of the first embodiment, the buffer layer 12 and the low-concentration layer 13 are epitaxially grown. At this time, the thickness of the low-concentration layer 13 is set to be the sum of the thickness of the JFET portion 14, the current dispersion layer 16, and the base region 17, source region 18, and contact region 19.

[0089] [Process shown in Figure 15B] After forming a mask (not shown), n-type impurities such as N and P are ion-implanted into the surface of the low-concentration layer 13 and then heat-treated to form the JFET section 14 and the current-dispersion layer 16, which are composed of ion-implanted layers. For the JFET section 14 and the current-dispersion layer 16, the dose amount of n-type impurities and the ion implantation energy are varied to implant them in different ways.

[0090] [Process shown in Figure 15C] A process similar to that shown in Figure 10B of the first embodiment is performed to form a mask, although not shown, so that the area where the deep layer 15 is to be formed is open. Then, p-type impurities such as Al are ion-implanted onto the mask and heat-treated to form the deep layer 15, which is composed of an ion-implanted layer.

[0091] In the process shown in Figure 15B, a thick low-concentration layer 13, composed of an epitaxial film, is formed. In this case, when forming the deep layer 15, the ion implantation energy is increased so that ion implantation is possible to a depth of 1 μm or more from the surface of the low-concentration layer 13, which will become the source region 18 in a later process. For example, the deep layer 15 is formed by high-acceleration ion implantation with a high ion implantation energy of 1 MeV or more.

[0092] When an ion implantation process is performed with a high impurity concentration and a deep implantation depth, it tends to cause significant warping in the SiC wafer 102 used to form the SiC substrate 11. However, this does not depend on the impurity concentration or implantation depth during ion implantation, but rather on the B concentration in the SiC wafer 102, that is, the amount of B mixed in during the manufacturing of the SiC ingot 100. Therefore, as in this embodiment, even when an ion implantation process is performed with a high ion implantation energy of 1 MeV or more, it is possible to keep the amount of warping of the SiC wafer 102 during the device formation process within a specified range.

[0093] [Process shown in Figure 15D] A mask with a cell region (not shown) opening is placed on the surface of the low-concentration layer 13, and then p-type impurities such as Al are ion-implanted and heat-treated. As a result, a base region 17 composed of the ion-implanted layer is formed on the JFET section 14, the deep layer 15, and the current-dispersing layer 16.

[0094] [Process shown in Figure 15E] After forming a mask (not shown) with an opening in the area where the source region 18 is to be formed, n-type impurities such as N and P are ion-implanted into the surface layer of the low-concentration layer 13 from above the mask and then heat-treated. This forms the source region 18, which is composed of an ion-implanted layer, on top of the base region 17. Subsequently, after forming a mask (not shown) with an opening in the area where the contact region 19 is to be formed, p-type impurities such as Al are ion-implanted into the mask and then heat-treated. This forms the contact region 19, which is composed of an ion-implanted layer.

[0095] [Process shown in Figure 15F] After forming a mask (not shown), the mask is patterned so that the area where the gate trench 21 is to be formed is open. Then, anisotropic etching is performed to form the gate trench 21. Furthermore, using the mask (not shown) as is, p-type impurities such as Al are ion-implanted into the bottom surface of the gate trench 21 and then heat-treated to form an electric field relaxation layer 27.

[0096] The subsequent steps are the same as those shown in Figure 10G and later in the first embodiment. In this way, the SiC semiconductor device of this embodiment is manufactured.

[0097] As described above, in this embodiment, the ion implantation energy in the ion implantation process is higher than in the first embodiment, but the amount of warpage of the SiC wafer 102 can be kept within a specified range. This makes it possible to transport the SiC wafer 102 in the device formation process and to adsorb the SiC wafer 102 in the vacuum chuck smoothly, thereby enabling the device formation process to proceed smoothly.

[0098] (Third embodiment) A third embodiment will now be described. This embodiment specifies the relationship between the B concentration in the SiC substrate 11 and other p-type impurities, in addition to the B concentration in the SiC substrate 11, and is otherwise the same as the first and second embodiments.

[0099] To prepare the SiC wafer 102 for the SiC substrate 11, SiC single crystals are grown in a growth crucible using either sublimation or gas growth. Specifically, a SiC ingot composed of SiC single crystals is manufactured, and the SiC wafer 102 is formed by slicing it. The B concentration in the SiC ingot is then adjusted so that the B concentration in the SiC substrate 11 reaches the desired value. That is, for the B concentration in the SiC ingot, if the current stress is 600A or higher, it is 9.0 × 10⁻¹⁴. 16 / cm 3 For 800A or more, use 1.5 x 10 17 / cm 3 The above is the intended result. Furthermore, considering the amount of warping, if it is a 350 μm specification, then 1.75 × 10 17 / cm 3 For the 500μm specification, multiply by 10. 17 / cm 3 The B concentration of the SiC ingot is adjusted as follows. At this time, it was found that the elemental ratio of p-type impurity elements contained in the SiC substrate 11 is ultimately determined according to the elemental ratio of the SiC raw material used for growing the SiC single crystal.

[0100] As an example, we will describe an experiment in which crystal growth was performed using the SiC single crystal manufacturing apparatus 200 shown in Figure 16 by the sublimation method. In the sublimation method, a raw material powder 201, which is a powder of SiC that serves as the raw material for SiC, is heated and sublimated to produce a SiC ingot 203 on the surface of a seed crystal 202 composed of a SiC single crystal. In the experiment, a growth crucible 204 made of graphite or the like was induction heated to approximately 2500°C to decompose the raw material powder 201 placed below the base 205, and a SiC ingot 203 was grown on the surface of the seed crystal 202 attached to the base 205. In addition to SiC powder, which is a powder of SiC, a B powder containing boron carbide or boron nitride as a B raw material was introduced as the raw material powder 201. Furthermore, by introducing N2 gas as an n-type dopant, an n-type SiC ingot 203 was obtained.

[0101] In addition to B, the raw material powder 201 contains various impurities, including p-type impurity elements, and the amount of these impurities depends on the purity of the raw material powder 201. Experiments were conducted to measure the amount of various p-type impurity elements contained in the raw material powder 201 and the amount of various p-type impurity elements contained in the SiC substrate 11 obtained by manufacturing a SiC wafer 102 using a SiC ingot 203 manufactured using the raw material powder 201. Figure 17A is a graph of the amount of various impurity elements contained in the SiC substrate 11, and Figure 17B is a graph of the amount of various impurity elements contained in the raw material powder 201.

[0102] Furthermore, the ratio R when p-type impurity elements contained in the raw material powder 201 are incorporated into the SiC substrate 11 P / S The ratio R of the p-type impurity content in the raw material powder 201 to the p-type impurity content in the SiC substrate 11. S / P We investigated the ratio R P / S or magnification R S / P This indicates the ease with which elements are incorporated into the SiC substrate 11. Ratio R P / S For this, the larger the magnification R, S / P The smaller the size, the easier it is for the element to be incorporated into the SiC substrate 11. Figures 18A and 18B summarize these results.

[0103] As shown in this figure, the concentration of B in the raw material powder 201 is 7.0 × 10 17 / cm 3 At that time, the B concentration in the SiC substrate 11 is 9.5 × 10 17 / cm 3 The ratio R is as follows: P / S 136%, magnification R S / P The ratio was 0.7 times. Furthermore, for p-type impurities such as Al (aluminum), Nb (niobium), Ti (titanium), V (vanadium), and Fe (iron), the ratios were as shown in Figures 18A and 18B. As shown in Figure 18B, the ratio R for each element was P / S and magnification R S / PAlthough the proportions differed, the ratio of each element to its content in the raw material powder 201 approximated a straight line of 1:1, as shown in Figure 18A. In other words, the amount of impurities contained in the raw material powder 201, or in other words, the quality of the raw material powder 201, is important, and once that is determined, the B concentration in the SiC substrate 11 can be adjusted.

[0104] For example, for B, the magnification R S / P If the B concentration in the raw material powder 201 is set to 0.7 times the target value, the B concentration in the SiC substrate 11 can be set to the target value. For this reason, the SiC ingot 203 is grown with the B concentration in the raw material powder 201 set to approximately 0.7 times the target value of the B concentration in the SiC substrate 11. Similarly, for Al, the SiC ingot 203 is grown so that the Al concentration in the raw material powder 201 is approximately 1.4 times the target value. For Nb, the SiC ingot 203 is grown so that the Nb concentration in the raw material powder 201 is approximately 1.5 times the target value. For Ti, the SiC ingot 203 is grown so that the Ti concentration in the raw material powder 201 is approximately 6.7 times the target value. For V, the SiC ingot 203 is grown so that the V concentration in the raw material powder 201 is approximately 10 times the target value. For Fe, the SiC ingot 203 is grown so that the Fe concentration in the raw material powder 201 is approximately 1.7 times the target value. This allows the concentrations of various p-type impurities in the SiC substrate 11 to be set to the desired target values.

[0105] Furthermore, if there is an upper limit to the impurity concentration in the SiC substrate 11, and the target value is to be below that upper limit, the impurity concentration in the raw material powder 201 will be reduced to the target value by the multiplier R of the impurity. S / P The value is to be less than or equal to the value obtained by dividing by . This makes it possible to set the impurity concentration in the SiC substrate 11 to a desired upper limit or less. Also, if there is a lower limit to the impurity concentration in the SiC substrate 11 and the target value is to be greater than or equal to that lower limit, the impurity concentration in the raw material powder 201 is set to the target value impurity concentration multiplied by the ratio R of the impurity. S / PThe value obtained by dividing by this factor should be greater than or equal to the value obtained by this factor. This allows the impurity concentration in the SiC substrate 11 to be set to a value greater than or equal to the desired lower limit.

[0106] Furthermore, the B concentration in the SiC substrate 11 is 7.0 × 10 16 ~×1.4×10 17 / cm 3 The concentrations of various p-type impurities were measured in the given conditions, and it was investigated whether changes in the concentrations of p-type impurities other than B affected the expansion of BPD50 to SSF60. The effect on the warpage of the SiC wafer 102 was also investigated. The results showed that the effect on the expansion of BPD50 to SSF60 and the warpage of the SiC wafer 102 was limited, confirming that adjusting the B concentration was sufficient. Specifically, the amount of other impurities present was measured when the B concentration in the SiC substrate 11 was set to a range that suppressed the expansion of BPD50 to SSF60 while keeping the warpage within a specified range. The results showed that the total impurity concentration of p-type impurities other than B was 2.3 × 10⁶ in a 6-inch wafer. 17 / cm 3 Below, for 8-inch wafers, 2.9 × 10 17 / cm 3 The following was observed. Furthermore, the Al concentration for both the 6-inch and 8-inch wafers was 5.0 × 10⁶. 15 / cm 3 Below, the Ti concentration is 1.0 × 10 16 / cm 3 Below, the V concentration is 4.0 × 10 15 / cm 3 Below, the Fe concentration is 6.0 × 10 16 / cm 3 The following conditions were observed. Therefore, if the total impurity concentration of p-type impurities other than B was below these concentrations, it was possible to keep the amount of warping within the specified range while suppressing the expansion of BPD50 to SSF60 by adjusting at least the B concentration to the range described in the first and second embodiments.

[0107] Here, we have given an example of producing SiC ingot 203 by the sublimation method, but it may also be produced by the gas growth method. In the case of the gas growth method, a gas inlet is provided at the bottom of the growth crucible 204, and an exhaust port is provided at the top or side of the growth crucible 204, and SiC raw material gas, n-type dopant, and B-dopant gas are introduced to produce SiC ingot 203.

[0108] In the sublimation method, the raw material powder 201 is placed in the growth crucible 204, but its state cannot be observed during growth. However, in the gas growth method, the introduced gas can be controlled. For this reason, the gas growth method makes it easier to control the concentration of p-type impurities, including B, in the SiC ingot 203 than the sublimation method. In fact, SiC ingot 203 was manufactured using both the sublimation method and the gas growth method, and the concentrations of each p-type impurity were measured. When examining the deviation of the actual impurity concentration from the target value, the gas growth method brought the actual impurity concentration closer to the target value for B than the sublimation method. For other p-type impurities, the gas growth method sometimes brought the actual impurity concentration closer to the target value, and conversely, the sublimation method sometimes brought the actual impurity concentration closer to the target value. Therefore, when controlling the B concentration with greater precision, the gas growth method is preferable, but when controlling the concentrations of other p-type impurities, both the gas growth method and the sublimation method can provide a similar level of control.

[0109] When producing SiC ingots 203 by gas growth, a B-containing gas is introduced into the growth crucible 204 in addition to the SiC raw material gas and n-type dopant gas. For example, one of the Si raw materials, SiH4, H2SiCl2, or HSiCl3, and one of the C raw materials, C3H8 or C2H4, are introduced into the growth crucible 204 as SiC raw material gases. In addition, N2 or the like is introduced as an n-type dopant gas, and a B-containing gas such as BCl3 or B2H3 is also introduced. This makes it possible to produce SiC single crystal ingots with the above-mentioned B concentration. At this time, by also introducing an etching gas such as HCl and a carrier gas such as H2 into the growth crucible 204, it becomes possible to optimize the atmosphere inside the crucible and suppress polycrystalline formation, thereby enabling the production of SiC ingots 203 with better performance.

[0110] Furthermore, in the sublimation method, we also measured whether the purity of the growth crucible 204 affects the accuracy of the p-type impurity concentration. Specifically, by supplying Cl2 gas or the like to the growth crucible 204 before the growth of the SiC ingot 203 to perform a metal removal treatment, the constituent material of the growth crucible 204, such as graphite or graphite coated with a high-melting-point metal, can be purified. We measured the p-type impurity concentration in the SiC substrate 11 when a SiC semiconductor device was manufactured using a SiC wafer 102 cut from a SiC ingot 203, both with and without this purification process. Figure 19 shows the results, and it was confirmed that the difference in the p-type impurity concentration in the SiC substrate 11 was small whether or not purification was performed, and that the p-type impurity concentration could be controlled accurately in both cases. Therefore, it is possible to control the p-type impurity concentration regardless of whether or not purification is performed.

[0111] In this example, when manufacturing SiC ingot 203 by sublimation, a B raw material powder containing boron carbide or boron nitride was added to the raw material powder 201 to adjust the B concentration. Alternatively, to adjust the Al concentration, aluminum carbide powder can be added as the Al raw material; to adjust the Ti concentration, titanium carbide powder as the Ti raw material; and to adjust the Ta concentration, tantalum carbide powder as the Ta raw material can be added to the raw material powder 201. Of course, when adjusting the concentrations of multiple p-type impurity elements, these can be added to the raw material powder 201 in multiple combinations. Furthermore, a sintered body can be used instead of a powder containing p-type impurity elements.

[0112] Alternatively, the raw material powder 201 may consist solely of high-purity SiC, and a chloride gas, such as BCl3 for raw material B, or a hydride gas, such as B2H3 for raw material B, may be introduced into the growth crucible 204 as a p-type dopant gas.

[0113] Furthermore, in addition to the fine-grained SiC powder, there is a coarser-grained B concentration of 1.2 × 10 17 / cm 3 Alternatively, the above SiC powders can be prepared and stacked in two layers to be used as the raw material powder 201. Specifically, a fine-grained SiC powder can be placed on top of a coarse-grained SiC powder, so that p-type impurity elements are supplied to the growth surface of the SiC ingot 203 through the gaps in the fine-grained SiC powder.

[0114] (Other embodiments) This disclosure is written in accordance with the embodiments described above, but is not limited to those embodiments and includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure.

[0115] For example, in the third embodiment described above, a case was described in which p-type impurities other than B are introduced when manufacturing the SiC ingot 203. However, it is also possible to prevent the introduction of p-type impurities other than B into the SiC ingot 203. For example, before placing the seed crystal 202 used in the manufacture of the SiC ingot 203 into the growth crucible, a heat treatment is performed to remove p-type impurities other than B from the raw material powder 201. In this case, if the raw material powder 201 contains B raw material powder containing boron carbide or boron nitride, sufficient B will remain even after the heat treatment, so B will not be completely removed. Alternatively, the B raw material powder containing boron carbide or boron nitride may be added after performing the heat treatment to remove p-type impurities other than B from the raw material powder 201. Then, after removing p-type impurities other than B, the seed crystal 202 is placed in the growth crucible to produce the SiC ingot 203. This makes it possible to achieve the desired concentration of B in the SiC ingot 203 while keeping the concentration of p-type impurities other than B as low as possible.

[0116] Furthermore, although 6-inch and 8-inch wafers were given as examples of SiC wafer 102 in the above embodiments, this disclosure can also be applied to wafers of different dimensions. In that case as well, the B concentration that can suppress the expansion of BPD50 to SSF60 is 9.0 × 10⁻¹⁶ when the current stress is 600A or more. 16 / cm 3 In summary, if the electrical stress is 800A or higher, the B concentration should be 1.5 × 10 17 / cm 3 That should be sufficient.

[0117] (Perspective of this disclosure) The above disclosure can be understood from the following perspectives, for example.

[0118] [First point of view] A silicon carbide wafer comprising a silicon carbide substrate (11) composed of n-type silicon carbide doped with n-type impurities, The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0 × 10⁻⁶ 16 / cm 3 The silicon carbide wafer is described as such. [Second perspective] The boron concentration is 1.5 × 10 17 / cm 3 The silicon carbide wafer described in the first point of view, as stated above. [Third perspective] It consists of a 6-inch or 8-inch wafer with a thickness of 325-375 μm, and the boron concentration is 1.75 × 10⁻¹⁵ 17 / cm 3 A silicon carbide wafer as described in the first or second aspect, as follows: [Fourth perspective] It consists of an 8-inch wafer with a thickness of 475-525 μm, and the boron concentration is 7.2 × 10⁻¹⁵ 17 / cm 3 A silicon carbide wafer as described in the first or second aspect, as follows: [Fifth perspective] A silicon carbide substrate (11) composed of n-type silicon carbide doped with n-type impurities, A low-concentration n-type layer (13) is formed on the silicon carbide substrate, and has a lower n-type impurity concentration than the silicon carbide substrate. A p-type deep layer (15) is formed on the low-concentration layer and has multiple linear portions with one direction in the planar direction of the substrate as the longitudinal direction, An n-type JFET section (14) is disposed on the low-concentration layer and has a linear portion sandwiched between the deep layers, A p-type base region (17) is disposed on the JFET section and the deep layer, An n-type source region (18) formed on the surface of the base region, The trench gate structure includes a gate insulating film (22) formed on the wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film, A source electrode (25) electrically connected to the source region and the base region, The substrate is electrically connected to a drain electrode (26), The built-in diode (40) is composed of the deep layer, the JFET section, and the low-concentration layer, and the current density of the current that flows when the built-in diode performs freewheeling is 11.6 A / mm². 2 That is considered to be the case. The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0 × 10⁻⁶ 16 / cm 3 The silicon carbide semiconductor device is described as such. [Sixth perspective] The current density of the current flowing when the aforementioned internal diode performs freewheeling operation is 14.6 A / mm². 2 That is considered to be the case. The boron concentration is 1.5 × 10 17 / cm 3 The silicon carbide semiconductor device described in the fifth aspect, as stated above. [Seventh perspective] The silicon carbide substrate has a thickness of 325-375 μm, and the boron concentration is 1.75 × 10⁻¹⁵ 17 / cm 3 A silicon carbide semiconductor device as described in the fifth or sixth aspect, as follows: [Perspective 8] The silicon carbide substrate has a thickness of 475-525 μm, and the boron concentration is 7.2 × 10⁻¹⁵ 17 / cm 3 A silicon carbide semiconductor device as described in the fifth or sixth aspect, as follows: [Perspective 9] The silicon carbide semiconductor device according to any one of the fifth to eighth views, wherein the deep layer has a thickness of 1 μm or less. [Perspective 10] An n-type current dispersion layer (16) is formed on the JFET portion and the deep layer, and is in contact with the leading edge in the depth direction of the gate trench, It has a p-type connecting layer (20) that connects the base region and the deep layer, The base region is formed on the current distribution layer and the connecting layer, The silicon carbide semiconductor device according to any one of the fifth to eighth aspects, wherein the deep layer is composed of an ion implantation layer, and the depth from the surface of the source region to the bottom of the deep layer is 1 μm or more. [Perspective 11] The silicon carbide semiconductor device according to any one of the fifth to tenth aspects, wherein the low-concentration layer is composed of an epitaxial film formed on the silicon carbide substrate. [Perspective 12] A method for producing n-type silicon carbide single crystals, A seed crystal (202) for growing a silicon carbide single crystal is placed on one side of a base (205) located inside a growth crucible (204), The process includes supplying a thermally decomposed silicon carbide raw material, an n-type dopant, and boron to the surface of the seed crystal to produce a silicon carbide ingot (203) composed of an n-type silicon carbide single crystal on the surface of the seed crystal, By growing the silicon carbide ingot, the boron concentration within the silicon carbide ingot is increased to 9.0 × 10⁻⁶. 16 / cm 3 The above is a method for producing silicon carbide single crystals. [Perspective 13] A method for producing a silicon carbide single crystal according to the twelfth aspect, wherein in growing the silicon carbide ingot, a raw material powder (201) having a boron raw material powder containing boron carbide or boron nitride, which is a raw material for boron, in addition to the silicon carbide powder which is a raw material for silicon carbide, is placed below the base, an n-type dopant is supplied, the raw material powder is heated and decomposed and supplied to the seed crystal, thereby producing the silicon carbide ingot by sublimation. [Perspective 14] In growing the silicon carbide ingot, a silicon carbide raw material gas and an n-type dopant gas, in addition to a boron dopant gas, are supplied from below the base, and the silicon carbide raw material gas is heated and decomposed and supplied to the seed crystal, thereby producing the silicon carbide ingot by gas growth, according to the method for producing a silicon carbide single crystal according to the twelfth aspect. [Explanation of Symbols]

[0119] 11…SiC substrate, 12…Buffer layer, 13…Low-concentration layer, 14…JFET section, 15…Deep layer, 16…Current dispersion layer, 17…Base region, 18…Source region, 19…Contact region, 20…Connecting layer, 21…Gate trench, 22…Gate insulating film, 23…Gate electrode, 24…Interlayer insulating film, 25…Source electrode, 26…Drain electrode, 27…Field relaxation layer, 30…Vertical MOSFET, 31…Mask, 40…Built-in diode, 100…SiC ingot, 101…Growth surface, 102…SiC wafer, 110…Seed crystal, 200…SiC single crystal manufacturing equipment, 201…Raw material powder, 202…Seed crystal, 203…SiC ingot, 204…Growth crucible, 205…Base

Claims

1. A silicon carbide substrate (11) composed of n-type silicon carbide doped with n-type impurities, A low-concentration n-type layer (13) is formed on the silicon carbide substrate, and has a lower n-type impurity concentration than the silicon carbide substrate. A p-type deep layer (15) is formed on the low-concentration layer and has multiple linear portions with one direction in the planar direction of the silicon carbide substrate as the longitudinal direction, A p-type base region (17) is placed on the deep layer, An n-type source region (18) formed on the surface of the base region, A trench gate structure having a gate insulating film (22) formed on the wall surface of a gate trench (21) penetrating the source region and the base region, and a gate electrode (23) formed on the gate insulating film, A source electrode (25) electrically connected to the source region and the base region, The silicon carbide substrate is electrically connected to a drain electrode (26), The built-in diode (40) is formed by the deep layer and the low-concentration layer, The silicon carbide substrate contains boron, and the boron concentration in the silicon carbide substrate is 9.0 × 10⁻⁶. １６ / cm ３ The silicon carbide semiconductor device is described as such.

2. The current density of the current flowing when the aforementioned internal diode performs freewheeling operation is 14.6 A / mm². ２ That is considered to be the case. The boron concentration is 1.5 × 10 １７ / cm ３ The silicon carbide semiconductor device according to claim 1, as described above.

3. The silicon carbide substrate has a thickness of 325 to 375 μm, and the boron concentration is 1.75 × 10⁻¹⁶ １７ / cm ３ The silicon carbide semiconductor device according to claim 1 or 2, as follows:

4. The silicon carbide substrate has a thickness of 475 to 525 μm, and the boron concentration is 7.2×10 １７ / cm ３ The silicon carbide semiconductor device according to claim 1 or 2, wherein the boron concentration is equal to or lower than the above value.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein the deep layer has a thickness of 1 μm or less.

6. An n-type current dispersion layer (16) is formed on the deep layer and is in contact with the leading edge of the gate trench in the depth direction, It has a p-type connecting layer (20) that connects the base region and the deep layer, The base region is formed on the current distribution layer and the connecting layer, The silicon carbide semiconductor device according to claim 1 or 2, wherein the deep layer is composed of an ion implantation layer, and the depth from the surface of the source region to the bottom of the deep layer is 1 μm or more.

7. The silicon carbide semiconductor device according to claim 1 or 2, wherein the low-concentration layer is composed of an epitaxial film formed on the silicon carbide substrate.

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