Machine learning for synchronizing multiple FPGA ports in quantum systems

Abstract

This invention provides a method and system for synchronizing multiple FPGA ports in a quantum system. [Solution] In a quantum computer, quantum algorithms are implemented by qubits interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals transmitted via asynchronous ports to a DAC, which is digitally generated in the baseband and fed into an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multitap delay line. The setting of the multitap delay line is determined by a function of the port's setup and hold time. This function is trained via machine learning to be applicable across various ports.

Description

[[Background Art]]

[0001] [

[0001] ] By comparing several aspects of the present method and system set forth in the remainder of the present disclosure with conventional approaches with reference to the drawings, the limitations and disadvantages of conventional purposes of use of a plurality of FPGA ports will become apparent to those skilled in the art. [[Summary of Invention]] [[Means for Solving the Problems]]

[0002] [

[0002] ] As more fully set forth in the claims, a method and system for synchronizing a plurality of FPGA ports in a quantum system, substantially as illustrated by and / or described in connection with at least one of the figures, is provided. [[Brief Description of the Drawings]]

[0003] [Figure 1] FIG. 1 is a diagram illustrating an example quantum system comprising a plurality of synchronized FPGA ports, in accordance with various example implementations of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating an example system for training a quantum system to synchronize a plurality of FPGA ports, in accordance with various example implementations of the present disclosure. [Figure 3] FIG. 3 is a flowchart of an example method for synchronizing a plurality of FPGA ports, in accordance with various example implementations of the present disclosure. [Figure 4] FIG. 4 is a graph of example phase values measured over a range of delays, in accordance with various example implementations of the present disclosure. [Figure 5] FIG. 5 illustrates an example tap / delay estimation function as a linear fit to ideal phase values for different ports having different setup and hold times, in accordance with various example implementations of the present disclosure. [[Mode for Carrying Out the Invention]]

[0004]

[0008] Traditional computers operate by storing information in the form of binary digits ("bits") and processing these bits through binary logic gates. At any given time, each bit can take only one of two discrete values: 0 (i.e., "off") and 1 (i.e., "on"). The logical operations performed by binary logic gates are defined by Boolean algebra, and the circuit operation is governed by traditional physics. In modern traditional systems, the circuits for storing bits and performing logical operations are typically made from electrical wires capable of carrying two different voltages representing the 0s and 1s of the bits, and transistor-based logic gates that perform Boolean operations.

[0005]

[0009] Traditional computer logic operations are performed in a fixed state. For example, at time 0, a bit is in a first state; at time 1, a logic operation is applied to the bit; and at time 2, the bit is in a second state, such as the state at time 0 and the state determined by the logic operation. The state of a bit is typically represented by a voltage (e.g., 1V for "1"). dc , or 0V for "0" dc It is stored as ). A logical operation typically involves one or more transistors.

[0006]

[0010] Clearly, traditional computers using single bits and single logic gates have limited effectiveness, which is why modern traditional computers, which sometimes have relatively little computing power, house billions of bits and transistors. In other words, traditional computers capable of solving increasingly complex problems inevitably require more and more bits and transistors, as well as / or more and more time, to execute algorithms. Even so, to reach a solution, it becomes impractical to... There are several problems that require a large number of transistors and / or an impossibly large amount of time. Such problems are called intertractable.

[0007]

[0011] Quantum computers operate by storing information in the form of quantum bits ("qubits") and processing these qubits through quantum gates. Unlike bits, which can only be in one state at a time (0 or 1), qubits can be a superposition of two states simultaneously. More precisely, a quantum bit is a system in which states reside in a two-dimensional Hilbert space, and is therefore described as a linear combination α|0〉+β|1〉, where |0〉 and |1〉 are two fundamental states, and α and β are |α| 2 +|β| 2 It is a complex number that satisfies = 1, usually called the probability amplitude. Using this notation, when a qubit is measured, the qubit is given by probability |α| 2 The probability becomes 0, and |β| 2 This becomes 1. The base states |0〉 and |1〉 are 2-dimensional basis vectors.

number

number

number

[0008]

[0012] Unlike traditional bits, qubits cannot be stored as a single voltage value on a wire. Instead, qubits are physically realized using a two-level quantum mechanical system. For example, at time 0, a qubit is:

number

number

[0009]

[0013] Figure 1 shows an example quantum system with multiple synchronized FPGA ports in various implementations of the present disclosure. The quantum system comprises a quantum programming subsystem (QPS) 101, a quantum controller (QC) 103, and a quantum processor 107.

[0010]

[0014] The QPS101 has the ability to construct a QC103 and generate a quantum algorithm description containing instructions that the QC103 can execute to run a quantum algorithm (i.e., generate the necessary outbound quantum control pulses) with little to no human intervention during execution time. In an example implementation, the QPS101 is a personal computer with a processor, memory, and other associated circuitry (e.g., an x86 or x64 chipset). The QPS101 compiles the high-level quantum algorithm description into a machine language version of the quantum algorithm description (i.e., a set of binary vectors representing instructions that the QC103 can directly translate and execute).

[0011]

[0015] QPS 101 may be coupled to QC 103 via an interconnection that can use, for example, Universal Serial Bus (USB), Peripheral Component Interconnect (PCIe) bus, wired or wireless Ethernet, or any other suitable communication protocol.

[0012]

[0016] QC 103 comprises circuit equipment operable to load a machine language quantum algorithm description from QPS 101 via the interconnection. By executing the machine language by QC 103, QC 103 generates necessary outbound quantum control pulses corresponding to a desired operation to be implemented on a quantum processor 107 (e.g., transmitted to qubits to manipulate the states of the qubits, or transmitted to readout resonators to read the states of the qubits, etc.). The machine language further causes QC 103 to perform analysis of input signals. The analysis results may be used to determine the states of qubits or a quantum register (quantum measurement). Depending on the quantum algorithm to be implemented, outbound pulses for executing the algorithm may be predetermined at design time and / or may have to be determined during runtime. Determination of pulse runtime can include performing conventional computation and processing at QC 103 during runtime of the algorithm (e.g., runtime analysis of inbound pulses received from the quantum processor).

[0013]

[0017] QC 103 generates a precise sequence of external signals, typically pulses of electromagnetic waves and pulses of baseband voltage, to perform a desired logical operation (and thus to execute a desired quantum algorithm).

[0014]

[0018] During and / or upon completion of execution of a quantum algorithm implemented by QC 103, QC 103 can output data / results to QPS 101. In an example implementation, these results are used as a new quantu It may be used to generate a logic description and / or to update the quantum algorithm description during execution time. Furthermore, QC103 can output raw or processed inbound pulses received from quantum processor 107 representing qubit state estimation, or metadata representing quantum program control flow and branch information, as well as internal variable calculations during program execution.

[0015]

[0019] The QC103 comprises multiple pulse processors, which may be implemented as field-programmable gate arrays (FPGAs), application-specific integrated circuits, or similar. The pulse processors are operable to control analog outbound pulses that drive quantum elements (e.g., one or more qubits and / or resonators) or to enable interaction between quantum elements and digital outbound pulses, enabling control of auxiliary equipment necessary for programmed execution (e.g., gating of analog outbound pulses or control of external devices such as photon detectors).

[0016]

[0020] The quantum algorithm is implemented in the quantum processor 107 when one or more qubits interact with quantum control pulses. These quantum control pulses are electromagnetic RF signals or pulses that are digitally generated in baseband in QC103, converted to analog waveforms via multiple DACs 109-0, 109-1, 109-2, and 109-3, and upconverted by RF circuit 105. The desired signal may be generated according to a known set of instructions involving various operations such as arithmetic or logical calculations, communication with various components, and traditional control flow operations (jumps, branching, etc.). The application layer (APP) in QC103 controls the physical layer (PHY) to digitally generate (and further modify) samples of this analog waveform. The inbound pulses are further received by QC103 from the quantum processor 107 via RF circuit 105 and multiple ADCs 111-0 and 111-1.

[0017]

[0021] Qubits can have lifetimes ranging from hundreds of microseconds, resulting in extremely low program execution times. Furthermore, in a data center where a quantum computer is acting as a co-accelerator for a particular computation, there could be thousands of programs queuing to use a designated quantum processor 107.

[0018]

[0022] When the process, voltage, and temperature (PVT) change, periodic recalibration is required. Therefore, a fast, robust, and independent approach to recalibration can facilitate much better use of quantum computers while minimizing dead time between programs.

[0019]

[0023] Figure 2 shows an example system for training a quantum system to synchronize multiple FPGA ports, based on various implementations of the examples of this disclosure.

[0020]

[0024] The quantum controller 103 in Figure 1 may comprise PCB 201-0 and FPGA 203-0. FPGA 203-0 may have numerous ports 207-0 and 207-1 that need to be synchronized with each other. Furthermore, PCB 201-0 and FPGA 203-0 may have design differences 201-1 and 203-1, respectively, and therefore, transmissions via ports 207-0 and 207-1 of FPGA 203-0 do not need to be in line with transmissions via ports 207-0 and 207-1 of FPGA 203-1. Synchronization is required so that the outputs from FPGA 203-0 or 203-1 reach all DACs 109-0 and 109-1 simultaneously and independently without bias, regardless of design differences between similar system components. Any delay or shift in one of the signals output from FPGA 203-0 or 203-1 This could dramatically undermine the reliability of quantum computers.

[0021]

[0025] The hardware path from FPGA203-0 to ports 207-0 and 207-1 may vary depending on the variant of FPGA203-1 (e.g., a revised version of the same PCB201-0 but from a different batch of FPGA203-1). The varying characteristics of FPGA203-1 may affect the time it takes for signals to reach DAC109-0 and 109-1, potentially disrupting the calibrated synchronization for different PCBs. To train this machine learning model, several FPGA designs 203-0 and 203-1 with different layouts, as well as several quantum control units with different PCBs 201-0 and 201-1, are used for training.

[0022]

[0026] Synchronizing ports 207-0 and 207-1 of FPGA203-0 and / or 203-1 incorporates delay lines 113-0 and 113-1 for each port 207-0 and 207-1. This allows the signals exiting FPGA203-0 and / or 203-1 to be programmatically and digitally "shifted" in constant and individual steps so that all signals are aligned at their destinations, as required by quantum control applications.

[0023]

[0027] A machine learning approach is disclosed for synchronizing all quantum FPGA ports 207-0 and 207-1 without the need to save, load, and maintain previously acquired data for each quantum control unit (i.e., without using external storage). The machine learning approach further eliminates the need for calibration using external input / output devices and the need for lengthy and repeated calibrations of the quantum control platform.

[0024]

[0028] To train a machine learning model, information is collected for each port 207-0 and 207-1 from different PCBs 201-0 and / or 201-1, as well as from different FPGA logic designs 203-0 and / or 203-1. Training is required only once.

[0025]

[0029] Test signals may be generated by generators 205-0 and 205-1. The test signals may be sinusoidal signals or any other signal with deterministic phase. For each PCB 201-0 or 201-1, and for each FPGA design 203-0 or 203-1, the possible delay length (from 0 to N) is programmed into delay lines 113-0 and 113-1. The phase of the test signals is measured at DACs 109-0 and 109-1. This provides which tap / delay information is required for each port 207-0 and 207-1. The test signals are synchronized at DACs 109-0 and 109-1 when the test signals have the same phase. The formula for determining tap / delay may be derived from the measured phase values ​​using linear regression as a function of the port setup-and-hold time. Alternatively, a nonlinear equation for determining tap / delay may be derived to take into account nonlinear delay lines.

[0026]

[0030] Figure 3 shows flowcharts illustrating example methods for synchronizing multiple FPGA ports in various implementations of the present disclosure.

[0027]

[0031] Each FPGA logic design is characterized by a setup-and-hold (S / H) time, which also serves as part of the input to the training phase. In 301, the S / H time is determined for each port of the FPGA. The FPGA ports may be asynchronous.

[0028]

[0032] A test signal is generated. In 303, the test signal is sent to a destination via each of the FPGA ports. The destination may be a DAC. Each FPGA port is connected to a multitap delay line. Each of the multiple multitap delay lines is started by setting a tap (i.e., a selectable delay).

[0029]

[0033] In 305, the phase of the test signal is measured as if it were received at the destination from any port. For example, if each of the eight ports sends a sinusoidal test signal to each of the eight DACs, the test signals received by the DACs are processed to determine the phase value.

[0030]

[0034] In 307, it is determined whether all taps have been used. If more taps are available, in 309 the next tap is selected, in 303 the test signal is retransmitted, and in 305 the phase value of the test signal as if it had been received at the destination from any port is measured.

[0031]

[0035] Once each tap / delay is selected and the data acquisition phase is performed, the application can operate in 311 to select the ideal tap / delay from multiple phase values ​​for each of the multiple ports. The ideal tap / delay for all ports will correspond to the same phase.

[0032]

[0036] In step 313, it is determined whether more PCBs are available for training. If more PCBs are available, in step 315, the new PCBs are used, the taps / delays are reinitialized for each delay line, in step 303, the test signal is retransmitted, and in step 305, the phase value of the test signal is measured as if it were received at the destination from any port.

[0033]

[0037] In step 317, it is determined whether more FPGAs are available for training. If more FPGAs are available, in step 319, the new FPGAs are used, the taps / delays are reinitialized for each delay line, in step 303, the test signal is retransmitted, and in step 305, the phase value of the test signal is measured as if it were received at the destination from any port.

[0034]

[0038] Figure 4 shows graphs of examples of phase values ​​measured over a range of delays for various implementations of the present disclosure.

[0035]

[0039] The horizontal axis represents the delay value (i.e., the amount of time the test signal is delayed). The vertical axis represents the measured phase. Such graphs can be generated for each port.

[0036]

[0040] As shown in the diagram, the tap scales on each delay line may range from 0 to 63. This range is an example, as any range may be used. Ideally, each tap should correspond to an exact delay, for example, in the range of 0 to 4 nsec with a resolution of 62.5 psec. However, exact delays are not always possible, and a linear relationship between time and tap is not a requirement for this method.

[0037]

[0041] As shown in the figure, the test signal is a sine wave, but any test signal with deterministic phase may be used. The ideal tap / delay is selected as 18 because 18 corresponds to the center of the constant-phase period. Thus, the selected ideal tap may be determined according to the midpoint between two phase changes for a particular port of multiple asynchronous ports. In other embodiments, the test signal may include pulses. For a strike signal pulse, the selected ideal tap may be based on a phase transition (i.e., from on to off, or vice versa).

[0038]

[0042] Now, returning to Figure 3, in 321, a tap estimation function is generated for each of the multiple ports, depending on the selected / ideal tap and the setup and hold time.

[0039]

[0043] Figure 5 shows the example tap / delay estimation function as a linear fit to an ideal phase value (as discussed with respect to Figure 4) for different ports with different setup-and-hold times, in various implementations of the present disclosure.

[0040]

[0044] When using linear regression on the training data, the coefficients a and b may be determined by the following functions to fit the collected data: Delay = a(S / H) + b Here, S / H is the port's setup and hold time (which can be changed for each FPGA logic design), and delay is the delay required for a port so that all ports on a given PCB are synchronized.

[0041]

[0045] This machine learning approach can determine the optimal delay for different logic designs, different PVTs, and different batches of FPGA chips. This optimal delay may be achieved without repeated calibration using external wiring and persistent storage.

[0042]

[0046] The method and / or system may be implemented in hardware, software, or a combination of hardware and software. The method and / or system may be implemented in a concentrated manner on at least one computing system, or in a distributed manner with different elements spread across several interconnected computing systems. Any type of computing system or other device adapted to perform the method described herein is suitable. A typical implementation may comprise one or more application-specific integrated circuits (ASICs), one or more field-programmable gate arrays (FPGAs), and / or one or more processors (e.g., x86, x64, ARM, PIC, and / or any other suitable processor architecture) and associated support circuitry (e.g., storage, DRAM, flash, bus interface circuits, etc.). Each individual ASIC, FPGA, processor, or other circuit may be referred to as a “chip,” and multiple such circuits may be referred to as a “chipset.” Another implementation may include a non-temporary machine-readable (e.g., computer-readable) medium (e.g., flash drive, optical disc, magnetic storage disk, or similar) that stores one or more lines of code that, when executed by the machine, will cause the machine to perform the processing described herein. Another implementation may include a non-temporary machine-readable (e.g., computer-readable) medium (e.g., flash drive, optical disc, magnetic storage disk, or similar) that stores one or more lines of code that, when executed by the machine, will cause the machine to be configured to operate as the system described herein (e.g., by loading software and / or firmware into its circuitry).

[0043]

[0047] As used herein, the terms “circuit” and “circuit equipment” refer to physical electronic components (i.e., hardware), as well as any software and / or firmware ("code") that can constitute, run on, and / or otherwise associate with the hardware. As used herein, for example, a particular processor and memory may be one or more of the first of the code. A first “circuit” may be provided when executing a line of code, and a second “circuit” may be provided when executing a second one or more lines of code. As used herein, “and / or” means any one or more items in the list joined by “and / or”. For example, “x and / or y” means any element of the set of three elements {(x),(y),(x,y)}. For another example, “x, y, and / or z” means any element of the set of seven elements {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}. As used herein, the term “exemplary” means serving as an unrestricted example, case, or illustration. As used herein, the terms “e.g.” and “for example” emphasize a list of one or more unrestricted examples, cases, or illustrations. As used herein, a circuit device is “operable” to perform a function whenever the circuit device has the necessary hardware and code to perform the function, regardless of whether the performance of the function is disabled or enabled (for example, by user-configurable settings, factory maintenance, etc.). As used herein, the term “based on” means “at least partially based on.” For example, “x based on y” means that “x” is at least partially based on “y” (and may also be based on z, for example).

[0044]

[0048] While the Method and / or System has been described in relation to certain implementations, it will be understood by those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the Method and / or System. Furthermore, many modifications may be made to adapt the teachings of the Disclosure to specific circumstances or materials without departing from the scope of the Disclosure. Thus, it is intended that the Method and / or System is not limited to the specific implementations disclosed, and that the Method and / or System includes all implementations included in the appended claims.

Claims

1. For each of the multiple multi-tap delay lines, the step is to set one of the multiple taps, A step of sending a test signal to a destination via each of a plurality of asynchronous ports, wherein each of the plurality of asynchronous ports is operablely connected to one of the plurality of multitap delay lines, The steps include measuring the phase of the test signal at the destination corresponding to each of the plurality of asynchronous ports, After setting each of the multiple taps, the phase measurement is repeated. The steps include selecting one tap for each of the plurality of asynchronous ports according to the phase measurement value of each of the plurality of asynchronous ports, The steps include generating a tap estimation function according to the selected taps for the plurality of asynchronous ports, and Methods that include...

2. The method according to claim 1, wherein the tap estimation function is generated according to the setup and hold time for each of the plurality of asynchronous ports.

3. The method according to claim 1, wherein the field-programmable gate array (FPGA) comprises the plurality of asynchronous ports.

4. The method according to claim 3, wherein the FPGA comprises the plurality of multi-tap delay lines.

5. The method according to claim 3, wherein the tap estimation function is generated according to phase measurements from a plurality of FPGAs.

6. The method according to claim 1, wherein the destination comprises one or more digital-to-analog converters (DACs).

7. The method according to claim 1, wherein the test signal is a sine wave.

8. The method according to claim 1, wherein the test signal has pulses.

9. The method according to claim 1, wherein a selected tap for a specific port of the plurality of asynchronous ports corresponds to a constant phase period.

10. The method according to claim 1, wherein a selected tap for a specific port of the plurality of asynchronous ports is determined in accordance with one or more phase changes.

11. A signal generator capable of generating test signals, A plurality of multitap delay lines operable to receive the test signal, wherein each multitap delay line is operable to output a delayed test signal corresponding to one of the taps, Multiple asynchronous ports, each of which is capable of operating to send the delayed test signal to a destination, An application for generating a tap estimation function, For each of the plurality of asynchronous ports, the application is capable of measuring a plurality of phase values, the plurality of phase values ​​corresponding to the plurality of taps, For each of the plurality of asynchronous ports, the application is capable of operating to select a tap from the plurality of phase values. The tap estimation function is generated according to the selected tap for each of the plurality of asynchronous ports. Applications and A system equipped with these features.

12. The system according to claim 11, wherein the tap estimation function is generated according to the setup and hold time for each of the plurality of asynchronous ports.

13. The system according to claim 11, wherein the field-programmable gate array (FPGA) comprises the plurality of asynchronous ports.

14. The system according to claim 13, wherein the FPGA comprises the plurality of multi-tap delay lines.

15. The system according to claim 13, wherein the tap estimation function is generated according to phase measurements from a plurality of FPGAs.

16. The system according to claim 11, wherein the destination includes one or more digital-to-analog converters (DACs).

17. The system according to claim 11, wherein the test signal is a sine wave.

18. The system according to claim 11, wherein the test signal has pulses.

19. The system according to claim 11, wherein a selected tap for a specific port of the plurality of asynchronous ports corresponds to a constant phase period.

20. The system according to claim 11, wherein a selected tap for a specific port of the plurality of asynchronous ports is determined in accordance with one or more phase changes.

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