Liquid crystal device, wavelength selective switch device, and method for controlling a liquid crystal device

Abstract

To provide a liquid crystal device capable of improving quality, a wavelength selective switch device, and a control method for a liquid crystal device. [Solution] The liquid crystal device according to this disclosure comprises: a plurality of comparators that compare each of a plurality of video signals with a gradation signal indicating a monotonically transitioning count value and activate each matching signal when they match; a plurality of first switch elements provided between a common wiring through which a ramp signal propagates and a plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when each of the matching signals of the plurality of comparators becomes active; a plurality of second switch elements provided between an initialization wiring on a separate path from the common wiring and a plurality of data lines, which initialize the potential of the plurality of data lines; and a plurality of low-pass filters provided between the common wiring and each of the plurality of first switch elements.

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal device, a wavelength selective switch device, and a method for controlling a liquid crystal device, and more particularly, to a liquid crystal device, a wavelength selective switch device, and a method for controlling a liquid crystal device that are suitable for improving quality. [Background Art]

[0002] The liquid crystal display device disclosed in Patent Document 1 includes: a plurality of pixels arranged in a matrix; a plurality of sets of data lines provided corresponding to respective columns of the plurality of pixels; a plurality of gate lines provided corresponding to respective rows of the plurality of pixels; a plurality of switches for sequentially supplying positive-polarity and negative-polarity video signals in set units to the plurality of sets of data lines; and a driving means for driving the plurality of switches and the plurality of gate lines. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Laid-Open No. 2009-223289 [Summary of the Invention] [Problems to be Solved by the Invention]

[0004] Incidentally, liquid crystal display devices are required to display high-quality images. However, in the liquid crystal display device disclosed in Patent Document 1, noise generated when the plurality of switches for supplying video signals to the data lines switches from on to off propagates through the parasitic capacitance formed in each of the plurality of switches to the ramp signal used for generating the video signal, causing fluctuations in the video signal, which results in a problem that high-quality images cannot be displayed.

[0005] The present disclosure has been made in view of the above points, and an object thereof is to provide a liquid crystal device, a wavelength selective switch device, and a method for controlling a liquid crystal device that can improve quality. [Means for solving the problem]

[0006] The liquid crystal device according to this disclosure comprises: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate the respective matching signal when they match; a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates; a plurality of first switch elements provided between the plurality of data lines and the common wiring, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when the matching signal of each of the plurality of comparators becomes active; a plurality of second switch elements provided between an initialization wiring on a separate path from the common wiring and the plurality of data lines, which initialize the potential of the plurality of data lines; and a plurality of low-pass filters provided between the common wiring and each of the plurality of first switch elements.

[0007] A control method for a liquid crystal device according to this disclosure includes: a plurality of pixels; a plurality of data lines provided corresponding to each row of the plurality of pixels; a shift register unit that sequentially captures video signals for the number of rows of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value and activate the respective matching signal when they match; a common wiring through which a ramp signal whose potential changes linearly with each horizontal ramp period propagates; a plurality of first switch elements provided between the plurality of data lines, which turn on when the potential of the ramp signal begins to change linearly and turn off individually when the matching signal of each of the plurality of comparators becomes active; and an initialization wiring on a separate path from the common wiring, provided between the plurality of data lines. A control method for a liquid crystal device comprising: a plurality of second switch elements for initializing the potentials of the plurality of data lines; a common wiring; and a plurality of low-pass filters provided between each of the plurality of first switch elements, wherein during a certain horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly; during a certain horizontal ramp period, the plurality of first switch elements are individually turned off at the timing when the matching signal of each of the plurality of comparators becomes active; after the current horizontal ramp period has elapsed and before the start of the next horizontal ramp period, the plurality of second switch elements are temporarily turned on; during the next horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly; and during the next horizontal ramp period, the plurality of first switch elements are individually turned off at the timing when the matching signal of each of the plurality of comparators becomes active. [Effects of the Invention]

[0008] This disclosure provides a liquid crystal device capable of improving quality, a wavelength selective switch device, and a method for controlling a liquid crystal device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a view of the wavelength selective switch related to this disclosure, as seen from the x-axis direction. [Figure 2] This is a view of the wavelength selective switch related to this disclosure, as seen from the y-axis direction. [Figure 3] This figure shows an example of a wavelength channel focused on a reflective liquid crystal element applied to the wavelength selective switch according to this disclosure. [Figure 4] This figure shows an example configuration of a liquid crystal device in the conceptual stage. [Figure 5] This is an enlarged view of the horizontal driver and analog switch section provided in the liquid crystal device shown in Figure 4. [Figure 6] This figure shows a specific example of the pixel configuration provided in the liquid crystal device shown in Figure 4. [Figure 7] Figure 4 is a timing chart illustrating the pixel driving method using the liquid crystal device shown. [Figure 8] This diagram illustrates the voltage levels from black to white for both positive and negative polarity video signals written to pixels. [Figure 9] Figure 4 is a timing chart showing the operation of the liquid crystal device in image display mode. [Figure 10] This diagram illustrates the effect of lamp signal ringing on the image. [Figure 11] This is a waveform diagram of the reference lamp voltage Ref_R+ used to write the image to the pixel in column m of row La of a liquid crystal device in the conceptual stage. [Figure 12] This is a waveform diagram of the reference lamp voltage Ref_R+ used to write the image to the pixel in column m of row B of a liquid crystal device in the conceptual stage. [Figure 13] This figure shows an example configuration of a liquid crystal device according to Embodiment 1. [Figure 14] Figure 13 is an enlarged view of the horizontal driver, analog switch section, and filter section provided in the liquid crystal device shown. [Figure 15] It is a diagram showing a specific example of a low-pass filter. [Figure 16] It is a waveform diagram of reference ramp voltage Ref_R+ used for writing an image to a pixel in the m-th column of the La-th row of the liquid crystal device according to the first embodiment. [Figure 17] It is a waveform diagram of reference ramp voltage Ref_R+ corresponding to the resistance value of each low-pass filter in the liquid crystal device according to the first embodiment. [Figure 18] It is a waveform diagram of reference ramp voltage Ref_R+ corresponding to the capacitance value of each low-pass filter in the liquid crystal device according to the first embodiment. [Figure 19] It is a diagram showing the cross-sectional structure of a low-pass filter provided in the liquid crystal device according to the first embodiment. [Figure 20] It is a diagram for explaining problems occurring in a liquid crystal device at the conceptual stage. [Figure 21] It is a diagram for explaining problems occurring in the liquid crystal device according to the first embodiment. [Figure 22] It is a diagram showing a configuration example of the liquid crystal device according to the second embodiment. [Figure 23] It is a diagram showing in further detail the horizontal driver, analog switch section, filter section, and initialization switch section 19 provided in the liquid crystal device shown in FIG. 22. [Figure 24] It is a diagram showing a configuration example of a switch element provided in the initialization switch section of the liquid crystal device according to the second embodiment. [Figure 25] It is a timing chart for explaining a pixel driving method by the liquid crystal device according to the second embodiment. [Figure 26] It is a diagram for explaining effects obtained in the liquid crystal device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Description of wavelength selective switch to which the liquid crystal device according to the present disclosure is applied> Figure 1 shows an example configuration of a Wavelength Selective Switch (WSS) array 100 according to this disclosure. Figure 1 is a view of the WSS array 100 from the x-axis direction.

[0011] In recent years, optical communication networks have been developed to meet the demands for higher speeds and larger capacities in telecommunications and data networks. Generally, optical communication networks employ Wavelength Division Multiplexing (WDM) technology, which utilizes as much of the optical spectrum as possible. In optical WDM, as in wireless WDM, data is modulated on multiple carrier waves of different wavelengths. These multiple carrier waves are called channels (wavelength channels). In optical WDM, optical waves are used instead of radio waves compared to wireless WDM, and different wavelength channels correspond to different frequencies (wavelengths) of light. Generally, in optical communication, channels within or near the wavelength range of 1 to 2 μm are used.

[0012] In many optical communication networks, optical nodes are used that correspond to branching points in the network. Each optical node uses, for example, a reconfigurable optical add-drop multiplexer (ROADM) device with reconfigurable add-drop functionality. Generally speaking, the ROADM functionality allows for the removal or addition of one or more wavelength channels at each optical node.

[0013] The WSS array 100 may be used in a ROADM system for routing arbitrary wavelength channels. In this case, the WSS array 100 may use an optical beam deflection device such as a spatial light modulator, and the optical beam deflection device may select a wavelength for deflection to a desired output port. For example, deflection of a wavelength channel to a drop port results in that channel being removed from the WDM signal. Furthermore, the WSS array 100 may use a spatial light modulator using a reflective liquid crystal element.

[0014] Here, the ROADM function uses a broadcast-and-select (BS) scheme that requires a WSS and an optical splitter at each node. However, future devices may use a route-and-select (RS) scheme with multiple WSS devices instead of an optical splitter.

[0015] The WSS array 100 according to this disclosure comprises at least two WSS devices within a single package. In the WSS array 100, at least two WSS devices share most of the optical components, while at least two WSS devices are configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also have independent processing capabilities comparable to larger, more expensive devices. Such a WSS array 100 is suitable for use in optical communication networks, for example, as a reconfigurable optical ROADM, and is also suitable for use as a component in branch nodes using a route-and-select (RS) architecture. Furthermore, the liquid crystal device according to this disclosure is applied as a reflective liquid crystal element in the WSS array 100.

[0016] As shown in Figure 1, the WSS array 100 comprises two independent WSS devices 100a and 100b, each capable of operating as an independent WSS device. In this specification, the term “independent” refers to the function of the other WSS device 100a or 100b to process one or more WDM signals independently of the other WSS device 100a or 100b. In this specification, the term “processing” is used broadly and includes, for example, modulating, attenuating, blocking, redirecting, and switching the individual wavelength channels that constitute each WDM signal.

[0017] The WSS array 100 comprises an input unit 110, an optical system 120, and a reflective liquid crystal element 130.

[0018] The optical system 120 is configured to beam-shape each WDM signal beam. The optical system 120 is also configured to spectrally disperse (multiplex decouple) each WDM signal into the wavelength channels or groups thereof that constitute them, and spectrally couple (multiplex) the dispersed wavelength channels or groups thereof into one or more WDM signals. The reflective liquid crystal element 130 optically processes the dispersed wavelength channels or groups thereof, for example, to redirect the individual wavelength channels along a predetermined path in the WSS array 100.

[0019] The WSS array 100 is configured to be line-symmetric with respect to the symmetry axis Z1 extending in the z-axis direction. This allows the WSS array 100 to enable a single optical system 120 and a single reflective liquid crystal element 130 to be shared by multiple WSS devices (WSS devices 100a and 100b in this example). In the WSS array 100, WSS devices 100a and 100b can share most of the optical components, while each WSS device is configured to operate independently. Therefore, the WSS array 100 not only achieves miniaturization and reduces optical complexity, but can also possess independent processing capabilities comparable to larger and more expensive devices.

[0020] The input unit 110 has input ports and output ports for transmitting one or more WDM signals to each WSS device 100a, 100b. Each input port and each output port can be, for example, an optical fiber or a planar waveguide, but in this embodiment, the case of an optical fiber will be described as an example. Therefore, below, each input port will also be referred to as an input fiber, and each output port will also be referred to as an output fiber.

[0021] Specifically, the input unit 110 includes an input fiber FI1 and n (where n is an integer greater than or equal to 1) output fibers FO1_1 to FO1_n for the WSS device 100a, and an input fiber FI2 and n output fibers FO2_1 to FO2_n for the WSS device 100b. Here, in the input unit 110, the optical fibers FI1, FO1_1 to FO1_n that constitute the fiber stack for the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n that constitute the fiber stack for the WSS device 100b are arranged along the y-axis.

[0022] The input unit 110 further includes collimating lenses LI1, LO1_1 to LO1_n corresponding to optical fibers FI1, FO1_1 to FO1_n for WSS device 100a, and collimating lenses LI2, LO2_1 to LO2_n corresponding to optical fibers FI2, FO2_1 to FO2_n for WSS device 100b. The collimating lenses LI1, LO1_1 to LO1_n and collimating lenses LI2, LO2_1 to LO2_n constitute a microlens array. In the input unit 110, each collimating lens is positioned on the optical system 120 side of each optical fiber. Each collimating lens is an arbitrary optical element that has the ability to guide or change the direction of light rays and to focus a set of light rays.

[0023] In the input section 110, the optical fibers FI1, FO1_1 to FO1_n and the collimating lenses LI1, LO1_1 to LO1_n constitute the input section of the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n and the collimating lenses LI2, LO2_1 to LO2_n constitute the input section of the WSS device 100b.

[0024] In the example shown in Figure 1, the WSS array 100 employs a microlens array, but other types of arrays may be used as long as they do not deviate from the intended purpose.

[0025] As shown in Figure 1, the optical axes of the collimating lenses LI1,LO1_1~LO1_n are displaced relative to the optical axes of the optical fibers FI1,FO1_1~FO1_n, respectively. Due to this relative positional shift between the collimating lenses LI1,LO1_1~LO1_n and the optical fibers FI1,FO1_1~FO1_n, the input beam for the WSS device 100a is input to the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100a is output from the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100a are tilted in the negative y-axis direction by an angle θ1 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0026] Similarly, the optical axes of the collimating lenses LI2,LO2_1~LO2_n are displaced with respect to the optical axes of the optical fibers FI2,FO2_1~FO2_n, respectively. Due to this relative positional shift between the collimating lenses LI2,LO2_1~LO2_n and the optical fibers FI2,FO2_1~FO2_n, the input beam for the WSS device 100b is input to the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100b is output from the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100b are tilted in the positive y-axis direction by an angle θ2 with respect to the axis of symmetry Z1 from the input section 110 to the optical system 120.

[0027] In the WSS array 100, the first WDM signal incident from the outside is supplied to the input fiber FI1. The input fiber FI1 transmits the first WDM signal parallel to the axis of symmetry Z1. The first WDM signal transmitted from the input fiber FI1 passes through the collimating lens LI1, tilting by an angle θ1 in the negative direction of the y-axis, and is supplied to the optical system 120. The first WDM signal supplied to the optical system 120 forms a WDM signal beam BI1 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI1.

[0028] The WDM signal beam BI1 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0029] In the WSS array 100, the second WDM signal incident from the outside is supplied to the input fiber FI2. The input fiber FI2 transmits the second WDM signal parallel to the axis of symmetry Z1. The second WDM signal transmitted from the input fiber FI2 passes through the collimating lens LI2, tilting by an angle θ2 in the positive direction of the y-axis, and is supplied to the optical system 120. The second WDM signal supplied to the optical system 120 forms a WDM signal beam BI2 that travels along the yz plane in the optical system 120. In the optical system 120, the WDM signal beam BI2 is incident on a lens 121 that shapes the WDM signal beam BI2 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, when viewed from the x-axis direction (in other words, when viewed from the yz plane), the lens 121 does not affect the shaping of the WDM signal beam BI2.

[0030] The WDM signal beam BI2 that has passed through lens 121 is incident on lens 122. Lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The action of lens 122 depends on a reflective liquid crystal element 130 positioned at the focal plane of lens 122. Furthermore, the center of lens 122 is located on the axis of symmetry Z1.

[0031] Here, since the reflective liquid crystal element 130 is positioned at the focal plane of the lens 122, any pair of light rays reflected by the reflective liquid crystal element 130 that are reflected from positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1 will be emitted from the lens 122 as a pair of parallel rays. Conversely, any pair of parallel rays incident on the lens 122 from the input section 110 will be focused in the reflective liquid crystal element 130 at positions at the same distance in the y-axis direction with respect to the axis of symmetry Z1.

[0032] In the example shown in Figure 1, an arbitrary incident beam (in this example, the WDM signal beam BI1) traveling at an angle θ1 with respect to the axis of symmetry Z1 is directed by the lens 122 toward position LC1 on the reflective liquid crystal element 130. Conversely, rays starting from position LC1 on the reflective liquid crystal element 130 (in this example, the output beams BO1_1 to BO1_n) are directed by the lens 122 as parallel rays traveling at an angle θ1 with respect to the axis of symmetry Z1.

[0033] Similarly, any incident beam traveling at an angle θ2 with respect to the axis of symmetry Z1 (in this example, the WDM signal beam BI2) is directed by the lens 122 toward position LC2 on the reflective liquid crystal element 130. Conversely, rays starting from position LC2 on the reflective liquid crystal element 130 (in this example, the output beams BO2_1 to BO2_n) are directed by the lens 122 as parallel rays traveling at an angle θ2 with respect to the axis of symmetry Z1.

[0034] Figure 2 shows the WSS array 100 as viewed from the y-axis direction. Figure 3 shows an example of a wavelength channel focused by a reflective liquid crystal element 130.

[0035] Referring to Figures 2 and 3, the WDM signal beam BI1 passes through lens 122 and then through a dispersion element 124 located between lenses 122 and 123. The dispersion element 124 is a transmissive optical component, such as a diffraction grating or prism, which angularly disperses the wavelength channel of the WDM signal beam BI1. The wavelength channel dispersed by the dispersion element 124 passes through lens 123. Lens 123 is, for example, a cylindrical lens, which focuses the wavelength channel dispersed by the dispersion element 124 onto position LC1 on the reflective liquid crystal element 130.

[0036] Similarly, the WDM signal beam BI2 passes through lens 122 and then through the dispersion element 124 located between lenses 122 and 123. The dispersion element 124 angularly disperses the wavelength channel of the WDM signal beam BI2. The wavelength channel dispersed by the dispersion element 124 passes through lens 123. Lens 123 focuses the wavelength channel dispersed by the dispersion element 124 onto position LC2 on the reflective liquid crystal element 130.

[0037] The reflective liquid crystal element 130 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator, which can reflect or redirect one or more of the dispersed wavelength channels so that one or more of the dispersed wavelength channels are routed to any one of the output fibers, as will be described in more detail below.

[0038] In the WSS device 100a, all light rays starting from position LC1 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel light rays traveling at an angle θ1. Therefore, when the deflection angle is set appropriately, the output light rays reflected by the reflective liquid crystal element 130 (for example, reflected output light rays corresponding to a group of light rays, each of which may contain one or more wavelength channels of the WDM signal beam BI1) can be routed to the output fibers FO1_1 to FO1_n, respectively. Here, since the output light rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO1_1 to LO1_n, they can be recombined to the output fibers FO1_1 to FO1_n with improved efficiency.

[0039] Similarly, in the WSS device 100b, all rays originating from position LC2 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and directed as parallel rays traveling at an angle θ2. Therefore, if the deflection angle is set appropriately, the output rays reflected by the reflective liquid crystal element 130 (for example, reflected output rays corresponding to a group of rays, each potentially containing one or more wavelength channels of the WDM signal beam BI2) can be routed to the output fibers FO2_1 to FO2_n, respectively. Here, since the output rays reflected by the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO2_1 to LO2_n, they can be recombined to the output fibers FO2_1 to FO2_n with improved efficiency.

[0040] Therefore, the combination of the input unit 110 and the lens 122 results in a WSS array 100 device that, after sending out a predetermined set of beams along a predetermined angle (for example, angle θ1 in the case of WSS device 100a, and angle θ2 in the case of WSS device 100b), directs these beams toward a position on the reflective liquid crystal element 130 that depends only on the input angle (for example, position LC1 in the case of WSS device 100a, and position LC2 in the case of WSS device 100b). Thus, in the WSS array 100, as will be described in more detail below with reference to Figures 2 and 3, the rays from WSS device 100a and the rays from WSS device 100b are each processed by a common optical system 120 and reflective liquid crystal element 130, while each wavelength channel is processed separately by the processing capabilities of the WSS array 100.

[0041] Next, the WSS array 100 will be described using Figures 2 and 3. As already explained, Figure 2 is a view of the WSS array 100 from the y-axis direction. As already explained, Figure 3 is a diagram showing an example of a wavelength channel focused on the reflective liquid crystal element 130. In the following, we will mainly describe the WSS device 100a of the WSS devices 100a and 100b, but the same can be said for the WSS device 100b.

[0042] As shown in Figure 2, in the WSS device 100a, the WDM signal beam BI1 that has passed through the input fiber FI1 is incident on the optical system 120. In the example in Figure 2, the WDM signal beam BI1 travels along a plane perpendicular to the plane of paper (yz plane) at an angle θ1. The WDM signal beam BI1 also contains multiple wavelength channels. These multiple wavelength channels have a wavelength range from the longest wavelength λ1 to the shortest wavelength λn. The WDM signal beam BI1 may contain a large number of wavelength channels, in which case the large number of wavelength channels may be, for example, 96 wavelength channels spaced at 50 or 100 GHz on a fixed grating. In other examples, the WSS device 100a can use a frequency spacing of 12.5 GHz and can be used in an adaptive grating system having, for example, 130 or more wavelength channels (i.e., 97 or more wavelength channels).

[0043] In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 expands the WDM signal beam BI1, for example, so that the diameter of the WDM signal beam BI1 is suitable for achieving a desired beam size in the dispersive element 124. The collimating lens provided in the input section 110 and the lens 121 provided in the optical system 120 may also function as a beam-expanding telescope.

[0044] In the optical system 120, the dispersion element 124 angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels λ1 to λn dispersed by the dispersion element 124 are then focused onto the reflective liquid crystal element 130 by the lens 123. As a result, the wavelength channels λ1 to λn are spatially dispersed on the reflective liquid crystal element 130 in the wavelength dispersion direction (x-axis direction).

[0045] Figure 3 shows an example of the distribution of wavelength channels in the pixel area of ​​a reflective liquid crystal element 130. Note that in Figure 3, only wavelength channels λ1 to λ3 are shown among the wavelength channels λ1 to λn. More generally, each wavelength channel can be arranged on the two-dimensional surface of the reflective liquid crystal element 130 as a long strip or elliptical spot. In short, each wavelength channel is processed as a discrete wavelength signal that can be independently acted upon by the reflective liquid crystal element 130. However, the reflective liquid crystal element 130 is not limited to acting on individual wavelength channels, but may also act on groups of wavelength channels. Furthermore, as shown in Figure 3, the wavelength channels themselves or groups of wavelength channels themselves do not need to have a fixed bandwidth. This is because the reflective liquid crystal element 130 can be implemented in the WSS array 100 as a dynamically and completely reconfigurable spatial light modulator. Therefore, the WSS array 100 can be used in general fixed-grid architectures and in systems of general or future-developed highly adaptable grid architectures.

[0046] As shown in Figure 2, the reflective liquid crystal element 130 can then redirect selected wavelength channels λ1 to λn toward the output fibers FO1_1 to FO1_n. In the example in Figure 2, the redirection by the reflective liquid crystal element 130 is performed along a plane perpendicular to the plane of the paper (yz plane). The wavelength channels redirected by reflection in the reflective liquid crystal element 130 are incident on the lens 123. The lens 123 redirects the incident wavelength channels so that they are recombined in the dispersive element 124. For example, in the dispersive element 124, multiple wavelength channels are recombined to form a single beam (output beam). The output beams BO1 to BOn formed in the dispersive element 124 are redirected by the lens 122 and the collimating lens of the input unit 110 so that they become parallel rays, and then output to the outside as processed signals via the output fibers FO1_1 to FO1_n.

[0047] For example, consider the case where the WDM signal beam BI1 includes three wavelength channels (hereinafter referred to as wavelength channels λ1 to λ3) having wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3, respectively. In this case, as shown in the example in Figure 1, the WDM signal beam BI1 is incident on the optical system 120 at an angle θ1. The light rays of the WDM signal beam BI1 traveling at an angle θ1 pass through the center of the lens 122, thus maintaining the angle θ1. The WDM signal beam BI1 that has passed through the lens 122 is dispersed in the dispersing element 124 into multiple wavelength channels, including the three wavelength channels mentioned above, along a plane (zx plane) perpendicular to the plane of Figure 1. However, all of the multiple wavelength channels that have passed through the dispersing element 124 maintain an angle θ1 in a plane (yz plane) parallel to the plane of Figure 1. The three dispersed wavelength channels described above are then focused by the lens 123 at different positions on the pixel area of ​​the reflective liquid crystal element 130, as shown in Figure 3.

[0048] Furthermore, several different routing functions may be combined in relation to the device's routing capabilities. For example, consider the case where all three wavelength channels λ1 to λ3 are routed to a common output fiber FO_n. The wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and focused before reaching the dispersive element 124. Subsequently, they are recombined (multiplexed) by the dispersive element 124 to form a single output beam BO1_n. The output beam BO1_n that has passed through the dispersive element 124 is redirected by the lens 122 to tilt at an angle θ1.

[0049] The output beam BO1_n, having passed through lens 122, travels along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, passes through lens 121, and then enters the collimating lens LO1_n. The collimating lens LO1_n redirects the output beam BO1_n so that it is parallel to the axis of symmetry Z1. The output beam BO1_n, having passed through the collimating lens LO1_n, is emitted outside the WSS array 100 via the output fiber FO1_n.

[0050] Furthermore, the case is not limited to the routing of multiple wavelength channels to a common output fiber; multiple wavelength channels may be routed to multiple different output fibers. For example, considering the case where the three wavelength channels λ1 to λ3 described above are routed to different output fibers FO1_1 to FO1_3, the wavelength channels λ1 to λ3 reflected by the reflective liquid crystal element 130 are deflected by the lens 123 and then redirected by the dispersing element 124, forming output beams BO1_1 to BO1_3 that spread out in a fan shape. The output beams BO1_1 to BO1_3 that have passed through the dispersing element 124 are then redirected by the lens 122 so that they are tilted at an angle θ.

[0051] The output beams BO1_1 to BO1_3 of the parallel light rays that have passed through lens 122 travel along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, and after passing through lens 121, they are incident on collimating lenses LO1_1 to LO1_3, respectively. The collimating lenses LO1_1 to LO1_3 redirect the output beams BO1_1 to BO1_3 so that they are parallel to the axis of symmetry Z1, respectively. The output beams BO1_1 to BO1_3 that have passed through collimating lenses LO1_1 to LO1_3 are then emitted outside the WSS array 100 via output fibers FO1_1 to FO1_3, respectively. In other words, in the WSS device 100a, wavelength channels λ1 to λ3 are routed from the input fiber FI1 through the reflective liquid crystal element 130 to the respective output fibers FO1_1 to FO1_3.

[0052] As described above, the wavelength channels of any WDM signal in WSS device 100a can be routed to one or more output fibers among multiple output fibers as needed. The same applies to the wavelength channels of any WDM signal in WSS device 100b as to WSS device 100a. That is, the wavelength channels of any WDM signal in WSS device 100b can be routed to one or more output fibers among multiple output fibers as needed. This is because, in the WSS array 100, the optical system 120 and the reflective liquid crystal element 130 are configured to be line-symmetric with respect to the symmetry axis Z1, and the wavelength channels dispersed in WSS device 100a and the wavelength channels dispersed in WSS device 100b are focused at different positions on the reflective liquid crystal element 130.

[0053] Furthermore, while the examples in Figures 1 to 3 describe a case where each WSS device is provided with one input port (input fiber) and n output ports (output fibers), the invention is not limited to this, and each WSS device may be provided with any number of input ports and any number of output ports. In addition, some or all of the n output ports may be reconfigured as input ports, and one input port may be reconfigured as an output port. Moreover, while the examples in Figures 1 to 3 describe a case where the WSS array 100 is composed of two WSS devices 100a and 100b, the invention is not limited to this, and may be composed of three or more WSS devices.

[0054] Next, we will describe the details of the reflective liquid crystal element 130 applied to the WSS array 100.

[0055] <Preliminary considerations regarding liquid crystal devices> First, the liquid crystal device 50, which the inventors have previously studied, will be described. The liquid crystal device 50 can also be used as a reflective liquid crystal element 130 of the WSS array 100.

[0056] (Conceptual configuration of liquid crystal device 50) Figure 4 shows an example configuration of an active-matrix liquid crystal device 50 in the conceptual stage.

[0057] As shown in Figure 4, the liquid crystal device 50 comprises an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 16, an analog switch unit 17, and AND circuits ADA1 to ADan and ADB1 to ADBn. The horizontal driver 16, together with the analog switch unit 17, constitutes a data line driving circuit and includes a shift register circuit 161, a 1-line latch circuit 162, a comparator unit 163, and a grayscale counter 164. Figure 4 also shows a ramp signal generator 40 that is connected to the liquid crystal device 50 during normal operation.

[0058] Figure 5 is an enlarged view of the horizontal driver 16 and analog switch section 17 provided on the liquid crystal device 50. The comparator section 163 comprises m comparators 163_1 to 163_m corresponding to m rows of pixels 12 (where m is an integer of 2 or more). The analog switch section 17 comprises m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- corresponding to m rows of pixels 12.

[0059] The pixel arrangement area of ​​the image display unit 11 is wired with row scan lines G1 to Gn, read switch selection lines TG1 to TGn, data lines D1+, D1- to Dm+, Dm-, gate control signal lines S+, S-, and gate control signal line B.

[0060] Row scan lines G1 to Gn are wired in n rows in the vertical direction (J-axis direction) and each extends horizontally. Read switch selection lines TG1 to TGn are wired in n rows in the vertical direction and each extends horizontally. Data lines D1+, D1- to Dm+, Dm- are wired in m columns in the horizontal direction and each extends vertically. Hereinafter, any of the row scan lines G1 to Gn will also be referred to as row scan line Gj. Any of the read switch selection lines TG1 to TGn will also be referred to as read switch selection line TGj. Any of the data lines D1+ to Dm+ will also be referred to as data line Di+. Any of the data lines D1- to Dm- will also be referred to as data line Di-.

[0061] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at a total of n × m intersections where n rows of row scan lines G1 to Gn intersect with m sets of data lines D1+, D1- to Dm+, Dm-.

[0062] The row scan line Gj and the read switch selection line TGj are commonly connected to each of the m pixels 12 located in the jth row. The data lines Di+ and Di- are commonly connected to each of the n pixels 12 located in the i-th column. Furthermore, the gate control signal lines S+, S-, and gate control signal line B are all commonly connected to all pixels 12. However, the gate control signal lines S+, S-, and gate control signal line B may each be provided individually for each row.

[0063] The polarity switching control circuit 14 outputs a positive polarity gate control signal (hereinafter referred to as gate control signal S+) to the gate control signal line S+, a negative polarity gate control signal (hereinafter referred to as gate control signal S-) to the gate control signal line S-, and further outputs a gate control signal (hereinafter referred to as gate control signal B) to the gate control signal line B, based on the timing signal generated by the timing generator 13.

[0064] The vertical shift register & level shifter 15 outputs n-row scan pulses sequentially, one row at a time, from row 1 to row n, with a period of 1 horizontal scan period (HST). AND circuits ADA1 to ADan each control whether to output the n-row scan pulses, output sequentially from the vertical shift register & level shifter 15, to the row scan lines G1 to Gn, based on the externally supplied mode switching signal MD. AND circuits ADB1 to ADBn each control whether to output the n-row scan pulses, output sequentially from the vertical shift register & level shifter 15, to the readout switch selection lines TG1 to TGn, based on the externally supplied mode switching signal MD.

[0065] For example, in the operation where a video signal is written to pixel 12 (image writing operation), an H-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADA1 to ADan each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the row scan lines G1 to Gn. At this time, AND circuits ADB1 to ADBn each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the read switch selection lines TG1 to TGn. In other words, the read switch selection lines TG1 to TGn are all fixed at the L level.

[0066] In contrast, when the video signal written to pixel 12 is read out (image readout operation), an L-level mode switching signal MD is supplied from an external source. In this case, AND circuits ADB1 to ADBn each output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the readout switch selection lines TG1 to TGn. At this time, AND circuits ADA1 to ADan each do not output n lines of scan pulses, which are sequentially output one line at a time from the vertical shift register and level shifter 15, to the row scan lines G1 to Gn. In other words, the row scan lines G1 to Gn are all fixed at the L level.

[0067] (Specific example of the configuration of pixel 12) Figure 6 shows a specific example of the configuration of pixel 12. Here, we will describe a pixel 12 located in the jth row and ith column of an n-row × m-column pixel 12. Note that j is any integer from 1 to n, and i is any integer from 1 to m.

[0068] As shown in Figure 6, the pixel 12 includes N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6, Tr9, P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, Tr8, retention capacitors Cs1, Cs2, and liquid crystal display elements LC.

[0069] The transistor Tr1 and the holding capacitor Cs1 constitute a sample-and-hold circuit that samples and holds the positive polarity video signal supplied via the data line Di+. Specifically, the source of transistor Tr1 is connected to the data line Di+, the drain is connected to the gate of transistor Tr3, and the gate is connected to the row scan line Gj. The holding capacitor Cs1 is located between the gate of transistor Tr3 and the ground voltage terminal Vss.

[0070] The transistor Tr2 and the holding capacitor Cs2 constitute a sample-and-hold circuit that samples and holds the negative polarity video signal supplied via the data line Di-. Specifically, the source of transistor Tr2 is connected to the data line Di-, the drain is connected to the gate of transistor Tr4, and the gate is connected to the row scan line Gj. The holding capacitor Cs2 is provided between the gate of transistor Tr4 and the ground voltage terminal Vss. The holding capacitors Cs1 and Cs2 are provided independently of each other and hold the positive and negative polarity video signals in parallel, respectively.

[0071] Transistors Tr3 and Tr7 constitute a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitance Cs1. Specifically, in the source follower transistor Tr3, the drain is connected to the ground voltage line Vss and the source is connected to node Na. In transistor Tr7, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Na, and the gate is connected to the gate control signal line B.

[0072] Transistors Tr4 and Tr8 constitute a source follower buffer that outputs a voltage held in the holding capacitance Cs2. Specifically, in the source follower transistor Tr4, the drain is connected to the ground voltage line Vss and the source is connected to node Nb. In transistor Tr8, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Nb and the gate is connected to the gate control signal line B.

[0073] Transistors Tr5 and Tr6 constitute a polarity switching switch. Specifically, in transistor Tr5, the source is connected to node Na, the drain is connected to the pixel drive electrode PE, and the gate is connected to one of the gate control signal lines, S+. In transistor Tr6, the source is connected to node Nb, the drain is connected to the pixel drive electrode PE, and the gate is connected to the other gate control signal line, S-.

[0074] The liquid crystal display element (LC) consists of a pixel driving electrode (reflective electrode) PE having light-reflecting properties, a common electrode CE positioned opposite and spaced apart from the pixel driving electrode and having light-transmitting properties, and liquid crystal LCM filling and encapsulating the space between them. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the readout switch selection line TGj.

[0075] The data line pairs Di+ and Di- are supplied with video signals of opposite polarity, sampled by the analog switch unit 17. When a scan pulse output from the vertical shift register & level shifter 15 is supplied to the row scan line Gj, transistors Tr1 and Tr2 turn on simultaneously. As a result, the voltage of the positive polarity video signal propagating on the data line Di+ is held in the retaining capacitor Cs1 via transistor Tr1. Similarly, the voltage of the negative polarity video signal propagating on the data line Di- is held in the retaining capacitor Cs2 via transistor Tr2.

[0076] Furthermore, the input resistances of the positive and negative source follower buffers are virtually infinite. Therefore, the charge accumulated in the holding capacitors Cs1 and Cs2 is retained without leakage until one vertical scan period has elapsed and a new video signal is written.

[0077] Transistors Tr5 and Tr6, which constitute the polarity switching switch, switch on and off according to the gate control signals S+ and S-, thereby alternately selecting and outputting to the pixel drive electrode PE the output voltage of the positive-side source follower buffer (voltage of the positive polarity video signal) and the output voltage of the negative-side source follower buffer (voltage of the negative polarity video signal). As a result, the pixel drive electrode PE is supplied with a video signal voltage that periodically reverses polarity. In this way, the liquid crystal device 50 has a polarity reversal function in the pixels themselves, and by rapidly switching the polarity of the video signal voltage supplied to the pixel drive electrode PE at each pixel, AC driving at high frequencies becomes possible regardless of the vertical scanning frequency.

[0078] (Explanation of the AC driving method for pixel 12) Figure 7 is a timing chart illustrating the AC driving method of the pixel 12 by the liquid crystal device 50. Here, we will explain the AC driving method for the pixel 12 located in the jth row and ith column of an n-row × m-column pixel 12.

[0079] In Figure 7, VST represents the vertical synchronization signal which serves as the reference for vertical scanning of the video signal. B represents the gate control signals supplied to the gates of transistors Tr7 and Tr8, which are used as constant current loads for the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity switching switch. S- represents the gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity switching switch. VPE represents the voltage applied to the pixel drive electrode PE. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0080] Figure 8 is a diagram illustrating the voltage levels from black to white for both the positive and negative polarity video signals written to pixel 12. In the example in Figure 8, the positive polarity video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. Conversely, the negative polarity video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive polarity video signal may be configured to represent the white level when the voltage level is minimum and the black level when the voltage level is maximum, and the negative polarity video signal may be configured to represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed lines in the figure indicate the inversion centers of the positive and negative polarity video signals.

[0081] In pixel 12, transistor Tr9 remains in the off state because the readout switch selection line TGj is fixed at the low level. On the other hand, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to the row scan line Gj. When transistors Tr1 and Tr2 are turned on, the positive and negative polarity video signal voltages are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0082] As shown in Figure 7, the positive-side transistor Tr5 is turned on during the period when the gate control signal S+ is at the H level. At this time, by setting the gate control signal B to the L level, transistor Tr7 is turned on, and the positive-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the positive-polarity video signal. Also, by setting the gate control signal B to the L level, transistor Tr8 is turned on, and the negative-polarity source follower buffer also becomes active. However, since the negative-polarity transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative-polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the positive-polarity drive voltage is maintained in the liquid crystal capacitance.

[0083] On the other hand, during the period when the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, and the negative-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the negative polarity video signal. Furthermore, by setting the gate control signal B to the L level, the transistor Tr7 is turned on, and the positive-side source follower buffer also becomes active. However, since the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the negative polarity drive voltage is maintained in the liquid crystal capacitance.

[0084] In pixel 12, the operations of the positive and negative electrodes described above are repeated alternately, so that a drive voltage VPE, which is converted into AC using the voltages of the positive and negative video signals, is applied to the pixel drive electrode PE.

[0085] Furthermore, the charge held in the retention capacitors Cs1 and Cs2 is not directly transferred to the pixel drive electrode PE, but rather transferred via a source follower buffer. Therefore, even when the positive and negative polarity video signal charges are repeatedly charged and discharged at the pixel drive electrode PE, the charge is not neutralized, and pixel driving with suppressed voltage level attenuation can be achieved.

[0086] Furthermore, as shown in Figure 7, the voltage level of the voltage Vcom applied to the common electrode CE is switched to the opposite level to the voltage VPE applied to the pixel drive electrode PE in synchronization with the switching of the voltage level VPE applied to the pixel drive electrode PE. Note that the voltage Vcom applied to the common electrode CE is set as an inversion reference voltage that is approximately equal to the inversion reference voltage of the voltage VPE applied to the pixel drive electrode PE.

[0087] Here, the effective AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE. Therefore, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, the voltage Vcom applied to the common electrode CE switches in opposite phase to the voltage VPE applied to the pixel drive electrode PE, which reduces the amplitude of the voltage required to be applied to the pixel drive electrode PE. As a result, the breakdown voltage and power consumption of the transistors constituting the pixel circuit are reduced.

[0088] Even if the current flowing steadily through the source follower buffer per pixel is a minute current of 1 μA, the total current flowing steadily through all pixels of the liquid crystal device 50 can become a significant amount. For example, a liquid crystal device with 2 million pixels of full HD resolution could consume up to 2 A of current. Therefore, in pixel 12, transistors Tr7 and Tr8, which are used as constant current loads, are not kept on all the time, but are only turned on for a limited period of time while the positive and negative transistors Tr5 and Tr6, respectively, are on. This allows the operation of one source follower buffer to be stopped when the other source follower buffer is operating, thereby suppressing the increase in current consumption.

[0089] The AC drive frequency of a liquid crystal display element (LC) can be freely adjusted by adjusting the inversion control period of the pixel itself, regardless of the vertical scanning frequency. For example, suppose the vertical scanning frequency is 60Hz, which is commonly used in television video signals, and the number of vertical periodic scan lines n for full HD is 1125 lines. Also, assume that polarity switching at each pixel is performed at a period of about 15 line periods. In other words, the number of lines r per polarity switching period at each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal becomes 60Hz × 1125 / (15 × 2) = 2.25kHz. In other words, the liquid crystal device 50 can dramatically increase the AC drive frequency of the liquid crystal. This makes it possible to significantly improve the reliability, stability, and display quality of the image displayed on the liquid crystal screen, which were problems when the AC drive frequency of the liquid crystal was low.

[0090] Next, we will explain the operation of the liquid crystal device 50 in each operating mode.

[0091] (Operation of the liquid crystal device 50 in image display mode) First, the operation of the liquid crystal device 50 in image display mode (pixel writing mode) will be explained using Figure 9. Figure 9 is a timing chart showing the operation of the liquid crystal device 50 in image display mode.

[0092] As shown in Figure 9, when the horizontal synchronization signal HST pulse signal is supplied, the shift register circuit 161 sequentially captures m columns of video signals with an N (where N is an integer greater than or equal to 2) bit width in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 at the moment the trigger signal REG_S becomes temporarily active.

[0093] The grayscale counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a grayscale signal Cout indicating the count value. Here, the grayscale counter 164 outputs a grayscale signal Cout indicating the minimum count value at the start of one horizontal ramp period (the transition period of the ramp signal within one horizontal scanning period) R (when the horizontal synchronization signal HST rises), increases the grayscale level of the grayscale signal Cout as the count value increases, and outputs a grayscale signal Cout indicating the maximum count value at the end of one horizontal ramp period R (the time S before the next rising edge of the horizontal synchronization signal HST). The count value of the grayscale counter 164 is initialized to "0", for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST. The grayscale counter 164 is not limited to count-up operation, but may also be configured to count-down operation. In that case, the count value is initialized to the maximum value when the reset signal CNT_R becomes active.

[0094] The m-column comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the gradation signal Cout output from the gradation counter 164 matches each of the m-column video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0095] Of the m sets of switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- provided in the analog switch section 17, the positive polarity switch elements SW1_1+~SW1_m+ are provided between the data lines D1+~Dm+ and the common wiring Dcom+, respectively. The negative polarity switch elements SW1_1-~SW1_m- are provided between the data lines D1-~Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are switched on and off by the matching signals P1~Pm from comparators 163_1~163_m, respectively.

[0096] The common wiring Dcom+ is supplied with the reference lamp voltage Ref_R+, which is the positive polarity lamp signal output from the lamp signal generator 40. The common wiring Dcom- is supplied with the reference lamp voltage Ref_R-, which is the negative polarity lamp signal output from the lamp signal generator 40.

[0097] The reference ramp voltage Ref_R+ is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. The reference ramp voltage Ref_R- is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. Therefore, the reference ramp voltage Ref_R+ with respect to the common voltage Vcom and the reference ramp voltage Ref_R- with respect to the common voltage Vcom are inverse relationships with each other.

[0098] For example, the reference ramp voltage Ref_R+ linearly increases the voltage level from 0V (black level) to 4V (white level) from the start to the end of the horizontal ramp period R. The reference ramp voltage Ref_R- linearly decreases the voltage level from 4V (black level) to 0V (white level) from the start to the end of the horizontal ramp period R. Then, between the end of one horizontal ramp period R and the start of the next, the reference ramp voltage Ref_R+ returns to 0V (black level), and the reference ramp voltage Ref_R- returns to 4V (black level).

[0099] The switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are all turned on simultaneously when the start signal SW_Start becomes active (e.g., at level H) at the start of the horizontal ramp period R. Subsequently, each of the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- switches from on to off before the horizontal ramp period R has elapsed when the matching signals P1~Pm output from comparators 163_1~163_m become active (e.g., at level L). After the end of the horizontal ramp period R and before the start of the next horizontal ramp period R, the start signal SW_Start becomes inactive (e.g., at level L).

[0100] In the example in Figure 9, the waveform SPk represents the timing of switching the on and off states of the switch elements SWq+ and SWq- (where q is an integer from 1 to m), which are provided in correspondence with the pixel sequence on which the video signal of grayscale level k is written. Referring to Figure 9, the switch elements SWq+ and SWq- are turned on at the rising edge of the start signal SW_Start, and then switch from on to off when the matching signal Pq becomes active before the horizontal ramp period R has elapsed. Here, the switch elements SWq+ and SWq- sample the reference ramp voltages Ref_R+ and Ref_R- (voltages P and Q in Figure 9) at the timing of switching from on to off. The voltages P and Q sampled by the switch elements SWq+ and SWq- are supplied to the data lines Dq+ and Dq-, respectively. In other words, the analog voltages P and Q, which are the DA conversion results of the video signal of grayscale level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0101] In image display mode, an externally supplied H-level mode switching signal MD is provided. As a result, the n-row scan pulses output sequentially from the vertical shift register & level shifter 15 are supplied to the row scan lines G1 to Gn, respectively. Consequently, transistors Tr1 and Tr2, provided at each pixel 12 in the j-th row, are temporarily turned on. As a result, the corresponding positive and negative polarity video signal voltages are stored and held in the retention capacitors Cs1 and Cs2, provided at each pixel 12 in the j-th row. On the other hand, transistor Tr9, provided at each pixel 12, is fixed to the OFF position. The subsequent AC driving method for each pixel 12 is as previously described. This pixel writing operation is performed sequentially, row by row, from the m pixels 12 in the first row to the m pixels 12 in the n-th row.

[0102] As described above, the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are all turned on simultaneously at the start of each horizontal scanning period, but each can be turned off at any timing corresponding to the grayscale level of the image to be displayed on the corresponding pixel 12. In other words, the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- may all be turned off at the same time, or they may be turned off at different times. Furthermore, the order in which they are turned off is not fixed.

[0103] In this way, the liquid crystal device 50 can improve the linearity of the image by performing a digital-to-analog conversion of the video signal using the ramp signal and then writing it to the pixels 12.

[0104] (Operation of the liquid crystal device 50 in pixel inspection mode) Next, the operation of the liquid crystal device 50 in pixel inspection mode (pixel readout mode) will be described. In pixel inspection mode, an inspection device (not shown) is provided instead of the lamp signal generator 40. Alternatively, in pixel inspection mode, the lamp signal generator 40 may be configured to function as the inspection device.

[0105] In pixel inspection mode, first, a test video signal is written to the m pixels 12 in the j-th row that are to be inspected. The operation of writing the test video signal is basically the same as the operation of writing the video signal in pixel display mode. After that, the video signal (pixel drive voltage VPE) written to the m pixels 12 in the j-th row that are to be inspected is read out.

[0106] During the pixel readout operation, the mode switching signal MD switches from the high level to the low level, so the scan pulse for the j-th row output from the vertical shift register & level shifter 15 is supplied to the readout switch selection line TGj. As a result, the transistor Tr9 provided at each pixel 12 in the j-th row to be inspected is temporarily turned on. On the other hand, the transistors Tr1 and Tr2 provided at each pixel 12 are fixed to the off position.

[0107] For example, in pixel 12 located in the j-th row and i-th column, the pixel drive electrode PE and the data line Di+ become conductive when transistor Tr9 is turned on. At this time, by activating transistors Tr7 and Tr8, and turning on either transistor Tr5 or Tr6, the pixel drive electrode PE becomes driven by a source follower buffer consisting of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. As a result, the drive voltage VPE applied to the pixel drive electrode PE is read out to the data line Di+.

[0108] The m pixel drive voltages VPE, read from each of the m pixels 12 in the j-th row to data lines D1+ to Dm+, are sequentially supplied to the common wiring Dcom+ by sequentially turning on m sets of switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- provided in the analog switch unit 17. An inspection device (not shown), provided in place of the lamp signal generator 40, detects the presence or absence of failures (pixel defects and characteristic degradation) in the m pixels 12 in the j-th row based on the m pixel drive voltages VPE supplied sequentially via the common wiring Dcom+.

[0109] This type of inspection is performed row by row, starting from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0110] In this case, the voltage VPE of the pixel drive electrode PE, which is driven by a low-output impedance source follower buffer, is read directly from the pixel 12 being inspected. Therefore, defects and characteristic degradation of the pixel 12 being inspected can be detected accurately and easily.

[0111] (50 challenges of liquid crystal devices) Incidentally, the liquid crystal device 50 had a problem in that noise generated by the switching of each switch element in the analog switch section 17 from on to off propagates to the common wiring Dcom+, Dcom- via the parasitic capacitance formed in each switch element, causing fluctuations in the reference voltages Ref_R+, Ref_R- of the lamp signals propagating through the common wiring Dcom+, Dcom-, resulting in the inability to display high-quality images. This will be explained in detail below.

[0112] Referring to Figure 9, the switch elements SWq+ and SWq- (where q is an integer from 1 to m) of the analog switch unit 17 are switched from on to off when the matching signal Pq output from the comparator 163_q becomes active. At the timing when the switch elements SWq+ and SWq- switch from on to off, they sample the reference lamp voltages Ref_R+ and Ref_R- (voltages P and Q in Figure 9). These sampled voltages P and Q are supplied to the data lines Dq+ and Dq-. In other words, the analog voltages P and Q, which are the DA conversion results of the video signal at grayscale level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0113] Here, parasitic capacitance is formed between the gate and source (drain) of the MOS transistors that constitute the switching elements SWq+ and SWq-. Therefore, noise generated by the switching of the switching elements SWq+ and SWq- from on to off propagates to the common wiring Dcom+ and Dcom- through the parasitic capacitance formed in the switching elements SWq+ and SWq-. The noise propagated to the common wiring Dcom+ and Dcom- causes fluctuations in the reference voltages Ref_R+ and Ref_R- of the ramp signal propagating through the common wiring Dcom+ and Dcom-.

[0114] In particular, as the number of pixels 12 in multiple columns of the same row on which images of the same grayscale level (DA conversion results of the video signal) are written increases, the number of switch elements in the m-set of switch elements in the analog switch section 17 that switch from on to off simultaneously increases. As a result, the noise generated in the lamp signals propagating through the common wiring Dcom+, Dcom- increases, and the fluctuation range of the reference lamp voltages Ref_R+, Ref_R- increases.

[0115] Figure 10 is a diagram illustrating the effect of ringing of the lamp signal on the pattern (image). The left side of Figure 10 shows an example of an ideal pattern display, and the right side of Figure 10 shows an example of a pattern display when a problem occurs with the liquid crystal device 50. In the example in Figure 10, a 512-level pattern is written to m-1 pixels 12 in column m of row La (La is any integer from 1 to n), and a 513-level pattern is written to the remaining 1 pixel 12 in the ideal state. Also, in the example in Figure 10, a 512-level pattern is written to all pixels 12 in column m of row Lb (Lb is any integer from 1 to n other than La). Note that the display of patterns in this disclosure is not limited to the display example shown in Figure 10, but also includes displays of other patterns and at other resolutions.

[0116] Figure 11 is a waveform diagram of the reference lamp voltage Ref_R+ used to write a pattern to the pixel 12 in column m of row La of the liquid crystal device 50. Note that the ringing principle of the reference lamp voltage Ref_R- is the same as that of the reference lamp voltage Ref_R+, so its explanation is omitted.

[0117] Furthermore, in the example shown in Figure 11, at time t11, a 512-level pattern is written to m-1 pixels 12 in column m of row La, and at time t12, a 513-level pattern is written to the remaining 1 pixel 12 in an ideal state.

[0118] In the liquid crystal device 50, when a 512-level pattern is written to m-1 pixels 12 in column m of row La, m-1 sets of switch elements in the analog switch section 17 corresponding to those m-1 pixels 12 switch from on to off simultaneously. This generates significant noise in the lamp signal propagating through the common wiring Dcom+(Dcom-), causing the reference lamp voltage Ref_R+(Ref_R-) to fluctuate greatly.

[0119] At this time, for example, the reference lamp voltage Ref_R+, which is higher than the ideal value, attempts to return to the ideal value by the regular lamp signal generated by the lamp signal generator 40, but undershoots to a value lower than the ideal value. Subsequently, the reference lamp voltage Ref_R+, which is lower than the ideal value, attempts to return to the ideal value by the regular lamp signal generated by the lamp signal generator 40, but overshoots to a value higher than the ideal value. As this operation is repeated, the reference lamp voltage Ref_R+ converges to the ideal value. Such fluctuations in the reference lamp voltage Ref_R+ (Ref_R-) are also called ringing.

[0120] Here, the more the reference lamp voltage Ref_R+(Ref_R-) deviates from the ideal value due to ringing, the more the reference lamp voltage Ref_R+(Ref_R-) will deviate from the ideal gradation level.

[0121] Referring to Figure 11, first, at time t11, m-1 sets of switch elements in the analog switch section 17 corresponding to m-1 pixels 12 in row La are simultaneously switched from on to off. As a result, at the following time t12, the reference lamp voltage Ref_R+ fluctuates to a value 60 levels higher than the ideal value. Therefore, at time t12, the remaining pixel 12 in row La is not written with the ideal 513-level image, but rather with a 573-level image due to the ringing effect, which is 60 levels higher. In other words, as shown on the right side of Figure 10, the remaining pixel 12 in row La is written with a whiter image than ideal.

[0122] In the example in Figure 11, a 512-level pattern is written to m-1 pixels 12 in column m of row La, and a 513-level pattern is written to the remaining 1 pixel 12 in an ideal state. However, the explanation is not limited to this case. Similar problems can occur when multiple pixels 12 in column m of the same row are written with patterns of the same level of tonality, and when different pixels 12 in column m of the same row are written with patterns of different levels of tonality. However, the more pixels 12 in column m of the same row are written with patterns of the same level of tonality, the larger the ringing amount (variation range) of the reference lamp voltages Ref_R+,Ref_R- becomes, making the problem more likely to occur.

[0123] Figure 12 is a waveform diagram of the reference lamp voltage Ref_R+ used to write a pattern to the pixel 12 in column m of row Lb of the liquid crystal device 50. Note that the ringing principle of the reference lamp voltage Ref_R- is the same as that of the reference lamp voltage Ref_R+, so its explanation is omitted.

[0124] In the example shown in Figure 12, at time t21, a 512-level grayscale image is written to all of the pixels 12 in column m of row Lb. As shown in Figure 12, when a 512-level grayscale image is written to all of the pixels 12 in column m of row Lb, the m sets of switch elements in the analog switch unit 17 corresponding to those m pixels 12 are simultaneously switched from on to off. This generates significant noise in the ramp signal propagating through the common wiring Dcom+(Dcom-), causing the reference ramp voltage Ref_R+(Ref_R-) to fluctuate the most. However, since there are no pixels 12 in row Lb to which images with grayscale levels other than 512 levels are written, the above-mentioned problems due to ringing of the reference ramp voltages Ref_R+,Ref_R- do not occur.

[0125] Thus, in the liquid crystal device 50, noise generated by the switching of each switch element in the analog switch section 17 from on to off propagates to the common wiring Dcom+, Dcom- via the parasitic capacitance formed in each switch element, causing fluctuations in the reference voltages Ref_R+, Ref_R- of the ramp signals propagating through the common wiring Dcom+, Dcom-, resulting in the problem that high-quality images cannot be displayed.

[0126] Therefore, a liquid crystal device 1 according to Embodiment 1 was found that can solve the above-mentioned problems and improve quality.

[0127] <Embodiment 1> Figure 13 shows an example configuration of the liquid crystal device 1 according to Embodiment 1. The liquid crystal device 1 is also used as a reflective liquid crystal element 130 of the WSS array 100.

[0128] Liquid crystal device 1 further includes a filter section 18 compared to liquid crystal device 50. The filter section 18 is located between the common wiring Dcom+, Dcom- and the analog switch section 17. The other configurations of liquid crystal device 1 are the same as those of liquid crystal device 50, so their description is omitted.

[0129] Figure 14 is an enlarged view of the horizontal driver 16, analog switch section 17, and filter section 18 provided in the liquid crystal device 1. As shown in Figure 14, the filter section 18 includes m sets of low-pass filters F_1+, F_1- to F_m+, F_m-.

[0130] The positive-side low-pass filters F_1+ to F_m+ are provided between the common wiring Dcom+ through which the reference lamp voltage Ref_R+ propagates and the positive-side switch elements SW1_1+ to SW1_m+ of the analog switch unit 17, respectively. The negative-side low-pass filters F_1- to F_m- are provided between the common wiring Dcom- through which the reference lamp voltage Ref_R- propagates and the negative-side switch elements SW1_1- to SW1_m- of the analog switch unit 17, respectively.

[0131] The low-pass filters F_1+ to F_m+ remove noise (high-frequency ringing) generated by the on-to-off switching of the switch elements SW1_1+ to SW1_m+, respectively. Similarly, the low-pass filters F_1- to F_m- remove noise (high-frequency ringing) generated by the on-to-off switching of the switch elements SW1_1- to SW1_m-, respectively. As a result, the propagation of noise generated in each switch element of the analog switch section 17 to the common wiring Dcom+, Dcom- is suppressed, and fluctuations in the reference lamp voltages Ref_R+, Ref_R- of the lamp signals propagating through the common wiring Dcom+, Dcom+ are suppressed. Consequently, the liquid crystal device 1 can display high-quality images.

[0132] Figure 15 shows a specific example of the low-pass filter F_1+. Among the low-pass filters F_1+, F_1-~F_m+, and F_m-, the configurations other than the low-pass filter F_1+ are the same as those of the low-pass filter F_1+.

[0133] As shown in Figure 15, the low-pass filter F_1+ comprises a resistive element R1 and a capacitive element C1. The resistive element R1 is located between the common wiring Dcom+ and the switch element SW1_1+. The capacitive element C1 is located between the node between the resistive element R1 and the switch element SW1_1+ and the ground voltage terminal Vss, which is supplied with a reference voltage, the ground voltage Vss.

[0134] Figure 16 is a waveform diagram of the reference lamp voltage Ref_R+ used to write a pattern to pixel 12 in column m of row La of liquid crystal device 1. Note that the ringing principle of the reference lamp voltage Ref_R- is the same as that of the reference lamp voltage Ref_R+, so its explanation is omitted.

[0135] Furthermore, in the example shown in Figure 16, at time t31, a 512-level pattern is written to m-1 pixels 12 in column m of row La, and at time t32, a 513-level pattern is written to the remaining 1 pixel 12 in an ideal state.

[0136] In the liquid crystal device 1, when a 512-level pattern is written to m-1 pixels 12 in column m of row La, the m-1 pairs of switch elements in the analog switch unit 17 corresponding to those m-1 pixels 12 are simultaneously switched from on to off. As a result, noise (high-frequency ringing) generated in each of these m-1 pairs of switch elements attempts to propagate to the common wiring Dcom+, Dcom- via parasitic capacitance. However, the noise generated in the m-1 pairs of switch elements in the analog switch unit 17 is removed by the corresponding m-1 pairs of low-pass filters in the filter unit 18. This suppresses the propagation of noise generated in the m-1 pairs of switch elements in the analog switch unit 17 to the common wiring Dcom+, Dcom-, thus suppressing fluctuations in the reference lamp voltages Ref_R+, Ref_R- of the lamp signals propagating through the common wiring Dcom+, Dcom-.

[0137] Referring to Figure 16, first, at time t31, m-1 switch elements of the analog switch section 17 corresponding to m-1 pixels 12 in row La are simultaneously switched from on to off. As a result, at time t32, the reference lamp voltage Ref_R+(Ref_R-) fluctuates to a value two levels higher than the ideal value. Therefore, at time t32, the remaining pixel 12 in row La is written with a 515-level image, which is two levels higher than the ideal 513 levels. However, the error of two levels is negligible. In other words, the liquid crystal device 1 shows improved image quality compared to the liquid crystal device 50 in the conceptual stage.

[0138] In liquid crystal device 1, the ringing period is changed by the provision of the filter section 18. In the example in Figure 16, the peak of the deviation from the ideal value of the reference lamp voltage Ref_R+ towards the higher gradation side (white side) shifts from time t32 to time t33, which is later than time t32. Therefore, if, for the remaining pixel 12 of row La, a 513-gradation image is written in the ideal state at time t32, instead of a 515-gradation image being written in the ideal state at time t33, then the remaining pixel 12 of row La will have a 525-gradation image written to it, which is 10 gradations higher than the ideal 515 gradations. However, an error of 10 gradations is still smaller than the 60-gradation error in liquid crystal device 50. In other words, liquid crystal device 1 shows improved image quality compared to the liquid crystal device 50 in the conceptual stage.

[0139] Figure 17 shows the waveforms of the reference lamp voltage Ref_R+ corresponding to the resistance values ​​of each low-pass filter in the filter section 18 of the liquid crystal device 1. In the example in Figure 17, the waveforms for when the resistance value of the resistor element R1 provided in each low-pass filter F_1+, F_1- to F_m+, F_m- is 1kΩ and the waveforms for when the resistance value is 10kΩ are shown. Figure 17 also shows the waveform when the filter section 18 is not provided.

[0140] As shown in Figure 17, when the filter section 18 is provided, the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed compared to when the filter section 18 is not provided. Furthermore, when the resistance value of each low-pass filter in the filter section 18 is 10kΩ, the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed compared to when the resistance value is 1kΩ. Also, when the resistance value is 10kΩ, the ringing period is larger compared to when the resistance value is 1kΩ. From this, it can be seen that the larger the resistance value of each low-pass filter in the filter section 18, the more the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed. Therefore, the resistance value of the resistor element R1 of each low-pass filter in the filter section 18 is preferably 1kΩ or more. However, in order to prevent an increase in circuit size, each resistor element R1 is preferably about 50kΩ. Furthermore, in order to prevent an increase in circuit size, each resistor element R1 is preferably formed of polysilicon.

[0141] Figure 18 shows the waveform of the reference lamp voltage Ref_R+ corresponding to the capacitance value of each low-pass filter in the filter section 18 of the liquid crystal device 1. In the example in Figure 18, the waveforms for when the capacitance value of the capacitive element C1 provided in each low-pass filter F_1+, F_1- to F_m+, F_m- is 10fF and the waveforms for when the capacitance value is 100fF are shown. Figure 18 also shows the waveform when the filter section 18 is not provided.

[0142] As shown in Figure 18, when the filter section 18 is provided, the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed compared to when the filter section 18 is not provided. Furthermore, when the capacitance value of each low-pass filter in the filter section 18 is 100 fF, the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed compared to when the capacitance value is 10 fF. Also, when the capacitance value is 100 fF, the ringing period is larger compared to when the capacitance value is 10 fF. From this, it can be seen that the larger the capacitance value of each low-pass filter in the filter section 18, the more the fluctuation (ringing) of the reference lamp voltage Ref_R+ is suppressed. Therefore, it is preferable that the capacitance value of each capacitive element C1 of each low-pass filter in the filter section 18 is 10 fF or more. Furthermore, when each capacitive element C1 shows 10 fF or more, it is preferable that it be formed by MIM (Metal-Insulator-Metal). Each capacitive element C1 is not limited to being formed by MIM, but may also be formed by, for example, a gate electrode and a diffusion electrode.

[0143] Figure 19 shows the cross-sectional structure of a low-pass filter (LPF) provided in the filter section 18 of the liquid crystal device 1. In the example shown in Figure 19, metal layers M1 to M6 are stacked on a well, and through-holes TH1 to TH4 are formed between them. A contact CT is formed between the metal layer M1 and the diffusion electrode formed on the well surface. The capacitive element C1 of the low-pass filter is formed by MIM using metal layers M3 and M4. The resistive element R1 of the low-pass filter is formed by polysilicon placed on the well.

[0144] Thus, the liquid crystal device 1 according to this disclosure includes multiple low-pass filters between the common wiring Dcom+, Dcom- through which the ramp signal propagates and multiple sets of switch elements that capture the ramp signal at timings corresponding to each of the multiple video signals and output it to each of the multiple sets of data lines. As a result, the liquid crystal device 1 according to this disclosure can suppress the propagation of noise generated when the multiple sets of switch elements switch from on to off to the common wiring Dcom+, Dcom- via parasitic capacitance formed in the multiple sets of switch elements. As a result, fluctuations in the reference voltages Ref_R+, Ref_R- of the ramp signal propagating through the common wiring Dcom+, Dcom- are suppressed, and the liquid crystal device 1 can display high-quality images.

[0145] (Additional challenges for liquid crystal devices 50) By the way, the liquid crystal device 50 is required to display high-quality images. However, in the liquid crystal device 50, the switch elements SW1_q+, SW1_q- of the analog switch section 17, which are provided between the common wiring Dcom+, Dcom- on which the reference lamp voltages Ref_R+, Ref_R- propagate and the data lines Dq+, Dq- (where q is any integer from 1 to m) on which the reference lamp voltages Ref_R+, Ref_R- with voltage levels corresponding to the video signal are written, turn on when the reference lamp voltages Ref_R+, Ref_R- begin to change linearly and turn off at a timing corresponding to the gradation level of the video signal. Therefore, at the timing when the reference lamp voltages Ref_R+,Ref_R- begin to change linearly, the voltage (charge) written to the data lines Dq+,Dq- in the previous horizontal scanning period propagates to the common wiring Dcom+,Dcom- via the ON-state switch elements SW1_q+,SW1_q-, potentially causing the values ​​of the reference lamp voltages Ref_R+,Ref_R- to fluctuate while propagating through the common wiring Dcom+,Dcom-. As a result, the liquid crystal device 50 may not be able to display high-quality images. Furthermore, if the device waits until the fluctuations in the reference lamp voltages Ref_R+,Ref_R- subside, the frame rate must be lowered to ensure a longer horizontal scanning period, making it difficult to achieve a high frame rate. Also, even at the same frame rate, the time of the horizontal scanning period cannot be shortened to increase the pixel count, making it difficult to increase the pixel count.

[0146] The issues that occur in the liquid crystal device 50 will be explained in detail using the timing chart in Figure 9 and Figure 20. Figure 20 is a diagram illustrating the issues that occur in the liquid crystal device 50. Figure 20 shows the waveforms of the data line D1+, start signal SW_Start, and reference ramp voltage Ref_R+ near the end E1 of a certain horizontal ramp period R and the start S2 of the next horizontal ramp period R.

[0147] As shown in the timing chart in Figure 9, the reference ramp voltage Ref_R+ linearly increases from 0V (black level) to 4V (white level) during the horizontal ramp period R, from the start S1 to the end E1. Similarly, the reference ramp voltage Ref_R- linearly decreases from 4V (black level) to 0V (white level) during the same period. Then, at the end of the horizontal ramp period R, E1, the reference ramp voltage Ref_R+ returns to 0V (black level), and the reference ramp voltage Ref_R- returns to 4V (black level).

[0148] On the other hand, the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are all turned on simultaneously at the start of the horizontal ramp period R (S1) when the start signal SW_Start becomes active (e.g., at a high level). Subsequently, each of the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- switches from on to off before the horizontal ramp period R has elapsed when the matching signals P1~Pm output from comparators 163_1~163_m become active (e.g., at a low level). After the end of the horizontal ramp period R (E1) and before the start of the next horizontal ramp period R (S2), the start signal SW_Start becomes inactive (e.g., at a low level).

[0149] Here, at the end of the horizontal ramp period R, E1, the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are all in the off state. Therefore, at the end of the horizontal ramp period R, E1, the data lines D1+, D1-~Dm+, Dm- all have analog voltages corresponding to the grayscale level of the video signal written to them.

[0150] For example, as shown in Figure 20, if a high white level voltage (e.g., 4V) is written to all data lines D1+ to Dm+ during a certain horizontal ramp period R, a charge equivalent to the high white level voltage (e.g., 4V) will be stored in the parasitic capacitance of each data line D1+ to Dm+. The parasitic capacitance of data line Dq+ includes, for example, the wiring capacitance of data line Dq+ and the diffusion capacitance of transistor Tr1 provided in each of the n rows of pixels 12 connected to data line Dq+.

[0151] Subsequently, at the end of the horizontal ramp period R (E1), the reference ramp voltage Ref_R+ returns to a black level voltage (e.g., 0V). Then, at the start of the next horizontal ramp period R (S2), the start signal SW_Start becomes active (e.g., at the high level), causing the switch elements SW1_1+ to SW1_m+ to turn on simultaneously. At the same time, the reference ramp voltage Ref_R+ begins to increase linearly. However, at this time, the voltage written to the data lines D1+ to Dm+ during the previous horizontal scanning period propagates to the common wiring Dcom+ via the ON switch elements SW1_1+ to SW1_m+, which may cause the value of the reference ramp voltage Ref_R+ propagating through the common wiring Dcom+ to fluctuate.

[0152] In the example shown in Figure 20, the capacitance of the common wiring Dcom+ is approximately 20pF, and when the pixel count is FHD, the capacitance values ​​of all data lines D1+ to Dm+ become approximately 1000pF. As a result, the initial value of the reference lamp voltage Ref_R+ propagating through the common wiring Dcom+ fluctuates from 0V to approximately 0.5V due to the influence of the charge on the data lines D1+ to Dm+. Consequently, the liquid crystal device 50 may not be able to display high-quality images. This problem is not limited to cases where a high white level voltage (e.g., 4V) is written to all data lines D1+ to Dm+, but can also occur when a relatively high voltage is written to some of the data lines D1+ to Dm+.

[0153] Similarly, if a low white level voltage (e.g., 0V) is written to all data lines D1- to Dm- during a certain horizontal ramp period R, a charge equivalent to the low white level voltage (e.g., 0V) will be stored in the parasitic capacitance of each data line D1- to Dm-. The parasitic capacitance of data line Dq- includes, for example, the wiring capacitance of data line Dq- and the diffusion capacitance of transistor Tr2 provided in each of the n rows of pixels 12 connected to data line Dq-.

[0154] Subsequently, at the end of the horizontal ramp period R (E1), the reference ramp voltage Ref_R- returns to a black level voltage (e.g., 4V). Then, at the start of the next horizontal ramp period R (S2), the start signal SW_Start becomes active (e.g., at the high level), causing the switch elements SW1_1-~SW1_m- to turn on simultaneously. At this time, the reference ramp voltage Ref_R- also begins to increase linearly. However, at this time, the voltage written to the data lines D1-~Dm- during the previous horizontal scanning period propagates to the common wiring Dcom- via the ON switch elements SW1_1-~SW1_m-, which may cause the value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom- to fluctuate. For example, the initial value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom- may fluctuate from 5V to around 4.5V due to the influence of the charge on the data lines D1-~Dm-. As a result, the liquid crystal device 50 may not be able to display high-quality images. This issue is not limited to cases where a low voltage (e.g., 0V) at the white level is written to all of the data lines D1- to Dm-, but can also occur when a relatively low voltage is written to some of the data lines D1- to Dm-.

[0155] The above-mentioned problems of the liquid crystal device 50 can also occur in the liquid crystal device 1 according to Embodiment 1. In the liquid crystal device 1, a filter unit 18 is provided between the common wiring Dcom+, Dcom- and the analog switch unit 17. Therefore, compared to the case where the filter unit 18 is not provided, the movement of charge between the data lines D1+, D1- to Dm+, Dm- and the common wiring Dcom+, Dcom- after the switch element of the analog switch unit 17 is turned on is slower.

[0156] Therefore, the time from when the switch elements SW1_1+~SW1_m+ of the analog switch section 17 are turned on until the voltage between the data lines D1+~Dm+ and the common wiring Dcom+ is averaged, and until the initial value of the reference lamp voltage Ref_R+ propagating through the common wiring Dcom+ returns to 0V becomes longer. In other words, the linear change start time of the reference lamp voltage Ref_R+ occurs before the initial value of the reference lamp voltage Ref_R+, which has been affected by the charge on the data lines D1+~Dm+, returns to 0V.

[0157] Similarly, the time from when the switch elements SW1_1-~SW1_m- of the analog switch section 17 are turned on until the voltage between the data line D1-~Dm- and the common wiring Dcom- is averaged, and until the initial value of the reference lamp voltage Ref_R- propagating through the common wiring Dcom- returns to 5V becomes longer. In other words, the linear change start time of the reference lamp voltage Ref_R- occurs before the initial value of the reference lamp voltage Ref_R-, which has been affected by the charge on the data line D1-~Dm-, returns to 5V.

[0158] Figure 21 is a diagram illustrating the challenges of liquid crystal device 1. Figure 21 shows the waveforms of data line D1+, start signal SW_Start, and reference ramp voltage Ref_R+ near the end E1 of one horizontal ramp period R and the start S2 of the next horizontal ramp period R.

[0159] In the example shown in Figure 21, the capacitance of the common wiring Dcom+ is approximately 20pF, and when the number of pixels is FHD, the capacitance values ​​of all data lines D1+ to Dm+ become approximately 1000pF. As a result, the initial value of the reference lamp voltage Ref_R+ propagating through the common wiring Dcom+ fluctuates from 0V to about 1V due to the influence of the charge on the data lines D1+ to Dm+.

[0160] Therefore, a liquid crystal device 2 according to Embodiment 2 was found that solves the above-mentioned problems and is capable of displaying high-quality images.

[0161] <Embodiment 2> Figure 22 shows an example configuration of the liquid crystal device 2 according to Embodiment 2. The liquid crystal device 2 is also used as a reflective liquid crystal element 130 of the WSS array 100.

[0162] As shown in Figure 22, liquid crystal device 2 further includes an initialization switch unit 19 compared to liquid crystal device 1. Figure 22 also shows a lamp signal generator 40 that is connected to liquid crystal device 2 during normal operation. The initialization switch unit 19 is located between the analog switch unit 17 and the multiple pixels 12. The other configurations of liquid crystal device 2 are the same as those of liquid crystal device 50, so their description is omitted.

[0163] Figure 23 is a diagram showing in more detail the horizontal driver 16, analog switch unit 17, filter unit 18, and initialization switch unit 19 provided in the liquid crystal device 2.

[0164] As shown in Figure 23, the initialization switch unit 19 is equipped with m sets of switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m- corresponding to the m-row pixels 12. Of the m sets of switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m-, the positive polarity switch elements SW2_1+~SW2_m+ are provided between the data lines D1+~Dm+ and the signal line (initialization wiring) dis+, respectively, and are switched on and off based on the control signal Rmp_dis. The negative polarity switch elements SW2_1-~SW2_m- are provided between the data lines D1-~Dm- and the signal line (initialization wiring) dis-, respectively, and are switched on and off based on the control signal Rmp_dis. The signal line dis+ is set to the same voltage (e.g., 0V) as the value at the start of the linear increase of the reference lamp voltage Ref_R+ (initial value). The signal line dis- is set to the same voltage (e.g., 4V) as the value at which the linear decrease of the reference ramp voltage Ref_R- begins (initial value).

[0165] However, the signal line dis+ is not limited to being set to the same voltage as the initial value of the reference lamp voltage Ref_R+, but may also be set to a voltage close to the initial value of the reference lamp voltage Ref_R+. Similarly, the signal line dis- is not limited to being set to the same voltage as the initial value of the reference lamp voltage Ref_R-, but may also be set to a voltage close to the initial value of the reference lamp voltage Ref_R-. Therefore, for example, the signal line dis+ may be connected to the reference voltage terminal GND to which a reference voltage such as 0V is supplied, and the signal line dis- may be connected to the power supply voltage terminal VDD to which a power supply voltage such as 5V is supplied.

[0166] For example, the m-set of switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m- turns off when the control signal Rmp_dis is at a low level and turns on when the control signal Rmp_dis is at a high level. When the control signal Rmp_dis is at a high level, the switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m- turn on, initializing the positive polarity data lines D1+~Dm+ to the voltage of the signal line dis+ (0V), and the negative polarity positive data lines D1-~Dm- to the voltage of the signal line dis- (4V).

[0167] Figure 24 shows an example configuration of the switch element SW2_1+, which is one of the switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m-. As shown in Figure 24, the switch element SW2_1+ comprises a P-channel MOS transistor (hereinafter simply referred to as transistor) MP1, an N-channel MOS transistor (hereinafter simply referred to as transistor) MN1, and an inverter INV1. The source of transistor MP1 and the drain of transistor MN1 are connected to the signal line dis+. The drain of transistor MP1 and the source of transistor MN1 are connected to the data line D1+. The gate of transistor MN1 is supplied with the control signal Rmp_dis, and the gate of transistor MP1 is supplied with a signal obtained by inverting the control signal Rmp_dis by the inverter INV1. In other words, transistors MP1 and MN1 constitute a complementary switch.

[0168] Of the switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m-, all switch elements except SW2_1+ have the same configuration as SW2_1+, so their explanation is omitted. However, the switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m- are not limited to being composed of transistors MP1 and MN1; for example, they may be composed of transistor MP1 alone, or transistor MN1 alone.

[0169] (Operation of liquid crystal device 2 in image display mode) Figure 25 is a timing chart showing the operation of the liquid crystal device 2 in image display mode (pixel writing mode). Compared to the timing chart shown in Figure 9, the timing chart in Figure 25 includes the waveform of the control signal Rmp_dis.

[0170] As shown in Figure 25, the control signal Rmp_dis becomes temporarily active (e.g., at a high level) between the end E1 of one horizontal ramp period R and the start S2 of the next horizontal ramp period R. As a result, the m-set of switch elements SW2_1+, SW2_1-~SW2_m+, SW2_m- are turned on, so that the positive polarity data lines D1+~Dm+ are initialized to the voltage of the signal line dis+ (0V), and the negative polarity positive data lines D1-~Dm- are initialized to the voltage of the signal line dis- (4V).

[0171] Subsequently, when the next horizontal synchronization signal HST pulse signal is supplied, the shift register circuit 161 sequentially captures m columns of N (where N is an integer greater than or equal to 2) bit wide video signals in synchronization with the clock signal HCK. The 1-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 at the moment the trigger signal REG_S becomes temporarily active.

[0172] The m-column comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the gradation signal Cout output from the gradation counter 164 matches each of the m-column video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0173] The m-set of switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- provided in the analog switch section 17 are all turned on simultaneously at the start of the horizontal ramp period R S2 when the start signal SW_Start becomes active (e.g., at level H). Subsequently, each of the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- switches from on to off before the horizontal ramp period R has elapsed when the matching signals P1~Pm output from comparators 163_1~163_m become active (e.g., at level L). After the end of the horizontal ramp period R E2 and before the start of the next horizontal ramp period R, the start signal SW_Start becomes inactive (e.g., at level L).

[0174] Here, at the start of the horizontal ramp period R, S2, the data lines D1+ to Dm+ on the positive side have already been initialized to the voltage of the signal line dis+ (0V) by the initialization switch unit 19, and the data lines D1- to Dm- on the negative positive side have already been initialized to the voltage of the signal line dis- (4V). In other words, as shown in Figure 26, the initial value of the reference ramp voltage Ref_R+ propagating through the common wiring Dcom+ is approximately the same as the initial value of the data lines D1+ to Dm+ after initialization, and is also approximately the same as the initial value of the reference ramp voltage Ref_R- propagating through the common wiring Dcom-. Therefore, as shown in Figure 26, even when the switch elements SW1_1+, SW1_1- to SW1_m+, SW1_m- are turned on, the initial values ​​of the reference ramp voltages Ref_R+, Ref_R- propagating through the common wiring Dcom+, Dcom- do not change. As a result, the liquid crystal device 2 can display high-quality images. Furthermore, since the liquid crystal device 2 does not need to wait until the fluctuations in the reference lamp voltages Ref_R+ and Ref_R- subside, the time from the end of horizontal lamp period R E1 to the start of the next horizontal lamp period R S2 can be shortened. As a result, the liquid crystal device 2 can achieve a higher frame rate, thereby enabling a higher pixel count.

[0175] As described above, the liquid crystal device 2 according to this disclosure initializes the voltages of data lines D1+, D1-~Dm+, Dm- to a voltage corresponding to the initial value of the reference lamp voltage Ref_R+, Ref_R- using a separate path from the common wiring Dcom+, Dcom- before the start of the next horizontal ramp period. As a result, even when the switch elements SW1_1+, SW1_1-~SW1_m+, SW1_m- are turned on, the movement of charge between data lines D1+~Dm+ and the common wiring Dcom+, and the movement of charge between data lines D1-~Dm- and the common wiring Dcom- are suppressed, and fluctuations in the initial value of the reference lamp voltage Ref_R+, Ref_R- propagating through the common wiring Dcom+, Dcom- are suppressed. As a result, the liquid crystal device 2 can display high-quality images. Furthermore, since the liquid crystal device 2 does not need to wait until the fluctuations in the reference lamp voltages Ref_R+ and Ref_R- subside, the time from the end of horizontal lamp period R E1 to the start of the next horizontal lamp period R S2 can be shortened. As a result, the liquid crystal device 2 can achieve a higher frame rate, thereby enabling a higher pixel count.

[0176] When the liquid crystal device 2 according to this disclosure is used as a reflective liquid crystal display element in a wavelength-selective switch, the switching time between optical signal processing and the no-signal state is shortened. As a result, the wavelength-selective switch can shorten the horizontal scanning period, which enables a higher frame rate. Furthermore, at the same frame rate, the shorter horizontal scanning period allows for higher pixel counts. Higher pixel counts lead to an increase in the number of channels in the optical switch, enabling the processing of a large amount of optical data at once. This means that, for example, when the wavelength-selective switch is used as a large-scale data switch requiring multiple ports, fewer LCOSs for the WSS are needed, thus reducing costs.

[0177] This disclosure is not limited to the embodiments described above, and may be modified as appropriate without departing from its spirit. [Explanation of symbols]

[0178] 1. Liquid crystal device 2. Liquid Crystal Devices 11 Image display section 12 pixels 13 Timing Generator 14 Polarity switching control circuit 15 Vertical Shift Register & Level Shifter 16 Horizontal Driver 17 Analog switch section 18 Filter section 19 Initialization switch section 40 Lamp signal generator 50 LCD devices 100 WSS arrays 100a, 100b WSS devices 110 Input Section 120 Optical system 121-123 Lens 124 Dispersion Elements 130 Reflective liquid crystal elements 161 Shift Register Circuit 162 1-line latch circuit 163 Comparator section 163_1~163_m Comparator 164-level grayscale counter ADA1~ADAn AND circuit ADB1~ADBn AND circuit B Gate control signal line C1 Capacitive element CE Common Electrode Cs1,Cs2 retention capacity D1+, D1- ~ Dm+, Dm- data lines Dcom+, Dcom- Common wiring FI1 Input Fiber (Input Port) FI2 Input Fiber (Input Port) FO1_1~FO1_n Output Fiber (Output Port) FO2_1~FO2_n Output Fiber (Output Port) G1~Gn row scanning line INV1 Inverter LC liquid crystal display element LCM LCD LI1, LI2 collimating lenses LO1_1~LO1_n Collimating Lens LO2_1~LO2_n collimating lenses MN1 N-channel MOS transistor MP1 P-channel MOS transistor Na,Nb nodes PE pixel driving electrode (reflector electrode) R1 Resistor S+, S- gate control signal lines SW1_1+, SW1_1- ~ SW1_m+, SW1_m- Switch elements SW2_1~SW2_m Switch elements TG1~TGn Switch selection lines for reading Tr1~Tr9 Transistors

Claims

1. Multiple pixels, Multiple data lines provided corresponding to each row of the aforementioned multiple pixels, A shift register unit that sequentially captures the video signal for the number of rows of pixels mentioned above, synchronized with the clock signal, A latch unit that simultaneously outputs the multiple video signals acquired by the shift register unit in synchronization with a trigger signal, Multiple comparators that compare each of the multiple video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value, and activate the respective matching signals when they match, A plurality of first switch elements are provided between a common wiring on which a ramp signal, whose potential changes linearly with each horizontal ramp period, propagates, and the plurality of data lines, and which turn on when the potential of the ramp signal begins to change linearly, and turn off individually when the matching signal of each of the plurality of comparators becomes active. A plurality of second switch elements are provided between the initialization wiring, which is a separate path from the common wiring, and the plurality of data lines, and which initialize the potential of the plurality of data lines. A plurality of low-pass filters are provided between the common wiring and each of the plurality of first switch elements, A liquid crystal device equipped with [a specific feature / feature].

2. Each of the aforementioned low-pass filters is A resistive element is provided between the common wiring and the corresponding first switch element, A capacitive element is provided between the node between the resistive element and the corresponding first switch element, and the reference voltage terminal to which the reference voltage is supplied. Having, The liquid crystal device according to claim 1.

3. The aforementioned common wiring consists of a common wiring on the positive polarity side and a common wiring on the negative polarity side. Each of the aforementioned data lines is composed of a positive polarity data line and a negative polarity data line. Each first switch element is A first switch element on the positive side is provided between the common wiring on the positive side and the corresponding data line on the positive side. A first switch element on the negative side is provided between the common wiring on the negative side and the corresponding data line on the negative side. It has, Multiple sets of gate control signals are provided corresponding to each row of the aforementioned multiple pixels, A polarity switching control circuit supplies a set of gate control pulses to each of the multiple sets of gate control lines, thereby alternately connecting each pixel to the corresponding positive polarity data line and the corresponding negative polarity data line. Furthermore, Each of the aforementioned low-pass filters is A positive-side low-pass filter is provided between the positive-side common wiring and the corresponding positive-side switch element. A negative-side low-pass filter is provided between the negative-side common wiring and the corresponding negative-side switch element. Having, The liquid crystal device according to claim 1.

4. The plurality of second switch elements are temporarily turned on before the plurality of first switch elements are turned on. The liquid crystal device according to claim 1.

5. The potential of the initialization wiring is set to a potential corresponding to the initial value of the lamp signal potential. The liquid crystal device according to claim 4.

6. Input port, One or more output ports, A reflective liquid crystal element, which is a liquid crystal device according to any one of claims 1 to 5, having a plurality of pixels that deflect an optical signal incident on the input port and emit it from one or more output ports selected from the plurality of output ports, A wavelength-selective switching device equipped with the following features.

7. Multiple pixels, Multiple data lines provided corresponding to each row of the aforementioned multiple pixels, A shift register unit that sequentially captures the video signal for the number of rows of pixels mentioned above, synchronized with the clock signal, A latch unit that simultaneously outputs the multiple video signals acquired by the shift register unit in synchronization with a trigger signal, Multiple comparators that compare each of the multiple video signals output from the latch unit with a gradation signal indicating a monotonically transitioning count value, and activate the respective matching signals when they match, A plurality of first switch elements are provided between a common wiring on which a ramp signal, whose potential changes linearly with each horizontal ramp period, propagates, and the plurality of data lines, and which turn on when the potential of the ramp signal begins to change linearly, and turn off individually when the matching signal of each of the plurality of comparators becomes active. A plurality of second switch elements are provided between the initialization wiring, which is a separate path from the common wiring, and the plurality of data lines, and which initialize the potential of the plurality of data lines. A plurality of low-pass filters are provided between the common wiring and each of the plurality of first switch elements, Equipped with, A method for controlling a liquid crystal device, During a certain horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly. During the aforementioned horizontal ramp period, the multiple first switch elements are individually turned off at the timing when the matching signal of each of the multiple comparators becomes active. After the expiration of a certain horizontal ramp period and before the start of the next horizontal ramp period, the plurality of second switch elements are temporarily turned on. During the next horizontal ramp period, the plurality of first switch elements are turned on at the timing when the potential of the ramp signal begins to change linearly. During the subsequent horizontal ramp period, the plurality of first switch elements are individually turned off at the timing when the matching signal of each of the plurality of comparators becomes active. A method for controlling liquid crystal devices.

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