RC-IGBT

Abstract

To improve the electrical characteristics of RC-IGBTs. [Solution] The RC-IGBT10 comprises a semiconductor layer 20 including a first surface 20S and a second surface 20R opposite to the first surface 20S; an IGBT region 14 and a diode region 16 arranged in a first direction when viewed from the thickness direction of the semiconductor layer 20; a collector region 26C of a first conductivity type located in the IGBT region 14, which is a portion of the semiconductor layer 20 closer to the second surface 20R than the first surface 20S; a cathode region 26K of a second conductivity type located in the diode region 16, which is a portion of the semiconductor layer 20 closer to the second surface 20R than the first surface 20S; a first trench 62A located in the IGBT region 14; a second trench 62B located in the diode region 16; and an island region 80 of a first conductivity type located in the semiconductor layer 20 between the bottom wall 632 of the first trench 62A and the collector region 26C in the thickness direction.

Description

[Technical Field]

[0001] This disclosure relates to RC-IGBT. [Background technology]

[0002] An RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) includes an IGBT and a freewheeling diode connected in antiparallel to the IGBT on a single chip. Patent Document 1 shows the active region of an RC-IGBT, which includes the IGBT region and the diode region. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2020 / 080476

[0004] [overview] Improvements to the electrical characteristics of RC-IGBTs are desired.

[0005] An RC-IGBT according to one aspect of the present disclosure includes a semiconductor layer including a first surface and a second surface opposite to the first surface; an IGBT region and a diode region arranged in a first direction in a plan view of the semiconductor layer as seen from the thickness direction; a collector region of a first conductivity type located in the IGBT region, which is a portion of the semiconductor layer closer to the second surface than the first surface; a cathode region of a second conductivity type located in the diode region, which is a portion of the semiconductor layer closer to the second surface than the first surface; a first trench located in the IGBT region of the semiconductor layer and recessed from the first surface; a second trench located in the diode region of the semiconductor layer and recessed from the first surface; and an island region of a first conductivity type located in the semiconductor layer between the bottom wall of the first trench and the collector region in the thickness direction. [Brief explanation of the drawing]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary RC-IGBT according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the arrangement of an IGBT region and a diode region of the RC-IGBT shown in FIG. 1. [Figure 3] FIG. 3 is a schematic enlarged view of a region F3 of the RC-IGBT shown in FIG. 2. [Figure 4] FIG. 4 is a schematic cross-sectional view of the RC-IGBT along line F4-F4 shown in FIG. 3. [Figure 5] FIG. 5 is a schematic enlarged view of a region F5 shown in FIG. 4. [Figure 6] FIG. 6 is a graph showing the relationship between emitter-collector voltage and leakage current in an RC-IGBT. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an exemplary manufacturing process of an RC-IGBT. [Figure 8] FIG. 8 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 7. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing an RC-IGBT according to a second embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing an RC-IGBT according to a third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a modified RC-IGBT. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a modified RC-IGBT.

[0007] [Detailed explanation] Embodiments of the RC-IGBT of this disclosure will be described below with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in the cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting this disclosure.

[0008] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are formed between the first and second elements.

[0010] <First Embodiment> The RC-IGBT10 of the first embodiment will be described with reference to Figures 1 to 5. Figure 1 is a schematic plan view of an exemplary RC-IGBT 10 according to the first embodiment. Figure 2 is a schematic plan view showing the arrangement of the IGBT region 14 and diode region 16 of the RC-IGBT 10 shown in Figure 1. In Figure 2, dots are added to the diode region 16 to aid understanding. Figure 3 is a schematic enlarged view of region F3 of the RC-IGBT 10 shown in Figure 2. Figure 3 schematically shows the planar structure of region F3. Figure 4 is a schematic cross-sectional view of the RC-IGBT 10 along the line F4-F4 shown in Figure 3. Figure 5 is a schematic enlarged view of region F5 shown in Figure 4.

[0011] [Overall planar structure of RC-IGBT10] As shown in Figures 1 and 2, the RC-IGBT10 has a flat plate shape. In Figure 1, the RC-IGBT10 is shown with the Z-axis direction of the mutually orthogonal XYZ axes shown in Figure 1 as the thickness direction. The RC-IGBT10 has a rectangular shape when viewed from the Z-axis direction.

[0012] The RC-IGBT 10 may include a cell region 11 and an outer peripheral region 12 that surrounds the cell region 11 when viewed from the Z-axis direction. The cell region 11 may have a rectangular shape when viewed from the Z-axis direction. The outer peripheral region 12 may have a rectangular ring shape.

[0013] The cell region 11 includes an IGBT region 14 and a diode region 16. The diode region 16 acts as a freewheeling diode (FWD) connected in antiparallel to the IGBT formed by the IGBT region 14. Both the IGBT and the freewheeling diode are provided on the same chip.

[0014] The RC-IGBT 10 includes a semiconductor layer 20. The semiconductor layer 20 includes a first surface 20S and a second surface 20R (see Figure 4) opposite to the first surface 20S. Here, the term "plan view" as used in this disclosure means viewing the RC-IGBT 10 from a direction perpendicular to the first surface 20S, unless explicitly stated otherwise. As shown in Figure 1, the Z-axis direction may be perpendicular to the first surface 20S of the semiconductor layer 20. Therefore, "plan view" can also mean viewing the RC-IGBT 10 from the Z-axis direction. In this disclosure, the Z-axis direction corresponds to the "thickness direction," the X-axis direction to the "first direction," and the Y-axis direction to the "second direction." That is, the thickness direction of the semiconductor layer 20 coincides with the direction perpendicular to the first surface 20S of the semiconductor layer 20. Furthermore, in the following explanation, the direction from the second surface 20R to the first surface 20S will be referred to as "upward," and the direction from the first surface 20S to the second surface 20R will be referred to as "downward."

[0015] The semiconductor layer 20 may include a semiconductor substrate and an epitaxial layer. For this reason, the semiconductor layer 20 may be referred to as, for example, a "chip" or a "semiconductor chip". The semiconductor layer 20 may be made of a material containing Si. For this reason, a Si substrate may be used as the semiconductor substrate in the semiconductor layer 20. In this case, the epitaxial layer may be a Si epitaxial layer epitaxially grown on the Si substrate.

[0016] As shown in Figure 1, the RC-IGBT 10 includes an insulating layer 40 and a first electrode layer 50. The insulating layer 40 and the first electrode layer 50 are provided on a first surface 20S. In a plan view, the insulating layer 40 overlaps both the IGBT region 14 and the diode region 16. In a plan view, the first electrode layer 50 is positioned to overlap both the IGBT region 14 and the diode region 16.

[0017] The insulating layer 40 may contain at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al2O3). The insulating layer 40 may consist of a single insulating layer or may be a laminated structure of multiple insulating layers made of different materials.

[0018] The first electrode layer 50 may contain at least one of the following: aluminum (Al), copper (Cu), Al alloy, Cu alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The first electrode layer 50 may consist of a single metal layer or a laminated structure of multiple metal layers made of different materials. In one example, the first electrode layer 50 is composed of a single metal layer. In another example, the first electrode layer 50 is composed of aluminum silicon copper (AlSiCu) as an Al alloy. In another example, the first electrode layer 50 may have a thickness of 3 μm or more and 6 μm or less. The thickness of the first electrode layer 50 can be arbitrarily changed.

[0019] The first electrode layer 50 includes a first pad electrode 50E and a second pad electrode 50G. The first pad electrode 50E and the second pad electrode 50G are spaced apart from each other in a plan view. The first pad electrode 50E is positioned to overlap both the IGBT region 14 and the diode region 16 in a plan view. In one example, as shown in Figure 1, the first pad electrode 50E is provided to overlap the entire area of ​​both the IGBT region 14 and the diode region 16. The first pad electrode 50E is provided on most of the first surface 20S of the semiconductor layer 20.

[0020] The second pad electrode 50G is located in a region different from both the IGBT region 14 and the diode region 16 in a plan view. The second pad electrode 50G is located at a position separated from the first pad electrode 50E in the X-axis direction.

[0021] The RC-IGBT 10 may further include a gate wiring 52 electrically connected to the second pad electrode 50G. The gate wiring 52 is located above the semiconductor layer 20 and below the first pad electrode 50E. The gate wiring 52 may be insulated from both the semiconductor layer 20 and the first pad electrode 50E by an insulating layer 40. Thus, the gate wiring 52 can be said to be embedded in the insulating layer 40. In one example, the gate wiring 52 may be made of conductive polysilicon. In another example, the gate wiring 52 may be made of another metallic material.

[0022] The gate wiring 52 may include multiple gate fingers 54. In one example, as shown in Figure 1, the gate wiring 52 includes five gate fingers 54. Each gate finger 54 may extend in the X-axis direction. The number of gate fingers 54 may be set appropriately according to the desired characteristics of the RC-IGBT 10.

[0023] As shown in Figure 4, the RC-IGBT 10 includes a second electrode layer 56 provided on the second surface 20R of the semiconductor layer 20. The second electrode layer 56 may contain at least one of Ti, Ni, palladium (Pd), gold (Au), silver (Ag), and aluminum (Al).

[0024] As shown in Figure 2, the RC-IGBT 10 may include multiple IGBT regions 14 and multiple diode regions 16. The multiple IGBT regions 14 and multiple diode regions 16 can be arranged in an array without overlapping each other in a plan view. The multiple IGBT regions 14 may be spaced apart from each other in the X-axis and Y-axis directions. The multiple diode regions 16 may be spaced apart from each other in the X-axis and Y-axis directions. In one example, as shown in Figure 2, both the IGBT regions 14 and the diode regions 16 are rectangular in shape in a plan view.

[0025] Each IGBT region 14 may be located in close proximity to some of the diode regions 16. In one example, some of the IGBT regions 14 may be arranged alternately with some of the diode regions 16, one at a time, in the X-axis direction. That is, in a plan view, the IGBT regions 14 and diode regions 16 are arranged side by side in the X-axis direction. In one example, as shown in Figure 2, four IGBT regions 14 and three diode regions 16 are arranged alternately, one at a time, in the X-axis direction. A sub-region 18 containing such alternately arranged IGBT regions 14 and diode regions 16 may be located in close proximity to the gate finger 54 shown in Figure 1. The RC-IGBT 10 may include multiple sub-regions 18 that are spaced apart from each other. In one example, as shown in Figure 2, the multiple sub-regions 18 are arranged spaced apart from each other in the Y-axis direction. The multiple sub-regions 18 and multiple gate fingers 54 may be arranged alternately, one at a time, in the Y-axis direction. The number of IGBT regions 14 and diode regions 16 included in the sub-region 18, and the number of sub-regions 18, are set appropriately according to the desired characteristics of the RC-IGBT 10.

[0026] In one example, as shown in Figure 2, the area of ​​the IGBT region 14 in a plan view is larger than the area of ​​the diode region 16 in a plan view. The areas of the IGBT region 14 and the diode region 16 in a plan view may be changed as appropriate. In one example, the areas of the IGBT region 14 and the diode region 16 in a plan view may be set as appropriate according to the desired characteristics of the RC-IGBT 10.

[0027] (Detailed structure of part of the RC-IGBT) Refer to Figures 3 to 5 to describe some of the detailed planar and cross-sectional structures of the RC-IGBT10.

[0028] As shown in Figure 3, the RC-IGBT 10 includes a plurality of first trench structures 60A and a plurality of second trench structures 60B provided in the semiconductor layer 20. In one example, as shown in Figure 3, each trench structure 60A, 60B extends in the Y-axis direction in a plan view.

[0029] The first trench structures 60A are arranged spaced apart from each other in the X-axis direction. In one example, the pitch of multiple first trench structures 60A in the X-axis direction may be constant. The second trench structures 60B are arranged spaced apart from each other in the X-axis direction. In one example, the pitch of multiple second trench structures 60B in the X-axis direction may be constant. The pitch of multiple second trench structures 60B in the X-axis direction may be the same as the pitch of multiple first trench structures 60A in the X-axis direction. Also, the distance between adjacent first trench structures 60A and second trench structures 60B in the X-axis direction is the same as the pitch of the first trench structures 60A. Note that the pitches of the first trench structures 60A and second trench structures 60B can be arbitrarily changed.

[0030] The first trench structure 60A includes a first trench 62A. Multiple first trenches 62A are arranged spaced apart in the X-axis direction, corresponding to the arrangement of the first trench structure 60A. The first trenches 62A are located in the IGBT region 14 of the semiconductor layer 20. The second trench structure 60B includes a second trench 62B. Multiple second trenches 62B are arranged spaced apart in the X-axis direction, corresponding to the arrangement of the second trench structure 60B. The second trenches 62B are located in the diode region 16 of the semiconductor layer 20.

[0031] The first trench structure 60A and the second trench structure 60B include a first embedded electrode 64A located in the first trench 62A and a second embedded electrode 64B located in the second trench 62B. The first trench 62A and the second trench 62B are respectively filled with the first embedded electrode 64A and the second embedded electrode 64B via a first insulating layer 401. Each embedded electrode 64A, 64B can be electrically connected to a first pad electrode 50E or a second pad electrode 50G. Both embedded electrodes 64A, 64B may be made of conductive polysilicon. The first insulating layer 401 may be part of the insulating layer 40 shown in Figure 1.

[0032] (Contact structure) RC-IGBT10 includes a mesa 70 located between two adjacent trenches in the X direction. Specifically, the mesa 70 is located between two adjacent first trenches 62A in the X direction, between two adjacent second trenches 62B in the X direction, and between the adjacent first trenches 62A and second trenches 62B in the X direction.

[0033] The RC-IGBT10 further includes a plurality of contact plugs 74, each embedded in a plurality of contact holes 72. Each contact hole 72 is located in the center of each mesa 70 in the X-axis direction. Each contact plug 74 may include a first metal portion 741 and a second metal portion 742. Each contact hole 72 may be filled with a first metal portion 741 extending along the side and bottom walls of each contact hole 72 and a second metal portion 742 provided adjacent to the first metal portion 741.

[0034] The first metal part 741 may contain at least one of Ti, TiN, Ta, and TaN. The second metal part 742 may contain at least one of W, Mo, Ni, Al, Cu, Al alloy, and Cu alloy.

[0035] (Cross-sectional structure of RC-IGBT) As shown in Figure 4, the RC-IGBT 10 includes a first region 22 containing n-type impurities and a second region 24 containing p-type impurities. Therefore, the first region 22 is an n-type region, and the second region 24 is a p-type region. The second region 24 is provided on top of the first region 22. The first region 22 includes the semiconductor substrate and a part of the epitaxial layer of the semiconductor layer 20. The second region 24 includes the epitaxial layer of the semiconductor layer 20. In this disclosure, p-type is also referred to as the first conductivity type, and n-type as the second conductivity type. The p-type impurities may be, for example, boron (B) or aluminum (Al). The n-type impurities may be, for example, phosphorus (P) or arsenic (As).

[0036] (IGBT area) As shown in Figure 4, in the IGBT region 14, the semiconductor layer 20 includes a p-type collector region 26C adjacent to the first region 22. The collector region 26C includes a portion of the second surface 20R of the semiconductor layer 20. That is, the collector region 26C is the portion of the semiconductor layer 20 that is closer to the second surface 20R than to the first surface 20S, and is located in the IGBT region 14. In one example, the p-type impurity concentration in the collector region 26C is 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 18 cm -3 The following is possible:

[0037] In the IGBT region 14, the first region 22 may include a buffer region 28 located on the collector region 26C, a drift region 30 located on the buffer region 28, and a carrier store region 32 located on the drift region 30. The carrier store region 32 is sandwiched between the base region 34 and the drift region 30 in the Z-axis direction. The drift region 30 and the carrier store region 32 are regions of the second conductivity type.

[0038] In one example, the n-type impurity concentration in buffer region 28 is 1 × 10⁻⁶. 15 cm-3 or more 1×10 17 cm -3 The following can be achieved. For example, the n-type impurity concentration in the drift region 30 is 1 × 10⁻⁶.13 cm -3 or more and 1×10 15 cm -3 or less. The drift region 30 has a lower n-type impurity concentration than the buffer region 28.

[0039] The carrier store region 32 is located in the mesa 70. The carrier store region 32 has a higher n-type impurity concentration than the drift region 30. In one example, the n-type impurity concentration of the carrier store region 32 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less.

[0040] The provision of the carrier store region 32 suppresses the discharge of carriers (holes) to the base region 34, thereby promoting the accumulation of carriers (holes) in a region directly below the first trench structure 60A in the IGBT region 14. Therefore, the carrier store region 32 can reduce the on-resistance and on-voltage of the IGBT.

[0041] In the IGBT region 14, the second region 24 may include the base region 34. The base region 34 is located in the mesa 70. The base region 34 is a region of a first conductivity type. In one example, the p-type impurity concentration of the base region 34 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less.

[0042] In the IGBT region 14, the semiconductor layer 20 may further include an n-type emitter region 36 located on the base region 34. The emitter region 36 includes a part of the first surface 20S of the semiconductor layer 20. That is, in the IGBT region 14, the emitter region 36 is provided in a surface layer portion of the semiconductor layer 20 closer to the first surface 20S. In other words, the emitter region 36 is provided in a surface layer portion of the mesa 70.

[0043] In one example, the n-type impurity concentration of the emitter region 36 is 1×1019 cm -3 The above 1 x 10 20 cm -3 The following is possible. Preferably, the carrier store region 32 has a lower n-type impurity concentration than the emitter region 36.

[0044] The first trench 62A is recessed from the first surface 20S of the semiconductor layer 20. The first trench 62A extends from the first surface 20S of the semiconductor layer 20 toward the second surface 20R. The first trench 62A extends so as to penetrate the base region 34. Therefore, the first trench 62A also penetrates the emitter region 36. The first trench 62A penetrates the carrier store region 32 and reaches the drift region 30.

[0045] Multiple first trenches 62A may be arranged at intervals of 0.1 μm to 10 μm in the X-axis direction. Each first trench 62A may have a width (dimension in the X-axis direction) of 0.5 μm to 3 μm. Each first trench 62A may have a depth (dimension in the Z-axis direction) of 1 μm to 10 μm.

[0046] The first trench 62A includes a side wall 631 and a bottom wall 632. The side wall 631 extends from the first surface 20S of the semiconductor layer 20 toward the bottom wall 632. The bottom wall 632 constitutes the end of the first trench 62A on the side of the second surface 20R of the semiconductor layer 20. In one example, as shown in Figure 4, the side wall 631 extends along the Z-axis direction. The bottom wall 632 is curved and convex toward the second surface 20R of the semiconductor layer 20.

[0047] The side wall 631 may have a tapered shape, with the opening width (dimension in the X-axis direction) narrowing from the first surface 20S of the semiconductor layer 20 towards the bottom wall 632. The bottom wall 632 may be a flat surface perpendicular to the Z-axis direction. In this case, the corner portion between the bottom wall 632 and the side wall 631 may be curved, convex outwards.

[0048] The first insulating layer 401 is provided within the first trench 62A. The first insulating layer 401 may be formed, for example, by thermal oxidation. In this case, the boundary portion of the semiconductor layer 20 with the outer surface of the first insulating layer 401 may constitute the side wall 631 and bottom wall 632 of the first trench 62A. The first insulating layer 401 may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0049] The first insulating layer 401 is provided in layers on the side walls 631 and bottom wall 632 of the first trench 62A. As a result, a recess space is formed within the first trench 62A by the first insulating layer 401. The first embedded electrode 64A is embedded in this recess space. Therefore, it can be said that the first embedded electrode 64A is embedded within the first insulating layer 401 within the first trench 62A.

[0050] The first embedded electrode 64A is configured to have a gate potential applied to it. That is, the first embedded electrode 64A may be electrically connected to the second pad electrode 50G (see Figure 1). In one example, although not shown, the first embedded electrode 64A is connected to a gate contact at one end of the first trench 62A in the Y-axis direction. The gate contact is connected to a gate finger 54 (see Figure 1). Thus, the first embedded electrode 64A is electrically connected to the second pad electrode 50G via the gate contact and the gate finger 54. The upper end surface of the first embedded electrode 64A may be located closer to the bottom wall 632 of the first trench 62A than the first surface 20S of the semiconductor layer 20.

[0051] Here, the second electrode layer 56 is electrically connected to the collector region 26C in the IGBT region 14. The second electrode layer 56 forms ohmic contact with the collector region 26C. Thus, the structure between the first pad electrode 50E and the second electrode layer 56 in the IGBT region 14 constitutes an IGBT. The first pad electrode 50E constitutes the emitter of the IGBT, and the second electrode layer 56 constitutes the collector of the IGBT. The first pad electrode 50E can be called the emitter pad electrode of the RC-IGBT 10. The second pad electrode 50G can be called the gate pad electrode of the RC-IGBT 10. The second electrode layer 56 can be called the collector pad electrode of the RC-IGBT 10.

[0052] (Diode region 16) In the diode region 16, the semiconductor layer 20 includes an n-type cathode region 26K adjacent to the first region 22, instead of the collector region 26C of the IGBT region 14. The cathode region 26K includes a portion of the second surface 20R of the semiconductor layer 20. That is, the cathode region 26K is the portion of the semiconductor layer 20 that is closer to the second surface 20R than to the first surface 20S, and is located in the diode region 16. The cathode region 26K is adjacent to the collector region 26C in a direction perpendicular to the Z-axis direction. In Figure 4, the cathode region 26K is adjacent to the collector region 26C in the X-axis direction. In one example, the n-type impurity concentration in the cathode region 26K is 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 20 cm -3 The following is possible: In other words, the n-type impurity concentration in the cathode region 26K may be higher than the p-type impurity concentration in the collector region 26C.

[0053] In the diode region 16, the second region 24 may include a p-type anode region 38 instead of the base region 34 of the IGBT region 14. The diode region 16 does not have a carrier store region 32. Therefore, the anode region 38 is located on the drift region 30. Also, the diode region 16 does not have an emitter region 36. Therefore, the anode region 38 includes a part of the first surface 20S of the semiconductor layer 20. That is, in the diode region 16, the anode region 38 is located in the surface layer of the semiconductor layer 20 closer to the first surface 20S. In one example, the p-type impurity concentration of the anode region 38 is 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 18 cm -3 The following are possible: In one example, the p-type impurity concentration in the anode region 38 may be equal to the p-type impurity concentration in the base region 34. In another example, the p-type impurity concentration in the anode region 38 may be different from the p-type impurity concentration in the base region 34.

[0054] The second trench 62B is recessed from the first surface 20S of the semiconductor layer 20. The second trench 62B extends from the first surface 20S of the semiconductor layer 20 toward the second surface 20R. The second trench 62B penetrates the anode region 38. The second trench 62B reaches the drift region 30.

[0055] Multiple second trenches 62B may be arranged at intervals of 0.1 μm to 10 μm in the X-axis direction. Each second trench 62B may have a width (dimension in the X-axis direction) of 0.5 μm to 3 μm. Each second trench 62B may have a depth (dimension in the Z-axis direction) of 1 μm to 10 μm.

[0056] The second trench 62B includes a side wall 633 and a bottom wall 634. The side wall 633 extends from the first surface 20S of the semiconductor layer 20 toward the bottom wall 634. The bottom wall 634 constitutes the end of the second trench 62B on the side of the second surface 20R of the semiconductor layer 20. In one example, as shown in Figure 4, the side wall 633 extends along the Z-axis direction. The bottom wall 634 is curved and convex toward the second surface 20R of the semiconductor layer 20.

[0057] The side wall 633 may have a tapered shape, with the opening width (dimension in the X-axis direction) narrowing from the first surface 20S of the semiconductor layer 20 towards the bottom wall 634. The bottom wall 634 may be a flat surface perpendicular to the Z-axis direction. In this case, the corner portion between the bottom wall 634 and the side wall 633 may be curved, convex outwards.

[0058] In other words, the shape of the second trench 62B may be the same as the shape of the first trench 62A. For example, the size of the second trench 62B may be the same as that of the first trench 62A. The pitch of the second trench 62B is the same as that of the first trench 62A. However, the size of the second trench 62B may be different from that of the first trench 62A. Also, the pitch of the second trench 62B may be different from that of the first trench 62A.

[0059] The first insulating layer 401 is provided within the second trench 62B. If the first insulating layer 401 is formed, for example, by thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the first insulating layer 401 may constitute the side wall 633 and bottom wall 634 of the second trench 62B. The first insulating layer 401 may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the first insulating layer 401 may be made of the same material as the insulating layer 40.

[0060] The first insulating layer 401 is provided in layers on the side walls 633 and bottom wall 634 of the second trench 62B. As a result, a recess space is formed within the second trench 62B by the first insulating layer 401. The second embedded electrode 64B is embedded in this recess space. Therefore, it can be said that the second embedded electrode 64B is embedded within the first insulating layer 401 within the second trench 62B.

[0061] The second embedded electrode 64B is configured to be supplied with a gate potential or emitter potential. In other words, the second embedded electrode 64B may be electrically connected to the first pad electrode 50E or the second pad electrode 50G (see Figure 1).

[0062] In one example, the second embedded electrode 64B can be connected to a gate contact at one end of the second trench 62B in the Y-axis direction. The gate contact is connected to a gate finger 54 (see Figure 1). This allows the second embedded electrode 64B to be electrically connected to the second pad electrode 50G via the gate contact and gate finger 54. In another example, the second embedded electrode 64B can be connected to an emitter contact. The emitter contact is connected to the first pad electrode 50E. This allows the second embedded electrode 64B to be electrically connected to the first pad electrode 50E via the emitter contact.

[0063] The upper end surface of the second embedded electrode 64B may be located closer to the bottom wall 634 of the second trench 62B than the first surface 20S of the semiconductor layer 20. The second embedded electrode 64B is made of, for example, conductive polysilicon. Thus, the second embedded electrode 64B may be made of the same material as the first embedded electrode 64A.

[0064] The second electrode layer 56 is electrically connected to the cathode region 26K in the diode region 16. The second electrode layer 56 forms ohmic contact with the cathode region 26K. In this way, the structure between the first pad electrode 50E and the second electrode layer 56 in the diode region 16 constitutes a diode in the diode region 16. For this reason, it can be said that the first pad electrode 50E constitutes the anode of the diode and the second electrode layer 56 constitutes the cathode of the diode. Thus, the emitter of the IGBT and the anode of the diode are electrically connected by the first pad electrode 50E. The collector of the IGBT and the cathode of the diode are electrically connected by the second electrode layer 56.

[0065] (Contact structure) As shown in Figure 4, a second insulating layer 402 is positioned on the first surface 20S of the semiconductor layer 20. The second insulating layer 402 includes an upper surface 40S and a lower surface 40R. The lower surface 40R of the insulating layer 40 faces the first surface 20S of the semiconductor layer 20 in the Z-axis direction. The second insulating layer 402 is located on the first insulating layer 401. The second insulating layer 402 covers the upper surfaces of the first embedded electrode 64A and the second embedded electrode 64B. The second insulating layer 402 may be a part of the insulating layer 40 shown in Figure 1.

[0066] The contact hole 72 has an opening in the upper surface 40S of the second insulating layer 402. The contact hole 72 penetrates the second insulating layer 402 in the Z-axis direction. The contact hole 72 extends in the Z-axis direction toward the second surface 20R of the semiconductor layer 20. The contact hole 72 reaches the second region 24 of the semiconductor layer 20. The contact hole 72 includes side walls and bottom walls.

[0067] In one example, as shown in Figure 4, the side wall of the contact hole 72 extends along the Z-axis direction. The bottom wall of the contact hole 72 is a flat surface perpendicular to the Z-axis direction. The corner portion between the bottom wall and the side wall of the contact hole 72 may be curved and convex outward. The side wall of the contact hole 72 may also have a tapered shape, with the opening width (dimension in the X-axis direction) narrowing from the upper surface 40S of the insulating layer 40 towards the bottom wall. Furthermore, the bottom wall of the contact hole 72 may be curved and convex toward the second surface 20R of the semiconductor layer 20.

[0068] The contact plug 74 is embedded in the contact hole 72. The contact plug 74 is in contact with the emitter region 36 in the IGBT region 14. The contact plug 74 penetrates the emitter region 36 in the IGBT region 14 and reaches the base region 34. The contact plug 74 is in contact with the anode region 38 in the cathode region 26K.

[0069] The upper surfaces of the multiple contact plugs 74 are covered by a first pad electrode 50E formed on the insulating layer 40. The multiple contact plugs 74 are electrically connected to the first pad electrode 50E.

[0070] (Island area) As shown in Figure 4, the RC-IGBT 10 includes an island region 80 located in the semiconductor layer 20 between the bottom wall 632 of the first trench 62A and the collector region 26C in the Z-axis direction. The island region 80 is located in the IGBT region 14. Multiple island regions 80 are arranged, one for each of the first trenches 62A, spaced apart in the X-axis direction. Each island region 80 is spaced apart from each other in the X-axis direction. Each island region 80 is in contact with the bottom wall 632 of each first trench 62A. In the Y direction, the island region 80 may be in contact with the entire bottom wall 632 of the first trench 62A. The island region 80 is located in the first region 22 of the semiconductor layer 20. The island region 80 is located in the drift region 30.

[0071] Island region 80 is the region of the first conductivity type. In one example, the impurity concentration in island region 80 is 1 × 10⁻⁶ 12 cm -3 The above 1 x 10 13 cm -3 The following applies: The impurity concentration in the island region 80 may be lower than the p-type impurity concentration in the collector region 26C. The impurity concentration in the island region 80 may be lower than the n-type impurity concentration in the buffer region 28. The impurity concentration in the island region 80 may be lower than the n-type impurity concentration in the drift region 30. The impurity concentration in the island region 80 may be lower than the p-type impurity concentration in the base region 34.

[0072] As shown in Figure 5, when viewed from the Y-axis direction, the island region 80 as a whole has an elongated shape that is long in the Z-axis direction. The island region 80 includes an upper end portion 82, a constant width portion 84, a widened portion 86, and a tapered portion 88. The upper end portion 82 is located closer to the first surface 20S of the semiconductor layer 20 in the Z-direction. The upper end portion 82 is in contact with the first trench 62A. More specifically, the upper end portion 82 is in contact with the bottom wall 632 of the first trench 62A. On the other hand, the upper end portion 82 is not in contact with the side wall 631 of the first trench 62A. The constant width portion 84 is located closer to the second surface 20R (see Figure 4) of the semiconductor layer 20 than the upper end portion 82. The width of the constant width portion 84 is constant regardless of the Z-axis direction, i.e., the dimension in the X-axis direction. The widened portion 86 is located closer to the second surface 20R of the semiconductor layer 20 than the constant width portion 84. The width of the widened portion 86 increases towards the second surface 20R of the semiconductor layer 20. The tapered portion 88 is located closer to the second surface 20R of the semiconductor layer 20 than the widened portion 86. The width of the tapered portion 88 decreases towards the second surface 20R of the semiconductor layer 20.

[0073] The tapered portion 88 constitutes the bottom of the island region 80; that is, the bottom of the island region 80 is curved, convex downwards, due to the tapered portion 88. The widening portion 86 makes the curvature of the bottom of the island region 80 (tapered portion 88) smaller than the curvature of a circle whose diameter is the dimension D2 in the X-axis direction of the island region 80 (constant width portion 84). Since dimension D2 is larger than the width of the first trench 62A, the curvature of the bottom of the island region 80 is smaller than the curvature of the bottom wall 632 of the first trench 62A. Furthermore, the bottom of the island region 80 is curved, with the X-axis direction being the major axis and the Z-axis direction being the minor axis, forming an ellipse shape. In addition, the island region 80 is curved, convex outwards in the X-axis direction, due to the widening portion 86 and the tapered portion 88. The dimension of the tapered portion 88 in the X-axis direction is larger than the dimension of the constant width portion 84 in the X-axis direction due to the widening portion 86.

[0074] In a plan view, each island region 80 is positioned differently from the contact plug 74. More specifically, the widened portion 86 of each island region 80 is positioned differently from the contact plug 74 in a plan view.

[0075] The Z-axis dimension D1 of each island region 80 is greater than the X-axis dimension D2 of each island region 80. Dimension D1 may be more than twice the dimension D2. Dimension D1 may be less than or equal to three times the dimension D2. Note that dimension D2 is the X-axis dimension of the fixed-width portion 84 within each island region 80. The Z-axis dimension D1 of each island region 80 is greater than the X-axis distance D3 between two adjacent island regions 80 in the X-axis direction. Note that distance D3 is the X-axis distance between the fixed-width portions 84 of two adjacent island regions 80 in the X-axis direction. The Z-axis dimension D1 of each island region 80 is smaller than the Z-axis dimension of the first trench 62A.

[0076] The X-axis dimension D2 of each island region 80 is smaller than the X-axis dimension D4 of the mesa 70. The X-axis dimension D2 of each island region 80 is smaller than the distance D3 between two adjacent island regions 80 in the X-axis direction. The X-axis dimension D2 of each island region 80 is larger than the X-axis dimension of the first trench 62A. In each island region 80, the Z-axis dimension D5 of the constant-width section 84 is larger than the Z-axis dimension D6 of the tapered section 88. Since dimension D2 is larger than the width of the first trench 62A, the distance D3 is smaller than dimension D4. On the other hand, distance D3 is larger than half of dimension D4. In one example, distance D3 may be greater than or equal to two-thirds of dimension D4.

[0077] As shown in Figure 4, in the Z-axis direction, a drift region 30 of the second conductivity type is located between the bottom wall 634 of the second trench 62B and the cathode region 26K. The drift region 30 is in contact with the bottom wall 634 of the second trench 62B. In other words, there is no island region 80 located between the bottom wall 634 of the second trench 62B and the cathode region 26K.

[0078] (RC-IGBT manufacturing method) Next, an example of a manufacturing method for RC-IGBT10 will be described. Figures 7 to 13 are schematic cross-sectional views showing an exemplary manufacturing process for RC-IGBT10. For ease of understanding, in Figures 7 to 13, components similar to those in Figure 5 are denoted by the same reference numerals.

[0079] As shown in Figure 7, the manufacturing process of the RC-IGBT 10 includes forming trenches 62 in the semiconductor layer 20. In this process, a mask (not shown) is formed on the first surface 20S of the semiconductor layer 20, exposing the areas where multiple trenches 62 should be formed and covering the other areas. Then, etching (e.g., dry etching, wet etching, etc.) is performed using the mask (e.g., hard mask, resist mask, etc.) to form multiple trenches 62. Furthermore, by forming multiple trenches 62, mesas 70 are formed between the multiple trenches 62.

[0080] Furthermore, the manufacturing process for RC-IGBT10 includes forming a first insulating layer 401. The first insulating layer 401 is formed on the first surface 20S of the semiconductor layer 20 and within a plurality of trenches 62. The first insulating layer 401 is formed along the side and bottom walls of the trenches 62 without completely filling the trenches 62. The first insulating layer 401 can be formed, for example, by chemical vapor deposition (CVD), oxidation treatment (e.g., thermal oxidation), etc. The first insulating layer 401 may contain at least one of SiO2, SiN, SiON, and Al2O3.

[0081] Figure 8 is a schematic cross-sectional view showing the manufacturing process following Figure 7. As shown in Figure 8, the manufacturing process for RC-IGBT 10 includes forming an n-type region 100. The n-type region 100 is a region that later constitutes the carrier store region 32 (see Figure 5). The n-type region 100 is formed on the surface of the mesa 70. The n-type region 100 can be formed by ion implantation of n-type impurities. The n-type impurities may be, for example, phosphorus (P) or arsenic (As). In the formation of the n-type region 100, heat treatment may be performed after ion implantation. The formation of the n-type region 100 forms a drift region 30. The n-type region 100 is located on the drift region 30. The impurity concentration in the n-type region 100 is higher than the impurity concentration in the drift region 30. Although not shown in the illustration, by forming the n-type region 100 after the formation of the trench 62, n-type impurities are also implanted from the side walls and bottom walls of the trench 62. Therefore, in the drift region 30, the concentration of n-type impurities near the side walls and bottom walls of the trench 62 increases.

[0082] Figure 9 is a schematic cross-sectional view showing the manufacturing process following Figure 8. As shown in Figure 9, the manufacturing process for RC-IGBT 10 includes forming an island region 80. The island region 80 can be formed by ion implantation of p-type impurities. The island region 80 can be formed by implanting p-type impurities from the bottom wall of the trench 62. The p-type impurities may be, for example, B, Al, etc. Ion implantation to form the island region 80 may be performed multiple times with varying ion implantation energies. In the formation of the island region 80, heat treatment may be performed after ion implantation. In addition, a p-type region 102 may be formed along with the formation of the island region 80. The p-type region 102 is the region that will later form the base region 34. The p-type region 102 is formed on the surface of the mesa 70.

[0083] In the drift region 30, the concentration of n-type impurities near the side and bottom walls of the trench 62 increases with the formation of the n-type region 100. As a result, the island region 80 tends to take on a shape that extends more in the Z-axis direction than in the X-axis direction. In other words, by forming the island region 80 after the formation of the n-type region 100, the island region 80 tends to take on a vertically elongated shape.

[0084] Figure 10 is a schematic cross-sectional view showing the manufacturing process following Figure 9. As shown in Figure 10, the manufacturing process for the RC-IGBT 10 includes forming an embedded electrode 64. In one example, the embedded electrode 64 is formed by forming a metal layer on a first insulating layer 401 and then removing a portion of it. In one example, the metal layer may be formed by a CVD method. The embedded electrode 64 may contain, for example, polysilicon.

[0085] Figure 11 is a schematic cross-sectional view showing the manufacturing process following Figure 10. As shown in Figure 11, the manufacturing process for RC-IGBT 10 includes forming a base region 34. The base region 34 can be formed by ion implantation of p-type impurities. In the formation of the base region 34, heat treatment may be performed after ion implantation. Ion implantation of p-type impurities and heat treatment expand the p-type region 102 (see Figure 10) to form the base region 34. Along with the formation of the base region 34, a carrier store region 32 is formed. The base region 34 is located on the carrier store region 32.

[0086] Figure 12 is a schematic cross-sectional view showing the manufacturing process following Figure 11. As shown in Figure 12, the manufacturing process for the RC-IGBT 10 includes forming the emitter region 36. The emitter region 36 can be formed by ion implantation of n-type impurities. The emitter region 36 is formed on the surface of the mesa 70. The emitter region 36 is located on the base region 34.

[0087] Figure 13 is a schematic cross-sectional view showing the manufacturing process following Figure 12. As shown in Figure 13, the manufacturing process for the RC-IGBT 10 includes forming a second insulating layer 402 and forming a contact plug 74. The second insulating layer 402 is formed on the first insulating layer 401 and on the embedded electrode 64. In one example, the second insulating layer 402 may be formed by a CVD method. The second insulating layer 402 may contain at least one of SiO2, SiN, SiON, and Al2O3.

[0088] Forming the contact plug 74 may include forming the contact hole 72. In one example, the contact hole 72 can be formed by forming a mask that covers the area other than the area where the contact hole 72 is to be formed, and then selectively removing the first insulating layer 401, the second insulating layer 402, and the semiconductor layer 20 by etching. The formation of the contact hole 72 may be carried out by multiple etching steps. Also, different masks may be used between the multiple etching steps as needed.

[0089] The contact plug 74 may include forming a second metal portion 742 and a first metal portion 741 on the second insulating layer 402 and within the contact hole 72. In one example, the second metal portion 742 is formed along the side and bottom walls of the contact hole 72 without completely filling the contact hole 72. In one example, the second metal portion 742 may be formed by at least one of sputtering and CVD. The second metal portion 742 may contain at least one of Ti, TiN, Ta, and TaN. The first metal portion 741 can be formed by removing the unnecessary portion after it has been formed on the second metal portion 742. At this time, the second metal portion 742 may also be removed to expose the second insulating layer 402. The first metal portion 741 may be formed by at least one of sputtering, CVD, and plating. The first metal portion 741 may also contain at least one of W, Mo, Ni, Al, Cu, Al alloy, and Cu alloy.

[0090] (Operation of the first embodiment) The operation of the RC-IGBT10 in this embodiment will be described below with reference to Figure 6. Figure 6 is a graph showing the relationship between the collector-emitter voltage and leakage current in the IGBT region 14 of the RC-IGBT 10 when no gate voltage is applied. In Figure 6, the relationship between the collector-emitter voltage and leakage current of the RC-IGBT 10 is shown by a solid line. As a comparative example, Figure 6 also shows the relationship between the collector-emitter voltage and leakage current when the RC-IGBT does not have an island region 80, shown by a dashed line. In Figure 6, the horizontal axis represents the collector-emitter voltage, and the vertical axis represents the leakage current. The leakage current is displayed on a logarithmic scale.

[0091] In the comparative example RC-IGBT, which does not have an island region 80, electric field concentration is likely to occur near the bottom wall of the first trench. When breakdown (hereinafter referred to as "BV breakdown") occurs due to this electric field concentration, the leakage current increases.

[0092] In the RC-IGBT10 of the first embodiment, an island region 80 is provided on the bottom wall 632 of the first trench 62A. This reduces the concentration of the electric field near the bottom wall 632 of the first trench 62A, making BV breakdown less likely to occur.

[0093] As shown in Figure 6, the inventors of the present invention performed simulations for the RC-IGBT10 of the first embodiment and the RC-IGBT of the comparative example, to determine the voltage at which BV breakdown occurs (breakdown voltage (BV)) by increasing the collector-emitter voltage in the IGBT region 14 of the RC-IGBT10 when no gate voltage is applied.

[0094] As shown by the solid and dashed lines in Figure 6, in an RC-IGBT, when the collector-emitter voltage exceeds a certain value, BV breakdown occurs and the leakage current increases sharply. The dielectric breakdown voltage BV1 of RC-IGBT10 is greater than the dielectric breakdown voltage BV2 of the comparative example RC-IGBT. In other words, the withstand voltage of the IGBT region 14 of RC-IGBT10 is improved by the island region 80.

[0095] In an RC-IGBT, it is desirable that breakdown is less likely to occur in the IGBT region 14 than in the diode region 16. That is, it is desirable that the dielectric breakdown voltage of the IGBT region 14 be higher than the dielectric breakdown voltage of the diode region 16.

[0096] In the RC-IGBT10 of this embodiment, an island region 80 is located in the IGBT region 14, while an island region 80 is not located in the diode region 16. Therefore, the dielectric breakdown voltage of the IGBT region 14 tends to be higher than the dielectric breakdown voltage of the diode region 16.

[0097] (Effects of the first embodiment) The RC-IGBT10 of this embodiment has the following advantages. (1-1) The RC-IGBT 10 comprises a semiconductor layer 20 including a first surface 20S and a second surface 20R opposite to the first surface 20S, and an IGBT region 14 and a diode region 16 arranged side by side in a first direction (X-axis direction) in a plan view of the semiconductor layer 20 viewed from the thickness direction (Z-axis direction). The RC-IGBT 10 also comprises a collector region 26C of a first conductivity type located in the IGBT region 14, which is a portion of the semiconductor layer 20 closer to the second surface 20R than the first surface 20S, and a cathode region 26K of a second conductivity type located in the diode region 16, which is a portion of the semiconductor layer 20 closer to the second surface 20R than the first surface 20S. Furthermore, the RC-IGBT10 includes a first trench 62A located in the IGBT region 14 of the semiconductor layer 20 and recessed from the first surface 20S, a second trench 62B located in the diode region 16 of the semiconductor layer 20 and recessed from the first surface 20S, and a first conductivity type island region 80 which is a portion of the semiconductor layer 20 located between the bottom wall 632 of the first trench 62A and the collector region 26C in the thickness direction. With this configuration, the breakdown voltage of the IGBT region 14 can be improved by the island region 80. Therefore, the electrical characteristics of the RC-IGBT10 can be improved.

[0098] (1-2) The semiconductor layer 20 includes a drift region of second conductivity type located between the bottom wall 634 of the second trench 62B and the cathode region 26K in the thickness direction. The drift region 30 is in contact with the bottom wall 634 of the second trench 62B. With this configuration, the diode region 16 does not have an island region 80. Therefore, the dielectric breakdown voltage of the IGBT region 14 tends to be higher than the dielectric breakdown voltage of the diode region 16. Therefore, the IGBT region 14 is easily protected.

[0099] (1-3) The dimension D1 of the island region 80 in the Z-axis direction is larger than the dimension D2 of the island region 80 in the X-axis direction. The larger the area of ​​the island region 80 as viewed from the Y-axis direction, the easier it is to mitigate electric field concentration. On the other hand, if the dimension D2 of the island region 80 in the X-axis direction becomes excessively large, the current flow path becomes narrower. With this configuration, the island region 80 has a vertically elongated shape in which the dimension D1 in the Z-axis direction is larger than the dimension D2 in the X-axis direction. Because the island region 80 has a vertically elongated shape, the area as viewed from the Y-axis direction is increased while suppressing the dimension in the X-axis direction from becoming excessively large. Therefore, the current flow path can be secured, and the electrical characteristics of the RC-IGBT10 can be improved.

[0100] (1-4) Multiple first trenches 62A are arranged spaced apart in the X-axis direction, and one island region 80 is arranged for each of the first trenches 62A, spaced apart in the X-axis direction. With this configuration, a current flow path can be secured between adjacent island regions 80 in the X-axis direction, thereby improving the electrical characteristics of the RC-IGBT 10.

[0101] (1-5) The Z-axis dimension D1 of each island region 80 is greater than the X-axis dimension D4 between two adjacent island regions 80 in the X-axis direction. With this configuration, the island regions 80 tend to have a vertically elongated shape. Therefore, a current flow path can be secured, and the electrical characteristics of the RC-IGBT 10 can be improved.

[0102] (1-6) The semiconductor layer 20 includes mesas 70 located between adjacent first trenches 62A in the X-axis direction. The X-axis dimension D2 of each island region 80 is smaller than the X-axis dimension D4 of the mesa 70. This configuration prevents the X-axis dimension D2 of the island regions 80 from becoming excessively large. Therefore, a current flow path can be secured, and the electrical characteristics of the RC-IGBT 10 can be improved.

[0103] (1-7) The dimension D2 in the X-axis direction of each island region 80 is smaller than the distance D3 between two adjacent island regions 80 in the X-axis direction. This configuration prevents the dimension D2 in the X-axis direction of the island regions 80 from becoming excessively large. Therefore, a current flow path can be secured, and the electrical characteristics of the RC-IGBT 10 can be improved.

[0104] (1-8) The island region 80 includes a portion that widens as it approaches the second surface 20R. With this configuration, the area of ​​the island region 80 viewed from the Y-axis direction increases, which helps to mitigate electric field concentration. Therefore, the breakdown voltage of the IGBT region 14 can be increased.

[0105] (1-9) The island region 80 includes a constant-width section 84 whose width is constant regardless of the Z-axis direction, and a tapered section 88 which is located closer to the second surface 20R than the constant-width section 84 and whose width narrows as it approaches the second surface 20R. With this configuration, the island region 80 tends to have a vertically elongated shape. Therefore, a current flow path can be secured, and the electrical characteristics of the RC-IGBT 10 can be improved. In addition, the bottom of the island region 80 is curved and convex downwards due to the tapered section 88. As a result, electric field concentration is more easily mitigated compared to the case where the bottom of the island region 80 is flat. Therefore, the withstand voltage of the IGBT region 14 can be increased.

[0106] (1-10) The Z-axis dimension of the constant-width portion 84 is larger than the Z-axis dimension of the tapered portion 88. With this configuration, the island region 80 tends to have a vertically elongated shape. Therefore, a current flow path can be secured, and the electrical characteristics of the RC-IGBT 10 can be improved.

[0107] <Second Embodiment> Referring to Figure 14, the RC-IGBT10 of the second embodiment will be described. The RC-IGBT10 of the second embodiment differs from the RC-IGBT10 of the first embodiment in the cross-sectional shape of the island region 80. In the following, components common to the first embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0108] In the second embodiment, the island region 80 consists of multiple unit regions 801 connected in the Z-axis direction. In this embodiment, three unit regions 801 are connected in the Z-axis direction. The number of unit regions 801 connected in the Z-axis direction is not limited to three. The number of unit regions 801 may be two or more than three.

[0109] In this embodiment, each unit region 801 is circular. The unit region 801 may also be oval in shape. Furthermore, the island region 80 may consist of multiple unit regions 801 of different sizes and shapes connected in the Z-axis direction.

[0110] (Effects of the second embodiment) The RC-IGBT10 of the second embodiment has the following advantages in addition to (1-1) to (1-8).

[0111] (2-1) The island region 80 consists of multiple unit regions 801 connected in the Z-axis direction. With this configuration, the island region 80 tends to have a vertically elongated shape. Therefore, the electrical characteristics of the RC-IGBT 10 can be improved.

[0112] <Third Embodiment> Referring to Figure 15, the RC-IGBT10 of the third embodiment will be described. The RC-IGBT10 of the third embodiment differs from the RC-IGBT10 of the first embodiment in the arrangement and cross-sectional shape of the island region 80. In the following, components common to the first embodiment will be denoted by the same reference numerals, and their descriptions may be omitted.

[0113] In the third embodiment, the island region 80 consists of multiple unit regions 801 connected in the Z-axis direction. That is, the island region 80 of the third embodiment has the same shape as the island region 80 of the second embodiment. The shape of the island region 80 is not limited to the above. The island region 80 may have the same shape as the first embodiment, or it may have a different shape from the first and second embodiments.

[0114] In the third embodiment, the island region 80 is separated from the bottom wall 632 of the first trench 62A. More specifically, the drift region 30 is located between the upper end 82 of the island region 80 and the bottom wall 632 of the first trench 62A. The distance D7 in the Z-axis direction between the bottom wall 632 of the first trench 62A and the island region 80 is greater than the X-axis dimension D4 of the mesa 70.

[0115] (Effects of the third embodiment) The RC-IGBT10 of the third embodiment has the following advantages in addition to (1-1) to (1-8) and (2-1).

[0116] (3-1) The island region 80 is separated from the bottom wall 632 of the first trench 62A in the Z-axis direction. With this configuration, the region where electric field concentration is mitigated tends to be larger. Therefore, the breakdown voltage of the IGBT region 14 tends to be improved.

[0117] (3-2) The distance D7 in the Z-axis direction between the bottom wall 632 of the first trench 62A and the island region 80 is greater than the dimension D4 in the X-axis direction of the mesa 70. With this configuration, the pressure resistance of the IGBT region 14 can be increased by increasing the distance D7 in the Z-axis direction between the bottom wall 632 of the first trench 62A and the island region 80.

[0118] [Example of changes] Each of the above embodiments can be implemented with the following modifications. Each of the above embodiments and the following modifications can be implemented individually or in combination with each other to the extent that they do not contradict each other technically.

[0119] As shown in Figure 16, the RC-IGBT 10 may include a boundary region 15 located between the IGBT region 14 and the diode region 16 in the X-axis direction. In one example, the boundary region 15 can be a region that includes third trenches 62C located on both sides in the X-axis direction with respect to a boundary line L that extends the boundary between the collector region 26C and the cathode region 26K in the Z-axis direction. In another example, although not shown, the boundary region 15 can be a region that includes adjacent mesa 70 in the X-axis direction, one mesa 70 with an emitter region 36 and one mesa 70 without an emitter region 36, and three third trenches 62C where the two mesa 70 are adjacent.

[0120] In the example shown in Figure 16, an island region 80 is positioned between the bottom wall of the third trench 62C and the collector region 26C or the cathode region 26K. Note that the presence or absence of the island region 80 in the boundary region 15 can be determined as appropriate. In other words, the island region 80 does not necessarily have to be located in the boundary region 15.

[0121] The island region 80 may be selectively provided for a plurality of first trenches 62A. That is, the island region 80 may be positioned between the bottom wall 632 of some of the first trenches 62A and the collector region 26C in the Z-axis direction, and the island region 80 may not be positioned between the bottom wall 632 of some of the first trenches 62A and the collector region 26C in the Z-axis direction. The island region 80 should be positioned such that the dielectric breakdown voltage of the IGBT region 14 of the RC-IGBT 10 is higher than the dielectric breakdown voltage of the diode region 16.

[0122] The island regions 80 may be provided intermittently in the Y-axis direction. That is, there may be parts in the Y-axis direction where island regions 80 are provided and parts where island regions 80 are not provided. In other words, multiple island regions 80 may be spaced apart in the Y-axis direction. In this way, the island regions 80 should be arranged such that the dielectric breakdown voltage of the IGBT region 14 of the RC-IGBT 10 is higher than the dielectric breakdown voltage of the diode region 16.

[0123] As shown in Figure 17, the RC-IGBT 10 may include a second island region 81 when the island region 80 is designated as the first island region 80. The second island region 81 may be located between the bottom wall 634 of the second trench 62B and the cathode region 26K. The second island region 81 may be a region of the first conductivity type.

[0124] The impurity concentration in the second island region 81 may be lower than that in the first island region 80. In this case, the dielectric breakdown voltage of the entire RC-IGBT 10 can be increased while keeping the dielectric breakdown voltage of the IGBT region 14 higher than that of the diode region 16. Therefore, the electrical characteristics of the RC-IGBT 10 can be improved.

[0125] The second island region 81 may be smaller overall than the first island region 80. That is, the dimensions of the second island region 81 in the Z-axis direction and the X-axis direction may be smaller than the dimensions of the first island region 80 in the Z-axis direction and the X-axis direction, respectively. This can suppress the narrowing of the current path in the diode region 16. Therefore, it can suppress the on-resistance of the diode region 16 from becoming high.

[0126] Furthermore, the second island region 81 may be selectively provided for a plurality of second trenches 62B. That is, the second island region 81 may be positioned between the bottom wall 634 of some of the second trenches 62B and the cathode region 26K in the Z-axis direction, while the second island region 81 may not be positioned between the bottom wall 634 and the cathode region 26K in some of the second trenches 62B in the Z-axis direction.

[0127] The semiconductor layer 20 may include a base contact region. The base contact region is located at the bottom wall of the contact hole 72. In other words, the base contact region is exposed at the bottom wall of the contact hole 72. Therefore, the contact plug 74 is in contact with the base contact region at the bottom wall of the contact hole 72. The p-type impurity concentration in the base contact region may be higher than the p-type impurity concentration in the base region 34. In one example, the p-type impurity concentration in the base contact region is 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 20 cm -3 The following is possible:

[0128] The shape of the island region 80 can be changed as appropriate. The Z-axis dimension D1 of the island region 80 may be smaller than the X-axis dimension D2 of the island region 80. Also, the Z-axis dimension D1 of the island region 80 may be smaller than the X-axis distance D3 between two adjacent island regions 80 in the X-axis direction. Also, the X-axis dimension D2 of each island region 80 may be larger than the X-axis dimension D4 of the mesa 70. Also, the X-axis dimension D2 of each island region 80 may be larger than the X-axis distance D3 between two adjacent island regions 80 in the X-axis direction.

[0129] The island region 80 does not necessarily include a portion that widens towards the second surface 20R of the semiconductor layer 20. Furthermore, the island region 80 does not necessarily include a constant-width portion 84 whose width is constant regardless of the Z-axis direction, nor a tapered portion 88 that is located closer to the second surface 20R than the constant-width portion 84 and whose width narrows towards the second surface 20R. The Z-axis dimension of the constant-width portion 84 may be smaller than the Z-axis dimension of the tapered portion 88.

[0130] The impurity concentration in island region 80 can be changed as appropriate. The impurity concentration in island region 80 may be higher than the p-type impurity concentration in collector region 26C. The impurity concentration in island region 80 may be higher than the n-type impurity concentration in buffer region 28. The impurity concentration in island region 80 may be higher than the n-type impurity concentration in drift region 30. The impurity concentration in island region 80 may be higher than the p-type impurity concentration in base region 34.

[0131] The n-type impurity concentration in the carrier store region 32 may be lower than the n-type impurity concentration in the drift region 30. The semiconductor layer 20 does not necessarily have to include the carrier store region 32. The Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 3) are not limited to the Z-axis direction "up" and "down" being vertical. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0132] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0133] [Note 1] A semiconductor layer (20) including a first surface (20S) and a second surface (20R) opposite to the first surface (20S), In a plan view of the semiconductor layer (20) as seen from the thickness direction (Z), the IGBT region (14) and the diode region (16) are arranged side by side in the first direction (X), The portion of the semiconductor layer (20) that is closer to the second surface (20R) than to the first surface (20S), and which includes a collector region (26C) of the first conductivity type arranged in the IGBT region (14), The portion of the semiconductor layer (20) that is closer to the second surface (20R) than to the first surface (20S) is a cathode region (26K) of the second conductivity type arranged in the diode region (16), A first trench (62A) is located in the IGBT region (14) of the semiconductor layer (20) and is recessed from the first surface (20S), A second trench (62B) is provided in the diode region (16) of the semiconductor layer (20) and is recessed from the first surface (20S), Of the semiconductor layer (20), the island region (80) of the first conductivity type is the portion located between the bottom wall (632) of the first trench (62A) and the collector region (26C) in the thickness direction (Z), Equipped with, RC-IGBT(10).

[0134] [Note 2] The semiconductor layer (20) includes a second conductivity type drift region (30) located between the bottom wall (634) of the second trench (62B) and the cathode region (26K) in the thickness direction (Z), The drift region (30) is in contact with the bottom wall (634) of the second trench (62B). RC-IGBT(10) as described in Appendix 1.

[0135] [Note 3] When the aforementioned island region (80) is referred to as the first island region (80), In the thickness direction (Z), the second island region (81) of the first conductivity type is provided, which is located between the bottom wall (634) of the second trench (62B) and the cathode region (26K). The impurity concentration in the second island region (81) is lower than the impurity concentration in the first island region (80). RC-IGBT(10) as described in Appendix 1.

[0136] [Note 4] The dimension (D1) of the island region (80) in the thickness direction (Z) is greater than the dimension (D2) of the island region (80) in the first direction (X). RC-IGBT(10) as described in any one of the appendices 1 to 3.

[0137] [Note 5] Multiple first trenches (62A) are arranged spaced apart in the first direction (X), The island regions (80) are arranged one for each of the first trenches (62A), separated in the first direction (X). RC-IGBT(10) as described in any one of the appendices 1 to 4.

[0138] [Note 6] The dimension (D1) in the thickness direction (Z) of each island region (80) is greater than the distance (D3) in the first direction (X) between two adjacent island regions (80) in the first direction (X). RC-IGBT(10) as described in Appendix 5.

[0139] [Note 7] The semiconductor layer (20) includes a mesa (70) located between adjacent first trenches (62A) in the first direction (X), The dimension (D2) of each island region (80) in the first direction (X) is smaller than the dimension (D4) of the mesa (70) in the first direction (X). RC-IGBT(10) as described in Appendix 5.

[0140] [Note 8] The dimension (D2) of each island region (80) in the first direction (X) is smaller than the distance (D3) between two adjacent island regions (80) in the first direction (X). RC-IGBT(10) as described in Appendix 5.

[0141] [Note 9] The island region (80) includes a portion that widens towards the second surface (20R) side. RC-IGBT(10) as described in any one of the appendices 1 to 8.

[0142] [Note 10] The aforementioned island region (80) is A constant width portion (84) whose width is constant regardless of the thickness direction (Z), A tapered portion (88) is located closer to the second surface (20R) than the constant width portion (84), and its width narrows as it approaches the second surface (20R), including, RC-IGBT(10) as described in Appendix 9.

[0143] [Note 11] The dimension of the constant width portion (84) in the thickness direction (Z) (D5) is greater than the dimension of the tapered portion (88) in the thickness direction (Z) (D6). RC-IGBT(10) as described in Appendix 10.

[0144] [Note 12] The aforementioned island region (80) consists of multiple unit regions (801) connected in the thickness direction (Z). RC-IGBT(10) as described in any one of the appendices 1 to 8.

[0145] [Note 13] The island region (80) is separated from the bottom wall (632) of the first trench (62A) in the thickness direction (Z). RC-IGBT(10) as described in any one of the appendices 1 to 8.

[0146] [Note 14] Multiple first trenches (62A) are arranged spaced apart in the first direction (X), The semiconductor layer (20) includes a mesa (70) located between adjacent first trenches (62A) in the first direction (X), The distance (D7) between the bottom wall (632) of the first trench (62A) and the island region (80) in the thickness direction (Z) is greater than the dimension (D4) of the mesa (70) in the first direction (X). RC-IGBT(10) as described in Appendix 13.

[0147] [Note 15] The impurity concentration in the aforementioned island region (80) is 1 × 10⁻⁶ 12 cm -3 The above 1 x 10 13 cm -3 The following is: RC-IGBT(10) as described in any one of the appendices 1 to 14.

[0148] [Note 16] The aforementioned semiconductor layer (20) is The second conductivity type drift region (30) and A second conductive carrier store region (32) located on the drift region (30), A base region (34) of the first conductive type located on the carrier store region (32), Includes, The impurity concentration in the carrier store region (32) is higher than the impurity concentration in the drift region (30). RC-IGBT(10) as described in any one of the appendices 1 to 15.

[0149] [Note 17] In the first direction (X), the boundary region (15) located between the IGBT region (14) and the diode region (16) is included. RC-IGBT(10) as described in any one of the appendices 1 to 16.

[0150] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0151] 10…RC-IGBT 11…Cell area 12...Outer area 14…IGBT area 16…Diode region 18…Sub-region 20... Semiconductor layer 20S…Side 1 20R…Page 2 22...First area 24…Second area 26C...Collector area 26K... Cathode region 28... Buffer area 30... Drift area 32…Carrier Store Area 34…Base area 36…Emitter region 38... Anode region 40…Insulating layer 40S…Top surface 40R…Bottom surface 401...First insulating layer 402...Second insulating layer 50...first electrode layer 50E…First pad electrode 50G…Second pad electrode 52…Gate wiring 54... Gate Finger 56…Second electrode layer 60A…First trench structure 60B...Second trench structure 62A... Trench 1 62B...Trench 2 631,633…Side wall 632,634…Bottom wall 64A...First implanted electrode 64B...Second implanted electrode 70… Mesa 72… Contact holes 74... Contact plug 741...First metal part 742…Second metal part 80…Island area 82...Top end 84…Constant width part 86... Widening section 88...Tapered section 100...n type region 102...p-type region

Claims

1. A semiconductor layer including a first surface and a second surface opposite to the first surface, In a plan view of the semiconductor layer as seen from the thickness direction, the IGBT region and the diode region are arranged side by side in the first direction, A portion of the semiconductor layer that is closer to the second surface than the first surface, comprising a collector region of a first conductivity type arranged in the IGBT region, A portion of the semiconductor layer that is closer to the second surface than the first surface, comprising a cathode region of a second conductivity type arranged in the diode region, A first trench is provided in the IGBT region of the semiconductor layer, recessed from the first surface, A second trench is provided in the diode region of the semiconductor layer, and is recessed from the first surface. Of the semiconductor layer, the island region of the first conductivity type is the portion located between the bottom wall of the first trench and the collector region in the thickness direction, Equipped with, RC-IGBT.

2. The semiconductor layer includes a drift region of a second conductivity type located between the bottom wall of the second trench and the cathode region in the thickness direction. The drift region is in contact with the bottom wall of the second trench. The RC-IGBT according to claim 1.

3. When the aforementioned island region is designated as the first island region, The semiconductor layer includes a second island region of a first conductivity type, which is positioned between the bottom wall of the second trench and the cathode region in the thickness direction. The impurity concentration in the previous second island region is lower than that in the previous first island region. The RC-IGBT according to claim 1.

4. The dimension of the island region in the thickness direction is greater than the dimension of the island region in the first direction. The RC-IGBT according to claim 1.

5. Multiple first trenches are arranged spaced apart in the first direction. The island regions are arranged one for each of the first trenches, separated from each other in the first direction. The RC-IGBT according to claim 1.

6. The dimension in the thickness direction of each island region is greater than the distance in the first direction between two adjacent island regions. The RC-IGBT according to claim 5.

7. The semiconductor layer includes a mesa located between adjacent first trenches in the first direction. The dimension of each island region in the first direction is smaller than the dimension of the mesa in the first direction. The RC-IGBT according to claim 5.

8. The dimension of each island region in the first direction is smaller than the distance between two adjacent island regions in the first direction. The RC-IGBT according to claim 5.

9. The island region includes a portion that widens towards the second surface side. The RC-IGBT according to claim 1.

10. The aforementioned island region is A constant width portion regardless of the thickness direction, A tapered portion located closer to the second surface than the aforementioned fixed-width portion, and whose width narrows towards the second surface, including, The RC-IGBT according to claim 9.

11. The dimension in the thickness direction of the constant width portion is larger than the dimension in the thickness direction of the tapered portion. The RC-IGBT according to claim 10.

12. The aforementioned island region consists of multiple unit regions connected in the thickness direction. The RC-IGBT according to claim 1.

13. The island region is separated from the bottom wall of the first trench in the thickness direction. The RC-IGBT according to claim 1.

14. Multiple first trenches are arranged spaced apart in the first direction. The semiconductor layer includes a mesa located between adjacent first trenches in the first direction. The distance in the thickness direction between the bottom wall of the first trench and the island region is greater than the dimension of the mesa in the first direction. The RC-IGBT according to claim 13.

15. The impurity concentration in the aforementioned island region is 1 × 10 １２ cm －３ The above 1 x 10 １３ cm －３ The following is: The RC-IGBT according to claim 1.

16. The aforementioned semiconductor layer is The drift region of the second conductivity type, A second conductive carrier store region located on the drift region, A base region of the first conductive type located on the carrier store region, Includes, The impurity concentration in the carrier store region is higher than the impurity concentration in the drift region. The RC-IGBT according to claim 1.

17. In the first direction, including a boundary region located between the IGBT region and the diode region, The RC-IGBT according to claim 1.

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