Contact via formation method

Abstract

This invention provides a contact via formation method that contributes to the miniaturization of semiconductor patterning processes. [Solution] The contact via formation method includes steps (A) to (C). Step (A) involves preparing a substrate having a metal layer in which a first recess is formed. Step (B) involves depositing a first insulator around the metal layer including the first recess. Step (C) involves anisotropically etching the metal layer using a mask material on the metal layer as a mask to form contact vias in the second recess formed around the first insulator.

Description

Technical Field

[0001] The present disclosure relates to a contact via forming method.

Background Art

[0002] For example, Patent Document 1 proposes a method for manufacturing a semiconductor device capable of simultaneously forming a wiring pattern and a via pattern using anisotropic etching.

[0003] For example, Patent Document 2 proposes a method for manufacturing a semiconductor device capable of forming a void having a desired shape and size in the semiconductor device.

Prior Art Literature

Patent Literature

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problem to be Solved by the Invention

[0005] The present disclosure provides a contact via forming method that contributes to miniaturization of semiconductor patterning processes.

Means for Solving the Problem

[0006] A contact via forming method provided in one aspect of the present disclosure includes steps (A) to (C). In step (A), a substrate having a metal layer in which a first recess is formed is prepared. In step (B), a first insulator is deposited around the metal layer including the first recess. In step (C), the metal layer is anisotropically etched using a mask material on the metal layer as a mask, and a contact via is formed in a second recess formed around the first insulator.

Effects of the Invention

[0007] According to this disclosure, a contact via formation method that contributes to the miniaturization of semiconductor patterning processes can be provided. [Brief explanation of the drawing]

[0008] [Figure 1A] Figure 1A is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1B] Figure 1B is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1C] Figure 1C is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1D] Figure 1D is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1E] Figure 1E is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1F] Figure 1F is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1G] Figure 1G is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 1H] Figure 1H is a cross-sectional perspective view showing an example of a contact via formation method according to one embodiment. [Figure 2] Figure 2 is a flowchart showing a first embodiment of a contact via formation method according to one embodiment. [Figure 3] Figure 3 is a flowchart of the first example of the first embodiment, following the flowchart in Figure 2. [Figure 4A] Figure 4A shows the pattern formation process according to the first embodiment. [Figure 4B] Figure 4B shows the pattern formation process according to the first embodiment. [Figure 4C] Figure 4C shows the pattern formation process according to the first embodiment. [Figure 4D]FIG. 4D is a diagram showing the pattern forming step according to the first embodiment. [Figure 4E] FIG. 4E is a diagram showing the pattern forming step according to the first embodiment. [Figure 4F] FIG. 4F is a diagram showing the pattern forming step according to the first embodiment. [Figure 4G] FIG. 4G is a diagram showing the pattern forming step according to the first example of the first embodiment. [Figure 4H] FIG. 4H is a diagram showing the pattern forming step according to the first example of the first embodiment. [Figure 5] FIG. 5 is a flowchart showing a second example of the first embodiment continuing from the flowchart of FIG. 2. [Figure 6A] FIG. 6A is a diagram showing the pattern forming step according to the first embodiment. [Figure 6B] FIG. 6B is a diagram showing the pattern forming step according to the first embodiment. [Figure 6C] FIG. 6C is a diagram showing the pattern forming step according to the first embodiment. [Figure 6D] FIG. 6D is a diagram showing the pattern forming step according to the first embodiment. [Figure 6E] FIG. 6E is a diagram showing the pattern forming step according to the second example of the first embodiment. [Figure 6F] FIG. 6F is a diagram showing the pattern forming step according to the second example of the first embodiment. [Figure 7] FIG. 7 is a flowchart showing a second embodiment of a contact via forming method according to an embodiment. [Figure 8A] FIG. 8A is a diagram showing the pattern forming step according to the second embodiment. [Figure 8B] FIG. 8B is a diagram showing the pattern forming step according to the second embodiment. [Figure 8C] FIG. 8C is a diagram showing the pattern forming step according to the second embodiment. [Figure 8D] FIG. 8D is a diagram showing the pattern forming step according to the second embodiment. [Figure 8E]Figure 8E shows the pattern formation process according to the second embodiment. [Figure 8F] Figure 8F shows the pattern formation process according to the second embodiment. [Figure 8G] Figure 8G shows the pattern formation process according to the second embodiment. [Figure 8H] Figure 8H shows the pattern formation process according to the second embodiment. [Modes for carrying out the invention]

[0009] An embodiment of the contact via formation method disclosed below will be described in detail with reference to the drawings. It should be noted that the contact via formation method disclosed in this embodiment is not limited, and the following embodiments can be appropriately combined within the scope of the disclosed configurations and processes without contradiction.

[0010] Furthermore, the figures referenced below are schematic for illustrative purposes only. Therefore, details may be omitted, and the dimensional ratios do not necessarily correspond to those of reality. Also, in the figures referenced below, the vertically upward direction is defined as the Z-axis direction for the sake of clarity.

[0011] Furthermore, the embodiments of the contact via formation method disclosed below are methods for forming contact vias on a substrate, and are performed by an apparatus that processes the substrate, such as film deposition using plasma, etching, and heat treatment, in a chamber. The apparatus is controlled by a control unit connected to the apparatus. The apparatus described below refers to any of a plurality of apparatuses, including a film deposition apparatus, an etching apparatus, and an annealing apparatus. Automatic transport of substrates between the plurality of apparatuses is possible in a vacuum atmosphere or an atmospheric atmosphere using a transport device.

[0012] <Overview of Contact Via Formation Method> The outline of a contact via formation method according to one embodiment of this disclosure will be described with reference to Figures 1A to 1H. Figures 1A to 1H are cross-sectional perspective views showing an example of a contact via formation method according to one embodiment.

[0013] In a contact via formation method according to one embodiment, as shown in Figure 1A, the apparatus performs the step of preparing a substrate W having a metal layer 101 on which a first recess U1 is formed in a chamber. The step shown in Figure 1A is an example of step (A). The metal layer 101 is formed on a base layer 100 including, for example, a barrier film and a seed film. The material of the base layer 100 is a film that can suppress the diffusion of the metal layer 101, and may be, for example, a SiCN film or a SiC film. The base layer 100 can be laminated on the substrate W by, for example, sputtering. The material of the metal layer 101 may be copper or ruthenium. The metal layer 101 can be formed by, for example, PVD or CVD. A first mask material 103 is formed on the metal layer 101. The first mask material 103 can be formed by a photolithography method capable of forming a fine pattern. For example, the pattern of the first mask material 103 corresponds to the internal wiring pattern of a semiconductor integrated circuit device, and the metal layer 101 can become a wiring layer.

[0014] A first recess U1 is formed in the metal layer 101 by anisotropic etching using the first mask material 103 on the metal layer 101 as a mask. One method of anisotropically etching the metal layer 101 is to irradiate it with oxygen ions in an organic compound gas atmosphere, for example, in an organic acid gas atmosphere, and etch the metal layer 101 anisotropically. Another method is to irradiate the metal layer 101 with oxygen ions to anisotropically oxidize the metal layer 101 and remove the anisotropically oxidized portion, but the method is not limited to these. The metal layer 101 is anisotropically etched until the underlying layer 100 is exposed. Here, the metal layer 101 has a line / space shape in which the first recess U1 is formed in a line shape, and may function as a lower layer wiring connected to upper layer wiring (not shown) by contact vias described later.

[0015] The metal layer 101 may have a lower metal layer 101a, an upper metal layer 101b, and an intermediate layer 102 between the lower metal layer 101a and the upper metal layer 101b. This allows the intermediate layer 102 to function as a stopper film during etching of the metal layer 101, enabling the removal of only the upper metal layer 101b while leaving the lower metal layer 101a intact. The material of the intermediate layer 102 can be any film that is selective to the upper metal layer 101b. However, the metal layer 101 does not necessarily have an intermediate layer 102.

[0016] Next, as shown in Figure 1B, the apparatus performs the step of forming a first air gap 110 in a part of the first recess U1. The step shown in Figure 1B is an example of step (D). The first air gap 110 is a void partitioned within the first recess U1 by the sealing film 111 formed during the formation of the first air gap 110 (described later), the side wall of the lower metal layer 101a, and the base layer 100. In the example in Figure 1B, the height of the first air gap 110 is approximately the same as the height of the lower metal layer 101a, but it is not limited to this and may be lower than the height of the lower metal layer 101a. The method for forming the first air gap 110 will be described later.

[0017] Next, as shown in Figure 1C, the apparatus performs a step of depositing a first insulator 104 around the metal layer 101 (lower metal layer 101a, upper metal layer 101b) containing the first recess U1 on the substrate W. The step shown in Figure 1C is an example of step (B). After depositing the first insulator 104, the apparatus may polish the upper part of the substrate W by CMP (Chemical Mechanical Polishing). In this step, the endpoint of chemical mechanical polishing can be detected by detecting a change in the current flowing to the motor of the CMP apparatus when the first mask material 103 is exposed. Alternatively, the endpoint of chemical mechanical polishing may be defined as the point when the upper metal layer 101b is exposed.

[0018] Next, as shown in Figure 1D, the apparatus performs the step of forming a second mask material 105 at the positions where contact vias (connection holes) are to be formed on the upper metal layer 101b. The formation of the second mask material 105 may be done using a photolithography method capable of forming fine patterns. For example, the pattern of the second mask material 105 corresponds to a via pattern that electrically connects the lower wiring (lower metal layer 101a) and the upper wiring (not shown) of the semiconductor integrated circuit device.

[0019] Next, as shown in Figure 1E, the apparatus uses the second mask material 105 as a mask to anisotropically etch the upper metal layer 101b until the intermediate layer 102 is exposed. This removes the upper metal layer 101b, leaving the upper metal layer 101b in the contact via V portion under the second mask material 105. In other words, the upper metal layer 101b around the first insulator 104, excluding the contact via V portion, is removed by anisotropic etching, forming the second recess U2. The process shown in Figure 1E is an example of process (C).

[0020] Next, as shown in Figure 1F, the apparatus performs the step of forming a second air gap 210 in the second recess U2. The step shown in Figure 1F is an example of step (E). The second air gap 210 is a void partitioned within the second recess U2 by the sealing film 211 formed during the formation of the second air gap 210 (described later), the side wall of the first insulator 104, and the intermediate layer 102. In the example in Figure 1F, the height of the second air gap 210 is lower than the height of the first insulator 104. The method for forming the second air gap 210 will be described later.

[0021] Next, as shown in Figure 1G, the apparatus performs a step of depositing a second insulator 204 around the first insulator 104, which includes the second recess U2 on the substrate W. In Figure 1G, the second insulator 204 is shown by a dashed line. The step shown in Figure 1G is an example of step (F).

[0022] Next, as shown in Figure 1H, the apparatus performs a process of grinding away the second insulator 204 by CMP treatment to open the contact vias V. The process shown in Figure 1H is an example of process (G). In this process, the endpoint of chemical mechanical polishing can be detected by detecting a change in the current flowing to the motor of the CMP apparatus when the first insulator 104 is exposed.

[0023] <Problems with conventional methods and the operation and effects of a contact via formation method according to one embodiment> When forming contact vias V on fine wiring, it is important that the contact vias V maintain a sufficient size and are positioned so as not to short-circuit with adjacent wiring in order to suppress the wiring resistance of the contact vias V themselves. Conventional contact via formation methods can be broadly classified into post-via methods and top-via methods.

[0024] In conventional post-via methods, after forming metal wiring with a metal layer, holes are drilled in the metal layer at the locations where contact vias will be formed, and metal is embedded in these holes to create the contact vias. This presents a problem in that misalignment can occur when drilling holes in the metal layer after the metal wiring has been formed. In particular, the narrower the pitch between wirings, the more likely misalignment of the holes is to occur. Furthermore, if the holes are misaligned and contact vias are formed in unintended locations, there is a risk of short circuits occurring due to contact between the contact vias and adjacent wiring.

[0025] In the conventional top via method, contact vias are formed simultaneously with the formation of metal wiring using a metal layer, so misalignment of the contact vias does not occur. However, when forming contact vias in the metal layer, the side walls of the contact via portion of the metal layer are etched, making it easy for the width of the contact vias to become narrower. This presents a problem in that the wiring resistance of the contact vias increases. Furthermore, in the CMP process after embedding the insulating film on the substrate W, if the endpoint of chemical mechanical polishing is defined as the point when the contact vias are exposed, it is difficult because the contact vias may break.

[0026] In contrast, in a contact via formation method according to one embodiment of the present disclosure, in the top via method, a first insulator 104 is embedded in the first recess U1 before the formation of the contact via V. As a result, the first insulator 104 protects the sidewall of the contact via V during its formation and prevents the sidewall of the contact via V from being shaved off by etching of the upper metal layer 101b. This maintains the shape of the upper metal layer 101b in the contact via V portion, prevents the width of the contact via V from becoming narrower, and reduces wiring resistance. This can contribute to the miniaturization of the semiconductor patterning process.

[0027] Furthermore, even if the second mask material 105 shown in Figure 1D is slightly misaligned from the position corresponding to the via portion on the upper metal layer 101b, as long as the misalignment is within the range on the first insulator 104 adjacent to the upper metal layer 101b, contact between the contact via V and the adjacent wiring will not occur. In contrast, the position of the via formation mask material in the conventional top via method is limited to the upper surface of the upper metal layer 101b. Therefore, in the contact via formation method according to one embodiment of the present disclosure, the degree of controllability of the positioning of the second mask material 105 can be increased compared to the positioning of the via formation mask material in the conventional top via method. In this respect as well, it can contribute to the miniaturization of the semiconductor patterning process.

[0028] In addition, according to a contact via formation method according to one embodiment of the present disclosure, at least one of a first air gap 110 or a second air gap 210 can be formed between the wirings of the metal layer 101 or around the contact via V. This makes it possible to reduce parasitic capacitance between wirings, etc. As a result, a microdevice structure with low power consumption and improved operating speed can be fabricated. However, an insulator may be embedded in place of the air gap between the wirings of the metal layer 101 or around the contact via V.

[0029] <First Example> A first embodiment of the contact via formation method according to the above-described embodiment will be explained with reference to Figures 2, 3, and 4A to 4H. Figure 2 is a flowchart of the first embodiment of the contact via formation method according to the above-described embodiment. Figure 3 is a flowchart of the first example of the first embodiment following the flowchart in Figure 2. Figures 4A to 4F show the pattern formation process according to the first embodiment. Figures 4G and 4H show the pattern formation process according to the first example of the first embodiment.

[0030] In step S1 of Figure 2, the apparatus prepares a substrate W having a metal layer 101 on which a first recess U1 is formed, inside the chamber. The process shown in step S1 is an example of process (A). In the example of Figure 4A, a substrate W is prepared inside the chamber in which a lower metal layer 101a, an intermediate layer 102, an upper metal layer 101b, and a first mask material 103 are stacked in this order on a base layer 100. The substrate W has a first recess U1 formed by anisotropic etching using the first mask material 103 as a mask.

[0031] Next, in step S2, the apparatus forms the first air gap 110. The process shown in step S2 is an example of process (D). The first air gap 110 is formed through the pattern forming process shown in Figures 4B(a) to 4B(d), which corresponds to processes (D-1) to (D-4).

[0032] Step (D-1) is a step of embedding a sacrificial film 112 around the lower metal layer 101a and the upper metal layer 101b, which include the first recess U1 on the substrate W, as shown in Figure 4B(a). The sacrificial film 112 is, for example, a polymer film and may be formed by CVD (Chemical Vapor Deposition). By causing a vapor deposition polymerization reaction of two types of raw material monomers, a polymer film sacrificial film 112 can be laminated on the surface of the substrate W. The two types of raw material monomers may be carbon-containing materials. When the two types of raw material monomers are isocyanate and amine, a polymer film of polyurea is laminated on the surface of the substrate W as the sacrificial film 112.

[0033] An example of the processing conditions for step (D-1) is shown below. In the following description, the temperature of the substrate W may also be the temperature of the stage on which the substrate W is placed. Chamber pressure: 0.5~20 Torr (66.7~2666 Pa) Raw material monomers: Isocyanates and amines Temperature of substrate W: 40~150℃

[0034] Step (D-2) is performed after step (D-1) and is a step in which a portion of the sacrificial film 112 of the first recess U1 is removed by anisotropic etching using plasma, as shown in Figure 4B(b). In the example in Figure 4B(b), the sacrificial film 112 of the first recess U1 is removed to a height below the intermediate layer 102. In the first embodiment, the apparatus creates the first air gap 110 between the wirings while controlling the height of the first air gap 110 to be below the intermediate layer 102, and forms the first insulator 104 on top of it. Specifically, the first air gap 110 is formed between the lower metal layers 101a, which are between the wirings below the intermediate layer 102. Therefore, the sacrificial film 112 is removed to a position slightly below the intermediate layer 102.

[0035] An example of processing conditions for step (D-2) is shown. A plasma of the processing gas is generated by high-frequency power applied in the chamber, and a portion of the sacrificial film 112 is removed by anisotropic etching using the plasma. Chamber pressure: 0.05~1.0 Torr (6.67~133 Pa) Processing gas: H2 / N2 gas Temperature of substrate W: 40~200℃

[0036] Step (D-3) is performed after step (D-2) and is a step of forming a sealing film 111 on the substrate W, as shown in Figure 4B(c). The sealing film 111 is laminated on the substrate W by, for example, ALD (Atomic Layer Deposition). In this embodiment, the sealing film 111 is a low-temperature oxide film (LTO) composed of SiO2, and is a less dense film compared to a thermal oxide film formed at high temperatures.

[0037] An example of the processing conditions for executing step (D-3) is shown below. Chamber pressure: 0.1~10 Torr (13.3~1333 Pa) Processing gas: Organic aminosilane gas Temperature of substrate W: 20~200℃

[0038] Step (D-4) is performed after step (D-3) and, as shown in Figure 4B(d), removes the sacrificial film 112 of the first recess U1 by annealing to form the first air gap 110. When the substrate W is heated, the sacrificial film 112 formed on the substrate W depolymerizes into two types of raw material monomers when it reaches the temperature at which a depolymerization reaction occurs. For example, if the sacrificial film 112 is polyurea, when the substrate W is heated to 300°C or higher, for example 350°C, the sacrificial film 112 depolymerizes into isocyanate and amine, which are raw material monomers. The isocyanate and amine generated by the depolymerization then pass through the sparse sealing film 111 and are released from between the sealing film 111. As a result, as shown in Figure 4B(d), for example, the first air gap 110 is formed, surrounded by the side wall of the lower metal layer 101a, the sealing film 111 and the base layer 100.

[0039] Next, in step S3, the apparatus deposits the first insulator 104 onto the substrate W. The process shown in step S3 is an example of the process in (B). As a result, as shown in Figure 4C, the first insulator 104 is embedded in the first recess U1 on the sealing film 111 and is also deposited on the surface of the substrate W.

[0040] Next, in step S4, the apparatus removes the first insulator 104 by CMP treatment. In this process, the endpoint of chemical mechanical polishing can be detected by detecting a change in the current flowing to the motor of the CMP apparatus when the first mask material 103 is exposed. As a result, the upper part of the substrate W is removed until the first mask material 103 is exposed, as shown in Figure 4D.

[0041] Next, in step S5, the apparatus performs the step of forming a second mask material 105 for via formation corresponding to the positions where contact vias are to be formed. The second mask material 105 may be formed on the upper metal layer 101b after the first mask material 103 has been removed, or it may be formed on the first mask material 103. In this example, the second mask material 105 is formed on the upper metal layer 101b. As a result, as shown in Figure 4E, the second mask material 105 is formed on the metal layer 101 in the areas where contact vias are to be formed.

[0042] Next, in step S6, the apparatus uses the second mask material 105 as a mask to anisotropically etch the metal layer 101 until the intermediate layer 102 is exposed. As a result, the upper metal layer 101b is removed, leaving the contact vias V under the second mask material 105. In other words, the upper metal layer 101b, excluding the contact via V portion around the first insulator 104, is anisotropically etched, and the contact vias V and the second recess U2 are formed, as shown in Figure 4F. The process shown in step S6 is an example of the process in (C).

[0043] <Example 1 of the First Embodiment> Next, a first example of the first embodiment of the contact via formation method following the flowchart in Figure 2 will be described with reference to Figures 3, 4G, and 4H. In step S9 of Figure 3, the apparatus deposits the second insulator 204 around the first insulator 104, which includes the second recess U2 on the substrate W. The process shown in step S9 is an example of process (F). As a result, as shown in Figure 4G, the second insulator 204 is embedded in the second recess U2 and also deposited on the surface of the substrate W.

[0044] Next, in step S10, the apparatus grinds the second insulator 204 by CMP treatment until the first insulator 104 is exposed, thereby opening the contact via V. In this process, the endpoint of chemical mechanical polishing can be detected by detecting a change in the current flowing to the motor of the CMP apparatus when the first insulator 104 is exposed. The process shown in step S10 is an example of process (G). As a result, the contact via V is opened, as shown in Figure 4H.

[0045] <Effects and Actions of the First Example of the First Embodiment> In the first example of the first embodiment, when opening the contact via V, the apparatus determines the endpoint of chemical mechanical polishing as the point when the first insulator 104 is exposed. If the endpoint of chemical mechanical polishing is determined as the point when the contact via V is exposed, it may be difficult to determine the endpoint of the CMP treatment, such as when the thin contact via V breaks off. Therefore, the apparatus uses the first insulator 104 as a stopper film for the CMP treatment to determine the endpoint. This makes it easier to control the endpoint detection of chemical mechanical polishing and improves control accuracy compared to when the contact via V is used as a stopper film.

[0046] Furthermore, in the first example of the first embodiment, the first air gap 110 is formed between the wiring below the intermediate layer 102, and the second insulator 204 is embedded in the second recess U2. This prevents the wiring on which the contact via V is formed from short-circuiting with other wiring.

[0047] <Second example of the first embodiment> Next, a second example of the first embodiment of the contact via formation method, following the flowchart in Figure 2, will be described with reference to Figures 5 and 6A to 6F. Figure 5 is a flowchart of the second example of the first embodiment, following the flowchart in Figure 2. When the step number in Figure 5 is the same as the step number in Figure 3, it indicates that the process of the step number in Figure 5 is the same as the process of the same step number in Figure 3. Therefore, step S9 in Figure 5 is the same process as step S9 in Figure 2. Figures 6A to 6D are diagrams showing the pattern formation process according to the first embodiment. Figures 6E and 6F are diagrams showing the pattern formation process according to the second example of the first embodiment. Figure 6A shows the state after the process of step S6 in Figure 2 has been executed, and contact vias V have been formed on the substrate W.

[0048] In step S7 of Figure 5, following step S6 of Figure 2, the apparatus deposits a first stopper film 301 on the substrate W, as shown in Figure 6B. The process shown in step S7 is an example of process (H). The first stopper film 301 is laminated on the substrate W by, for example, ALD or CVD. The first stopper film 301 is a film with high selectivity for the second insulator 204. The first stopper film 301 is a thin film, and there are no restrictions on the dielectric constant of its material; for example, it may be a SiCN film or a SiC film. The process in step S7 may be omitted.

[0049] Next, in step S8, the apparatus forms a second air gap. The process shown in step S8 is an example of process (E). The second air gap is formed by processes (E-1) to (E-4). Process (E-1) is the process of embedding a sacrificial film 212 on the first stopper film 301 on the substrate W, as shown in Figure 6C(a). If the process in step S7 is omitted, process (E-1) involves embedding the sacrificial film 212 in the second recess U2 formed in the first insulator 104 on the substrate W. The sacrificial film 212 is, for example, a polymer film and may be formed by the CVD method. By causing a vapor deposition polymerization reaction of two types of raw material monomers, a polymer film, the sacrificial film 212, can be laminated on the surface of the substrate W, as illustrated in Figure 6C(a). When the two types of raw material monomers are isocyanate and amine, a polymer film of polyurea is laminated on the surface of the substrate W as the sacrificial film 212. Note that the processing conditions for executing step (E-1) may be the same as the processing conditions for executing step (D-1).

[0050] Step (E-2) is performed after step (E-1) and is a step in which a portion of the sacrificial film 212 of the second recess U2 is removed by anisotropic etching using plasma, as shown in Figure 6C(b). In the example in Figure 6C(b), the sacrificial film 212 on the substrate W is removed, and about 1 / 3 of the sacrificial film 212 of the second recess U2 is removed. Note that the processing conditions for performing step (E-2) may be the same as the processing conditions for performing step (D-2).

[0051] Step (E-3) is performed after step (E-2) and is a step of forming a sealing film 211 on the substrate W, as shown in Figure 6C(c). The sealing film 211 is laminated on the substrate W by, for example, ALD. In this embodiment, the sealing film 211 is a low-temperature oxide film composed of SiO2, and is a less dense film than a thermal oxide film formed at high temperatures. The processing conditions for performing step (E-3) may be the same as the processing conditions for performing step (D-3).

[0052] Step (E-4) is performed after step (E-3) and, as shown in Figure 6C(d), removes the sacrificial film 212 of the second recess U2 by annealing to form the second air gap 210. When the substrate W is heated, the sacrificial film 212 formed on the substrate W depolymerizes into two types of raw material monomers when it reaches the temperature at which the depolymerization reaction occurs. The processing conditions for performing step (E-4) may be the same as the processing conditions for performing step (D-4). For example, if the sacrificial film 212 is polyurea, when the substrate W is heated to 300°C or higher, for example 350°C, the sacrificial film 212 depolymerizes into isocyanate and amine, which are raw material monomers. The isocyanate and amine generated by the depolymerization then pass through the sparse sealing film 211 and are released from between the sparse sealing film 211. As a result, a second air gap 210 is formed, which is an air gap surrounded by the side surface of the first insulator 104, the first stopper film 301, and the sealing film 211, as shown in Figure 6C(d), for example.

[0053] Next, in step S9, the apparatus deposits the second insulator 204 around the first insulator 104, which includes the second recess U2 on the substrate W. The process shown in step S9 is an example of process (F). As a result, as shown in Figure 6D, the second insulator 204 is embedded in the second recess U2 on the sealing film 211 and is also deposited on the surface of the substrate W.

[0054] Next, in step S10-1, the apparatus grinds away the second insulator 204 by CMP treatment until the first stopper film 301 is exposed. In other words, the endpoint of chemical mechanical polishing in this process can be detected by detecting a change in the current flowing to the motor of the CMP apparatus when the first stopper film 301 is exposed. The process shown in step S10-1 is an example of process (G). As a result, the second insulator 204 is removed until the first stopper film 301 is exposed, as shown in Figure 6E.

[0055] Finally, in step S10-1, the apparatus removes the first stopper film 301 on the surface of the substrate W by etching. As a result, the contact via V is opened, as shown in Figure 6F.

[0056] <Effects and Effects of the Second Example of the First Embodiment> In the second example of the first embodiment, when opening the contact via V, the apparatus determines the endpoint of chemical mechanical polishing as the point when the first stopper film 301 is exposed. The first stopper film 301 is a film that is more selective to the second insulator 204 than the first insulator 104. Therefore, by using the first stopper film 301 for endpoint detection of chemical mechanical polishing, the accuracy of the polishing endpoint of the second insulator 204 can be improved compared to when using the first insulator 104.

[0057] Furthermore, by forming a second air gap 210 around the contact via V in addition to the first air gap 110, it is possible to further reduce parasitic volume.

[0058] <Second Example> Next, a second embodiment of the contact via formation method according to one embodiment will be described with reference to Figures 7 and 8A to 8H. Figure 7 is a flowchart of the second embodiment of the contact via formation method according to one embodiment. When the step numbers in Figure 7 are the same as the step numbers in Figure 2, it indicates that the processing of the step number in Figure 7 is the same as the processing of the same step number in Figure 2. Therefore, steps S1 to S6 in Figure 7 are the same processing as steps S1 to S6 in Figure 2, and further include step S1-1. Figures 8A to 8H are diagrams showing the pattern formation process according to the second embodiment. Figure 8A is the same as Figure 4A.

[0059] In step S1 of Figure 7, the apparatus prepares a substrate W having a metal layer 101 on which the first recess U1 is formed, within the chamber. As a result, a substrate W having a metal layer 101 is prepared, as shown in Figure 8A.

[0060] Next, in step S1-1, the apparatus deposits a liner film 302. The liner film 302 is an example of a second stopper film. The liner film 302 may be a film with a low dielectric constant, such as an SiO2 film, in order to reduce parasitic capacitance.

[0061] Next, in step S2, the apparatus forms a first air gap. The process shown in step S2 is an example of process (D). The first air gap is formed by the processes (D-1) to (D-4) described above. As a result, the first air gap 110 is formed in the first recess U1 by the processes shown in Figures 8C(a) to 8C(d), which correspond to the processes (D-1) to (D-4).

[0062] Next, in steps S3 and S4, the apparatus performs embedding and CMP processing of the first insulator 104. As a result, the first mask material 103 is removed, and the upper metal layer 101b is exposed on the upper surface of the substrate W, as shown in Figures 8D and 8E, which correspond to steps S3 and S4.

[0063] Next, in step S5, the apparatus performs a process of forming a second mask material 105 to be used as a via mask at the position where contact vias are to be formed on the metal layer 101. Next, in step S6, the apparatus uses the second mask material 105 as a via mask to anisotropically etch the metal layer 101 until the intermediate layer 102 is exposed. As a result, contact vias V and a second recess U2 are formed, as shown in Figure 8F.

[0064] After the processing in step S5, the apparatus can perform the processes shown in Figure 3 or Figure 5. For example, if the apparatus performs steps S9 and S10 in Figure 3, in step S9, the apparatus deposits the second insulator 204 on the substrate W. As a result, the second insulator 204 is deposited on the substrate W, including the second recess U2, as shown in Figure 8G.

[0065] Next, in step S10, the apparatus grinds away the second insulator 204 by CMP treatment until the first insulator 104 is exposed. As a result, the contact via V is opened, as shown in Figure 6F.

[0066] <Effects and Actions of the Second Embodiment> In the second embodiment, the liner film 302 eliminates the need to control the height when forming the first air gap 110, thereby increasing the degree of controllability. In other words, when embedding the second insulator 204 after the formation of the contact via V shown in Figure 8F, the liner film 302 can block the intrusion of the second insulator 204 into the first air gap 110. For this reason, in the second embodiment, when creating the first air gap 110, height control of the first air gap 110 is unnecessary, and the height of the first air gap 110 can be freely controlled to a position higher than the intermediate layer 102.

[0067] It should be noted that the embodiments disclosed herein are illustrative and not restrictive in all respects. Indeed, the embodiments described above can be embodied in a variety of forms. Furthermore, the embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended claims.

[0068] Furthermore, the following additional information is disclosed regarding the above embodiments. <Note> (1) (A) A step of preparing a substrate having a metal layer in which a first recess is formed, (B) A step of depositing a first insulator around the metal layer including the first recess, (C) A step of anisotropically etching the metal layer using the mask material on the metal layer as a mask, and forming contact vias in the second recess formed around the first insulator, A method for forming contact vias, including the method described above. (2) (D) The contact via formation method according to (1), further comprising the step of forming a first air gap in the first recess before step (B). (3) In step (D) above, (D-1) A step of embedding a sacrificial film in the first recess, (D-2) A step of removing a portion of the sacrificial film in the first recess by etching, (D-3) A step of forming a sealing film on the substrate after the step in (D-2), (D-4) A method for forming a contact via according to (2), comprising the step of removing the sacrificial film of the first recess by annealing after the step of (D-3) to form the first air gap. (4) (E) A method for forming a contact via according to any one of (1) to (3), comprising the step of forming a second air gap in the second recess after the step of (C). (5) In step (E) above, (E-1) A step of embedding a sacrificial film in the second recess, (E-2) A step of removing a portion of the sacrificial film in the second recess by etching, (E-3) A step of forming a sealing film on the substrate after the step in (E-2), (E-4) A method for forming a contact via according to (4), comprising the step of removing the sacrificial film in the second recess by annealing after the step of (E-3) to form a second air gap. (6) (F) A step of depositing a second insulator around the first insulator including the second recess, (G) A method for forming a contact via according to any one of (1) to (5), comprising the step of removing the second insulator by CMP treatment to open the contact via. (7) (H) The process includes a step of forming a first stopper film on the substrate after step (C) and before step (F), The contact via formation method according to (6), wherein in step (G) above, the second insulator is scraped until the first stopper film is exposed. (8) (I) The step of forming a second stopper film on the substrate before step (B) is performed, The contact via formation method according to (6), wherein in step (D), a first air gap is formed in the first recess after step (I). [Explanation of symbols]

[0069] 100: Substrate layer, 101: Metal layer, 101a: Lower metal layer, 101b: Upper metal layer, 102: Intermediate layer, 103: First mask material, 104: First insulator, 105: Second mask material, 110: First air gap, 204: Second insulator, 210: Second air gap, U1: First recess, U2: Second recess, V: Contact via, W: Substrate

Claims

1. (A) A step of preparing a substrate having a metal layer in which a first recess is formed, (B) A step of depositing a first insulator around the metal layer including the first recess, (C) A step of anisotropically etching the metal layer using the mask material on the metal layer as a mask, and forming contact vias in the second recess formed around the first insulator, A method for forming contact vias, including the method described above.

2. (D) The contact via formation method according to claim 1, further comprising the step of forming a first air gap in the first recess before step (B).

3. In step (D) above, (D-1) A step of embedding a sacrificial film in the first recess, (D-2) A step of removing a portion of the sacrificial film in the first recess by etching, (D-3) A step of forming a sealing film on the substrate after the step in (D-2), (D-4) A method for forming a contact via according to claim 2, comprising the step of removing the sacrificial film in the first recess by annealing after the step of (D-3) to form the first air gap.

4. (E) The contact via formation method according to claim 1, further comprising the step of forming a second air gap in the second recess after the step of (C).

5. In step (E) above, (E-1) A step of embedding a sacrificial film in the second recess, (E-2) A step of removing a portion of the sacrificial film in the second recess by etching, (E-3) A step of forming a sealing film on the substrate after the step in (E-2), (E-4) A method for forming a contact via according to claim 4, comprising the step of removing the sacrificial film in the second recess by annealing after the step of (E-3) to form the second air gap.

6. (F) A step of depositing a second insulator around the first insulator including the second recess, (G) A method for forming a contact via according to any one of claims 1 to 5, comprising the step of removing the second insulator by CMP treatment to open the contact via.

7. (H) The process includes a step of forming a first stopper film on the substrate after step (C) and before step (F), The contact via formation method according to claim 6, wherein in step (G) above, the second insulator is scraped until the first stopper film is exposed.

8. (I) The process includes a step of forming a second stopper film on the substrate before step (B), The contact via formation method according to claim 6, wherein in step (D), a first air gap is formed in the first recess after step (I).

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