Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To improve the crystallinity of the channel layer. [Solution] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar includes a first semiconductor layer extending within the laminate in the stacking direction, a second semiconductor layer disposed above the first semiconductor layer, and a third semiconductor layer interposed between the first and second semiconductor layers, and the second semiconductor layer contains at least one additive of carbon, nitrogen, oxygen, and fluorine.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor memory devices and methods for manufacturing semiconductor memory devices. [Background technology]

[0002] In three-dimensional non-volatile memory, multiple memory cells, each having a channel layer, are arranged along the height of a pillar that extends in the height direction. While the memory cell characteristics are improved by crystallizing the channel layer, incomplete crystallization can lead to variations in memory cell characteristics. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-157748 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve the crystallinity of the channel layer. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment comprises a laminate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and a pillar extending within the laminate in the stacking direction of the laminate, wherein the pillar includes a first semiconductor layer extending within the laminate in the stacking direction, a second semiconductor layer disposed above the first semiconductor layer, and a third semiconductor layer interposed between the first and second semiconductor layers, and the second semiconductor layer contains at least one additive of carbon, nitrogen, oxygen, and fluorine. [Brief explanation of the drawing]

[0006] [Figure 1] FIG. 1 is a diagram showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to an embodiment. [Figure 3] FIGS. 3A to 3C are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] FIGS. 4A to 4C are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] FIGS. 5A to 5B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] FIGS. 6A to 6B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] FIGS. 7A to 7B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] FIGS. 8A to 8B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] FIGS. 9A to 9B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] FIGS. 10A to 10B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] FIGS. 11A to 11B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] FIGS. 12A to 12B are diagrams sequentially illustrating part of the steps of a method for manufacturing a semiconductor memory device according to an embodiment. DESCRIPTION OF EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited by the following embodiments. In addition, the constituent elements in the following embodiments include those that can be easily conceived by those skilled in the art and those that are substantially the same.

[0008] Embodiment Hereinafter, embodiments will be described in detail with reference to the drawings.

[0009] (Configuration Example of Semiconductor Memory Device) FIG. 1 is a diagram showing a schematic configuration example of the semiconductor memory device 1 according to the embodiment. More specifically, FIG. 1(a) is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0010] However, hatching is omitted in FIG. 1(a) for the sake of visibility of the drawing. In addition, in FIG. 1(a), structures not necessarily present in the same cross-section are shown together, and some upper-layer wirings and the like are omitted.

[0011] In addition, in the present specification, both the X direction and the Y direction are directions along the plane orientation of the word line WL, and the X direction and the Y direction are orthogonal to each other. Further, the electrical lead-out direction of the word line WL may be referred to as a first direction, and this first direction is a direction along the X direction. Further, a direction intersecting the first direction may be referred to as a second direction, and this second direction is a direction along the Y direction. However, since the semiconductor memory device 1 may include manufacturing errors, the first direction and the second direction are not necessarily orthogonal to each other.

[0012] As shown in FIG. 1(a), the semiconductor memory device 1 includes a semiconductor substrate SB provided with an electrode film EL, a source line SL, one or more selection gate lines SGS, a plurality of word lines WL, one or more selection gate lines SGD, and a peripheral circuit CBA in order from the lower side of the drawing.

[0013] On the electrode film EL, the source line SL is arranged with an insulating layer 60 interposed therebetween. A plurality of plugs PG are arranged in the insulating layer 60, and electrical conduction is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are provided in the same layer as the electrode film EL. On the source line SL, the selection gate line SGS, the plurality of word lines WL, and the selection gate line SGD are stacked in this order.

[0014] As shown in Figures 1(a) and 1(b), a memory area MR is located in the center of multiple word lines WL in the X direction, and stepped areas SR are located at both ends of the multiple word lines WL in the X direction. These memory areas MR and stepped areas SR are divided into multiple regions by multiple plate-shaped contacts LI that penetrate the multiple word lines WL and extend in a direction along the X direction.

[0015] Furthermore, the area located between adjacent plate-shaped contacts LI in the Y direction, and including the memory area MR and the step area SR, is called the block area BLK. As will be described later, the memory area MR contains multiple memory cells that hold data non-volatilely, and the block area BLK described above serves as the unit for erasing this data.

[0016] Furthermore, between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the selected gate line SGD. These multiple isolation layers SHE extend in the direction along the X direction throughout the entire memory area MR, and also reach a portion of the stepped area SR at both ends in the X direction.

[0017] In the memory region MR, multiple pillars PL are arranged that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction. The lower end of the pillar PL reaches the source line SL. Multiple memory cells are formed at the intersections of the pillar PL and the word line WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the stepped region SR, multiple word lines WL and selection gate lines SGD and SGS are processed and terminated in a stepped manner. As we move away from the memory region MR in the X direction, the multiple word lines WL and selection gate lines SGD and SGS that make up the terrace section move from the upper layer to the lower layer, causing the height of the terrace section to decrease towards the source line SL.

[0019] In this specification, the direction in which the terrace surfaces of multiple word lines WL and selected gate lines SGD and SGS face is defined as the upper side of the semiconductor memory device 1.

[0020] The aforementioned isolation layer SHE extends from the memory region MR to the stepped portion of the step region SR where the selected gate line SGD is processed in a step-like manner. As a result, within a single block region BLK, the selected gate line SGD is separated into multiple regions. In other words, the isolation layer SHE penetrates the portion above multiple word lines WL, thereby dividing these upper portions into multiple patterns of selected gate line SGD.

[0021] Each terrace section of a layer, composed of multiple word lines WL and selection gate lines SGD and SGS, has contact CCs connected to the word lines WL and selection gate lines SGD and SGS of each layer. One contact CC is connected to each layer of the word lines WL and selection gate lines SGS. For the selection gate lines SGD, one contact CC is connected to each section separated by the isolation layer SHE per layer.

[0022] Here, within a single block region BLK, multiple contacts CC are positioned on one side of the staircase region SR on both sides in the X direction. Also, looking at one side in the X direction, for example, multiple contacts CC are positioned every two block regions BLK.

[0023] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0024] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0025] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0026] Multiple word lines WL, selection gate lines SGD, SGS, pillar PL, and contact CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components, including the multiple word lines WL, etc.

[0027] The semiconductor substrate SB above the insulating layer 50 covering the above configuration is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0028] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers multiple word lines WL, etc., a semiconductor memory device 1 is formed that includes multiple word lines WL, selection gate lines SGD, SGS, pillar PL, contact CC, etc., and the peripheral circuit CBA.

[0029] Next, a detailed example of the configuration of the semiconductor memory device 1 will be described using Figure 2. Figure 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0030] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0031] Figure 2(b) is an enlarged cross-sectional view of pillar PL at the height of the selected gate wires SGD and SGS. Figure 2(c) is an enlarged cross-sectional view of pillar PL at the height of the word wire WL. Figure 2(d) is an enlarged cross-sectional view of pillar PL at the height of the uppermost insulating layer OL.

[0032] As shown in Figure 2(a), the source wire SL has a multilayer structure in which, for example, a lower source wire DSLa, an intermediate source wire BSL, and an upper source wire DSLb are stacked in this order on an insulating layer 60. The lower source wire DSLa, the intermediate source wire BSL, and the upper source wire DSLb are, for example, polysilicon layers. Of these, at least the intermediate source wire BSL may be a conductive polysilicon layer in which impurities have been diffused.

[0033] The source wire SL is connected to the peripheral circuit CBA via the electrode film EL through a through-contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA, within the aforementioned insulating layer 50 on the outside of the laminate LM.

[0034] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0035] The LMa laminate is positioned above the source line SL. Below the bottommost word line WL of the LMa laminate, multiple selectable gate lines SGS0 and SGS1 are arranged in this order from the top of the LMa laminate, via an insulating layer OL. The LMb laminate is positioned on top of the LMa laminate. Above the topmost word line WL of the LMB laminate, multiple selectable gate lines SGD0 and SGD1 are arranged in this order from the top of the LMB laminate, via an insulating layer OL.

[0036] However, the number of layers of these word lines WL and selective gate lines SGD,SGS in the laminate LM is arbitrary. The word lines WL and selective gate lines SGD,SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0037] The upper surface of the laminate LM is covered in this order by insulating layers 52 and 53. Insulating layers 52 and 53 each constitute a part of the insulating layer 50 in Figure 1.

[0038] As described above, the laminate LM is divided in the Y direction by multiple plate-like contacts LI. That is, each plate-like contact LI is aligned with the others in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM.

[0039] Thus, the plate-shaped contact LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0040] Furthermore, the plate-shaped contact LI may have a tapered shape in which its width in the Y direction decreases from the upper end to the lower end, for example. Alternatively, the plate-shaped contact LI may have a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0041] Each plate-shaped contact LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer.

[0042] The insulating layer 54 covers the side walls of the plate-shaped contact LI that face each other in the Y direction. The conductive layer 24 is filled further inside the insulating layer 54 that covers the side walls of the plate-shaped contact LI and is electrically connected to the source wire SL, including the intermediate source wire BSL.

[0043] However, instead of the plate-shaped contact LI, a plate-shaped member filled with an insulating layer may penetrate the laminate LM and extend in a direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0044] Between adjacent plate-shaped contacts LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the upper portion of the laminate LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0045] In other words, these separation layers SHE, which penetrate the upper portion of the laminated LMb, extend in the X direction between the plate-shaped contacts LI, dividing the upper portion of the laminated LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0046] In the memory region MR, multiple pillars PL are distributed and arranged, penetrating the stacked structure LM, the upper source line DSLb, and the intermediate source line BSL, and reaching the lower source line DSLa.

[0047] Multiple pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape in the direction along the layering direction of the laminate LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0048] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper and lower layers, for example.

[0049] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN extending in the stacking direction within the laminate LM inside the memory layer ME, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR which serves as the core material of the pillar PL.

[0050] The channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is located on the side of the pillar PL, excluding the depth of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0051] As a result, the channel layer CN is in contact with the intermediate source line BSL on its side, and further, electrically connected to the entire source line SL via the intermediate source line BSL.

[0052] The cap layer CP is positioned at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. Furthermore, the cap layer CP is connected to the bit wire BL located in the insulating layer 53 via a plug CH located in the uppermost insulating layer OL, 52 of the laminate LM. The bit wire BL extends above the laminate LM in a direction along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0053] As shown in Figures 2(b) and 2(c), the memory layer ME has a laminated structure including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, in that order from the outer periphery of the pillar PL. The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer.

[0054] The channel layer CN is a highly crystalline semiconductor layer, such as a single-crystal silicon layer. However, the channel layer CN may contain polycrystalline silicon in part. Even in this case, it is preferable that the channel layer CN has single-crystal silicon as its main component.

[0055] The cap layer CP is, for example, a polycrystalline semiconductor layer such as a polysilicon layer. However, the cap layer CP may also contain a portion of an amorphous semiconductor such as amorphous silicon.

[0056] As shown in Figure 2(c), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0057] As shown in Figure 2(b), selection gate STD is formed on the side of pillar PL where it faces selection gate lines SGD0 and SGD1. Additionally, selection gate STS is formed on the side of pillar PL where it faces selection gate lines SGS0 and SGS1, which are lower than the word line WL.

[0058] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0059] As shown in Figure 2(d), the pillar PL further comprises a semiconductor layer CNn interposed between the channel layer CN and the cap layer CP. More specifically, the semiconductor layer CNn is located at least above the height of the word line WL of the uppermost layer of the laminate LM, and more preferably above the height of the selected gate line SGD0 of the uppermost layer of the laminate LM, for example, at the height of the insulating layer OL of the uppermost layer of the laminate LM.

[0060] The semiconductor layer CNn is, for example, a single-crystal silicon layer. However, the semiconductor layer CN may contain polycrystalline silicon in part. Even in this case, it is preferable that the semiconductor layer CN has single-crystal silicon as its main component.

[0061] Further, the semiconductor layer CNn contains, for example, at least one of carbon, nitrogen, oxygen, and fluorine as an additive. The concentration of the additive in the semiconductor layer CNn is, for example, 1×10 20 atm / cm 3 or more and 3×10 21 atm / cm 3 or less, preferably 5×10 20 atm / cm 3 or more and 2×10 21 atm / cm 3 or less, more preferably 9×10 20 atm / cm 3 or more and 1.5×10 21 atm / cm 3 or less.

[0062] (Method of Manufacturing Semiconductor Memory Device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to FIGS. 3 to 12. FIGS. 3 to 12 sequentially illustrate part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the embodiment. Note that FIGS. 3 to 12 excluding FIG. 7 each show a cross-section along the Y direction of a region that will later become the memory region MR. FIG. 7 is a partially enlarged cross-sectional view of a pillar PL in the middle of manufacturing.

[0063] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are formed in this order on a support substrate SS.

[0064] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The above-described insulating layer 60 (see FIG. 2(a) and the like) may be formed on the upper surface side of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer or the like, and is a layer that will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0065] On the upper source line DSLb, a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, one layer at a time. The insulating layer NL is, for example, a silicon nitride layer and functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0066] Although not shown in the diagram, in a portion of the laminated LMsa, the insulating layer NL and insulating layer OL are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminated LMsa.

[0067] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa again, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0068] Subsequently, the stepped shape at both ends in the X direction is covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0069] As shown in Figure 3(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa later become the substructure of the pillar PL.

[0070] As shown in Figure 3(c), these memory holes MHa are filled with a sacrificial layer 26, such as an amorphous silicon layer or a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 26.

[0071] As shown in Figure 4(a), the laminate LMsa is covered, and a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0072] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0073] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0074] Subsequently, the stepped shape at both ends in the X direction is further covered with a portion of the insulating layer 50 (see Figure 1(a)) described above.

[0075] As shown in Figure 4(b), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts that will later become the upper structure of the pillars PL.

[0076] As shown in Figure 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0077] Furthermore, if the sacrificial layer 26 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 26 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like.

[0078] As shown in Figure 5(b), a memory layer ME is formed on the side wall of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, in the order of block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)), starting from the side wall side of the memory hole MH. The memory layer ME is also formed on the top surface of the laminate LMsb.

[0079] Furthermore, the channel layer CNa and core layer CRs are formed in this order within the memory hole MH. As a result, the channel layer CNa is formed on the memory layer ME that covers the sides and bottom of the memory hole MH, and the core layer CRs fills the center of the memory hole MH. The channel layer CNa and core layer CRs are also formed in this order on the upper surface of the laminate LMsb via the memory layer ME.

[0080] Note that the channel layer CNa is the semiconductor layer that will later become the channel layer CN. At this point, the entire channel layer CNa is an amorphous semiconductor layer, such as an amorphous silicon layer. Also, at this point, the channel layer CNa is formed to be thicker than the channel layer CN that the pillar PL will ultimately have. Furthermore, the core layers CRs formed at this point are temporary core layers CRs that will later be removed.

[0081] As shown in Figure 6(a), the core layer CRs formed on the upper surface of the laminate LMsb is removed by etching back, and the core layer CRs inside the memory hole MH is receded to form a void DNa at the upper end of the memory hole MH.

[0082] As shown in Figure 6(b), a cap layer CPa is formed in the above-mentioned void DNa. At this time, the cap layer CPa is an amorphous semiconductor layer such as an amorphous silicon layer, similar to the channel layer CNa. The cap layer CPa formed at this stage is a temporary cap layer CPa that will be removed later. The cap layer CPa is also formed on the upper surface of the laminate LMsb via the memory layer ME and the channel layer CNa.

[0083] Furthermore, when forming the cap layer CPa, at least one of nitrogen, boron, and carbon may be added to the cap layer CPa. In this case, the concentration of the additive in the cap layer CPa is preferably lower than the concentration of the additive in the semiconductor layer CNn described above.

[0084] Subsequently, the channel layer CNa is crystallized, and for example, a single-crystal channel layer CN is formed. In the crystallization of the channel layer CNa, a semiconductor layer containing high concentrations of carbon, nitrogen, oxygen, or fluorine is formed at the interface between the channel layer CNa and the cap layer CPa as described in Figures 5 and 6 above. This controls the crystallization of the channel layer CNa.

[0085] Figure 7 below shows a detailed example of the crystallization method for the channel layer CNa.

[0086] As shown in Figure 7(a), within the memory hole MH, the memory layer ME, core layer CRs, channel layer CNa, semiconductor layer CNna, and cap layer CPa are formed by the processes described in Figures 5 and 6 above.

[0087] The semiconductor layer CNna is formed, for example, by adding at least one of carbon, nitrogen, oxygen, and fluorine to the semiconductor layer's raw material gas at the end of the process of forming the channel layer CNa using chemical vapor deposition (CVD). The semiconductor layer CNna is the layer that will later become the semiconductor layer CNn, and at this point, it is an amorphous semiconductor layer such as an amorphous silicon layer.

[0088] Subsequently, as described above, the core layer CRs within the memory hole MH is retracted. At this time, the semiconductor layer CNna may be etched back along with the core layer CRs. As a result, the cap layer CPa is formed in the void DNa (see Figure 6(a)) created at the upper end of the memory hole MH, as described above.

[0089] As described above, a metal layer NS, such as a nickel layer, is formed on the upper surface of the cap layer CPa, which is filled into the voids DNa of the memory holes MH and covers the upper surface of the laminate LMsb. The entire support substrate SS is then heated and subjected to an annealing treatment. At this time, the annealing temperature is set to a low temperature, for example, such that crystallization does not proceed in the channel layer CNa alone.

[0090] On the other hand, the metal layer NS formed on the upper surface of the cap layer CPa is silicided by bonding with silicon and other elements in the cap layer CPa, at least in part. Such silicides, such as nickel silicide, promote the crystallization of the cap layer CPa and the channel layer CNa. In other words, the silicide functions as a catalyst for the crystallization of the channel layer CNa and other elements. Furthermore, if at least one of nitrogen, boron, and carbon is added to the cap layer CPa, these additives promote the formation of silicides.

[0091] As a result, even during annealing at low temperatures, crystallization begins from the upper surface of the cap layer CPa in contact with the metal layer NS, moving in the depth direction.

[0092] As shown in Figure 7(b), crystallization that begins on the upper surface of the cap layer CPa reaches the semiconductor layer CNna below the cap layer CPa. Some of the silicides that catalyzed the crystallization of the cap layer CPa are fragmented into metal fragments NSf and diffuse into the cap layer CPa and the semiconductor layer CNna.

[0093] In the areas where the metal fragment NSf has entered, the cap layer CPa and semiconductor layer CNna are transformed into a cap layer CPc and semiconductor layer CNn, which are, for example, single-crystal silicon layers. As crystallization into the cap layer CPc and semiconductor layer CNn progresses in this way, the metal layer NS on the upper surface of the cap layer CPc becomes thinner.

[0094] Here, the semiconductor layer CNna contains high concentrations of additives such as carbon, nitrogen, oxygen, or fluorine, as described above. By containing these additives at high concentrations, the semiconductor layer CNna has the function of slowing down the crystallization rate. This makes it easier for metal fragments NSf to aggregate in the semiconductor layer CNna, and as crystallization progresses downwards in the semiconductor layer CNna, the highly aggregated metal fragments NSf can reach the channel layer CNa.

[0095] The highly concentrated aggregated metal fragments NSf increase the crystallization rate in the channel layer CNa, allowing for more homogeneous crystallization. Therefore, a channel layer CN, such as a highly crystalline single-crystal silicon layer, can be obtained.

[0096] Thus, the process of crystallizing the channel layer CNa, semiconductor layer CNna, and cap layer CPa by low-temperature annealing using silicide NS or the like as a catalyst is also called metal-assisted annealing.

[0097] As shown in Figure 7(c), the crystallization of the channel layer CNa progresses, and the entire channel layer CNa becomes, for example, a single-crystal channel layer CN, thus completing the metal-assisted annealing process. By the time the annealing process is complete, the metal layer NS on the upper surface of the cap layer CPc may have disappeared.

[0098] Furthermore, the channel layer CN, semiconductor layer CNn, and cap layer CPc may contain polycrystalline semiconductors due to partial incomplete crystallization, etc. However, even in this case, the channel layer CN, semiconductor layer CNn, and cap layer CPc, which are mainly composed of single-crystal semiconductors, are formed by annealing using metal assistance.

[0099] As shown in Figure 7(d), metal fragments NSf are segregated in the channel layer CN after crystallization. To remove these metal fragments NSf, a gettering layer GT, such as an amorphous silicon layer, is formed on the upper surface of the cap layer CPc.

[0100] As shown in Figure 7(e), annealing causes the metal fragments NSf that were segregated in the channel layer CN to move into the gettering layer GT. This makes it possible to remove most of the metal fragments NSf from the channel layer CN.

[0101] As shown in Figure 7(f), the gettering layer GT is removed.

[0102] Furthermore, in annealing using metal assistance, crystallization is more easily promoted when the layer to be crystallized is thicker. Therefore, as described above, the channel layer CNa is formed thicker than the channel layer CN that will ultimately be present in the pillar PL. For this reason, after crystallizing the channel layer CNa to obtain the channel layer CN, the channel layer CN is slimmed as follows.

[0103] As shown in Figure 7(g), the cap layer CPc is temporarily removed to form a void DNb at the upper end of the memory hole MH.

[0104] As shown in Figure 7(h), the core layer CRs is removed, and the channel layer CN exposed in the resulting void DNc is slimmed down to the final thickness of the pillar PL.

[0105] As shown in Figure 7(i), a core layer CR is filled into the void DNc surrounded by the channel layer CN, and a cap layer CP is formed in the void DNb at the upper end of the memory hole MH. The cap layer CP thus formed is a polycrystalline semiconductor layer, such as a polysilicon layer. In this case, the cap layer CP may also contain an amorphous semiconductor, such as amorphous silicon, in part.

[0106] However, even if amorphous silicon or the like is included in part of the cap layer CP, the cap layer CP may undergo various thermal histories due to subsequent processing in the manufacturing process of the semiconductor memory device 1. Therefore, the proportion of amorphous material in the cap layer CP may decrease from the initial formation of the cap layer CP, or it may disappear in the final semiconductor memory device 1.

[0107] As a result, a channel layer CN, which is a semiconductor layer such as a single crystal, is formed.

[0108] As shown in Figure 8(a), the cap layer CP, channel layer CN, and memory layer ME on the upper surface of the laminated LMsb are removed by CMP or the like, along with a portion of the insulating layer OL on the top layer of the laminated LMsb.

[0109] As shown in Figure 8(b), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked again. This forms a pillar PL in which the cap layer CP is embedded in the insulating layer OL on the top layer. However, at this point, the memory layer ME covers the entire side wall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME.

[0110] As shown in Figure 9(a), a slit ST is formed that penetrates the laminates LMsb and LMsa, on which the pillar PL is formed, and the upper source wire DSLb, reaching the intermediate sacrificial layer SCN. In addition, an insulating layer 54s is formed on the side walls of the slit ST facing in the Y direction. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0111] As shown in Figure 9(b), a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through the slit ST, whose sidewalls are protected by the insulating layer 54s, to remove the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb.

[0112] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs. At this time, since the sidewall of the slit ST is protected by the insulating layer 54s, the removal of the insulating layer NL within the laminates LMsa and LMsb is suppressed.

[0113] As shown in Figure 10(a), chemical solutions are introduced into the gap layer GPs through the slit ST as needed, sequentially removing the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(b) and 2(c)) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0114] As shown in Figure 10(b), a raw material gas, such as amorphous silicon, is injected through the slit ST, whose sidewalls are protected by an insulating layer 54s, to fill the gap layer GPs with amorphous silicon or the like. The support substrate SS is then heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0115] As a result, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0116] As shown in Figure 11(a), the insulating layer 54s on the side wall of the slit ST is removed.

[0117] As shown in Figure 11(b), a solution for removing the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb from the slit ST from which the insulating layer 54s has been removed, thereby removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb having multiple gap layers GP from which the insulating layer NL between insulating layers OL has been removed.

[0118] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0119] As shown in Figure 12(a), a conductive material raw material gas, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc. This forms a laminate LM containing laminates LMa and LMb, in which multiple word lines WL, etc. and multiple insulating layers OL are alternately stacked one layer at a time.

[0120] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0121] As shown in Figure 12(b), a conductive layer 24 is filled into the slit ST via an insulating layer 54 to form a plate-shaped contact LI. In addition, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb, and an insulating layer 56 is filled into the groove to form a separation layer SHE that divides these conductive layers into a pattern of selected gate lines SGD.

[0122] Subsequently, although not shown in the diagram, multiple contacts CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0123] Furthermore, after forming an insulating layer 52 that covers the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL and insulating layer 52 of the laminate LM and are connected to the cap layer CP at the upper end of the pillar PL. In addition, an insulating layer 53 is formed that covers the insulating layer 52, and bit wires BL are formed in the insulating layer 53 to which the individual plugs CH are connected.

[0124] Furthermore, the plug CH and bit wire BL may be formed collectively by using methods such as the dual damascene method.

[0125] Furthermore, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40, and these are connected to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0126] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0127] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0128] (Overview) In semiconductor memory devices such as 3D non-volatile memory, there is a technique for single-crystallizing the channel layer of the pillars. This improves carrier mobility in the channel layer and reduces noise because traps are not generated by grain boundaries. Crystallization of the channel layer is performed, for example, by introducing a metal element such as nickel into an amorphous channel layer and then using a metal-assisted annealing process with this element as a catalyst.

[0129] However, during the crystallization of the channel layer, the crystallization process may stop with a certain probability, which can result in the presence of polycrystalline portions within the channel layer. Such cessation of crystallization can occur due to the influence of microcrystals such as silicon that form at the interface between the amorphous channel layer and the memory layer, and the decreasing concentration of catalysts such as nickel silicide as crystallization progresses. When variations occur in the crystallinity of the channel layer, such as the presence of polycrystalline material, variations may occur in memory cell characteristics such as cell current, threshold voltage, and operating speeds such as writing and reading.

[0130] According to the semiconductor memory device 1 of this embodiment, among the channel layer CN, semiconductor layer CNn, and cap layer CP, the semiconductor layer CNn contains at least one additive of carbon, nitrogen, oxygen, and fluorine. This reduces the rate of crystallization in the semiconductor layer CNn during annealing using metal assistance, and allows for the aggregation of silicides that act as a catalyst for crystallization. Therefore, it is possible to suppress the stagnation of crystallization in the channel layer CN and improve the crystallinity of the channel layer CN.

[0131] According to the semiconductor memory device 1 of the embodiment, the semiconductor layer CNn is located above the height of the word line WL, which is one layer below the selection gate lines SGD0 and SGD1 through which the isolation layer SHE penetrates. High concentrations of additives such as carbon can inhibit the crystallization of the channel layer CN and other elements, degrading the characteristics of the memory cell MC. Therefore, by placing the semiconductor layer CNn containing carbon above the word line WL of the uppermost layer of the stack LM, the inhibition of crystallization of the channel layer CN at the height of the word line WL is suppressed, thereby suppressing the degradation of the characteristics of the memory cell MC.

[0132] According to the semiconductor memory device 1 of this embodiment, the semiconductor layer CNn is positioned at a height above the selected gate line SGD0 of the uppermost layer of the stacked structure LM. This makes it possible to more reliably suppress the deterioration of the characteristics of the memory cell MC.

[0133] According to the semiconductor memory device 1 of this embodiment, the channel layer CN does not contain any additives. By not including additives that may inhibit crystallization, such as carbon, in the channel layer CN, the characteristics of the memory cell MC can be further improved.

[0134] According to the semiconductor memory device 1 of the embodiment, the concentration of the additive contained in the semiconductor layer CNn is 1 × 10⁻¹⁶ 20 cm -3 The above 3 x 10 21 cm -3 The following is preferably 5 × 10 20 cm -3 The above 2 x 10 21 cm -3 The following is more comfortable 9×10 20 cm -3 The above 1.5 × 10 21 cm -3 The following is the result: This reduces the crystallization rate in the semiconductor layer CNn, allowing for more reliable aggregation of silicides.

[0135] In the above embodiment, the semiconductor memory device 1 is provided with a stacked LM having a 2-tier structure in which two stacked layers LMa and LMb are stacked vertically. However, the configuration of the stacked layer is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0136] Furthermore, in the above-described embodiment, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this configuration. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0137] Furthermore, in the above embodiment, the peripheral circuit CBA is positioned above the laminate LM. However, the peripheral circuit may be positioned below the laminate, or on the same layer as the laminate. When the peripheral circuit is positioned below the laminate, the laminate can be formed directly above the semiconductor substrate on which the peripheral circuit is formed. Also, when the peripheral circuit is positioned on the same layer as the laminate, the laminate can be formed at a different location on the semiconductor substrate from where the peripheral circuit is formed.

[0138] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0139] 1... Semiconductor memory device, CN, CNa... Channel layer, CNn, CNna... Semiconductor layer, CP, CPa, CPc... Cap layer, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb... Stack, MC... Memory cell, MR... Memory region, NL, OL... Insulating layer, PL... Pillar, SR... Staircase region, SGD, SGS... Selected gate line, SHE... Isolation layer, WL... Word line.

Claims

1. A laminate in which multiple conductive layers and multiple insulating layers are stacked alternately, The laminate comprises pillars extending within the laminate in the stacking direction, The aforementioned pillar is A first semiconductor layer extending within the laminate in the aforementioned stacking direction, A second semiconductor layer is disposed above the first semiconductor layer, A third semiconductor layer interposed between the first and second semiconductor layers, The aforementioned second semiconductor layer is Contains at least one additive of carbon, nitrogen, oxygen, and fluorine. Semiconductor memory device.

2. The laminate further comprises, among the plurality of conductive layers, the uppermost conductive layer of the laminate, or a separation layer that penetrates the uppermost conductive layer and one or more conductive layers continuous with the uppermost conductive layer in the lamination direction, and extends in a first direction intersecting the lamination direction. The third semiconductor layer is Among the plurality of conductive layers, the one located above the height of the conductive layer one below the conductive layer through which the separation layer penetrates, The semiconductor memory device according to claim 1.

3. The first and third semiconductor layers are mainly composed of single-crystal semiconductors. The semiconductor memory device according to claim 1.

4. The concentration of the additive contained in the third semiconductor layer is 1 x 10 ２０ cm －３ The above 3 x 10 ２１ cm －３ The following is: The semiconductor memory device according to claim 1.

5. A laminate is formed in which multiple sacrificial layers and multiple insulating layers are stacked alternately, one layer at a time. A memory hole is formed in the laminate that extends within the laminate in the stacking direction of the laminate. A pillar is formed within the memory hole, including a first semiconductor layer extending within the stack in the stacking direction and a second semiconductor layer positioned above the first semiconductor layer. The formation of the aforementioned pillar is The first semiconductor layer is subjected to an annealing process to crystallize the first semiconductor layer, The process includes forming a third semiconductor layer containing an additive that reduces the rate of crystallization on the upper end of the first semiconductor layer before performing the aforementioned annealing treatment. A method for manufacturing semiconductor memory devices.

6. The aforementioned annealing process is an annealing process using metal assistance. The method for manufacturing a semiconductor memory device according to claim 5.

7. The formation of the third semiconductor layer is The additive includes adding at least one of carbon, nitrogen, oxygen, and fluorine to the third semiconductor layer. The method for manufacturing a semiconductor memory device according to claim 5.

8. The formation of the aforementioned pillar is The first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are formed in this order. Performing the aforementioned annealing process to crystallize the first, third, and fourth semiconductor layers, Removing the crystallized fourth semiconductor layer, This includes forming the second semiconductor layer, which is mainly composed of polycrystalline material, on the upper end of the third semiconductor layer. The method for manufacturing a semiconductor memory device according to claim 5.

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