Semiconductor equipment

Abstract

To improve the reliability and voltage resistance of semiconductor devices. [Solution] The semiconductor device comprises a lower electrode, a superjunction layer, a plurality of second-conductivity field relaxation layers, a first-conductivity current dispersion layer, and a second-conductivity body region. The semiconductor device comprises a second-conductivity connection region whose upper part is in contact with the body region and whose lower part is in contact with the field relaxation layer. The semiconductor device comprises a first-conductivity source region, a plurality of gate portions, and an upper electrode. In a vertical upward view of the substrate surface, a portion of the field relaxation layer overlaps with the gate portions. In a vertical upward view, between adjacent gate portions, there are a plurality of first aperture regions where the gate-to-gate distance is a first distance, and a plurality of second aperture regions where the gate-to-gate distance is a second distance smaller than the first distance. The connection region is located in at least one of the plurality of first aperture regions, but is not located in any of the plurality of second aperture regions.

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a vertical power semiconductor device provided with a trench gate. In this semiconductor device, a stripe-shaped p-type base region extending in parallel with the trench is provided below the trench gate. Further, between the trench gates, a p-type connection region is disposed below a p-type body region. The connection regions are provided at constant intervals in the longitudinal direction of the trench. The p-type base region is electrically connected to an upper electrode via the connection region. This stabilizes the potential of the p-type base region and relaxes the electric field in the gate insulating film below the trench gate. Prior Art Documents Patent Documents

[0003] Patent Document 1 Japanese Patent Laid-Open No. 2022-37757 Summary of the Invention Problem to be Solved by the Invention

[0004] In order to improve breakdown voltage by completely depleting the stripe-shaped p-type base region, it is necessary to further expand the depletion layer spreading from the interface of the p-type base region. If the p-type impurity concentration of the p-type base region is lowered to expand the depletion layer, the electrical resistance of the p-type base region increases. Then, when an avalanche current occurs, the voltage drop generated in the p-type base region due to hole current becomes large. As a result, the potential of the p-type base region may not be stabilized, and the electric field in the gate insulating film may increase. There is a risk that the gate insulating film may deteriorate. Means for Solving the Problem

[0005] The semiconductor device (1) disclosed herein comprises a lower electrode, a semiconductor substrate (12) disposed in contact with the upper surface of the lower electrode and having a source region and a body region, a plurality of gate portions (20) facing the body region and the source region, and an upper electrode (14) disposed on the surface of the semiconductor substrate and electrically connected to the source region and the body region. The semiconductor substrate includes a superjunction layer (60) disposed above the lower electrode. The superjunction layer has a first column (61) of a first conductivity type (n type) extending in a first direction (y) and a second column (62) of a second conductivity type (p type) extending in the first direction, which are alternately and repeatedly arranged along a second direction (x) intersecting the first direction. The semiconductor substrate includes a plurality of field relaxation layers (50) of a second conductivity type (p type) disposed in contact with the upper surface of the superjunction layer. The field relaxation layers extend in a third direction (x) intersecting the first direction, and semiconductor layers (54) of a first conductivity type are disposed between adjacent field relaxation layers. The semiconductor substrate includes a current dispersion layer (40) of a first conductivity type, which is located in contact with the upper surface of the field relaxation layer. The semiconductor substrate includes a body region (34) of a second conductivity type, which is in contact with the upper surface of the current dispersion layer. The semiconductor substrate includes a connection region (38) of a second conductivity type, which has its upper part in contact with the body region and its lower part in contact with the field relaxation layer. The connection region electrically connects the body region and the field relaxation layer. The semiconductor substrate includes a source region (30) of a first conductivity type, which is located above the body region and is exposed on the substrate surface (12a) of the semiconductor substrate. The concentration of second conductivity type impurities in the field relaxation layer is higher than the concentration of second conductivity type impurities in the second column. In a vertical upward view of the substrate surface of the semiconductor substrate, a portion of the field relaxation layer overlaps with the gate region. In a vertical upward view, between adjacent gate sections, there are multiple first opening regions (A1) with a gate-to-gate distance of a first distance (S1), and multiple second opening regions (A2) with a gate-to-gate distance of a second distance (S2) that is smaller than the first distance. The connecting region is located in at least one of the multiple first opening regions, but is not located within any of the multiple second opening regions.

[0006] In this specification, one of the first conductivity type and the second conductivity type means n-type, and the other means p-type.

[0007] In the above structure, the field relaxation layer is connected to the upper electrode via a connection region and a body region. Therefore, the field relaxation layer has approximately the same potential as the upper electrode. Consequently, when hole current is generated during high-speed switching or avalanche operation, the hole current flows into the field relaxation layer and then to the upper electrode via the connection region. Furthermore, in the above structure, the first aperture region is wider than the second aperture region, and the connection region is selectively placed in the first aperture region. Therefore, compared to the case where the connection region is placed in the second aperture region, the area of ​​the connection region can be increased, and thus the electrical resistance of the connection region can be reduced. This suppresses the voltage drop generated in the field relaxation layer by the hole current, making it possible to stabilize the potential of the field relaxation layer.

[0008] Furthermore, the above structure includes a superjunction layer. The concentration of the second conductivity type impurity in the field relaxation layer is higher than the concentration of the second conductivity type impurity in the second column of the superjunction layer. By increasing the concentration of the field relaxation layer, the electrical resistance of the field relaxation layer can be reduced, thereby suppressing the voltage drop that occurs in the field relaxation layer. In addition, by lowering the concentration of the second column, the depletion layer can be spread throughout the entire superjunction layer, thereby improving the breakdown voltage. This makes it possible to achieve both improved reliability and improved breakdown voltage of the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] A cross-sectional perspective view of the semiconductor device 1 of Example 1. [Figure 2] A cross-sectional perspective view of the semiconductor device 1 of Example 1. [Figure 3] A cross-sectional perspective view of the semiconductor device 1 of Example 1. [Figure 4] Cross-sectional view along line IV-IV in Figure 1. [Figure 5] A diagram showing the arrangement ratio of gate distances S1 and S2. [Figure 6] Cross-sectional view of the main part of semiconductor device 201 of Example 2. [Figure 7] Cross-sectional view of the main part of semiconductor device 201 of Example 2. [Figure 8] Plan view of semiconductor device 201 of Example 2. [Figure 9] A plan view showing a modified example of the semiconductor device 201 of Example 2. [Modes for carrying out the invention] [Examples]

[0010] (Outline configuration of semiconductor device 1) Figures 1 to 3 show a cross-sectional perspective view of the semiconductor device 1. The semiconductor device 1 is a power semiconductor element called a MOSFET. The semiconductor device 1 is a vertical device equipped with a trench-type gate portion 20. In Figures 1 to 3, the thickness direction of the semiconductor substrate 12 is called the z direction, one direction in the plane perpendicular to the z direction is called the x direction, and the direction perpendicular to the x direction in the said plane is called the y direction. For clarity, n-type regions are shown as solid gray, and p-type regions are shown as white. Electrodes are shown with thin hatching, and insulating layers are shown with thick hatching. In cases where multiple parts exist, one representative part may be given a reference number for explanation. The same applies to other drawings.

[0011] Figures 1 and 2 are cross-sectional views along line II in Figure 4, which will be described later. Figure 3 is a cross-sectional view along line III-III in Figure 4. That is, Figures 1 and 2 are cross-sectional views passing through the field relaxation layer 50, and Figure 3 is a cross-sectional view passing through the n-type layer 54. Figure 2 is a drawing from Figure 1 with the source electrode 14 omitted.

[0012] In Example 1, a configuration is described in which, when viewed from the +z direction perpendicular to the substrate surface 12a (vertical upward view), multiple gate portions 20 extend in the y direction and are arranged in a stripe pattern. The semiconductor device 1 has a semiconductor substrate 12, a source electrode 14, and a drain electrode 16. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials such as Si or GaN. As shown in Figure 1, the source electrode 14 covers the substrate surface 12a of the semiconductor substrate 12. Also, as shown in Figures 1 to 3, the drain electrode 16 covers the lower surface 12b of the semiconductor substrate 12.

[0013] The semiconductor substrate 12 mainly comprises a drain layer 42, a drift layer 41, a superjunction layer (SJ layer) 60, a field relaxation layer 50, an n-type layer 54, a current dispersion layer 40, a body region 34, a contact region 32, a source region 30, a connection region 38, and a gate region 20.

[0014] The drain layer 42 is an n-type region. The drain layer 42 is in ohmic contact with the drain electrode 16 on the lower surface 12b of the semiconductor substrate 12. The drift layer 41 is positioned in contact with the upper surface of the drain layer 42. In this embodiment, the drift layer 41 is an n-type region having a lower n-type impurity concentration than the drain layer 42.

[0015] The SJ layer 60 is positioned in contact with the upper surface of the drift layer 41. The SJ layer 60 comprises an n-type first column 61 extending in the y-direction and a p-type second column 62 extending in the y-direction. Multiple first columns 61 and multiple second columns 62 are arranged alternately and repeatedly along the x-direction.

[0016] Multiple field relaxation layers 50 are arranged in contact with the upper surface of the SJ layer 60. Each of the multiple field relaxation layers 50 extends in the x-direction. That is, the direction in which the field relaxation layers 50 extend (x-direction) intersects with the direction in which the second column 62 extends (y-direction). An n-type semiconductor layer, an n-type layer 54, is arranged between adjacent field relaxation layers 50.

[0017] Each of the plurality of electric field relaxation layers 50 includes a first electric field relaxation layer 51 and a second electric field relaxation layer 52. The second electric field relaxation layer 52 is located below the first electric field relaxation layer 51. The p-type impurity concentration of the second electric field relaxation layer 52 is higher than the p-type impurity concentration of the second column 62. Further, the p-type impurity concentration of the first electric field relaxation layer 51 is higher than the p-type impurity concentration of the second electric field relaxation layer 52. A specific planar structure of the electric field relaxation layers 50 will be described later.

[0018] The current spreading layer 40 is disposed in contact with the upper surfaces of the electric field relaxation layer 50 and the n-type layer 54. The current spreading layer 40 is an n-type region having a lower n-type impurity concentration than the source region 30. The body region 34 is in contact with the upper surface of the current spreading layer 40. The body region 34 is a p-type region.

[0019] The plurality of source regions 30 are disposed on an upper portion of the body region 34 and exposed to the substrate surface 12a. The source regions 30 are separated from the current spreading layer 40 by the body region 34. Each source region 30 is an n-type region having a high impurity concentration. Each source region 30 is in contact with the gate insulating film 20a at the upper end of the side surface of the gate portion 20. Each source region 30 extends linearly along the y direction. Each source region 30 is in ohmic contact with the source electrode 14.

[0020] Multiple gate portions 20 are provided on the substrate surface 12a of the semiconductor substrate 12. Each gate portion 20 comprises a trench 20T, a gate insulating film 20a, a gate electrode 20b, and an upper insulating film 20c. The trench 20T is a trench that extends from the substrate surface 12a toward a deeper layer. The trench 20T penetrates the source region 30 and the body region 34 and reaches the current dispersion layer 40. The gate insulating film 20a covers the inner surface of the trench 20T. The gate electrode 20b is positioned within the gate insulating film 20a. The gate electrode 20b is insulated from the semiconductor substrate 12 by the gate insulating film 20a. The gate electrode 20b faces the body region 34 and the source region 30 via the gate insulating film 20a. The gate electrode 20b faces the body region 34, which separates the current dispersion layer 40 from the source region 30, via the gate insulating film 20a.

[0021] The upper surface of the gate electrode 20b is covered by the upper insulating film 20c. The upper surface of the upper insulating film 20c is covered by the interlayer insulating film 21. The gate electrode 20b is insulated from the source electrode 14 by the upper insulating film 20c and the interlayer insulating film 21. Each gate electrode 20b is connected to a gate pad located at a position not shown. The gate pad controls the potential of each gate electrode 20b.

[0022] In a vertical upward view, each of the multiple gate sections 20 extends continuously in the y-direction and is spaced apart in the x-direction. There are two types of distances between adjacent gate sections 20 in the x-direction: gate distance S1 and S2. Gate distance S2 is smaller than gate distance S1. The regularity of the arrangement of gate distances S1 and S2 in the x-direction can vary. In this embodiment, gate distances S1 and S2 are arranged alternately, one at a time. That is, the arrangement ratio of gate distances S1 and S2 is "1:1".

[0023] In the following, the region sandwiched between two gate sections 20 arranged with a gate-to-gate distance S1 is defined as the first opening region A1. The region sandwiched between two gate sections 20 arranged with a gate-to-gate distance S2 is defined as the second opening region A2. The first opening region A1 and the second opening region A2 extend continuously in the y-direction.

[0024] Multiple contact regions 32 are arranged within the first aperture region A1 and the second aperture region A2. Each contact region 32 is a p-type region with a high impurity concentration. Source regions 30 are adjacent to the ±x sides of the contact regions 32. Each contact region 32 extends linearly along the y direction and is exposed to the substrate surface 12a. Each contact region 32 is in ohmic contact with the source electrode 14.

[0025] The connection region 38 is located within the regions of multiple first aperture regions A1, but not within the regions of multiple second aperture regions A2. The connection region 38 is a p-type region. The p-type impurity concentration in the connection region 38 is lower than that of the contact region 32. Furthermore, the p-type impurity concentration in the connection region 38 is higher than that of the body region 34 and the second field relaxation layer 52.

[0026] In a vertical upward view, the connection region 38 is located within the area of ​​the contact region 32. The connection region 38 extends linearly along the y-direction. The width W1 of the connection region 38 in the x-direction is smaller than the width W2 of the contact region 32 in the x-direction. That is, the entirety of the connection region 38 overlaps with the contact region 32. The body region 34 is adjacent to the ±x-direction sides of the connection region 38. That is, the connection region 38 and the gate electrode 20b are located apart.

[0027] The upper end 38U of the connection region 38 is in contact with the lower end of the contact region 32. The upper part of the connection region 38 is in contact with the body region 34, and the lower part is in contact with the field relaxation layer 50. In other words, the connection region 38 electrically connects the contact region 32 and the body region 34 with the field relaxation layer 50. The lower end 38L of the connection region 38 is located below the lower end 51L of the first field relaxation layer 51. The lower end 38L is located above the lower end 52L of the second field relaxation layer 52. In other words, the upper end 62U of the second column 62 is separated from the lower end 51L of the first field relaxation layer 51 and the lower end 38L of the connection region 38.

[0028] (Planar structure of the field relaxation layer 50) Figure 4 shows a cross-sectional view along the line IV-IV in Figure 1. Figure 4 is a cross-sectional view in a plane passing through the connection region 38 and the gate portion 20. In other words, Figure 4 shows the field relaxation layer 50 viewed vertically upward. In Figure 4, the field relaxation layer 50 is shown with a dotted line. For clarity, the gate insulating film 20a and gate electrode 20b are omitted from the description.

[0029] The field relaxation layer 50 comprises multiple base portions 50a, first portions 50b, and second portions 50c. Each of the multiple base portions 50a extends continuously in the x-direction and is spaced apart in the y-direction. Each base portion 50a crosses multiple gate portions 20; that is, a portion of the base portion 50a overlaps with the gate portions 20. Furthermore, the multiple base portions 50a cross the connection region 38. As a result, the connection region 38 is electrically connected to the multiple base portions 50a along the y-direction.

[0030] Each first portion 50b extends continuously in the y-direction and overlaps with the connection region 38. Each second portion 50c extends continuously in the y-direction and overlaps with the gate portion 20.

[0031] (Operation of semiconductor device 1) The semiconductor device 1 is used with a potential higher than that applied to the source electrode 14 applied to the drain electrode 16. When a potential higher than the gate threshold is applied to the gate electrode 20b, a channel is formed in the area of ​​the body region 34 adjacent to the gate insulating film 20a. The channel connects the source region 30 and the current dispersion layer 40. Then, electrons flow from the source electrode 14 to the current dispersion layer 40 via the source region 30 and the channel. The electrons that flow into the current dispersion layer 40 flow to the drain electrode 16 via the n-type layer 54, the first column 61, the drift layer 41, and the drain layer 42.

[0032] When the potential of the gate electrode 20b is reduced to a potential below the gate threshold, the channel disappears and the semiconductor device 1 turns off. The SJ layer 60 is configured such that, in the repeating direction (x direction), the density of positive fixed charge when multiple first columns 61 are depleted and the density of negative fixed charge when multiple second columns 62 are depleted are balanced. Therefore, multiple first columns 61 and multiple second columns 62 are substantially completely depleted, and a wide area of ​​the SJ layer 60 is depleted. In addition, the electric field distribution of the SJ layer 60 is leveled in the depth direction. As a result, the SJ layer 60 can bear a large potential difference, and the semiconductor device 1 can have the characteristic of high breakdown voltage.

[0033] Furthermore, when the semiconductor device 1 is turned off, the potentials of the n-type layer 54 and the current-dispersing layer 40 rise. Since the field-relaxing layer 50 is connected to the source electrode 14 via the connection region 38 and the contact region 32, the field-relaxing layer 50 has approximately the same potential as the source electrode 14. Therefore, when the potentials of the n-type layer 54 and the current-dispersing layer 40 rise, a reverse voltage is applied to the pn junction interface between the n-type layer 54 and the field-relaxing layer 50, and to the pn junction interface between the current-dispersing layer 40 and the field-relaxing layer 50. Consequently, a depletion layer spreads from the field-relaxing layer 50 to the n-type layer 54 and the current-dispersing layer 40. This spreading of the depletion layer can suppress the electric field generated at the lower end of the gate portion 20. In particular, since the field-relaxing layer 50 has approximately the same potential as the source electrode 14, it is possible to effectively suppress the electric field generated at the lower end of the gate portion 20.

[0034] (effect) When the semiconductor device 1 is turned off, the current flowing through the semiconductor device 1 decreases sharply, so a high surge voltage is applied to the semiconductor device 1. This generates a high electric field, which may cause an avalanche current to occur. In this embodiment, the semiconductor device 1 has a structure in which the electric field relaxation layer 50 is connected to the source electrode 14 via a connection region 38 and a contact region 32. The electric field relaxation layer 50 has a potential approximately the same as that of the source electrode 14. Therefore, when an avalanche current is generated, the avalanche current flows into the electric field relaxation layer 50 and flows to the source electrode 14 via the connection region 38. In this embodiment, the gate-to-gate distance S1 of the first aperture region A1 is wider than the gate-to-gate distance S2 of the second aperture region A2, and the connection region 38 is selectively placed in the first aperture region A1. Therefore, the area of ​​the connection region 38 can be increased compared to when the connection region 38 is placed in the second aperture region A2, and the electrical resistance of the connection region 38 can be reduced. This makes it possible to suppress the voltage drop generated in the connection region 38 by the avalanche current, thereby stabilizing the potential of the electric field relaxation layer 50. This also makes it possible to suppress the degradation of the gate insulating film 20a.

[0035] In this embodiment, the semiconductor device 1 is equipped with an SJ layer 60. The p-type impurity concentration in the field relaxation layer 50 is higher than the p-conductivity impurity concentration in the second column 62 and body region 34 of the SJ layer 60. By increasing the concentration of the field relaxation layer 50, the electrical resistance of the field relaxation layer 50 can be reduced, thereby suppressing the voltage drop that occurs in the field relaxation layer 50. Furthermore, by lowering the concentration of the second column 62, the depletion layer can be spread throughout the entire SJ layer 60, thereby improving the breakdown voltage. This makes it possible to achieve both improved reliability of the gate insulating film 20a and improved breakdown voltage of the semiconductor device 1.

[0036] The connection region 38 is electrically connected to multiple base portions 50a along the y-direction (see Figure 4). This allows the avalanche current flowing from the multiple base portions 50a to be concentrated in the low-resistance connection region 38 and then passed to the source electrode 14.

[0037] In a vertical upward view, the first portion 50b of the field relaxation layer 50 overlaps with the connection region 38 (see Figure 4). This increases the contact area between the connection region 38 and the field relaxation layer 50, thereby reducing electrical resistance. This suppresses the voltage drop during avalanche operation, making it possible to stabilize the potential of the field relaxation layer 50.

[0038] In a vertical upward view, the second portion 50c of the electric field relaxation layer 50 overlaps with the gate portion 20 (see Figure 4). This allows the electric field relaxation layer 50 to be placed along the entire length in the y-direction directly below the gate portion 20, thereby enhancing the electric field relaxation effect in the gate insulating film 20a.

[0039] The field relaxation layer 50 includes a first field relaxation layer 51 (high-concentration p-layer) and a second field relaxation layer 52 (low-concentration p-layer) located below it. This allows the depletion layer to spread within the low-concentration second field relaxation layer 52 when a reverse bias is applied, thereby further improving the breakdown voltage. In addition, the high-concentration first field relaxation layer 51 can reduce the resistance of the avalanche current discharge path.

[0040] The lower end 38L of the connection region 38 is located below the lower end 51L of the first field relaxation layer 51. This allows the connection region 38 (high-concentration p-layer) to penetrate the second field relaxation layer 52 (low-concentration p-layer). In the area where the connection region 38 penetrates, the volume of the low-concentration second field relaxation layer 52 decreases, making it difficult for the depletion layer to spread. As a result, the breakdown voltage of the second field relaxation layer 52 can be locally reduced only in the area where the connection region 38 penetrates. This limits the location of hole generation due to avalanche to the area where the connection region 38 penetrates. Since avalanche current can be prevented from occurring near the gate portion 20, the degradation of the gate insulating film 20a can be suppressed.

[0041] When the connection region 38 is formed with a high concentration using ion implantation, the crystal defect density in the connection region 38 increases. Therefore, when an electric field is applied, there is a risk of leakage current being generated in the connection region 38. In this embodiment, the semiconductor device 1 is positioned so that the lower end 38L of the connection region 38 is above the lower end 52L of the second electric field relaxation layer 52. By creating a structure in which the lower end 38L of the connection region 38 is surrounded by a low-concentration second electric field relaxation layer 52, the electric field applied to the connection region 38 can be reduced. This makes it possible to suppress the generation of leakage current.

[0042] The upper end 62U of the second column 62 is separated from the lower end 51L of the first field relaxation layer 51 and the lower end 38L of the connection region 38. This allows the second column 62 to have a structure that does not overlap in the depth direction with the high-concentration first field relaxation layer 51 and connection region 38. This makes it possible to suppress the decrease in breakdown voltage caused by an imbalance in the charge balance of the SJ layer 60.

[0043] In a vertical upward view, the gate portion 20 and the connection region 38 are positioned separately. This allows the connection region 38, which is the current path for the avalanche current, to be separated from the gate insulating film 20a. This prevents the gate insulating film 20a from degrading due to localized heat generation (temperature gradient) caused by the avalanche current.

[0044] The upper end 38U of the connection region 38 is in contact with the contact region 32. As a result, the current path from the connection region 38 to the source electrode 14 does not pass through the body region 34, which has a low concentration and high electrical resistance. This reduces the resistance of the avalanche current discharge path.

[0045] During avalanche operation, if the avalanche current flows laterally within the body region 34, a potential gradient is generated within the body region 34. As a result, the semiconductor device 1 may malfunction. Therefore, in the semiconductor device 1 of this embodiment, the connection region 38 is positioned within the area of ​​the contact region 32 when viewed vertically upward. This makes it possible to realize a structure in which the entire upper end 38U of the connection region 38 is in contact with the contact region 32. Thus, the avalanche current passing through the connection region 38 can be directed upward towards the source electrode 14 along the shortest distance. This makes it possible to suppress the generation of a potential gradient within the body region 34.

[0046] (Modified version of Example 1) In Example 1, the case where the arrangement ratio of gate distance S1 and S2 is "1:1" was described, but the invention is not limited to this form. For example, as shown in Figure 5, the arrangement ratio may be "1:2". Note that in Figure 5, only 20 and the connection area 38 are shown, and the illustration of other parts is omitted. Also, for example, the arrangement ratio may be "1:3", "1:4", etc. The higher the arrangement ratio of gate distance S2, the higher the arrangement density of the gate portion 20 can be, and thus the lower the on-resistance of the semiconductor device 1 can be.

[0047] The description has described a case where the arrangement ratio of gate distances S1 and S2 is the same throughout the entire chip of the semiconductor device 1, but the invention is not limited to this configuration. The arrangement ratio may differ between the inner region of the chip and the outer region of the chip when viewed vertically upward. For example, the arrangement ratio of gate distances S2 may be lower in the outer region of the chip than in the inner region of the chip. That is, the arrangement density of connection regions 38 may be higher in the outer region of the chip than in the inner region of the chip. The higher the arrangement density of connection regions 38, the greater the amount of heat generated when an avalanche current flows. Therefore, by placing regions that generate a large amount of heat in the outer region of the chip, where heat is less likely to accumulate and heat dissipation is higher, it is possible to improve the heat resistance of the semiconductor device 1. [Examples]

[0048] (Configuration of semiconductor device 201) In Example 1, a configuration was described in which, when viewed vertically upward, multiple gate portions 20 extend in the y-direction and are arranged in a stripe pattern. On the other hand, in Example 2, a configuration is described in which multiple gate portions 220 extend in the x and y directions and are arranged to have intersecting portions. Furthermore, in Example 2, a configuration comprising a planar type gate portion 220 is described.

[0049] Figures 6 and 7 show cross-sectional views of the main parts of the semiconductor device 201 according to Example 2. Figure 8 shows a plan view of the semiconductor device 201 viewed vertically from above. In Figure 8, the source electrode 14 is omitted for clarity. The gate portion 220 is shown with hatching, and the field relaxation layer 50 is shown with a dotted line. Figure 6 is a cross-sectional view taken along the line VI-VI in Figure 8. Figure 7 is a cross-sectional view taken along the line VII-VII in Figure 8. That is, Figure 6 is a cross-sectional view passing through the field relaxation layer 50, and Figure 7 is a cross-sectional view passing through the n-type layer 54. Note that parts common to the semiconductor device 201 of Example 2 and the semiconductor device 1 of Example 1 are given the same reference numerals, and their explanation is omitted. Furthermore, only the contents specific to the semiconductor device 201 of Example 2 will be described below.

[0050] The planar structure of the semiconductor device 201 will be explained using Figure 8. The gate portion 220 extends in the y-direction and the x-direction. Multiple rectangular opening regions are formed in the area enclosed by the gate portion 220. There are two types of opening regions: a first opening region A201 and a second opening region A202. The first opening region A201 has a side length Sx1 in the x-direction and a side length Sy1 in the y-direction. In this embodiment, the side length Sx1 is smaller than the side length Sy1. The second opening region A202 has a side length Sx2 in the x-direction and a side length Sy2 in the y-direction. In this embodiment, the side length Sx2 is smaller than the side length Sy2. Furthermore, the minimum side length of the second opening region A202 (side length Sx2) is smaller than the minimum side length of the first opening region A201 (side length Sx1).

[0051] The connection regions 38 are located within the areas of multiple first aperture regions A201, but not within the areas of multiple second aperture regions A202. In other words, the connection regions 38 are scattered in a dot-like pattern when viewed vertically upward.

[0052] The cross-sectional structure of the semiconductor device 201 will be explained using Figures 6 and 7. The semiconductor device 201 includes an n-type JFET region 244. The JFET region 244 is located in contact with the upper surface of the current dispersion layer 40 and is exposed to the substrate surface 12a. The n-type impurity concentration of the current dispersion layer 40 is higher than that of the JFET region 244. The body region 34 is located adjacent to the JFET region 244. The source region 30 is separated from the current dispersion layer 40 and the JFET region 244 by the body region 34. A channel region CR is formed in the body region 34 that separates the JFET region 244 and the source region 30.

[0053] The gate portion 220 is a planar electrode portion. The gate portion 220 is positioned opposite the JFET region 244 and the channel region CR. The gate portion 220 comprises a gate insulating film 220a and a gate electrode 220b. The gate insulating film 220a is positioned on the substrate surface 12a. The gate electrode 220b is positioned on the upper surface of the gate insulating film 220a. The upper surface of the gate electrode 220b is covered by an interlayer insulating film 221. The gate electrode 220b is insulated from the source electrode 14 by the interlayer insulating film 221.

[0054] The contact area 32 is located within both the first opening area A201 and the second opening area A202. Within the first opening area A201, a connecting area 38 is positioned so as to be in contact with the lower end of the contact area 32. On the other hand, within the second opening area A202, no connecting area 38 is positioned below the contact area 32. The width W3 of the contact area 32 within the second opening area A202 is smaller than the width W2 of the contact area 32 within the first opening area A201.

[0055] (effect) The semiconductor device 201 of Example 2 can also obtain the same effects as the semiconductor device 1 of Example 1. Specifically, by selectively arranging the connection region 38 in the large area first aperture region A201, the area of ​​the connection region 38 can be increased, thereby reducing electrical resistance. Furthermore, since the breakdown voltage can be maintained by the SJ layer 60, it becomes possible to increase the density of the field relaxation layer 50, and thus reduce the resistance of the field relaxation layer 50. As a result, the voltage drop generated in the field relaxation layer 50 by the avalanche current can be suppressed, and the potential of the field relaxation layer 50 can be stabilized.

[0056] By extending the gate portion 220 in both the x and y directions, the arrangement density of the gate portion 220 can be increased compared to the case where it is extended in only one direction. Furthermore, in the area where the connection region 38 is not placed (second aperture region A202), the arrangement density of the gate portion 220 can be increased by reducing the aperture area. As a result, the arrangement density of the channel region CR can be increased, making it possible to reduce the channel resistance of the semiconductor device 1.

[0057] By distributing the connection regions 38 in a dot-like pattern, the area ratio of the region where the gate portion 220 can be placed can be increased, and the gate portion 220 can be uniformly arranged. This makes it possible to reduce the channel resistance of the semiconductor device 1 and to make the channel resistance uniform within the plane.

[0058] By electrically connecting the body region 34 and the field relaxation layer 50 via the connection region 38, the current distribution layer 40 can be placed between the body region 34 and the field relaxation layer 50. As a result, as shown by arrow Y1 in Figure 6, electrons flowing from the channel region CR can be widely dispersed laterally with a small voltage drop through the low-resistance current distribution layer 40 and flow to the SJ layer 60. Therefore, the layout of the gate portion 220 and the pitch of the SJ layer 60 can be individually and optimally designed. This makes it possible to achieve both a reduction in on-resistance and an improvement in breakdown voltage.

[0059] (Modified version of Example 2) In Example 2, a case was described in which there are two types of first opening regions A201 and second opening regions A202, each having a different opening area, but the system is not limited to this configuration. There may be three or more types of opening regions, each having a different opening area. In this case, the opening region with the smallest side length among the three or more types of opening regions corresponds to the second opening region A202. Therefore, the opening region with the smallest side length does not have a connecting region 38. Note that the smallest side length may be either side length Sx or side length Sy.

[0060] The gate portion 220 may extend in various ways in the x and y directions. In Figure 8 of Embodiment 2, the gate portion 220 extends linearly in both the x and y directions and is arranged in a grid pattern, but the embodiment is not limited to this embodiment. As shown in the example in Figure 9, the gate portion 220 may extend linearly in the y direction and in a zigzag pattern in the x direction and be arranged in a ladder pattern.

[0061] The gate portion 220 extending in the x and y directions, as described in Example 2, is not limited to a planar type. It may also be a trench type, as described in Example 1.

[0062] (modified version) The following describes possible modifications that can be used in each of the above embodiments.

[0063] In the above embodiment, the case in which the second column 62 extends in the y direction and the field relaxation layer 50 extends in the x direction was described, but the embodiment is not limited to this. The direction in which the second column 62 and the field relaxation layer 50 extend may be any direction in which they intersect when viewed vertically upward. For example, the second column 62 and the field relaxation layer 50 may intersect at a 45° angle.

[0064] In the above embodiment, the case in which the field relaxation layer 50 extends in the x direction and the gate portion 20 extends in the y direction was described, but the embodiment is not limited to this. The direction in which the field relaxation layer 50 and the gate portion 20 extend may be any direction in which they intersect when viewed vertically upward. For example, the field relaxation layer 50 and the gate portion 20 may intersect at a 45° angle.

[0065] In the above embodiment, the switching element was a MOSFET, but the configuration is not limited to this, and various elements such as IGBTs can be applied. For example, in a MOSFET, an IGBT structure can be obtained by replacing the n-type drain layer 42 with a p-type collector layer. In this case, the source and drain can be rephrased as emitter and collector.

[0066] The configuration of the technology disclosed herein is listed below. [Configuration 1] A semiconductor device (1) comprising: a lower electrode (16); a semiconductor substrate (12) disposed in contact with the upper surface of the lower electrode and having a source region and a body region; a plurality of gate portions (20) facing the body region and the source region; and an upper electrode (14) disposed on the substrate surface (12a) of the semiconductor substrate and electrically connected to the source region and the body region, The aforementioned semiconductor substrate is A superjunction layer (60) located above the lower electrode, wherein a first column (61) of a first conductivity type (n-type) extending in a first direction (y) and a second column (62) of a second conductivity type (p-type) extending in the first direction are alternately and repeatedly arranged along a second direction (x) intersecting the first direction, A plurality of second conductivity type (p-type) field relaxation layers (50) are arranged in contact with the upper surface of the superjunction layer, extending in a third direction (x) intersecting the first direction, with first conductivity type semiconductor layers (54) arranged between adjacent field relaxation layers, A first conductivity type current dispersion layer (40) is disposed in contact with the upper surface of the electric field relaxation layer, The second conductive body region (34) is in contact with the upper surface of the current dispersion layer, A second conductive type connection region (38) whose upper part is in contact with the body region and whose lower part is in contact with the electric field relaxation layer, the connection region electrically connects the body region and the electric field relaxation layer, The first conductivity type source region (30) is located at the upper part of the body region and is exposed on the substrate surface of the semiconductor substrate, It has, The concentration of the second conductivity type impurity in the field relaxation layer is higher than the concentration of the second conductivity type impurity in the second column. In a vertical upward view of the substrate surface of the semiconductor substrate, a portion of the field relaxation layer overlaps with the gate portion. In the aforementioned vertical upward view, between adjacent gate portions, there are multiple first opening regions (A1) where the distance between gates is a first distance (S1), and multiple second opening regions (A2) where the distance between gates is a second distance (S2) smaller than the first distance. The connection region is located in at least one of the plurality of first opening regions, and is not located in the plurality of second opening regions. Semiconductor equipment. [Configuration 2] The semiconductor device according to configuration 1, wherein the concentration of the second conductivity type impurity in the connection region is higher than the concentration of the second conductivity type impurity in the body region. [Configuration 3] Each of the multiple gate portions and each of the multiple first opening regions extends continuously in a fourth direction (y) intersecting the third direction. The connection region extends continuously in the fourth direction within the first opening region. The semiconductor device according to configuration 1 or 2, wherein the connection region is electrically connected to a plurality of the field relaxation layers along the fourth direction. [Structure 4] The multiple electric field relaxation layers further comprise a first portion (50b) that extends continuously in the fourth direction, The semiconductor device according to configuration 3, wherein, in the aforementioned vertical upward view, the first portion overlaps with the connection region. [Composition 5] The multiple electric field relaxation layers further comprise a second portion (50c) that extends continuously in the fourth direction, The semiconductor device according to configuration 3 or 4, wherein, in the aforementioned vertical upward view, the second portion overlaps with the gate portion. [Composition 6] The electric field relaxation layer includes a first electric field relaxation layer (51) and a second electric field relaxation layer (52) located below the first electric field relaxation layer. The semiconductor device according to any one of configurations 1-5, wherein the concentration of the second conductivity type impurity in the first field relaxation layer is higher than the concentration of the second conductivity type impurity in the second field relaxation layer. [Composition 7] The semiconductor device according to configuration 6, wherein the lower end of the connection region is located below the lower end of the first field relaxation layer. [Structure 8] The semiconductor device according to configuration 6 or 7, wherein the lower end of the connection region is located above the lower end of the second field relaxation layer. [Composition 9] The semiconductor device according to any one of configurations 6-8, wherein the upper end of the second column is separated from the lower end of the first field relaxation layer and the lower end of the connection region. [Configuration 10] The gate portion extends in a fourth direction (y) intersecting the third direction, and also extends in a fifth direction (x) perpendicular to the fourth direction. In the aforementioned vertical upward view, multiple rectangular opening regions are formed, surrounded by the gate portion. A semiconductor device according to any one of configurations 1-3, wherein the plurality of aperture regions include a first aperture region whose minimum side length is the first distance and a second aperture region whose minimum side length is the second distance. [Composition 11] The source region is separated from the current distribution layer by the body region. A trench (20T) is formed that extends from the substrate surface through the source region and the body region and into the depths to reach the current dispersion layer. The gate portion includes a gate electrode (20b) disposed inside the trench via a gate insulating film (20a), The gate electrode faces the body region that separates the current dispersion layer from the source region, via the gate insulating film. A semiconductor device as described in any one of configurations 1-10. [Composition 12] The gate portion is a planar type electrode portion arranged on the substrate surface via a gate insulating film. The semiconductor device is arranged in contact with the upper surface of the current dispersion layer and includes a first conductivity type JFET region (244) that is positioned to be exposed on the substrate surface. The body region is arranged adjacent to the JFET region, The source region is separated from the current distribution layer and the JFET region by the body region. The semiconductor device according to any one of configurations 1-10, wherein the gate portion is arranged to face the JFET region and also to face the body region that separates the JFET region and the source region. [Composition 13] A semiconductor device according to any one of configurations 1-12, wherein, in the aforementioned vertical upward view, the gate portion and the connection region are arranged separately. [Composition 14] The semiconductor device further comprises a second conductivity type contact region (32) which is positioned on the substrate surface, adjacent to the source region, and in contact with the upper electrode. The upper end (38U) of the connection area is in contact with the contact area. The semiconductor device according to any one of configurations 1-13, wherein the concentration of the second conductivity type impurity in the contact region is higher than the concentration of the second conductivity type impurity in the connection region. [Composition 15] The semiconductor device according to configuration 14, wherein, in the aforementioned vertical upward view, the connection region is located within the region of the contact region.

[0067] According to configuration 2, the electrical resistance of the connection region can be reduced. This makes it possible to suppress the voltage drop that occurs in the connection region due to avalanche current.

[0068] According to configuration 3, avalanche currents flowing from multiple field relaxation layers can be concentrated into a low-resistance connection region.

[0069] According to configuration 4, electrical resistance can be reduced by increasing the contact area between the connection region and the electric field relaxation layer.

[0070] According to configuration 5, an electric field relaxation layer can be placed directly below the gate section, extending along the entire length of the gate section. This makes it possible to enhance the electric field relaxation effect in the gate section.

[0071] According to configuration 6, the depletion layer can be extended within the low-concentration second field relaxation layer, thereby further improving the breakdown voltage. In addition, the high-concentration first field relaxation layer can reduce the resistance of the avalanche current discharge path.

[0072] According to configuration 7, the connection region can be made to penetrate the second electric field relaxation layer. The location of holes generated by the avalanche can be limited to the area in which the connection region penetrates.

[0073] According to configuration 8, by creating a structure in which the lower end of the connection region is surrounded by a second electric field relaxation layer, the electric field applied to the connection region can be reduced.

[0074] According to configuration 9, the second column can be structured so that it does not overlap with the first field relaxation layer and connection region in the depth direction. This makes it possible to suppress the decrease in breakdown voltage caused by an imbalance in the charge balance of the superjunction layer.

[0075] According to configuration 10, by extending the gate portion in both the fourth and fifth directions, the density of the gate portion can be increased compared to the case where it is extended in only one direction.

[0076] According to configuration 11, a trench-shaped gate section can be formed.

[0077] According to configuration 12, a planar gate section can be constructed.

[0078] According to configuration 13, it is possible to prevent the gate portion from deteriorating due to localized heat generation caused by avalanche current.

[0079] According to configuration 14, the resistance of the avalanche current discharge path can be reduced.

[0080] According to configuration 15, it is possible to suppress the generation of a potential gradient within the body region 34.

[0081] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0082] 1: Semiconductor device 16: Drain electrode 14: Source electrode 20: Gate region 12: Semiconductor substrate 12a: Substrate surface 30: Source region 38: Connection region 34: Body region 40: Current dispersion layer 50: Field relaxation layer 54: n-type layer 60: SJ layer 61: First column 62: Second column

Claims

1. A semiconductor device (1) comprising: a lower electrode (16); a semiconductor substrate (12) arranged in contact with the upper surface of the lower electrode and having a source region and a body region; a plurality of gate portions (20) facing the body region and the source region; and an upper electrode (14) arranged on the substrate surface (12a) of the semiconductor substrate and electrically connected to the source region and the body region, The aforementioned semiconductor substrate is A superjunction layer (60) located above the lower electrode, wherein a first column (61) of a first conductivity type (n-type) extending in a first direction (y) and a second column (62) of a second conductivity type (p-type) extending in the first direction are alternately and repeatedly arranged along a second direction (x) intersecting the first direction, A plurality of second conductivity type (p-type) field relaxation layers (50) are arranged in contact with the upper surface of the superjunction layer, extending in a third direction (x) intersecting the first direction, with a first conductivity type semiconductor layer (54) arranged between adjacent field relaxation layers, A first conductivity type current dispersion layer (40) is disposed in contact with the upper surface of the electric field relaxation layer, The second conductive body region (34) is in contact with the upper surface of the current dispersion layer, A second conductive type connection region (38) whose upper part is in contact with the body region and whose lower part is in contact with the electric field relaxation layer, the connection region electrically connects the body region and the electric field relaxation layer, The first conductivity type source region (30) is located at the upper part of the body region and is exposed on the substrate surface of the semiconductor substrate, It has, The concentration of the second conductivity type impurity in the field relaxation layer is higher than the concentration of the second conductivity type impurity in the second column. In a vertical upward view of the substrate surface of the semiconductor substrate, a portion of the field relaxation layer overlaps with the gate portion. In the aforementioned vertical upward view, between adjacent gate portions, there are multiple first opening regions (A1) where the distance between gates is a first distance (S1), and multiple second opening regions (A2) where the distance between gates is a second distance (S2) smaller than the first distance. The connection region is located in at least one of the plurality of first opening regions, and is not located in the plurality of second opening regions. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the connection region is higher than the concentration of the second conductivity type impurity in the body region.

3. Each of the multiple gate portions and each of the multiple first opening regions extends continuously in a fourth direction (y) intersecting the third direction. The connection region extends continuously in the fourth direction within the first opening region. The semiconductor device according to claim 1, wherein the connection region is electrically connected to a plurality of the field relaxation layers along the fourth direction.

4. Each of the aforementioned electric field relaxation layers further comprises a first portion (50b) that extends continuously in the fourth direction, The semiconductor device according to claim 3, wherein, in the aforementioned vertical upward view, the first portion overlaps with the connection region.

5. The multiple electric field relaxation layers further comprise a second portion (50c) that extends continuously in the fourth direction, The semiconductor device according to claim 3, wherein, in the aforementioned vertical upward view, the second portion overlaps with the gate portion.

6. The electric field relaxation layer includes a first electric field relaxation layer (51) and a second electric field relaxation layer (52) located below the first electric field relaxation layer. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the first field relaxation layer is higher than the concentration of the second conductivity type impurity in the second field relaxation layer.

7. The semiconductor device according to claim 6, wherein the lower end of the connection region is located below the lower end of the first field relaxation layer.

8. The semiconductor device according to claim 7, wherein the lower end of the connection region is located above the lower end of the second field relaxation layer.

9. The semiconductor device according to claim 6, wherein the upper end of the second column is separated from the lower end of the first field relaxation layer and the lower end of the connection region.

10. The gate portion extends in a fourth direction (y) intersecting the third direction, and also extends in a fifth direction (x) perpendicular to the fourth direction. In the aforementioned vertical upward view, multiple rectangular opening regions are formed, surrounded by the gate portion. The semiconductor device according to claim 1, wherein the plurality of aperture regions include a first aperture region whose minimum side length is the first distance and a second aperture region whose minimum side length is the second distance.

11. The source region is separated from the current distribution layer by the body region. A trench (20T) is formed that extends from the substrate surface through the source region and the body region and toward the depths to reach the current dispersion layer. The gate portion includes a gate electrode (20b) disposed inside the trench via a gate insulating film (20a), The gate electrode faces the body region, which separates the current dispersion layer from the source region, via the gate insulating film. The semiconductor device according to claim 1.

12. The gate portion is a planar type electrode portion arranged on the substrate surface via a gate insulating film. The semiconductor device is arranged in contact with the upper surface of the current dispersion layer and includes a first conductivity type JFET region (244) that is positioned to be exposed on the substrate surface. The body region is arranged adjacent to the JFET region, The source region is separated from the current distribution layer and the JFET region by the body region. The semiconductor device according to claim 1, wherein the gate portion is arranged to face the JFET region and also to face the body region that separates the JFET region and the source region.

13. The semiconductor device according to any one of claims 1 to 12, wherein, in the aforementioned vertical upward view, the gate portion and the connection region are arranged separately.

14. The semiconductor device further comprises a second conductivity type contact region (32) which is positioned on the substrate surface, adjacent to the source region, and in contact with the upper electrode. The upper end (38U) of the connection area is in contact with the contact area. The semiconductor device according to any one of claims 1 to 12, wherein the concentration of the second conductivity type impurity in the contact region is higher than the concentration of the second conductivity type impurity in the connection region.

15. The semiconductor device according to claim 14, wherein, in the aforementioned vertical upward view, the connection region is located within the region of the contact region.

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