Gate driver circuit, motor drive device using the same, electronic equipment
Patent Information
- Application Number
- JP2025031839
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-09-09
Smart Images
Figure 2026144509000001_ABST
Abstract
Description
[Technical Field]
[0001] This disclosure relates to a gate driver circuit. [Background technology]
[0002] Half-bridge circuits, H-bridge circuits, and three-phase bridge circuits (hereinafter collectively referred to as switching circuits) using power transistors are used in motor driver circuits, DC / DC converters, power conversion devices, and the like.
[0003] The switching circuit comprises a bridge circuit (inverter circuit) including a high-side transistor and a low-side transistor, and a gate driver circuit that drives the high-side transistor and the low-side transistor. The switching circuit controls the high-side transistor and the low-side transistor in response to control signals from an external controller, such as a microcontroller or an ASIC (Application Specific Integrated Circuit).
[0004] The input interfaces of gate driver circuits can be broadly classified into two types. The first interface, similar to a three-state buffer, controls the on / off states of the high-side transistor MH and the low-side transistor ML using a control signal that is a combination of an enable signal EN and a pulse modulation signal PWM. The truth table for this interface is as follows. (EN,PWM)⇒(MH,ML) (0,0) ⇒(OFF,OFF) (0,1) ⇒(OFF,OFF) (1,0) ⇒(OFF,ON) (1,1) ⇒ (ON,OFF) This interface is called the EN-PWM format.
[0005] Another interface directly controls the on / off states of the high-side transistor MH and the low-side transistor ML using two control signals, HIN and LIN. The truth table for this interface is as follows: (HIN,LIN)⇒(MH,ML) (0,0) ⇒(OFF,OFF) (0,1) ⇒ (OFF,ON) (1,0) ⇒(ON,OFF) (1,1) ⇒ (OFF,OFF) This interface is called the IN-IN format.
[0006] [overview] Some gate driver circuits employ a control mechanism (called zero dead time control) that minimizes the dead time period (high impedance section) during which both the high-side and low-side transistors are simultaneously off, in order to reduce losses in the switching circuit.
[0007] The inventors of this invention have investigated the combination of zero-dead-time control and IN-IN configuration and have come to recognize the following problems. When zero-dead-time control is performed, the external controller changes the control signals HIN and LIN complementaryly. However, due to the delay in the transmission path of the control signals between the external controller and the gate driver circuit, a slight discrepancy may occur between the two input signals HIN and LIN received by the gate driver circuit. In this case, the gate driver circuit determines that the external controller is instructing (MH,ML)=(OFF,OFF), inserts a narrow high-impedance section, and causes an unintended malfunction by the external controller.
[0008] This disclosure is made in such circumstances, and one exemplary objective of a certain aspect thereof is to provide a gate driver circuit having an IN-IN interface that is less prone to malfunction.
[0009] A part of this disclosure relates to a gate driver circuit for driving high-side transistors and low-side transistors constituting a switching circuit. The gate driver circuit includes a first input terminal that receives an input high-side signal instructing the on or off of a high-side transistor in a first mode, a second input terminal that receives an input low-side signal instructing the on or off of a low-side transistor in a first mode, a logic circuit that converts the pair of input high-side and input low-side signals into a pair of internal enable signal and internal pulse modulation signal, a low-pass filter that receives the internal enable signal and internal pulse modulation signal and generates an output enable signal and an output pulse modulation signal, a high-side driver for driving the high-side transistor, a low-side driver for driving the low-side transistor, and a control circuit that receives the output enable signal and output pulse modulation signal and controls the high-side driver and the low-side driver based on dead-time zero control.
[0010] Furthermore, any combination of the above components, and any substitution of the components or expressions of this disclosure between methods, apparatus, systems, etc., are also valid embodiments of the present invention. [Brief explanation of the drawing]
[0011] [Figure 1] Figure 1 is a circuit diagram of a switching circuit equipped with a gate driver circuit related to the comparative technology. [Figure 2] Figure 2 is a time chart illustrating the zero-dead-time control of the switching circuit shown in Figure 1. [Figure 3] Figure 3 is a diagram illustrating the operation of the switching circuit shown in Figure 1. [Figure 4] Figure 4 is a circuit diagram of a switching circuit equipped with a gate driver circuit according to an embodiment. [Figure 5] Figure 5 is a time chart illustrating the operation of the gate driver circuit shown in Figure 4. [Figure 6] Figure 6 is a circuit diagram of a gate driver circuit according to Modification 1. [Figure 7] Figure 7 is a circuit diagram of a gate driver circuit according to modified example 2. [Figure 8] Figure 8 is a circuit diagram of the gate driver circuit according to Modification Example 3. [Figure 9] Figure 9 is a circuit diagram of a motor drive device according to an embodiment.
[0012] [Detailed explanation] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow later, and is not intended to limit the scope of the invention or disclosure. For convenience, “one embodiment” may be used to refer to one embodiment (example or variation) or more embodiments (example or variation) disclosed herein.
[0013] This summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to define the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that will follow.
[0014] A gate driver circuit according to one embodiment drives a high-side transistor and a low-side transistor that constitute a switching circuit. The gate driver circuit comprises: a first input terminal that receives an input high-side signal instructing turning on and off of the high-side transistor in a first mode; a second input terminal that receives an input low-side signal instructing turning on and off of the low-side transistor in the first mode; a logic circuit that converts a pair of the input high-side signal and the input low-side signal into a pair of an internal enable signal and an internal pulse modulation signal; a low-pass filter that receives the internal enable signal and the internal pulse modulation signal and generates an output enable signal and an output pulse modulation signal; a high-side driver that drives the high-side transistor; a low-side driver that drives the low-side transistor; and a control circuit that receives the output enable signal and the output pulse modulation signal and controls the high-side driver and the low-side driver based on zero dead time control.
[0015] According to this configuration, an input signal in IN-IN format is converted into a signal in EN-PWM format inside the gate driver circuit, and low-pass filter processing is performed on the enable signal and the pulse modulation signal, whereby short negation of the enable signal is masked. Therefore, generation of an unintended short high-impedance interval can be suppressed.
[0016] In one embodiment, the gate driver circuit may further comprise: a high-side turn-off detection circuit that asserts a high-side off detection signal when detecting turn-off of the high-side transistor based on a gate signal of the high-side driver; and a low-side turn-off detection circuit that asserts a low-side off detection signal when detecting turn-off of the low-side transistor based on a gate signal of the low-side driver. The control circuit may perform zero dead time control using the high-side off detection signal and the low-side off detection signal.
[0017] In one embodiment, the first input terminal may be capable of receiving either an input pulse modulation signal indicating the output level of the switching circuit or an input enable signal indicating whether the output of the switching circuit is high impedance or not, in the second mode. The second input terminal may be capable of receiving the other of the input pulse modulation signal and the input enable signal, in the second mode. The low-pass filter may be disabled in the second mode. The gate driver circuit may further include a first selector that receives an internal enable signal and an input enable signal, and in the first mode selects the internal enable signal and supplies it to the low-pass filter, and in the second mode selects the input enable signal and supplies it to the low-pass filter, and a second selector that receives an internal pulse modulation signal and an input pulse modulation signal, and in the first mode selects the internal pulse modulation signal and supplies it to the low-pass filter, and in the second mode selects the input pulse modulation signal and supplies it to the low-pass filter.
[0018] This configuration allows the gate driver circuit to be used in combination with either an external controller having an IN-IN output interface or an external controller having an EN-PWM output interface.
[0019] In one embodiment, the first input terminal may be capable of receiving either an input pulse modulation signal indicating the output level of the switching circuit or an input enable signal indicating whether the output of the switching circuit is high impedance or not, in the second mode. The second input terminal may be capable of receiving the other of the input pulse modulation signal and the input enable signal, in the second mode. The gate driver circuit may further include a first selector that receives an output enable signal and an input enable signal, and in the first mode selects the output enable signal and supplies it to the low-pass filter, and in the second mode selects the input enable signal and supplies it to the low-pass filter, and a second selector that receives an output pulse modulation signal and an input pulse modulation signal, and in the first mode selects the output pulse modulation signal and supplies it to the low-pass filter, and in the second mode selects the input pulse modulation signal and supplies it to the low-pass filter.
[0020] This configuration allows the gate driver circuit to be used in combination with either an external controller having an IN-IN output interface or an external controller having an EN-PWM output interface.
[0021] In one embodiment, the gate driver circuit may be integrated onto a single semiconductor substrate. "Integrated integration" includes cases where all the circuit components are formed on the semiconductor substrate, or where the main components of the circuit are integrated, and some resistors, capacitors, etc., may be provided outside the semiconductor substrate for adjusting circuit constants. Integrating the circuit onto a single chip can reduce the circuit area and maintain uniformity of the characteristics of the circuit elements.
[0022] A motor drive device according to one embodiment may include a bridge circuit including a high-side transistor and a low-side transistor, and any of the above-described gate driver circuits for driving the high-side transistor and the low-side transistor.
[0023] An electronic device according to one embodiment may include a motor and the motor drive device described above for driving the motor.
[0024] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the invention.
[0025] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.
[0026] Similarly, "the state in which member C is provided between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions or effects produced by their combination.
[0027] Before describing the gate driver circuit according to the embodiment, a gate driver circuit relating to the comparative technique will be described.
[0028] Figure 1 is a circuit diagram of a switching circuit 100R equipped with a gate driver circuit 200R relating to the comparative technology. The switching circuit 100R comprises a bridge circuit 110, an external controller 120, and a gate driver circuit 200R. Here, only the configuration of one phase of the switching circuit 100R is shown, but the switching circuit 100R may be a three-phase circuit or an H-bridge circuit.
[0029] The bridge circuit 110 includes a high-side transistor MH located between the input line (power line) 102 and the output line 104, and a low-side transistor ML located between the output line 104 and the ground line 106. The input line 102 has an input voltage V IN These are supplied. The high-side transistor MH and low-side transistor ML are N-channel MOSFETs.
[0030] The gate driver circuit 200R has an IN-IN input interface. The first input terminal IN1 of the gate driver circuit 200R receives an input high-side signal HIN from the external controller 120, which instructs the on / off state of the high-side transistor MH, and the second input terminal IN2 receives an input low-side signal LIN from the external controller 120, which instructs the on / off state of the low-side transistor ML.
[0031] The gate driver circuit 200R turns off the high-side transistor MH when the input high-side signal HIN at the first input terminal IN1 is at the first level (e.g., low), and turns on the high-side transistor MH when the input high-side signal HIN is at the second level (e.g., high). The gate driver circuit 200R turns off the low-side transistor ML when the input low-side signal LIN at the second input terminal IN2 is at the first level (e.g., low), and turns on the low-side transistor ML when the input low-side signal LIN is at the second level (e.g., high).
[0032] The gate driver circuit 200R includes a control circuit 230, a high-side driver 240, a low-side driver 250, a high-side off sensor 260, and a low-side off sensor 270.
[0033] The control circuit 230 generates a high-side control signal HCTRL that instructs the high-side transistor MH to be turned on or off in response to the input high-side signal HIN at the first input terminal IN1. The control circuit 230 also generates a low-side control signal LCTRL that instructs the low-side transistor ML to be turned on or off in response to the input low-side signal LIN at the second input terminal IN2. The control circuit 230 performs dead-time zero control so that the dead-time interval (high-impedance interval) in which the high-side transistor MH and the low-side transistor ML are simultaneously turned off is made as short as possible.
[0034] High-output state (V) where high-side transistor MH is ON and low-side transistor ML is OFF OUT =V IN ) From this state, the high-side transistor MH is off and the low-side transistor ML is on, resulting in a low output state (V OUT When transitioning to 0V, the gate signal HOUT of the high-side transistor MH is first reduced. Then, when the high-side transistor MH turns off, the gate signal LOUT of the low-side transistor ML begins to rise.
[0035] The high-side off sensor 260 monitors the gate signal (gate-source voltage) of the high-side transistor MH and, upon detecting the turn-off of the high-side transistor MH, asserts (for example, sets to high) the high-side off detection signal HOFF. In response to the assertion of the high-side off detection signal HOFF, the control circuit 230 initiates the turn-on operation of the low-side transistor ML by the low-side driver 250.
[0036] Conversely, in the low output state (V), the high-side transistor MH is off and the low-side transistor ML is on. OUT From (=0V), the high-output state (V) is reached when the high-side transistor MH is on and the low-side transistor ML is off. OUT =V INWhen transitioning to the first state, the gate signal LOUT of the low-side transistor MH is first reduced. Then, when the low-side transistor ML turns off, the gate signal HOUT of the high-side transistor MH begins to rise.
[0037] The low-side off sensor 270 monitors the gate signal (gate-source voltage) of the low-side transistor ML and, upon detecting the turn-off of the low-side transistor ML, asserts (e.g., high) the low-side off detection signal LOFF. In response to the assertion of the low-side off detection signal LOFF, the control circuit 230 initiates the turn-on operation of the high-side transistor MH by the high-side driver 240.
[0038] The above describes the configuration of the switching circuit 100R. Next, we will explain its operation.
[0039] Figure 2 is a time chart illustrating the dead-time zero control of the switching circuit 100R in Figure 1. At time t0, the input low-side signal LIN and the input high-side signal HIN at the output terminal of the external controller 120 transition substantially simultaneously and complementaryly.
[0040] The input high-side signal HIN and input low-side signal LIN are input from the external controller 120 to the gate driver circuit 200R via two wires. When the delays τ1 and τ2 of the two wires are equal, the input high-side signal HIN (IN1) and input low-side signal LIN (IN2) at the first input terminal IN1 and the second input terminal IN2 transition simultaneously at time t1, after the wire delay has elapsed from time t0.
[0041] The control circuit 230 generates a low-side control signal LCTRL such that when the input low-side signal LIN(IN1) transitions to low at time t1, the gate signal LOUT of the low-side transistor ML decreases. At time t1, the low-side driver 250 starts operating, and the gate signal LOUT begins to decrease.
[0042] At time t2, when the gate signal LOUT drops to a predetermined threshold voltage, the low-side off detection signal LOFF is asserted. In response to the assertion of the low-side off detection signal LOFF, the control circuit 230 generates a high-side control signal HCTRL such that the gate signal HOUT of the high-side transistor MH rises.
[0043] Thus, when the low-side transistor ML turns on, the high-side transistor MH turns on immediately afterward, effectively making the length of the high-impedance section zero.
[0044] Next, we will explain the problems that occur in the switching circuit 100R shown in Figure 1.
[0045] Figure 3 illustrates the operation of the switching circuit 100R in Figure 1. The input high-side signal HIN and the input low-side signal LIN are input from the external controller 120 to the gate driver circuit 200R via two wires. Consider the case where there is a difference τd between the propagation delays τ1 and τ2 of the two wires. At time t1, after the delay time τ2 has elapsed from time t0, the input low-side signal LIN (IN2) of the second input terminal IN2 transitions to a low level. At time t3, after the delay time τ1 has elapsed from time t0, the input high-side signal HIN (IN1) of the first input terminal IN1 transitions to a high level.
[0046] In other words, even though the external controller 120 generates control signals HIN and LIN that result in zero dead time, the gate driver circuit 200R is instructed to be in a high impedance state during the period from time t1 to t3.
[0047] The operation of the gate driver circuit 200R in the high-impedance state is not particularly limited. In this example, the gate voltage LOUT is sharply reduced to rapidly turn off the low-side transistor ML during the period when the high-impedance state is indicated.
[0048] At time t3, when the instruction to the gate driver circuit 200R becomes high output, a gate voltage LOUT is generated so that the low-side transistor ML turns off at its normal speed.
[0049] Thus, in the comparative technique, even though dead time zero control is performed, the delay time τ d Due to this effect, a narrow high-impedance section is inserted.
[0050] The following describes technologies for solving problems that arise in comparative technologies.
[0051] Figure 4 is a circuit diagram of a switching circuit 100 equipped with a gate driver circuit 200 according to an embodiment. The gate driver circuit 200 comprises a logic circuit 210, a low-pass filter 220, a control circuit 230, a high-side driver 240, a low-side driver 250, a high-side off sensor 260, and a low-side off sensor 270, and is integrated on a single semiconductor substrate.
[0052] The first input terminal IN1 of the gate driver circuit 200 receives the input high-side signal HIN, which instructs the on / off state of the high-side transistor MH. The second input terminal IN2 receives the input low-side signal LIN, which instructs the on / off state of the low-side transistor ML.
[0053] The logic circuit 210 converts the input high-side signal HIN and the input low-side signal LIN into an internal enable signal INT_EN and an internal PWM signal INT_PWM. The internal enable signal INT_EN is the signal equivalent to the enable signal EN in EN-PWM format. When it is at the first level corresponding to assertion, the bridge circuit 110 is in a high output state or a low output state. When it is at the second level corresponding to negate (deassert), the output of the bridge circuit 110 is in a high impedance state. The internal PWM signal INT_PWM is a pulse-modulated signal in EN-PWM format. When it is at the first level (e.g., low), the bridge circuit 110 is in a low output state, and when it is at the second level (e.g., high), the bridge circuit 110 is in a high output state.
[0054] The truth table for the input and output of logic circuit 210 can be defined, for example, as follows: Input Output (HIN,LIN) (INT_EN,INT_PWM) (0,0) (L,H*) (0,1) (H,L) (1,0) (H,H) (1,1) (L,L*) Note that * represents redundancy (Don't Care), and can be either H or L.
[0055] The low-pass filter 220 receives the internal enable signal INT_EN and the internal PWM signal INT_PWM and removes the high-frequency components of each. Specifically, the cutoff frequency of the low-pass filter 220 is set to a level that can remove narrow pulses of a few nanoseconds, for example, pulses with a pulse width narrower than 10 nm, that appear in the internal enable signal INT_EN and the internal PWM signal INT_PWM. The cutoff frequency for the internal enable signal INT_EN and the cutoff frequency for the internal PWM signal INT_PWM may be the same or different.
[0056] The control circuit 230 receives the internal enable signal INT_EN (also called the output enable signal OUT_EN) and the internal PWM signal INT_PWM (output PWM signal OUT_PWM) after passing through the low-pass filter 220. When the output enable signal OUT_EN is low, the control circuit 230 controls the high-side driver 240 and the low-side driver 250 so that the high-side transistor MH and the low-side transistor ML are turned off.
[0057] When the output enable signal OUT_EN is high, the control circuit 230 controls the high-side driver 240 and the low-side driver 250 based on dead-time zero control so that one of the high-side transistor MH and the low-side transistor ML, corresponding to the output PWM signal OUT_PWM, is turned on.
[0058] For zero dead time control, a high-side off sensor 260 and a low-side off sensor 270 are provided. The high-side off sensor 260 monitors the gate signal (gate-source voltage) of the high-side transistor MH and, upon detecting the turn-off of the high-side transistor MH, asserts (e.g., high) the high-side off detection signal HOFF. The low-side off sensor 270 monitors the gate signal (gate-source voltage) of the low-side transistor ML and, upon detecting the turn-off of the low-side transistor ML, asserts (e.g., high) the low-side off detection signal LOFF.
[0059] The control circuit 230 controls the low-side driver 250 so that the low-side transistor ML turns off when the output PWM signal OUT_PWM transitions from low to high. Then, in response to the assertion of the low-side off detection signal LOFF, it controls the high-side driver 240 so that the high-side transistor MH turns on.
[0060] When the output PWM signal OUT_PWM transitions from high to low, the control circuit 230 controls the high-side driver 240 such that the high-side transistor MH is turned off. Then, in response to assertion of the high-side turn-off detection signal HOFF, the control circuit 230 controls the low-side driver 250 such that the low-side transistor ML is turned on.
[0061] The configuration of the gate driver circuit 200 has been described above. Next, the operation of the gate driver circuit 200 will be described.
[0062] FIG. 5 is a timing chart explaining the operation of the gate driver circuit 200 of FIG. 4. At time t1, which is after the elapse of a delay time τ2 from time t0, the input low-side signal LIN(IN2) at the second input terminal IN2 transitions to a low level. At time t3, which is after the elapse of a delay time τ1 from time t0, the input high-side signal HIN(IN1) at the first input terminal IN1 transitions to a high level.
[0063] The logic circuit 210 receives the input low-side signal LIN(IN2) and the input high-side signal HIN(IN1), and generates the internal enable signal INT_EN and the internal PWM signal INT_PWM based on a truth table. The internal enable signal INT_EN has a delay time τ d that includes a narrow pulse (negative pulse) Pn that remains low for a corresponding period.
[0064] Since high-frequency components are removed from the internal enable signal INT_EN by the low-pass filter 220, the narrow pulse Pn is removed from the output enable signal OUT_EN.
[0065] When the output PWM signal OUT_PWM transitions from low to high at time t4 after the elapse of the filter delay time, the control circuit 230 controls the low-side driver 250 such that the low-side transistor ML is turned off, and lowers the gate signal LOUT.
[0066] When the low-side off detection signal LOFF is asserted at time t2, the control circuit 230 controls the high-side driver 240 to turn on the high-side transistor MH and raises the gate signal HOUT.
[0067] The above describes the operation of the gate driver circuit 200. The gate driver circuit 200 prevents the output of the bridge circuit 110 from becoming high impedance when IN-IN input signals HIN and LIN are input after different delays, thereby maintaining zero dead time control.
[0068] (modified version) Next, we will explain a modified version of the gate driver circuit 200.
[0069] Figure 6 is a circuit diagram of the gate driver circuit 200A according to Modification 1. In this modification, the truth table for the logic circuit 210A is different from that of the logic circuit 210 in Figure 4. Specifically, the truth table for the logic circuit 210A is expressed as follows.
[0070] The truth table for the input and output of logic circuit 210 can be defined as follows, for example, and the internal PWM signal INT_PWMB is a negative logic signal. Input Output (HIN,LIN) (INT_EN,INT_PWMB) (0,0) (L,L*) (0,1) (H,H) (1,0) (H,L) (1,1) (L,H*) Note that * represents redundancy (Don't Care), and can be either H or L.
[0071] The low-pass filter 220A removes the high-frequency components of the negative logic internal PWM signal INT_PWMB and generates the negative logic output PWM signal OUT_PWMB. The inverter 222 inverts the negative logic output PWM signal OUT_PWMB and generates the positive logic output PWM signal OUT_PWM.
[0072] Thus, the assignment of logic values for various digital signals in the gate driver circuit 200 can be changed.
[0073] Figure 7 is a circuit diagram of the gate driver circuit 200B according to Modification 2. This gate driver circuit 200B can accept IN-EN format input signals IN_EN and IN_PWM instead of IN-IN format input signals INH and INL. The gate driver circuit 200 is set to the first mode when used in an IN-IN format application circuit, and to the second mode when used in an EN-IN format application circuit.
[0074] When used in an EN-IN application circuit, the gate driver circuit 200B is configured to bypass the functionality of the logic circuit 210. Specifically, the gate driver circuit 200B includes a first selector SEL1 and a second selector SEL2.
[0075] The first selector SEL1 receives the internal enable signal INT_EN and the input enable signal IN_EN. In the first mode, the first selector SEL1 selects the internal enable signal INT_EN, and in the second mode, it selects the input enable signal IN_EN.
[0076] The second selector SEL2 receives the internal PWM signal INT_PWM and the input PWM signal IN_PWM. In the first mode, the second selector SEL2 selects the internal PWM signal INT_PWM, and in the second mode, it selects the input PWM signal IN_PWM.
[0077] In the second mode, the low-pass filter 220 may be disabled.
[0078] Figure 8 is a circuit diagram of the gate driver circuit 200C according to Modification 3. Similar to Figure 7 (Modification 2), the gate driver circuit 200C supports EN-IN and IN-IN interfaces, and when used in an EN-IN application circuit, the functions of the logic circuit 210 are bypassed. The gate driver circuit 200C includes a first selector SEL1 and a second selector SEL2, but the positions of the first selector SEL1 and the second selector SEL2 are different from those in Figure 7.
[0079] The first selector SEL1 receives the output enable signal OUT_EN and the input enable signal IN_EN. In the first mode, the first selector SEL1 selects the output enable signal OUT_EN and outputs it to the control circuit 230. In the second mode, the first selector SEL1 selects the input enable signal IN_EN and outputs it to the control circuit 230.
[0080] The second selector SEL2 receives the output PWM signal OUT_PWM and the input PWM signal IN_PWM. In the first mode, the second selector SEL2 selects the output PWM signal OUT_PWM and outputs it to the control circuit 230. In the second mode, the second selector SEL2 selects the input PWM signal IN_PWM and outputs it to the control circuit 230.
[0081] (Application) Next, the applications of the switching circuit 100 will be explained. The switching circuit 100 can be suitably used in a motor drive circuit.
[0082] Figure 9 is a circuit diagram of the motor drive device 300 according to the embodiment. The motor drive device 300 drives the load, a three-phase motor 302, and controls its rotational state.
[0083] The motor drive unit 300 comprises a bridge circuit 310, a controller 410, and a three-phase gate driver circuit 420. The bridge circuit 310 is a three-phase inverter having U-phase, V-phase, and W-phase legs, and each phase leg has a high-side transistor MH and a low-side transistor ML.
[0084] The three-phase gate driver circuit 420 includes U-phase, V-phase, and W-phase gate driver circuits 200U, 200V, and 200W. The gate driver circuit 200 is configured with the architecture described above. The controller 410 generates control signals that instruct the state of the legs (switching circuits) for each of the U-phase, V-phase, and W-phase based on the state of the load, the three-phase motor 302, and supplies them to the three-phase gate driver circuit 420.
[0085] Here, a three-phase motor is used as an example, but a single-phase motor can also be used. In this case, the bridge circuit 310 becomes an H-bridge circuit.
[0086] Next, the applications of the motor drive unit 300 will be explained. The motor drive unit 300 can be used to control the spindle motor of a hard disk, or to control the lens drive motor of an imaging device. Alternatively, it can be used to drive the drive motor of a printer head, or the paper feed motor. Alternatively, the motor drive unit 300 can be used to drive motors in electric vehicles, hybrid vehicles, and the like.
[0087] The embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible for each component and each processing process, and that such modifications also fall within the scope of this disclosure or the present invention. Such modifications will be described below.
[0088] (Variation 1) In this embodiment, the bridge circuit 110 is composed of discrete components, but it is not limited to that, and the bridge circuit 110 may be integrated into the gate driver circuit 200.
[0089] (Modification 2) The power transistor may be constructed using an IGBT (Insulated Gate Bipolar Transistor).
[0090] (Variation 3) The applications of the switching circuit 100 are not limited to the motor drive device 300. For example, the switching circuit 100 can be suitably used in switching regulators (DC / DC converters), various power conversion devices (inverters and converters), inverters for lighting discharge lamps, digital audio amplifiers, and so on. Therefore, the switching circuit 100 can be used in consumer electronics including electronic devices and home appliances, automobiles and in-vehicle components, industrial vehicles and industrial machinery.
[0091] (Modification 4) The method and configuration of dead-time zero control by the control circuit 230 are not limited to those using the high-side off sensor 260 and low-side off sensor 270 described in the embodiment. For example, the timing of the turn-off of the high-side transistor and low-side transistor may be predicted using a timer to perform dead-time zero control, or other methods may be employed.
[0092] The embodiments described using specific terminology merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments, without departing from the spirit of the present invention as defined in the claims.
[0093] (Note) This specification discloses the following technologies:
[0094] (Item 1) A gate driver circuit that drives the high-side transistor and low-side transistor that constitute a switching circuit, In the first mode, a first input terminal receives an input high-side signal that instructs the high-side transistor to be turned on or off, In the first mode, a second input terminal receives an input low-side signal that instructs the low-side transistor to be turned on or off, A logic circuit that converts the pair of input high-side signals and input low-side signals into a pair of internal enable signals and internal pulse modulation signals, A low-pass filter that receives the internal enable signal and the internal pulse modulation signal and generates an output enable signal and an output pulse modulation signal, A high-side driver that drives the aforementioned high-side transistor, A low-side driver that drives the low-side transistor, A control circuit that receives the output enable signal and the output pulse modulation signal and controls the high-side driver and the low-side driver based on dead-time zero control, A gate driver circuit equipped with the following features.
[0095] (Item 2) A high-side turn-off detection circuit that, based on the gate signal of the high-side driver, detects the turn-off of the high-side transistor and asserts a high-side turn-off detection signal, A low-side turn-off detection circuit that, based on the gate signal of the low-side driver, detects the turn-off of the low-side transistor and asserts a low-side turn-off detection signal, Furthermore, The control circuit is a gate driver circuit as described in item 1, which performs dead-time zero control using the high-side off detection signal and the low-side off detection signal.
[0096] (Item 3) In the second mode, the first input terminal can accept either an input pulse modulation signal that indicates the output level of the switching circuit or an input enable signal that indicates whether the output of the switching circuit is high impedance or not. In the second mode, the other of the input pulse modulation signal and the input enable signal can be input to the second input terminal. In the second mode, the low-pass filter is disabled. The aforementioned gate driver circuit is A first selector that receives the internal enable signal and the input enable signal, selects the internal enable signal in the first mode and supplies it to the low-pass filter, and selects the input enable signal in the second mode and supplies it to the low-pass filter, A second selector that receives the internal pulse modulated signal and the input pulse modulated signal, selects the internal pulse modulated signal in the first mode and supplies it to the low-pass filter, and selects the input pulse modulated signal in the second mode and supplies it to the low-pass filter, A gate driver circuit as described in item 1 or 2, further comprising the above.
[0097] (Item 4) In the second mode, the first input terminal can accept either an input pulse modulation signal that indicates the output level of the switching circuit or an input enable signal that indicates whether the output of the switching circuit is high impedance or not. In the second mode, the other of the input pulse modulation signal and the input enable signal can be input to the second input terminal. The aforementioned gate driver circuit is A first selector that receives the output enable signal and the input enable signal, selects the output enable signal in the first mode and supplies it to the low-pass filter, and selects the input enable signal in the second mode and supplies it to the low-pass filter, A second selector that receives the output pulse modulated signal and the input pulse modulated signal, selects the output pulse modulated signal in the first mode and supplies it to the low-pass filter, and selects the input pulse modulated signal in the second mode and supplies it to the low-pass filter, A gate driver circuit as described in item 1 or 2, further comprising the above.
[0098] (Item 5) A gate driver circuit described in any of items 1 to 4, integrated onto a single semiconductor substrate.
[0099] (Item 6) A bridge circuit including a high-side transistor and a low-side transistor, A gate driver circuit according to any one of items 1 to 5 for driving the high-side transistor and the low-side transistor, A motor drive device equipped with the following features.
[0100] (Item 7) Motor and, The motor drive device described in item 6 for driving the motor, An electronic device equipped with the following features. [Explanation of symbols]
[0101] 100 Switching Circuits 102 input lines 104 output lines 106 Grounding line 110 Bridge Circuit IN1 First Input Terminal IN2 Second Input Terminal MH High-Side Transistor ML Low-Side Transistor 120 External Controllers 200 Gate Driver Circuit 210 Logic Circuits 220 Low-Pass Filter 230 Control circuits 240 High-Side Driver 250 Low-Side Driver 260 High-side Off-Sensor 270 Low-side off-sensor SEL1 First Selector SEL2 Second Selector 300 Motor drive unit 302 Three-phase motor 310 Bridge Circuit 410 Controller 420 Three-phase gate driver circuit
Claims
1. A gate driver circuit that drives the high-side transistor and low-side transistor that constitute a switching circuit, In the first mode, a first input terminal receives an input high-side signal that instructs the high-side transistor to be turned on or off, In the second mode, a second input terminal receives an input low-side signal that instructs the low-side transistor to be turned on or off, A logic circuit that converts the pair of input high-side signals and input low-side signals into a pair of internal enable signals and internal pulse modulation signals, A low-pass filter that receives the internal enable signal and the internal pulse modulation signal and generates an output enable signal and an output pulse modulation signal, A high-side driver that drives the aforementioned high-side transistor, A low-side driver that drives the low-side transistor, A control circuit that receives the output enable signal and the output pulse modulation signal and controls the high-side driver and the low-side driver based on dead-time zero control, A gate driver circuit equipped with the following features.
2. A high-side turn-off detection circuit that, based on the gate signal of the high-side driver, detects the turn-off of the high-side transistor and asserts a high-side turn-off detection signal, A low-side turn-off detection circuit that, based on the gate signal of the low-side driver, detects the turn-off of the low-side transistor and asserts a low-side turn-off detection signal, Furthermore, The gate driver circuit according to claim 1, wherein the control circuit performs dead time zero control using the high-side off detection signal and the low-side off detection signal.
3. In the second mode, the first input terminal can accept either an input pulse modulation signal that indicates the output level of the switching circuit or an input enable signal that indicates whether the output of the switching circuit is high impedance or not. In the second mode, the other of the input pulse modulation signal and the input enable signal can be input to the second input terminal. In the second mode, the low-pass filter is disabled. The aforementioned gate driver circuit is A first selector that receives the internal enable signal and the input enable signal, selects the internal enable signal in the first mode and supplies it to the low-pass filter, and selects the input enable signal in the second mode and supplies it to the low-pass filter, A second selector that receives the internal pulse modulation signal and the input pulse modulation signal, selects the internal pulse modulation signal in the first mode and supplies it to the low-pass filter, and selects the input pulse modulation signal in the second mode and supplies it to the low-pass filter, The gate driver circuit according to claim 1 or 2, further comprising:
4. In the second mode, the first input terminal can accept either an input pulse modulation signal that indicates the output level of the switching circuit or an input enable signal that indicates whether the output of the switching circuit is high impedance or not. In the second mode, the other of the input pulse modulation signal and the input enable signal can be input to the second input terminal. The aforementioned gate driver circuit is A first selector that receives the output enable signal and the input enable signal, selects the output enable signal in the first mode and supplies it to the low-pass filter, and selects the input enable signal in the second mode and supplies it to the low-pass filter, A second selector that receives the output pulse modulated signal and the input pulse modulated signal, selects the output pulse modulated signal in the first mode and supplies it to the low-pass filter, and selects the input pulse modulated signal in the second mode and supplies it to the low-pass filter, The gate driver circuit according to claim 1 or 2, further comprising:
5. A gate driver circuit according to claim 1 or 2, which is integrated on a single semiconductor substrate.
6. A bridge circuit including a high-side transistor and a low-side transistor, A gate driver circuit according to claim 1 or 2 for driving the high-side transistor and the low-side transistor, A motor drive device equipped with the following features.
7. Motor and, A motor drive device according to claim 6 for driving the motor, An electronic device equipped with the following features.