Semiconductor memory device and method for manufacturing the same

Abstract

The objective is to provide a semiconductor memory device having a well-defined stacked structure. [Solution] According to the embodiment, the device includes a first conductive layer and a first semiconductor column, and a first region where a memory cell is formed; a second conductive layer and a second semiconductor column, and a second region where a memory cell is formed; and a third region including a plurality of third conductive layers, which is continuous with one of the first conductive layers and one of the second conductive layers, and the third region includes a fourth region that electrically connects one of the first conductive layers and one of the second conductive layers, and a fifth region to which one of the third conductive layers is connected to a contact, and the fifth region includes an inclined staircase portion in which the third conductive layers are stacked in a staircase shape, and is provided with a plurality of slit members that divide the region, some of the slit members are located at positions that divide the fifth region, and the slit members include intermittent portions that communicate with the fifth regions located on both sides in the width direction thereof, and include bridging portions that fill the intermittent portions.

Description

[Technical Field]

[0001] Embodiments relate to a semiconductor memory device and a method for manufacturing the same. [Background Art]

[0002] In recent years, semiconductor devices in which memory cells are three-dimensionally integrated have been proposed. In such a semiconductor device, a through hole is formed in a stacked body in which insulating layers and conductive layers are alternately stacked, and a charge-accumulable memory layer and a silicon layer are formed on the inner surface of the through hole, whereby a memory cell is formed between the silicon layer and the conductive layer. Further, in a semiconductor memory device including memory cells, a structure in which a contact electrode is connected to a conductive layer of the stacked body is known. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2022-120425 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing the same, in which in a semiconductor device including an inclined step portion in which a plurality of conductive layers connected with contacts are arranged in a stepped shape, deformation of the inclined step portion and the stacked structure existing around the inclined step portion is suppressed, so that a well-shaped stacked structure is obtained. [Means for Solving the Problem]

[0005] The semiconductor memory device of the embodiment includes a plurality of first conductive layers stacked in a first direction with spacing between them, and first semiconductor pillars extending in the first direction within the plurality of first conductive layers, and comprises a first region where a memory cell is formed at the intersection of the plurality of first conductive layers and the first semiconductor pillars. The semiconductor memory device includes a plurality of second conductive layers stacked with spacing between them, and second semiconductor pillars extending in the first direction within the plurality of second conductive layers, and comprises a second region where a memory cell is formed at the intersection of the plurality of second conductive layers and the second semiconductor pillars. The semiconductor memory device includes a plurality of third conductive layers stacked with spacing between them, and comprises a third region disposed between the first region and the second region in a second direction intersecting the first direction, wherein one of the plurality of third conductive layers is continuous with one of the plurality of first conductive layers and one of the plurality of second conductive layers. The third region includes a fourth region within which one of the plurality of third conductive layers electrically connects one of the plurality of first conductive layers and one of the plurality of second conductive layers, and a fifth region within which one of the plurality of third conductive layers is connected to a contact. The third region includes an inclined staircase portion in the fifth region where a part of the plurality of third conductive layers is stacked in a staircase shape. Furthermore, it includes a plurality of unit regions comprising the first region, the second region and the third region, and a plurality of slit members that individually divide the unit regions. Some of the plurality of slit members are formed at positions that divide the fifth region, and some of the slit members include an intermittent portion that communicates with the fifth regions located on both sides of the width direction of the slit member, and a bridging portion that fills the intermittent portion. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system equipped with a semiconductor memory device according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array in the semiconductor memory device. [Figure 3] Figure 3 is a perspective view showing an example of the appearance of the semiconductor memory device. [Figure 4] Figure 4 is a perspective view showing an overview of the bonding structure of the semiconductor memory device. [Figure 5] Figure 5 is a schematic plan view showing an example of the planar layout of the memory area and extraction area of ​​the memory cell array. [Figure 6] Figure 6 is a plan view showing an example of a planar layout in the memory area. [Figure 7] Figure 7 is a cross-sectional view along the line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region. [Figure 8] Figure 8 is a cross-sectional view along line VIII-VIII in Figure 6, showing an example of the cross-sectional structure of a columnar body provided in the memory area. [Figure 9] Figure 9 is a plan view showing an example of a planar layout in the memory area and the draw-out area. [Figure 10] Figure 10 is a perspective view showing the contacts connected to the inclined staircase. [Figure 11A] Figure 11A is a cross-sectional view along the XIA-XIA line in Figure 9. [Figure 11B] Figure 11B is a cross-sectional view along the line XIB-XIB in Figure 9. [Figure 12] Figure 12 shows a cross-sectional structure when the memory area has a three-layer structure. [Figure 13A] Figure 13A is an explanatory diagram showing the state in which the first layer is formed in the inclined staircase section when the drawer area has a three-layer structure. [Figure 13B] Figure 13B is an explanatory diagram showing the state in which the second layer region is formed in the inclined staircase section when the drawer region has a three-layer structure. [Figure 13C] Figure 13C is an explanatory diagram showing the state in which the third layer region is formed in the inclined staircase section when the drawer region has a three-layer structure. [Figure 14A] Figure 14A is an explanatory diagram showing a second embodiment in which the drawer area has a three-layer structure. [Figure 14B] Figure 14B is an explanatory diagram showing a third embodiment in which the drawer area has a three-layer structure. [Figure 14C]FIG. 14C is an explanatory view showing a fourth embodiment in which the lead-out region has a three-layer structure. [Figure 14D] FIG. 14D is an explanatory view showing a fifth embodiment in which the lead-out region has a three-layer structure. [Figure 15A] FIG. 15A is an explanatory view showing an example of a method for manufacturing the lead-out region according to the first embodiment. [Figure 15B] FIG. 15B is an explanatory view showing an example of a method for manufacturing the lead-out region according to the first embodiment. [Figure 15C] FIG. 15C is an explanatory view showing an example of a method for manufacturing the lead-out region according to the first embodiment. [Figure 16A] FIG. 16A is a cross-sectional view showing an example of a manufacturing method in which the lead-out region has a three-layer structure. [Figure 16B] FIG. 16B is a cross-sectional view showing an example of a manufacturing method in which the lead-out region has a three-layer structure. [Figure 16C] FIG. 16C is a cross-sectional view showing an example of a manufacturing method in which the lead-out region has a three-layer structure. [Figure 17] FIG. 17 is an explanatory view showing a structure according to a sixth embodiment of the lead-out region. [Figure 18] FIG. 18 is an explanatory view showing a structure according to a seventh embodiment of the lead-out region. [Figure 19A] FIG. 19A is an explanatory view for showing a structure according to an eighth embodiment of the lead-out region. [Figure 19B] FIG. 19B is a plan view for showing a structure according to the eighth embodiment of the lead-out region. [Figure 19C] FIG. 19C is a plan view for showing a structure according to the eighth embodiment of the lead-out region. [Figure 20A] FIG. 20A is a plan view showing a structure according to a ninth embodiment of the lead-out region. [Figure 20B] FIG. 20B is a cross-sectional view showing a structure according to the ninth embodiment of the lead-out region. MODE FOR CARRYING OUT THE INVENTION

[0007] The semiconductor memory devices according to each embodiment will be described in detail below with reference to the attached drawings. The following drawings are schematic, and the dimensions and proportions shown in the drawings are not necessarily the same as those of actual devices. Furthermore, the present invention is not limited by these embodiments. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0008] "First Embodiment" A semiconductor memory device according to the first embodiment will now be described. The semiconductor memory device is, for example, a non-volatile semiconductor memory device (semiconductor memory) in which multiple memory cells are arranged in a three-dimensional direction. 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0009] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0010] The semiconductor memory device 3 is, for example, a NAND flash memory capable of storing data non-volatilely. Communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0011] 1.1.2 Semiconductor memory devices Next, with reference to the block diagram shown in Figure 1, the internal configuration of the semiconductor memory device 3 according to the first embodiment will be described. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 10 is a collection of memory cell transistors and components connected to the memory cell transistors. The memory cell array 10 includes multiple blocks (unit regions) BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely. A block BLK is used, for example, as an erasure unit when erasing data stored by a memory cell transistor. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated, for example, with a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0013] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between it and the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 outputs command CMD and address information ADD, each transferred from the memory controller 2, to register 13. The input / output circuit 11 outputs status information STA, transferred from register 13, to the memory controller 2.

[0014] The logic control circuit 12 receives control signals input from the memory controller 2. Based on these control signals, the logic control circuit 12 controls the input / output circuit 11 and the sequencer 14, respectively. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signal it has received is a command CMD or address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signal. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. The logic control circuit 12 also outputs a signal to the memory controller 2 indicating whether the semiconductor memory device 3 is ready or busy.

[0015] Register 13 temporarily stores command CMD, address information ADD, and status information STA. Command CMD includes, for example, instructions to cause the sequencer 14 to perform read, write, erase, etc. Address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, block address BA, page address PA, and column address CA are used for selecting block BLK, word lines, and bit lines, respectively. Status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0016] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc., and performs read operations, write operations, erase operations, etc.

[0017] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0018] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0019] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0020] 1.1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the first embodiment. Figure 2 shows block BLK0. Block BLK0 includes, for example, four string units SU0 to SU3.

[0021] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilously based on the amount of charge in the charge storage film. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0022] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series in this order. The drain of selection transistor ST1 is connected to the associated bit line BL, and the source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. The drain of selection transistor ST2 is connected to the source of memory cell transistor MT0, and the source of selection transistor ST2 is connected to the source line SL.

[0023] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gate of selection transistor ST1 within string units SU0 to SU3 is connected to the corresponding selection gate lines SGD0 to SGD3. The gate of selection transistor ST2 within string units SU0 to SU1 is connected to selection gate line SGS0. The gate of selection transistor ST2 within string units SU2 to SU3 is connected to selection gate line SGS1.

[0024] Each bit line BL0 to BLm is assigned a different column address CA. Each bit line BL is shared by a NAND string NS, which is assigned the same column address CA across multiple block BLKs. Each word line WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0025] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For instance, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data." A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0026] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units SU included in each block BLK can be designed to be any number. However, it is desirable that the number of string units SU included in each block BLK be an even number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to be any number. In the following example, we will explain using a structure with seven memory cell transistors (MTs) as shown in Figure 2.

[0027] 1.1.4 Appearance of semiconductor memory devices The semiconductor memory device 3 according to the first embodiment is formed by bonding together two semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the bonded semiconductor circuit boards chip by chip. That is, the semiconductor memory device 3 according to the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is, for example, a silicon substrate. The following explanation describes the case where the semiconductor substrate W2 is removed during the manufacturing process of the semiconductor memory device 3. However, depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after bonding.

[0028] Figure 3 is a perspective view showing an example of the appearance of a semiconductor memory device according to the first embodiment. Hatching has been added to Figure 3 to improve the visibility of the drawing, but this does not necessarily relate to the material or characteristics of the components to which the hatching has been added. As shown in Figure 3, the semiconductor memory device 3 has a structure in which, for example, a semiconductor substrate W1, a control circuit layer 100, a junction layer B1, a junction layer B2, a memory layer 200, and a wiring layer 300 are stacked in order.

[0029] In the following explanation, the plane on which the semiconductor substrate W1 is stretched is defined as the XY plane. Of the directions in which the stacked structure is stacked, the direction from the semiconductor substrate W1 toward the wiring layer 300 is defined as the Z1 direction, and the direction from the wiring layer 300 toward the semiconductor substrate W1 is defined as the Z2 direction. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate W1. When the Z1 and Z2 directions are not distinguished, they are simply referred to as the Z direction. The Z direction is also called the first direction. When explaining the X direction, the +X direction and the -X direction may be distinguished, and when the directions are not distinguished, the +X direction and the -X direction are simply referred to as the X direction. The +X direction and the -X direction will be explained later. Similarly, when explaining the Y direction, the +Y direction and the -Y direction may be distinguished, and when the directions are not distinguished, the +Y direction and the -Y direction are simply referred to as the Y direction. The +Y direction and the -Y direction will be explained later.

[0030] The control circuit layer 100 includes a control circuit formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., according to the design of the control circuit. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a low decoder module 16, and a sense amplifier module 17.

[0031] The bonding layer B1 is formed using the semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the control circuit provided in the control circuit layer 100 and form a part of the semiconductor circuit. The junction layer B2 is formed using a semiconductor substrate W2 (not shown). The junction layer B2 includes a plurality of junction pads that are electrically connected to the memory cell array 10 provided on the memory layer 200 and form a part of the semiconductor circuit. The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2 (not shown).

[0032] The wiring layer 300 is formed after the semiconductor substrates W1 and W2 are bonded together. The wiring layer 300 includes wiring connected to semiconductor circuits provided on the memory layer 200, as well as a plurality of pads PD. The plurality of pads PD are exposed on the surface of the semiconductor memory device 3. The plurality of pads PD are used to connect the semiconductor memory device 3 to the memory controller 2, etc.

[0033] Figure 4 is a perspective view showing an overview of the bonding structure of the semiconductor memory device according to the first embodiment. The bonding of semiconductor substrates W1 and W2 will be explained using Figure 4.

[0034] As shown in Figure 4, the multiple bonding pads BP1 included in bonding layer B1 and the multiple bonding pads BP2 included in bonding layer B2 are connected to each other. As a result, the control circuit provided in the control circuit layer 100 and the memory cell array 10 provided in the memory layer 200 are electrically connected to each other via the bonding pads BP1 and BP2. The space between bonding layers B1 and B2 corresponds to the boundary between the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2 (not shown).

[0035] 1.1.5 Structure of a memory cell array An example of the structure of the memory cell array 10 provided in the semiconductor memory device 3 according to the first embodiment is described below. In the following description, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction (first direction) is the direction orthogonal to the X and Y directions. The Z direction is equal to the thickness direction of the semiconductor substrate W1. The plane extending in the X and Z directions is called the XZ plane. The plane extending in the Y and Z directions is called the YZ plane. In the plan view, hatching is added as appropriate to improve the visibility of the drawing. The hatching added to the plan view is not necessarily related to the material or characteristics of the component to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to improve the visibility of the drawing.

[0036] 1.1.5.1 Overview Figure 5 is a plan view showing an example of the planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. In Figure 5, areas corresponding to six blocks (unit areas) BLK0 to BLK5 are shown. The sequential numbers at the end to distinguish the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in Figure 5 is repeatedly arranged in the Y direction. As shown in Figure 5, the memory cell array 10 includes a plurality of slit members SLT and a plurality of slit portions SHE. The planar layout of the memory cell array 10 is divided in the X direction, for example, into memory areas MA1 and MA2 and a draw-out area HA. ​​The draw-out area HA is provided between memory area MA1 and memory area MA2.

[0037] Memory areas MA1 and MA2 are areas used for storing data, containing multiple NAND strings NS (see Figure 2). The lead area HA is an area used for connecting the stacked wiring, which is composed of multiple wiring layers (e.g., word lines WL0 to WL7, and selection gate lines SGS0, SGS1, and SGD) stacked apart from each other in the Z direction, and the raw decoder module 16.

[0038] Multiple slit members SLT each extend along the X direction and are aligned in the Y direction. Each slit member SLT crosses the memory area MA1, the extraction area HA, and the memory area MA2 in the X direction in the boundary region between adjacent blocks BLK. In other words, each region demarcated by a slit member SLT corresponds to one block (unit area) BLK in the memory cell array 10. Each slit member SLT has a structure in which, for example, a spacer SP and a plate-shaped contact LI are embedded. Each slit member SLT separates adjacent stacked wiring through the slit member SLT.

[0039] As shown in Figure 5, in this embodiment, among the multiple slit members SLT arranged in the Y direction, the slit member SLT located in odd-numbered positions counting from the top of the paper is called "SLTo," and the slit member SLT located in even-numbered positions is called "SLTe." Multiple pairs of slit members SLTo and SLTe are arranged in the Y direction in the memory cell array 10.

[0040] Multiple slit sections SHE are arranged in memory areas MA1 and MA2, respectively. The multiple slit sections SHE corresponding to memory area MA1 are each provided across memory area MA1 in the X direction and aligned in the Y direction. The multiple slit sections SHE corresponding to memory area MA2 are each provided across memory area MA2 in the X direction and aligned in the Y direction. In Figure 5, the right-hand end of each slit section SHE corresponding to memory area MA1 and the left-hand end of each slit section SHE corresponding to memory area MA2 are each included in the lead-out area HA. ​​For example, in memory areas MA1 and MA2, three slit sections SHE are each arranged between adjacent slit members SLT in the Y direction. Each combination of the area demarcated by the slit member SLT and slit section SHE in memory area MA1 and each combination of the area demarcated by the slit member SLT and slit section SHE in memory area MA2 corresponds to one string unit SU in the memory cell array 10. Each slit section SHE has, for example, a structure in which an insulator is embedded. Each slit section SHE separates adjacent selected gate lines SGD through the slit section SHE.

[0041] The planar layout of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of slit portions SHE arranged between adjacent slit members SLT can be designed to be any number. The number of string units SU formed between adjacent slit members SLT can be changed based on the number of slit portions SHE arranged between adjacent slit members SLT. It is desirable that the number of string units SU formed between adjacent slit members SLT be an even number. That is, it is desirable that the number of slit portions SHE in one block BLK be an odd number.

[0042] The lead-out region HA includes multiple lead-out sections HP. Each lead-out section HP is provided with a connection portion to a contact in each wiring layer of the multilayer wiring. Each lead-out section HP is arranged in the Y direction and is provided for every two adjacent blocks BLK in the Y direction, separated by a slit member SLTo. Each lead-out section HP is provided within the lead-out region HA so as to be sandwiched between two slit members SLTo that sandwich two adjacent blocks BLK. Each lead-out section HP is provided within the lead-out region HA so as to be divided by two slit members SLTe that sandwich two adjacent blocks BLK.

[0043] The lead-out area HA includes multiple bridge sections BRG. Each bridge section BRG is provided for each block BLK. In each bridge section BRG, the portion provided in the memory area MA1 of each wiring layer of the stacked wiring is connected to the portion provided in the memory area MA2. As shown in Figure 5, the draw-out area HA is provided between the memory area MA1 and the memory area MA2 in the X direction, and it is preferable that each block BLK is provided with an inclined staircase area SSA and a bridge area BRG as shown in Figure 9, etc.

[0044] In the inclined staircase region SSA, the ends of the selected gate line (source-side selected gate) SGS and the multiple word lines WL are stepped in the X direction sequentially from the lower layer, forming a staircase shape. In other words, in the inclined staircase region SSA, each of the selected gate line SGS and the multiple word lines WL has a terrace portion (also called a staircase, stair section, or lead-out section) at its end that does not overlap with the lower wiring layer (conductive layer). Contact CCs, as shown in Figures 9 and 10 which will be explained later, are formed on each terrace portion. Voltages can be applied separately to the selected gate line SGS and the multiple word lines WL via the contact CCs. As described above, the inclined staircase region SSA is provided as a terrace region for connecting multiple contacts to each of the multiple wiring layers 22 to 24, which will be described later and are connected to the selected gate line SGS and the multiple word lines WL.

[0045] The contact CC is electrically connected to a row decoder located beneath the memory cell array. This allows the row decoder to control the voltage of each wiring layer 21 (word line WL) via the contact CC.

[0046] The planar layout of the memory cell array 10 in the semiconductor memory device 3 of the first embodiment is not limited to the layout described above. For example, the number of slit portions SHE arranged between adjacent slit members SLT can be designed to be any number. The number of string units SU formed between adjacent slit members SLT can be changed based on the number of slit portions SHE arranged between adjacent slit members SLT. It is desirable that the number of string units SU formed between adjacent slit members SLT be an even number. That is, it is desirable that the number of slit portions SHE in a single block BLK be an odd number.

[0047] 1.1.5.2 Memory Area (Flat layout) Figure 6 is a plan view showing an example of a planar layout in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. In Figure 6, the structure of one block BLK within the memory region MA is shown as representative. As shown in Figure 6, in the memory region MA1, the memory cell array 10 includes a plurality of columnar bodies (memory pillars) MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each slit member SLT includes a contact LI and spacers SP on both sides of the thickness direction of the contact LI.

[0048] Each of the columnar members MP functions, for example, as a single NAND string NS. Multiple columnar members MP are arranged in a staggered pattern, for example, 19 rows in the Y direction, in the region between two adjacent slit members SLT. In the example shown in Figure 6, one slit SHE overlaps each of the columnar members MP in the 5th, 10th, and 15th rows, counting from the top of the paper.

[0049] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one columnar body MP for each string unit SU. In the example shown in Figure 6, two bit lines BL are positioned to overlap with one columnar body MP. If multiple bit lines BL overlap with a columnar body MP, one bit line BL and the corresponding columnar body MP are electrically connected via a contact CV. If only one bit line BL overlaps with a columnar body MP, that bit line BL and the corresponding columnar body MP are electrically connected via a contact CV.

[0050] For example, the contact CV between a columnar body MP in contact with a slit portion SHE and the corresponding bit line BL is omitted. In other words, the contact CV between a columnar body MP in contact with two different selected gate lines SGD and the bit line BL is omitted. The number and arrangement of columnar bodies MP and slit portions SHE between adjacent members SLT are not limited to the configuration shown in Figure 6 and can be changed as appropriate. For example, the number of bit lines BL overlapping each columnar body MP can be designed to be any number.

[0051] Contact LI is a conductor extending in the XZ plane. The lower surface of contact LI is in contact with a source wire SL (not shown). Spacer SP is an insulator provided on the side of contact LI. In other words, spacer SP is provided in contact with contact LI so as to sandwich it in the Y direction.

[0052] (Cross-sectional structure) Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. As shown in Figure 7, the memory cell array 10 further includes wiring layers 21-25, insulating layers 40-46, and slit members SLT. In the following description, the Z2 direction may be described as upward and the Z1 direction as downward.

[0053] The stacked wiring included in the memory cell array 10 includes a wiring layer 22 corresponding to the selected gate line SGS0, multiple wiring layers 23 corresponding to word lines WL0 to WL7, and a wiring layer 24 corresponding to the selected gate line SGD. Hereinafter, the selected gate line may simply be referred to as the selected gate line SGS.

[0054] In the example shown in Figure 7, two wiring layers 22 corresponding to the selected gate line SGS are provided. In the following explanation, the selection gate line SGS corresponding to the upper wiring layer 22 is referred to as selection gate line SGS0a, and the selection gate line SGS corresponding to the lower wiring layer 22 is referred to as selection gate line SGS0b. Each of the selection gate lines SGS0a and SGS0b is connected to the gates of the selection transistors ST2a and ST2b, respectively. The selection transistors ST2a and ST2b function as a single selection transistor ST2. The wiring layer 22 corresponding to the selection gate line SGS may be one layer or may consist of three or more layers. Furthermore, if the wiring layer 22 corresponding to the selection gate line SGS is formed from multiple layers, each of the selection transistors ST2a and ST2b may be configured to function independently. In addition, there may be further selection gate lines SGS1a and SGS1b above the selection gate line SGS0b, as shown in Figure 9. These may be collectively referred to as selection gate line SGS1.

[0055] An insulating layer 41 is stacked on top of a semiconductor substrate (not shown), and further above, a plurality of wiring layers 22 and a plurality of insulating layers 42 are stacked alternately in sequence. In the example shown in Figure 7, two layers of wiring layers 22 and two layers of insulating layers 42 are stacked alternately. The plurality of wiring layers 22 are formed, for example, in a plate shape stretched along the X direction on the XY plane. Each wiring layer 22 is used as a selection gate line SGS0a and SGS0b. Each wiring layer 22 contains, for example, tungsten (W) or molybdenum (Mo). Each of the insulating layer 41 and the plurality of insulating layers 42 contains, for example, silicon oxide (SiO2).

[0056] Multiple wiring layers 23 and multiple insulating layers 43 are alternately stacked above the uppermost insulating layer 42. In the example shown in Figure 7, eight wiring layers 23 and seven insulating layers 43 are alternately stacked. Each wiring layer 23 is formed, for example, as a plate stretched along the X direction on the XY plane. Each wiring layer 23 is used as word lines WL0 to WL7, in order from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten. Each insulating layer 43 contains, for example, silicon oxide.

[0057] An insulating layer 44, another insulating layer 24, and another insulating layer 45 are stacked in this order above the uppermost wiring layer 23. The wiring layer 24 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 24 is used as a selectable gate wire SGD. The wiring layer 24 contains, for example, tungsten. The insulating layers 44 and 45 contain, for example, silicon oxide.

[0058] A wiring layer 25 is laminated above the insulating layer 45. The wiring layer 25 is formed, for example, in a line extending along the Y direction. The wiring layer 25 is used as a bit line BL. In a region not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper. An insulating layer 46 is laminated above the wiring layer 25. The insulating layer 46 is a layer connected to the bonding layer B2 and includes multiple wirings (not shown).

[0059] In Figures 3 and 4, after the semiconductor substrate W2 (not shown) is removed, a wiring layer 21 and an insulating layer 40 are provided below the insulating layer 41 in the Z1 direction in that order. The wiring layer 21 is formed, for example, in a plate shape stretched along the X direction on the XY plane. The wiring layer 21 is used as a source wire SL. The wiring layer 21 contains, for example, phosphorus-doped silicon. Furthermore, a wiring layer 300 shown in Figure 3 may be provided below the insulating layer 40. This wiring layer 300 includes a plurality of wirings (not shown).

[0060] Each of the columnar members MP is provided extending along the Z direction (first direction). The columnar members MP penetrate the wiring layers 22-24 and the insulating layers 41-44.

[0061] A columnar body MP includes, for example, a core film 30, a semiconductor film 31, and a multilayer film 32, as shown in Figure 8. In each columnar body MP, the core film 30 is provided stretched along the Z direction. For example, the upper end of the core film 30 of columnar body MP3 is located within the insulating layer 45, and the lower end of the core film 30 of columnar body MP1 is located within the wiring layer 21. The core film 30 includes, for example, an insulator such as silicon oxide. The semiconductor film 31 covers, for example, the periphery of the core film 30. At the lower end of the columnar body MP, a portion of the semiconductor film 31 is in contact with the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion where the semiconductor film 31 and the wiring layer 21 are in contact.

[0062] Figure 8 shows an example of a cross-section of a columnar body MP provided in a semiconductor memory device according to the first embodiment. More specifically, Figure 8 shows the cross-sectional structure of the columnar body MP in a layer parallel to the surface of a semiconductor substrate (not shown) and including a wiring layer 23. As shown in Figure 8, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0063] In a cross-section including the wiring layer 23, the core film 30 is provided, for example, in the central part of the columnar body MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The block insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the block insulating film 35. In the columnar body MP, the core film 30, semiconductor film 31, tunnel insulating film 33, charge storage film 34, and block insulating film 35 are each continuous from one end to the other in the Z direction of the columnar body MP.

[0064] The semiconductor film 31, tunnel insulating film 33, charge storage film 34, and block insulating film 35 are formed to have a predetermined thickness in the XY direction (second direction), which is a direction intersecting the Z direction (first direction). Therefore, in the second direction, the block insulating film 35 is provided on a plurality of wiring layers 23 and a plurality of insulating layers 43. Similarly, in the second direction, the charge storage film 34 is provided on the block insulating film 35. In the second direction, the tunnel insulating film 33 is provided on the charge storage film 34. In the second direction, the semiconductor film 31 is provided on the tunnel insulating film 33.

[0065] The semiconductor film 31 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 33 and the block insulating film 35 each contain, for example, silicon oxide. The charge storage film 34 has the function of storing charge and contains, for example, silicon nitride (SiN). With this configuration, each columnar body MP can function as a single NAND string NS.

[0066] The columnar structure MP contains a memory cell as a non-volatile semiconductor memory device. The memory cell is, for example, a charge-trap type memory cell. The core film 30 functions as a region where channels are formed. The wiring layer 23 functions as the control gate for the memory cell. The charge storage film 34 functions as a data storage layer that stores the charge injected from the core film 30. In other words, at the intersection of the core film 30 and each wiring layer 23, a memory cell is formed with a structure in which a control gate surrounds the channel.

[0067] The block insulating film 35 is an insulating layer that prevents the charge accumulated in the charge storage film 34 from diffusing into the wiring layer 23. The block insulating film 35 is, for example, a film containing metal and oxygen, such as an aluminum oxide film. The block insulating film 35 may have a multilayer structure having a layer containing a material having a higher dielectric constant than silicon oxide. For example, silicon nitride can be used as the high dielectric constant material.

[0068] In the columnar body MP shown in Figure 7, the portion where the wiring layer 22 intersects the columnar body MP functions as a selection transistor ST2. The portions where the columnar body MP intersects with each wiring layer 23 function as memory cell transistors MT0 to MT7, respectively. The portion where the wiring layer 24 intersects the columnar body MP3 functions as a selection transistor ST1.

[0069] A columnar contact CV is provided on the upper surface of the semiconductor film 31 within the columnar body MP. In the region shown in Figure 7, two of the six columnar bodies MPs are shown with two corresponding contact CVs. For columnar bodies MP in this region that do not overlap with the slit portion SHE and to which no contact CV is connected, another contact CV is connected in a region not shown.

[0070] Each contact CV has a wiring layer 25, i.e., one bit wire BL, in contact with its upper surface. One contact CV is connected to each wiring layer 25 in each of the spaces separated by the slit member SLT and the slit section SHE. In other words, each wiring layer 25 is electrically connected, for example, to one columnar body MP in each region between adjacent slit members SLT and slit sections SHE, and to one columnar body MP in each region between two adjacent slit sections SHE.

[0071] The slit members SLT are formed, for example, to extend along the XZ plane. Each of the slit members SLT penetrates the wiring layers 22-24 and the insulating layers 41-44. For example, each of the slit members SLT has a width in the Y direction that increases from bottom to top.

[0072] Within the slit member SLT, the contact LI is provided so as to spread along the XZ plane, and the spacer SP is provided between the contact LI and the wiring layers 22-24 and the insulating layers 41-45. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is in contact with, for example, the wiring layer 21. Note that the contact LI may be omitted depending on the structure of the memory cell array 10.

[0073] The slit portion SHE is formed, for example, as a plate extending along the XZ plane, and divides the wiring layer 24. The upper end of the slit portion SHE is located within the insulating layer 45. The lower end of the slit portion SHE is located, for example, within the uppermost insulating layer 43. The slit portion SHE contains an insulator, for example, silicon oxide. The upper end of the slit portion SHE and the upper end of the member SLT may or may not be aligned. Similarly, the upper end of the slit portion SHE and the upper end of the columnar body MP may or may not be aligned.

[0074] The slit member SLT is formed in the memory areas MA1 and MA2 in a plate-like shape that extends along the XZ plane, for example, and divides a plurality of wiring layers 22. For example, the upper end of the slit member SLT may be located at the boundary between the uppermost insulating layer 42 and the lowermost wiring layer 23, or it may be located inside the uppermost insulating layer 42. For example, the lower end of the slit member SLT may be located at the boundary between the wiring layer 21 and the insulating layer 41, or it may be located inside the insulating layer 41. Preferably, the slit member SLT is provided in the memory areas MA1 and MA2 at a position that overlaps with one slit portion SHE in the Z direction. The slit portion SHE includes an insulator such as silicon oxide. The lower end of the slit portion SHE and the lower end of the slit member SLT may or may not be aligned.

[0075] 1.1.5.3 Drawer area The general planar layout of the extraction region HA was previously explained based on Figure 5. Here, we will describe the structure of the extraction region HA, which is divided by the slit member SLTe, and its surrounding structure. As shown in Figure 9, in each extraction region HA, each extraction section HP is arranged in the Y direction and is provided for every two adjacent blocks BLK in the Y direction, with the slit member SLTo in between. In other words, each extraction section HP is divided into two by the slit member SLTe located between two adjacent blocks BLK within the extraction region HA. Hereinafter, one of the drawer sections HP separated by the slit member SLTe will be referred to as the first drawer section HP1, and the other drawer section HP2, and will be described separately. In Figure 9, the drawer section HP drawn above the slit member SLTe is referred to as the first drawer section HP1. In Figure 9, the drawer section HP drawn below the slit member SLTe is referred to as the second drawer section HP2.

[0076] As described above, the lead-out region HA includes multiple bridge sections BRG. In this embodiment, each bridge section BRG is provided for each block BLK. In each bridge section BRG, the portion provided in the memory region MA1 of each wiring layer of the stacked wiring is connected to the portion provided in the memory region MA2. In the example shown in Figure 9, a bridge section BRG is provided at a position along the slit SLT0 extending from the +Y end of block BLK0. In the example shown in Figure 9, a bridge section BRG is provided at a position along the slit SLT0 extending from the -Y end of block BLK1. In the example shown in Figure 9, the direction in which block BLK0 is positioned relative to block BLK1 is defined as the +Y direction, and the direction in which block BLK1 is positioned relative to block BLK0 is defined as the -Y direction. Furthermore, the direction in which memory area MA2 is positioned relative to draw-out area HA is defined as the +X direction, and the direction in which memory area MA1 is positioned relative to draw-out area HA is defined as the -X direction.

[0077] Figure 10 shows an overview of the staircase region SSA formed in the pull-out section HP and an overview of the connection status of the contact CC connected to the staircase region SSA. Note that the contact CC connected to the inclined staircase section SSAa and the inclined staircase section SSAb are omitted from Figure 11A. In the drawer section HP separated by the slit member SLTe, when viewing the drawer section HP1 in the Y direction from the slit member SLTe, the first drawer section HP1 is mountain-shaped with inclined stair sections on both sides, as described above.

[0078] As shown in Figures 9 to 11, in the first lead-out section HP1, each wiring layer 22 to 23 has a terrace portion so as not to overlap with the upper wiring layers 23 and 24. The shape of the terrace portion in the first lead-out section HP1 is similar to the shape of a step, terrace, or rimstone. Contact CCs are connected to the terrace portions of each wiring layer 22 to 23.

[0079] The multiple wiring layers 23 include inclined stair sections SSAa and SSAb in the first lead-out section HP1. The inclined stair sections SSAa and SSAb are steps that include the ends of the multiple continuously stacked wiring layers 23, arranged in a rectangular shape in a plan view. In the inclined stair sections SSAa and SSAb, the ends of the multiple continuously stacked wiring layers 23 are inclined at approximately the same angle in the diagonal directions in the XZ and YZ planes, and the inclined stair sections SSAa and SSAb form an inclined surface. Each of the multiple wiring layers 23 is electrically connected to the portion provided in memory area MA1 and the portion provided in memory area MA2 via a portion provided in bridge section BRG in the lead-out area HA. ​​In other words, the same wiring layer 23 has the same potential regardless of the portion.

[0080] In block BLK0, two recesses RE1 and RE2 are formed in the region sandwiched between slit members SLT0 and SLTe, adjacent to the bridge portion BRG, with bottoms that gradually decrease in height. Recesses RE1 and RE2 are adjacent to each other in the X direction. In block BLK1, two recesses RE3 and RE4 are formed in the region sandwiched between slit members SLT0 and SLTe, adjacent to the bridge portion BRG, with bottoms that gradually decrease in height. Recesses RE3 and RE4 are adjacent to each other in the X direction.

[0081] In the recess RE1, the lowest region RE1a is located close to the slit member SLTe and is formed in a region close to the memory region MA1. In Figure 9, the lowest region RE1a in the recess RE1 is formed in a rectangular shape in plan view. Rectangular regions RE1b, RE1c, RE1d, RE1e, RE1f, and RE1g are formed with region RE1a as the base, and their planar size gradually increases in the +X and +Y directions. The bottom of the recess RE1 is formed by the combination of regions RE1b, RE1c, RE1d, RE1e, RE1f, and RE1g. The aforementioned inclined staircase section SSAa is formed when parts of regions RE1a, RE1b, RE1c, RE1d, RE1e, RE1f, and RE1g are arranged in a step-like manner in the X direction along the slit member SLTe.

[0082] In the recess RE2, the lowest region RE2a is located close to the slit member SLTe and is situated in a region close to the memory region MA2. In Figure 9, the lowest region RE2a of the recess RE2 is formed in a rectangular shape in plan view. Rectangular regions RE2b, RE2c, RE2d, RE2e, RE2f, and RE2g are formed with region RE2a as the base, and their planar size gradually increases in the -X and +Y directions. The bottom of the recess RE2 is formed by the aggregation of regions RE2b, RE2c, RE2d, RE2e, RE2f, and RE2g. The aforementioned inclined staircase section SSAb is formed when parts of regions RE2a, RE2b, RE2c, RE2d, RE2e, RE2f, and RE2g are arranged in a step-like manner in the X direction along the slit member SLTe. As explained above, the inclined stair sections SSAa and SSAb are arranged along the X direction. Therefore, as shown in the cross-section of Figure 11A, the inclined stair sections SSAa and SSAb are arranged to form a mountain shape when viewed from the side.

[0083] Figure 11A is a cross-sectional view along the XIA-XIA line in Figure 9, and Figure 11B is a cross-sectional view along the XIB-XIB line in Figure 9. Figure 11A is a cross-section at the boundary between the slit SLTe and the first lead-out section HP1 and the second lead-out section HP2. Therefore, in Figure 11A, the inclined stair sections SSAa and SSAb are depicted in a mountain-like arrangement. Figure 11B is a cross-section along the XIB-XIB line passing through the center of the width of the slit SLTe. Therefore, in Figure 11B, the inclined stair sections SSAa and SSAb, hidden by the insulating layer, are depicted with dashed lines.

[0084] Contact CCs are connected to each step of the inclined staircase section SSAa formed on the -X side of block BLK0 as shown in Figure 9. As an example, in the inclined staircase section SSAa, the first contact CC from the left corresponds to the selected gate line SGS0b. The second contact CC from the left corresponds to the selected gate line SGS0a. The third contact CC from the left corresponds to the word line WL4. The fourth contact CC from the left corresponds to the word line WL5. The fifth contact CC from the left corresponds to the word line WL6. The sixth contact CC from the left corresponds to the word line WL7. In Figure 9, the type of line to be connected is indicated by a symbol enclosed in parentheses at the position of the corresponding contact CC in the first lead-out section HP1.

[0085] In the inclined staircase section SSAb formed on the +X side of block BLK0 shown in Figure 9, the first contact CC from the left corresponds to word line WL3. The second contact CC from the left corresponds to word line WL2. The third contact CC from the left corresponds to word line WL1. The fourth contact CC from the left corresponds to word line WL0. The fifth contact CC from the left corresponds to selection gate line SGS1a. The sixth contact CC from the left corresponds to selection gate line SGS1b.

[0086] Furthermore, each contact CC connected to the inclined staircase sections SSAa and SSAb of block BLK0 is connected to a different type of wire. Therefore, the lowest region RE1a of the inclined staircase section SSAa and the lowest region RE2a of the inclined staircase section SSAb, as shown in Figure 9, are formed at different heights in the Z direction. Similarly, regions RE1b to RE1g of the inclined staircase section SSAa are formed at different heights relative to regions RE2b to RE2g of the inclined staircase section SSAb, and are connected to different types of wires via individual contact CCs.

[0087] In the drawer section HP, which is divided by the slit member SLTe, the other drawer section HP2 also has inclined stair sections SSAa and SSAb, similar to drawer section HP1. Contact CCs are connected to each step of the inclined stair sections SSAa and SSAb.

[0088] The recess RE3 formed in block BLK1 has a shape that is symmetrical to the recess RE1 formed in block BLK0 in a plan view, with respect to the center line of the slit member SLTe as the axis. The recess RE4 formed in block BLK1 has a shape that is symmetrical to the recess RE2 formed in block BLK0 in a plan view, with respect to the slit member SLTe as the axis. The lowest region of the recess RE3, RE3a, is depicted as a rectangle in plan view in Figure 9. Using this region RE3a as a reference, rectangular regions RE3b, RE3c, RE3d, RE3e, RE3f, and RE3g are formed, gradually increasing in size in the +X and -Y directions in plan view. The bottom of the recess RE3 is formed by the aggregation of regions RE3b, RE3c, RE3d, RE3e, RE3f, and RE3g. In block BLK1, the stepped region SSAa is formed by the arrangement of parts of regions RE3a, RE3b, RE3c, RE3d, RE3e, RE3f, and RE3g in a step-like manner along the slit member SLTe in the X direction.

[0089] The lowest region of the recess RE4, RE4a, is depicted as a rectangle in plan view in Figure 9. Using this region RE4a as a reference, rectangular regions RE4b, RE4c, RE4d, RE4e, RE4f, and RE4g are formed, gradually increasing in size in the -X and -Y directions in plan view. The bottom of the recess RE4 is formed by the aggregation of regions RE4b, RE4c, RE4d, RE4e, RE4f, and RE4g. In block BLK1, the inclined staircase portion SSAb is formed by the arrangement of regions RE4a, RE4b, RE4c, RE4d, RE4e, RE4f, and RE4g in a step-like manner along the slit member SLTe in the X direction.

[0090] In the extension section HP2, as in the extension section HP1, contact CCs are placed at each step of the inclined staircase. As an example, the line types corresponding to each contact CC are listed below, starting from the left end of the inclined staircase section SSAa on the left side of the extension section HP2 in Figure 9. Contact CC for word line WL7, contact CC for word line WL6, contact CC for word line WL5, contact CC for word line WL4, contact CC for select gate line SGS0a, contact CC for select gate line SGS0b. In the inclined staircase section SSAb on the right side of the drawer section HP2 shown in Figure 9, the following points are made from left to right. Contact CC corresponding to selection gate line SGS1b, contact CC corresponding to selection gate line SGS1a, contact CC corresponding to word line WL0, contact CC corresponding to word line WL1, contact CC corresponding to word line WL2, and contact CC corresponding to word line WL3.

[0091] Each contact CC connected to the inclined staircase sections SSAa and SSAb of block BLK1 is for a different type of wire. Therefore, the regions RE1a to RE1g of the inclined staircase section SSAa of block BLK1 are formed at different height positions relative to the regions RE2a to RE2g of the inclined staircase section SSAb of block BLK1, and are connected to different types of wires via individual contact CCs.

[0092] The planar layout shown in Figure 9 can be described as having an access area HA between memory areas MA1 and MA2. For example, the memory region MA1 has a structure in which wiring layers (first conductive layers) 23 are stacked in a first direction, and columnar bodies MP penetrate the stacked wiring layers 23. Therefore, the memory region MA1 can be called a first region in which multiple wiring layers (first conductive layers) 23 are stacked in a first direction with space between them, and columnar bodies (semiconductor columns) MP extend in the first direction within the multiple wiring layers 23, and memory cells are formed at the intersections of the multiple wiring layers 23 and the columnar bodies MP. The memory region MA2 includes a plurality of wiring layers (second conductive layers) 23 stacked in a first direction with spacing between them, and columnar bodies (semiconductor columns) MP extending in the first direction within the plurality of wiring layers 23. The memory cells are formed at the intersections of the plurality of wiring layers 23 and the columnar bodies MP, and this can be called the second region. The first region and the second region are spaced apart in the X direction, which is different from the stacking direction of the wiring layers 23.

[0093] Furthermore, the lead-out region HA is located between the memory region (first region) MA1 and the memory region (second region) MA2 in a second direction intersecting the first direction, with multiple wiring layers (multiple third conductive layers) 23 stacked at intervals from each other. In addition, one of the multiple wiring layers 23 has a lead-out section HP that is continuous with one of the multiple wiring layers (first conductive layers) 23 of the memory region MA1 and one of the multiple wiring layers (second conductive layers) 23 of the memory region MA2. The lead-out region HA can be referred to as the third region. The lead-out region HA includes a bridge section (fourth region) BRG in which one of the multiple wiring layers (third conductive layers) 23 electrically connects one of the multiple first conductive layers and one of the multiple second conductive layers, and a staircase region (fifth region) SSA in which one of the multiple wiring layers (third conductive layers) 23 is connected to contact CC. The inclined staircase region SSA includes inclined staircase sections SSAa and SSAb in which parts of the multiple wiring layers (multiple third conductive layers) 23 are stacked in a staircase shape.

[0094] In this embodiment, the slit member SLTe, which separates the first drawer portion HP1 and the second drawer portion HP2 shown in Figure 9, has a distinctive structure. In the slit member SLTe, there is an intermittent portion 36 in the end region of the draw-out region HA that is close to the memory region MA2. In the slit member SLTe, there is an intermittent portion 36 located between region RE2a, which is the lowest position of recess RE2, and region RE4a, which is the lowest position of recess RE4. The intermittent section 36 is formed in a region close to the +X end of the inclined staircase section SSAb.

[0095] In the slit member SLTe, there is an intermittent portion 37 in the end region of the draw-out region HA that is close to the memory region MA1. In the slit member SLTe, there is an intermittent portion 37 located between region RE1a, which is the lowest position of recess RE1, and region RE3a, which is the lowest position of recess RE3. The intermittent portion 37 is located in the slit member SLTe at a position close to the -X end of the extraction region HA. Alternatively, it can be described as being located in the end region of the extraction region HA that is close to the memory region MA1.

[0096] The intermittent portion 36 is the portion where the spacer SP and contact LI constituting the slit member SLTe have been removed. The intermittent portion 37 is the portion where the spacer SP and contact LI constituting the slit member SLTe have been removed. Furthermore, the intermittent portion 36 is embedded by the bridging portion (embedding layer) 38, and the intermittent portion 37 is embedded by the bridging portion (embedding layer) 39. The bridging portions 38 and 39 contain silicon oxide. The bridging portions 38 and 39 are located on both sides of the slit member SLTe in the Y direction and are provided to bridge the insulating layer which is provided to embed the inclined stair portions SSAa and SSAb. Figure 11A shows a side view of the mountain-shaped first extension section HP1, with the inclined stair sections SSAa and SSAb as its two hypotenuses. Figure 11A also shows the locations of the bridge sections 38 and 39 in the base region of the mountain-shaped first extension section HP1 in the side view. In Figure 11A, the contact CC is omitted, and the inclined stair sections SSAa and SSAb are the main components of the representation.

[0097] Furthermore, as can be seen by comparing Figures 11A and 11B with Figure 9, when a cross-section is taken at the positions of the slit member SLTe and the intermittent sections 36 and 37, the inclined stair sections SSAa and SSAb are hidden and not visible by the slit member SLTe.

[0098] As shown in Figure 11A, the bridging sections 38 and 39 are located on both sides in the X direction of the mountain-shaped first extension section HP1 when viewed from the side. Furthermore, the bridging sections 38 and 39 are formed as projections extending in the Z direction from the mountain-shaped first extension section HP when viewed from the side, with a height reaching from the bottom surface of the lowest layer to the top surface of the highest layer. In other words, the bridging section 38 is formed to a height that reaches from the lowest points in the recesses RE2 and RE4, regions RE2a and RE4a, to the top of the recesses RE2 and RE4. The bridging section 39 is formed to a height that reaches from the lowest points in the recesses RE1 and RE3, regions RE1a and RE3a, to the top of the recesses RE1 and RE3. The lowest layers of the bridging sections 38 and 39 are formed in a part of the staircase region (fifth region) SSA where the inclined staircase sections SSAa and SSAb are not formed. As shown in Figure 11A, in the bridged sections 38 and 39, the width of the slit member in the extension direction (width in the X direction) in the upper bridged section 38 and 39 is greater than the width of the slit member in the extension direction (width in the X direction) in the lower bridged section 38 and 39. In the configuration shown in Figure 11A, the cross-sectional width of the bridge sections 38 and 39 along the XY plane gradually decreases from the Z1 direction end to the Z2 direction end.

[0099] As shown in Figure 9, an access area HA is formed between memory area MA1 and memory area MA2. In recesses RE2 and RE4 formed in access area HA, a bridging portion 38 is positioned along a location close to memory area MA2, and in recesses RE1 and RE3, a bridging portion 39 is positioned along a location close to memory area MA1. An insulating layer 50 is formed above the inclined staircase section SSAb. The insulating layer 50 is formed to fill the recesses RE1, RE2, RE3, and RE4. Figure 11A shows a cross-section along the XIA-XIA line in Figure 9, and displays the insulating layer 50 that fills the recesses RE1 and RE3. Figure 11B shows a cross-section along the XIB-XIB line in Figure 9, and displays the cross-section of the layers that make up the slit member SLTe. In memory region MA1, the insulating layer 43 formed between the wiring layers 23 can be referred to as the first insulating layer. In memory region MA2, the insulating layer 43 formed between the wiring layers 23 can be referred to as the second insulating layer. In lead-out region HP, the insulating layer 43 provided between the wiring layers 23 can be referred to as the third insulating layer. In lead-out region HA, the insulating layer 50 formed on the inclined stair sections SSAa and SSAb can be referred to as the fourth insulating layer.

[0100] As shown in Figure 9, the slit member SLTe is positioned to divide the inclined stair sections SSAa and SSAb of block BLK0 and SSAa and SSAb of block BLK1 into two sections in a plan view. The slit member SLTe also extends along the direction of extension of the stairs (stair arrangement direction: X direction) of the inclined stair sections SSAa and SSAb. In this view, the slit member SLTe can be described as dividing the inclined stair sections SSAa and SSAb of block BLK0 from the inclined stair sections SSAa and SSAb of block BLK1 in the stair width direction (Y direction) of the inclined stair sections SSAa and SSAb.

[0101] Now, let's explain the manufacturing method for the drawer section. A laminate is formed on a semiconductor substrate (not shown) by stacking multiple sacrificial layers and multiple insulating layers, not shown. The insulating layers stacked here are insulating layers 41, 42, 43, and 44 in the memory regions MA1 and MA2. The insulating layer 43 in the memory region MA1 can be called the first insulating layer, the insulating layer 43 in the memory region MA2 can be called the second insulating layer, and the insulating layer 43 in the extraction region HP can be called the third insulating layer. The laminate is etched to have inclined stair sections SSAa and SSAb. The inclined stair sections SSAa and SSAb are filled with an insulating layer. This insulating layer can be called the fourth insulating layer. A groove-shaped slit is formed across the inclined stair sections SSAa and SSAb at a position corresponding to the linear slit member SLTe shown in Figure 9 in plan view. If a break is formed in the middle of the linear slit, the insulating layer present in the break becomes a bridged section 38, 39. The sacrificial layer is dissolved and removed by etching solution through the groove-shaped slit. After this, a conductive layer is formed in the area where multiple sacrificial layers have been removed. This forms the inclined stair sections SSAa and SSAb, in which the wiring layer 23 (or wiring layers 22, 24) and the insulating layer 43 (or 41, 42, 44) are laminated. At this time, the bottom of the bridged sections 38, 39 is at the same level as, or lower than, the bottom of the lowest conductive layer 23. The conductive layer formed on the side walls and bottom surface of the groove-shaped slit is removed by etching. A spacer SP is formed inside the slit SLTe. When a contact LI is formed inside the spacer SP, the slit member SLTe is formed. The contact LI may be a conductor, an insulator, or a semiconductor. For example, the contact LI may be a metal such as tungsten, an oxide such as SiO2, a nitride such as SiN, or a semiconductor containing Si or Ge. By forming an insulating layer 50 on the inclined stair sections SSAa and SSAb, bridging sections 38 and 39 can be formed in the interrupted portions in the middle of the slit groove. The slit member SLT divides a unit region (block BLK) into a memory region MA1 (first region), a memory region MA2 (second region), and a drawout region HA (third region). Insulating layers 50 are formed on both sides in the width direction of the slit member SLTe. Therefore, the intermittent sections 36 and 37 formed on the slit member SLTe are formed to communicate with the stair region (fifth region), and the bridging sections 38 and 39 connect the insulating layers 50 on both sides in the width direction of the slit member SLTe.

[0102] 1.2 Operation according to the first embodiment According to the first embodiment, an insulating layer 50 is formed on the inclined stair sections SSAa and SSAb. A bridging section 39 is formed adjacent to the inclined stair section SSAa, and an insulating layer 50 is formed around it. A bridging section 38 is formed adjacent to the inclined stair section SSAb, and an insulating layer 50 is formed around it. Furthermore, bridging portions 38 and 39 are provided as part of the slit member SLTe that divides the drawer portion HP into a first drawer portion AP1 and a second drawer portion HP2. In addition, the drawer portion HP is formed to span multiple blocks BLK, and the slit member SLTe divides this drawer portion HP. As described above, the structure with the bridged sections 38 and 39 provides the following effects.

[0103] The structure of this embodiment is such that inclined stair sections SSAa and SSAb are provided to connect the wiring layers 22 and 23 of the memory areas MA1 and MA2. The slit member SLTo passes through the laminate of wiring layers 23 and insulating layer 43 formed in the memory areas MA1 and MA2. In contrast, the slit member SLTe passes through the laminate of wiring layers 23 and insulating layer 43 formed in the memory areas MA1 and MA2, and also passes through the lead-out section HP of the mountain-shaped laminated structure in the lead-out area HA. To form slit members SLTo and SLTe that pass through different processing regions, it is necessary to first form groove-shaped slits corresponding to the different processing regions, and then embed spacers SP and contacts LI to fill the slits.

[0104] However, due to differences in the processing area, an imbalance occurs in the processing at the part that divides the draw-out portion HP of the mountain-shaped laminated structure and in its surrounding area, causing deformation at the end of the draw-out portion HA of the laminated structure formed in memory areas MA1 and MA2. For example, after slit formation, the slit is filled with the material that constitutes the spacer SP and contact LI, but when heat is applied due to subsequent heat treatment, stress is placed on the film, causing deformation. In current semiconductor memory devices with miniaturized circuits, there is a risk of deformation of, for example, several nanometers to several tens of nanometers.

[0105] In contrast, in the structures shown in Figures 9 to 11, bridging portions 38 and 39 are provided on a part of the slit member SLTe. These bridging portions 38 and 39 are formed by leaving the insulating layer that was in the slit formation region when forming the groove-shaped slit that forms the basis of the slit member SLTe. That is, after forming the laminated structures that form the basis of the memory regions MA1 and MA2 and the laminated structures that form the basis of the inclined stair sections SSAa and SSAb, an insulating layer is formed on top of the laminated structures that form the basis of the inclined stair sections SSAa and SSAb. Then, when forming the slit for forming the slit member SLTe on this insulating layer, the bridging portions 38 and 39 are formed by leaving a part of the insulating layer intermittently, rather than making a slit that is continuous throughout the entire X direction.

[0106] In the semiconductor memory device 3, after forming a stack of insulating layers 42 and 43 and a sacrificial layer in memory regions MA1 and MA2, memory holes are formed, and after depositing block insulating films, tunnel insulating films, charge storage films, core films, etc., within the memory holes, a process is carried out to fabricate memory cell transistors by replacing the sacrificial layer with a metal layer. When replacing the sacrificial layer with a metal layer, a groove-shaped slit for forming a slit member is used to carry out the replacement of the sacrificial layer. Therefore, when heat treatment is performed after the basic structure of the memory cell transistor MT is formed, the heat treatment is performed while the slits are not filled. Also, in the drawout region HA, the slits are heated while they are not filled, so there is a risk that the stacked structure that forms the basis of the inclined step sections SSAa and SSAb, or the end of the stacked structure formed in the memory regions MA1 and MA2 on the drawout region HA side may deform due to the heating. However, in the aforementioned structure, bridging portions 38 and 39 exist at this stage, and the presence of these bridging portions 38 and 39 reduces the risk of deformation. Therefore, a well-formed structure that does not deform can be obtained as the base laminated structure for the inclined stair sections SSAa and SSAb. In addition, a well-formed structure that does not deform can be obtained at the end of the drawout area HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0107] By the way, in the embodiments shown in Figures 7 to 11, we have described an example in which a single layer of laminate is arranged, consisting of a wiring layer 23 and an insulating layer 43, with columnar bodies MP penetrating them in the Z direction, and bridge sections 38 and 39 are provided. For a laminate comprising a wiring layer 23 and an insulating layer 43, and a columnar body MP penetrating them in the Z direction, any number of layers (2 or more) can be constructed. Furthermore, the plan view shapes of the inclined stair sections SSAa and SSAb shown in Figure 9 are just one example and are not limited to this shape. The plan view shapes of the recesses RE1 to RE4 for forming the inclined stair sections SSAa and SSAb shown in Figure 9 are not limited to rectangular shapes, but any shape that can form the inclined stair sections SSAa and SSAb can be adopted.

[0108] Figure 12 shows an example of a structure in which three layers of laminates are stacked, each consisting of a wiring layer 23 and an insulating layer 43, with columnar bodies MP penetrating them in the Z direction. Figure 12 shows a structure in which a first laminate 55 is provided on the insulating layer 40 side, comprising a wiring layer 23 and an insulating layer 43, with a first columnar body (first semiconductor column) MP1 penetrating them in the Z direction. On top of this first laminate 55, a second laminate 56 is formed, comprising a wiring layer 23 and an insulating layer 43, with a second columnar body (second semiconductor column) MP2 penetrating them in the Z direction. On top of this second laminate 56, a third laminate 57 is formed, comprising a wiring layer 23 and an insulating layer 43, with a third columnar body (third semiconductor column) MP3 penetrating them in the Z direction. Since the other structures are equivalent to those of the first embodiment, their description is omitted, and equivalent components are denoted by the same reference numerals.

[0109] The structure with the cross-linked portion described in the previous embodiment can be applied to the structure having a three-layer laminate as shown in Figure 12. Figures 13A to 13C are explanatory diagrams illustrating the outline of the manufacturing process for a structure in which the cross-linking portion of the previous embodiment is provided in a three-layer draw-out region corresponding to a stack of three-layer memory regions. In the following diagrams, to simplify the illustration, the number of wiring layers and insulating layers constituting the laminate is shown in fewer figures, and the following is a simplified explanatory diagram.

[0110] As shown in Figure 13A, a first laminate 61 is formed having an inclined staircase section with the required number of insulating layers and sacrificial layers stacked. An insulating layer 62 is formed on the inclined staircase section of the first laminate 61. Then, the portion corresponding to the slit member SLTe in Figure 9 is etched to form a slit groove. The portion where the slit groove is not formed becomes the first bridging portion 63 on both the left and right sides in the X direction of the first laminate 61. The slit groove is filled with a sacrificial layer different from the sacrificial layer included in the first laminate 61. As shown in Figure 13B, a second laminate 65 having an inclined staircase section is formed on the first laminate 61 by laminating the required number of insulating layers and sacrificial layers. An insulating layer 66 is formed on the inclined staircase section of the second laminate 65. Then, the portion corresponding to the slit member SLTe in Figure 9 is etched to form a slit groove. The portion where the slit groove is not formed becomes a second bridging portion 67 formed on both the left and right sides in the X direction of the second laminate 65. The slit groove is filled with a sacrificial layer different from the sacrificial layers included in the first laminate 61 and the second laminate 65. The sacrificial layer filling the slit groove may be the same sacrificial layer as the sacrificial layers included in the first laminate 61 and the second laminate 65. In this example, the width of the second bridge section 67 in the X direction is greater than the width of the first bridge section 63 in the X direction. The reason the width of the second bridge section 67 can be increased is that the inclination of the inclined stair section of the first laminate 61 and the inclined stair section of the second laminate 65 are continuously connected, and the width of the region between the adjacent memory area MA1 or MA2 in the X direction is increased. That is, the width of the second bridge section 67 in the X direction extension direction is greater than the width of the first bridge section 63 in the X direction extension direction.

[0111] As shown in Figure 13C, a third laminate 68 having an inclined staircase section is formed on the second laminate 65 by laminating the required number of insulating layers and sacrificial layers. An insulating layer 69 is formed on the inclined staircase section of the third laminate 68. Then, the portion corresponding to the slit member SLTe in Figure 9 is etched to form a slit groove. The portion where no slit groove is formed becomes a third bridging section 70 formed on both the left and right sides in the X direction of the third laminate 68. In this example, the width of the third bridge section 70 in the X direction is greater than the width of the second bridge section 67 in the X direction. The reason the width of the third bridge section 70 can be increased is that the inclination of the inclined stair section of the second laminate 65 and the inclined stair section of the third laminate 68 are continuously connected, and the width of the region between the adjacent memory area MA1 or MA2 in the X direction is increased. That is, the width of the third bridge section 70 in the X direction extension direction is greater than the width of the second bridge section 67 in the X direction extension direction. Subsequently, the sacrificial layer filling the slit grooves formed in the first laminate 61 and the second laminate 65 is removed. Then, the sacrificial layer, which is alternately laminated with the insulating layer of the first laminate 61, the second laminate 65, and the third laminate 68, is replaced with a conductive layer.

[0112] The structure shown in Figure 13C has first bridging sections 63 on both the left and right sides of the first laminate 61, second bridging sections 67 on both the left and right sides of the second laminate 65, and third bridging sections 70 on both the left and right sides of the third laminate 68. Therefore, according to the structure shown in Figure 13C, the risk of deformation at the memory area side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area, is reduced. Therefore, a well-formed stacked structure without deformation can be obtained as the base stacked structure for the inclined stair sections SSAa and SSAb, similar to the structure shown in Figures 9 to 11. Furthermore, a well-formed stacked structure without deformation can be obtained at the end of the draw-out area HA side of the stacked structure formed in the memory areas MA1 and MA2.

[0113] (Second Embodiment) Figure 14A shows a second embodiment of a structure in which a cross-linking portion is provided to the draw-out region of the three-layer structure. The structure shown in Figure 14A omits the first bridging portion 63 that was provided in the structure shown in Figure 13C, and an insulating layer 62 is formed in the position where the bridging portion 63 was formed.

[0114] In this structure as well, since it has bridging sections 67 and 70, it exhibits a deformation prevention function similar to that of the structure shown in Figure 13C. In other words, the risk of deformation at the memory area side of each layer of the stacked structures 65 and 68, and at the draw-out area HA side of each layer of the memory area, is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. In addition, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0115] (Third embodiment) Figure 14B shows a third embodiment of a structure in which a cross-linking portion is provided to the draw-out region of the three-layer structure. The structure shown in Figure 14B is an example in which the bridging portions 63 and 67 that were provided in the structure shown in Figure 13C are omitted, and insulating layers 62 and 66 are formed in the locations where the bridging portions 63 and 67 were formed.

[0116] In this structure as well, since it has a bridging section 70, a deformation prevention function similar to that of the structure shown in Figure 13C is exhibited. In other words, the risk of deformation at the memory area side of each layer of the stacked structure 68 and at the draw-out area HA side of each layer of the memory area is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. In addition, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0117] (Fourth embodiment) Figure 14C shows a fourth embodiment of a structure in which a cross-linking portion is provided to the three-layered drawout region. The structure shown in Figure 14C is an example in which the bridging portions 63 and 70 that were provided in the structure shown in Figure 13C are omitted, and insulating layers 62 and 69 are formed in the positions where the bridging portions 63 and 70 were formed.

[0118] In this structure as well, since it has a bridging section 67, a deformation prevention function similar to that of the structure shown in Figure 13C is exhibited. In other words, the risk of deformation at the memory area side of each layer of the stacked structure 65 and at the draw-out area HA side of each layer of the memory area is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. In addition, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0119] (Fifth embodiment) Figure 14D shows a fifth embodiment of a structure in which a cross-linking portion is provided to the three-layered drawout region. The structure shown in Figure 14D is an example in which the bridging portions 63, 67, and 70 on the +X direction side of the laminates 61, 65, and 68 that were provided in the structure shown in Figure 13C are omitted, and insulating layers 62, 66, and 69 are formed in the positions where the bridging portions 63, 67, and 70 on the +X direction side were formed.

[0120] In this structure as well, since the laminates 61, 65, and 68 have bridging portions 63, 67, and 70 on the -X direction side, a deformation prevention function similar to that of the structure shown in Figure 13C is achieved. In other words, the risk of deformation at the memory area MA1 side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area MA1, is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. Furthermore, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory area MA1.

[0121] Figures 15A to 15C are explanatory diagrams illustrating the manufacturing process in order for a structure similar to Figure 13C, in which a cross-linking section is provided to the three-layered drawout region HA. The manufacturing method for the structure shown in Figure 13C has been briefly described earlier. Figure 15A shows the state after forming the first laminate 61, first bridged portion 63 and insulating layer 62, the second laminate 65, second bridged portion 67 and insulating layer 66, and the third laminate 68, third bridged portion 70 and insulating layer 69, similar to the state shown in Figure 13C, and then removing the insulating layers 69, 66, and 62 from this laminate. Figure 15A shows the state after forming three layers of slits that will serve as the base for forming the slit member, and removing the insulating layers that fill the inside of the slits.

[0122] After forming groove-shaped slits, a memory cell transistor is constructed by depositing block insulating films, tunnel insulating films, charge storage films, core films, etc., inside the memory holes where columnar bodies are to be formed, within the laminated structure of the insulating layer 43 and sacrificial layer formed in the memory regions MA1 and MA2. When the material forming the block insulating film is aluminum oxide, an aluminum oxide film is formed, and then films of the materials constituting the tunnel insulating film, charge storage film, and core film are deposited.

[0123] Therefore, even in the structure shown in Figure 15A, where the insulating layer filling the inside of the slit has been removed, block insulating films, tunnel insulating films, charge storage films, core films, etc., are deposited. The block insulating films, tunnel insulating films, charge storage films, and core films formed in the memory holes are necessary and are therefore left, but the films formed in the slits are unnecessary and are therefore removed. However, even when etching means are used to remove the tunnel insulating film, charge storage film, and core film, the aluminum oxide film for the block insulating film remains and is not removed. Therefore, after removing the insulating layer, an aluminum oxide film 71 remains on the bottom and sides of the first bridged portion 63, the second bridged portion 67, and the third bridged portion 70. The aluminum oxide film 71 formed on the bottom and sides of the first bridged portion 63, the second bridged portion 67, and the third bridged portion 70 is shown in Figures 15B and 15C. Note that Figure 15B is a cross-sectional view in which a film for forming a memory cell transistor is filled inside the slit, and a sloping staircase portion is shown assuming that there is a sloping staircase behind this film. After removing the tunnel insulating film, charge storage film, and core film material layers that were formed inside the slit, the structure shown in Figure 15C is completed by embedding spacers SP and contacts LI inside the slit.

[0124] In the structure shown in Figure 15C, since the laminates 61, 65, and 68 have bridging portions 63, 67, and 70 on both sides in the X direction, the same deformation prevention function as in the structure shown in Figure 13C is achieved. In other words, the risk of deformation at the memory area MA1 side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area MA1, is reduced. Also, the risk of deformation at the memory area MA2 side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area MA2, is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. In addition, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0125] Figures 16A to 16C are explanatory cross-sectional views corresponding to each process in manufacturing the three-layer laminate shown in Figures 13A to 13C. They are cross-sectional views of the side where the inclined staircase is formed, along the cross-section in the width direction center of the slit member SLTe. As explained earlier, in Figures 13A to 13C, the bridge sections and the inclined staircase are shown on the same plane to make the relative positions of the first bridge section 63, the second bridge section 67, and the third bridge section 70 with respect to the inclined staircase easier to see. In reality, as shown in Figure 9, the slit member SLTe and the lead-out portion HP1 are formed with a misalignment in the Y direction. Therefore, as shown in Figures 16A and 16B, layers for forming the slit member exist between the left and right first bridging portions 63, 63 and between the left and right second bridging portions 67, 67. Figures 16A to 16C illustrate this relationship.

[0126] (Sixth Embodiment) Figure 17 is an explanatory diagram showing a sixth embodiment of a laminated structure having an inclined staircase section and a bridging section formed in the drawer area HA. ​​Figure 17 shows both a plan view showing the layout of the drawer area HA and memory areas MA1 and MA2, and cross-sectional views of the drawer area HA and memory areas MA1 and MA2. Figure 17 shows the slit members SLT0 and SLTe simplified as single-layer structures. In the structure shown in Figure 17, the configuration of the inclined staircase section and the structure of the memory areas MA and MA2 are equivalent to the structure shown in Figure 13C or Figure 15C.

[0127] In the structure shown in Figure 17, the structure of the bridging portion differs from that shown in Figures 13C and 15C. The structure of the first bridging portion 63 provided on the first laminate 61 is the same as in the structures shown in Figures 13C and 15C. In the structure shown in Figure 17, second bridging portions 73 are formed on both the left and right sides in the X direction of the second laminate 65 so as to connect to the first bridging portion 63. In addition, third bridging portions 75 are formed on both the left and right sides in the X direction of the third laminate 68 so as to connect to the second bridging portions 73. The first cross-linked portion 63, the second cross-linked portion 73, and the third cross-linked portion 75 are formed continuously so as to form a single line in the Z direction. A coating 76 equivalent to the aluminum oxide coating 71 described with reference to Figure 15C is formed on the sides of the first cross-linked portion 63, the second cross-linked portion 73, and the third cross-linked portion 75.

[0128] In the structure shown in Figure 17, a second second bridge section 77 is formed closer to the inclined stair section of the second laminate 65 than the second bridge section 73, and spaced apart from the inclined stair section. The structure of the second bridge section 77 is similar in shape to the second bridge section 73, but its formation location is different. In the structure shown in Figure 17, third bridge sections 78 are formed on both the left and right sides in the X direction of the third laminate 68, so as to be connected on top of the second bridge section 77. A third third bridge section 79 is formed closer to the inclined stair section of the third laminate 68 than the third bridge section 78, and spaced apart from the inclined stair section. The structure of the third bridge section 79 is similar in shape to the second bridge section 77, but its formation location is different.

[0129] According to the structure of the sixth embodiment shown in Figure 17, multiple bridging portions 75, 78, 79, or multiple bridging portions 73, 77 are provided in the stretching direction (Z direction) of the slit member SLTe. Even with a structure having multiple bridging portions in the stretching direction (Z direction) of the slit member SLTe, the same deformation prevention function as the structure shown in Figure 13C is achieved. In other words, the risk of deformation at the memory area MA1 side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area MA1, is reduced. Also, the risk of deformation at the memory area MA2 side of each layer of the stacked structures 61, 65, and 68, and at the draw-out area HA side of each layer of the memory area MA2, is reduced. Therefore, a well-formed, deformation-free laminated structure is obtained as the base for the inclined stair sections SSAa and SSAb. In addition, a well-formed, deformation-free laminated structure is obtained at the end of the draw-out section HA side of the laminated structure formed in the memory areas MA1 and MA2.

[0130] (Seventh Embodiment) Figure 18 is an explanatory diagram showing a seventh embodiment of a laminated structure having an inclined staircase section and a bridging section formed in the drawer area HA. ​​Figure 18 shows both a plan view showing the layout of the drawer area HA and memory areas MA1 and MA2, and cross-sectional views of the drawer area HA and memory areas MA1 and MA2. In the structure shown in Figure 18, the configuration of the inclined staircase section and the structure of memory areas MA and MA2 are equivalent to the structure shown in Figure 13C or Figure 15C.

[0131] The structure shown in Figure 18 also has a first bridge section 63, similar to the structure shown in Figure 17, and in addition, it has second bridge sections 73 and 77, and third bridge sections 75, 78, and 79. In the structure shown in Figure 17, the first bridge section 63, the second bridge section 73, and the third bridge section 75 were unified in the Z direction. In contrast, in the structure shown in Figure 18, the first bridge section 63 and the third bridge section 75 are arranged in the Z direction, but the second bridge section 73 is offset in the -X direction relative to the first bridge section 63 and the third bridge section 75. In the structure shown in Figure 18, the second bridge section 77 is offset in the -X direction relative to the third bridge section 78. As shown in Figure 18, even if the bridged sections are arranged in an alternating staggered pattern in the X direction, the deformation prevention function of the laminated structure is still achieved, similar to the previous embodiment.

[0132] (Eighth embodiment) Figures 19A to 19C are explanatory diagrams illustrating the manufacturing process in order for a structure similar to Figure 11, in which a cross-linking portion is provided to the extraction region HA. Figure 19A shows that in the structure shown in Figure 11, the slit member SLTe was formed inside a groove-shaped slit having the same width. In contrast, in the structure of the eighth embodiment, the slit consists of a collection of multiple holes. Holes 80 with a diameter corresponding to the width of the groove-shaped slit forming the slit member SLTe are arranged in a row. Multiple holes 80 are formed linearly along the X direction at predetermined intervals to match the position where the slit member SLTe is to be placed. That is, multiple holes 80 are etched linearly along the X direction at predetermined intervals to match the position where the slit member SLTo is to be formed. Alternatively, the holes 80 may be formed so that they slightly overlap each other in a linear manner. The holes 80 and the holes for forming the memory pillar MP may be formed by the same etching process. The planar layout in that state is shown in Figure 19A. Note that no holes 80 are formed at the location where the first bridge section 63 should be formed.

[0133] Next, by further etching, the spaces between adjacent holes 80, 80 are etched as shown in Figure 19B, connecting multiple holes 80 in the X direction. This forms a slit with multiple connected holes 80. By filling the slit 82, which is formed at the position where the slit member SLTo should be placed, with the material for forming the slit member SLTo, the slit member SLTo can be formed. By filling the slit 83, which is formed at the position where the slit member SLTe should be placed, with the material for forming the slit member SLTe, the slit member SLTe can be formed.

[0134] Subsequently, by performing the memory cell transistor formation process and other necessary processes similar to those described based on Figures 15A to 15C, a structure having a first bridging portion 84, a second bridging portion 85, and a third bridging portion 86 in the cross-sectional structure shown in Figure 19C can be obtained. The structure shown in Figure 19C also exhibits the deformation prevention function of the laminated structure, similar to the previous embodiment.

[0135] (Ninth Embodiment) Figures 20A and 20B show the structure of the ninth embodiment, in which a cross-linking portion is provided to the three-layered extension portion HP. The structure having the first cross-linking portion 63 on the first laminate 61 is the same as in the previous embodiment. In this embodiment, three second cross-linking portions 87 are formed on the second laminate 65, spaced apart in the X direction. Furthermore, in the third laminate 68, a third cross-linking portion 88 is formed that is wider than the X-direction formation width of the three second cross-linking portions 87 formed spaced apart along the X direction on the second laminate 65.

[0136] As shown in the eighth embodiment, there are no particular restrictions on the width in the X direction of the first bridging portion 63, the second bridging portion 87, and the third bridging portion 88. Any width can be selected for the X direction of the first bridging portion 63, the second bridging portion 87, and the third bridging portion 88, as long as the width does not come into contact with the first laminate 61, the second laminate 65, and the third laminate 68, and does not come into contact with the surrounding memory area MA1. In other words, the widths of the first bridge section 63, the second bridge section 87, and the third bridge section 88 along the extension direction of the slit member SLT can be selected to any width.

[0137] While embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0138] 1...Memory system, 3...Semiconductor memory device, 10...Memory cell array 21, 22... Wiring layer, 23... Wiring layer (first conductive layer, second conductive layer), 24... Wiring layer, 31... Semiconductor film, 33... Tunnel insulating film, 34... Charge storage film 35...block insulating film, 36, 37...intermittent sections, 38, 39...crosslinked sections, 43...Insulating layer (first insulating layer, second insulating layer), 44, 45, 46...Insulating layer, 55...First layer, 56...Second layer, 57...Third layer, 61...First layer 63...First bridge section, 65...Second laminate, 67...Second bridge section, 68...Third laminate, 70...Third crosslinked part, 71...Coating, 73...Second crosslinked part, 75...Third crosslinked part, 76...Coating, 77...Second crosslinked part, 78, 79...Third crosslinked part, 85...Second crosslinked part, 86...Third crosslinking part, BL...bit line, BLK0~BLK5...block (unit area) BRG...Bridge area (4th region), CC...Contact, HA...Drawer area (third area), HP...Drawer part, MA1…Memory area (first area), MA2…Memory area (second area) MP...Columnar body, MP1...Columnar body (first semiconductor column), MP2...Columnar body (second semiconductor column), MP3...Columnar body (third semiconductor column) MT, MT0~MTn...memory cell transistor, SHE...slit section, SGS0, SGS1, SGD... Selectable gate lines, SLT, SLTo, SLTe... Slit members, SSA...stairs area (5th area), SSAa, SSAb...slanted staircase part, W1…Semiconductor substrate, WL, WL0~WLn…Word lines

Claims

1. A first region comprising a plurality of first conductive layers stacked in a first direction with spacing between them, and a first semiconductor column extending in the first direction within the plurality of first conductive layers, wherein a memory cell is formed at the intersection of the plurality of first conductive layers and the first semiconductor column, A second region comprising a plurality of second conductive layers stacked at intervals from each other, and a second semiconductor column extending in the first direction within the plurality of second conductive layers, wherein a memory cell is formed at the intersection of the plurality of second conductive layers and the second semiconductor column, It includes a plurality of third conductive layers stacked at intervals from each other, and in a second direction intersecting the first direction, it is positioned between the first region and the second region, and one of the plurality of third conductive layers comprises a third region that is continuous with one of the plurality of first conductive layers and one of the plurality of second conductive layers. The third region includes a fourth region within which one of the plurality of third conductive layers electrically connects one of the plurality of first conductive layers and one of the plurality of second conductive layers, and a fifth region within which one of the plurality of third conductive layers is connected to a contact, wherein the fifth region includes an inclined staircase portion in which a part of the plurality of third conductive layers are stacked in a staircase shape. A plurality of unit regions comprising the first region, the second region, and the third region are provided, The device comprises a plurality of slit members that individually divide the aforementioned unit region, Of the plurality of slit members, some of the slit members are formed at positions that divide the fifth region. The aforementioned slit member includes an intermittent portion that communicates with the fifth region located on both sides of the slit member in the width direction, and includes a bridging portion that fills the intermittent portion. Semiconductor memory device.

2. The first semiconductor column and the second semiconductor column each have a block insulating film, a charge storage film, and a semiconductor film. The side or bottom surface of the crosslinked portion has a coating made of the same material as the block insulating film. The semiconductor memory device according to claim 1.

3. The aforementioned coating contains aluminum The semiconductor memory device according to claim 2.

4. The crosslinked portion contains silicon oxide, and the crosslinked portion has a height from the lowest to the highest layer of the inclined staircase. The semiconductor memory device according to claim 1.

5. The lowest layer of the bridge section is formed in a part of the fifth region where the inclined stair section is not formed. A semiconductor memory device according to any one of claims 1 to 4.

6. The first region has a laminated structure in which a plurality of first laminates, each containing a plurality of first conductive layers and a first semiconductor column extending through these plurality of first conductive layers in a first direction, are stacked in the first direction. The second region has a laminated structure in which a plurality of second laminates, each containing a plurality of second conductive layers and a second semiconductor column extending through these plurality of second conductive layers in the first direction, are stacked in the first direction. The third region is a laminated structure having conductive layers corresponding to the first laminate and the second laminate. A semiconductor memory device according to any one of claims 1 to 4.

7. The first region has a laminated structure in which a plurality of first laminates, each containing a plurality of first conductive layers and a first semiconductor column extending through these plurality of first conductive layers in a first direction, are stacked in the first direction. The second region has a laminated structure in which a plurality of second laminates, each containing a plurality of second conductive layers and a second semiconductor column extending through these plurality of second conductive layers in the first direction, are stacked in the first direction. The third region is a laminated structure having conductive layers corresponding to the first laminate and the second laminate. The bridging portion has a laminated structure with a height corresponding to the height in the stacking direction of the first laminate and the second laminate, and the width in the stretching direction of the slit member in the upper bridging portion is greater than the width in the stretching direction of the slit member in the lower bridging portion. A semiconductor memory device according to any one of claims 1 to 4.

8. A first region comprising a plurality of first conductive layers stacked via a first insulating layer and a first semiconductor column penetrating the plurality of first conductive layers, wherein a memory cell is formed at the intersection of the first conductive layer and the first semiconductor column, The structure includes a plurality of second conductive layers stacked via a second insulating layer and a plurality of second semiconductor pillars penetrating the second conductive layers, a memory cell formed at the intersection of the second conductive layers and the second semiconductor pillars, and a second region spaced apart from the first region in a direction different from the stacking direction, Multiple third conductive layers are stacked via a third insulating layer, and a third region is positioned between the first region and the second region. The third region has an inclined staircase portion formed in part of the third conductive layer, in which part of the third conductive layer is arranged in a staircase shape, a contact is connected to the inclined staircase portion, and a slit member is provided that extends in the direction of the staircase arrangement of the inclined staircase portion, divides the inclined staircase portion in the staircase width direction, and has an intermittent portion corresponding to a part of the inclined staircase portion. The aforementioned inclined staircase section is covered with a fourth insulating layer. A method for manufacturing a semiconductor memory device, After laminating a plurality of sacrificial layers and a plurality of first insulating layers in the first region, laminating a plurality of sacrificial layers and a plurality of second insulating layers in the second region, and laminating a plurality of sacrificial layers and a plurality of third insulating layers in the third region, the inclined staircase portion is formed in the third region by etching, and the inclined staircase portion is filled with a fourth insulating layer, The inclined stair section is divided in the width direction along the extending direction of the inclined stair section, forming a groove-shaped slit with an intermittent portion, and the formation of the slit creates a bridging portion made of the fourth insulating layer in the intermittent portion, thereafter, After dissolving and removing the plurality of sacrificial layers in the third region through the slit, the plurality of third conductive layers are formed in the positions of the plurality of sacrificial layers in the third region. A method for manufacturing semiconductor memory devices.

9. A spacer and contact are formed inside the groove-shaped slit to fill the groove-shaped slit. The method for manufacturing a semiconductor memory device according to claim 8.

10. The sacrificial layer is dissolved and removed by the etching solution through the aforementioned slit. The method for manufacturing a semiconductor memory device according to claim 8.

11. The method for manufacturing a semiconductor memory device according to claim 9 or 10, wherein the lowest part of the crosslinked portion is located lower than the lowest part of the plurality of third conductive layers.

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