Semiconductor equipment

Abstract

To provide a semiconductor device that maintains low capacitance values, ensures ESD withstand capability and surge withstand capability, and has a small surface area. [Solution] The semiconductor device includes a semiconductor substrate 10, an intermediate region 25 including a laminated structure in which a first semiconductor region 20 and a second semiconductor region 30 are stacked, a laminated structure in which a third semiconductor region 40 and a fourth semiconductor region 50 are stacked, and a second conductivity type embedded region 15 arranged surrounding the third semiconductor region 40. The impurity concentration of the second semiconductor region 30 is lower than that of the first semiconductor region 20 and the third semiconductor region 40. The fourth semiconductor region 50 and the third semiconductor region 40 constitute a Zener diode. The third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25 constitute a PIN diode. The first semiconductor region 20 and the lowermost first semiconductor region 25 constitute a Zener diode with the semiconductor substrate 10.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND ART

[0002] A semiconductor device (hereinafter also referred to as an "overvoltage protection element") that protects an internal circuit from unexpected surge voltage applied to input / output terminals due to static electricity or fluctuations in power supply voltage is used in semiconductor integrated circuits such as LSI (Large Scale Integration). The overvoltage protection element includes an ESD (electro-static discharge) protection element. As the overvoltage protection element, diodes including Transient Voltage Suppressors (TVS) diodes, thyristors, npn-type or pnp-type bipolar transistors, and the like are used. PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0003] Patent Document 1 Japanese Unexamined Patent Publication No. 2021-190531

[0004] [Summary] It is preferable that the capacitance value of an overvoltage protection element connected to an input / output terminal is low. An object of the present disclosure is to provide a semiconductor device that maintains a low capacitance value to ensure ESD withstand voltage and surge withstand voltage, and has a small area.

[0005] One aspect of this disclosure is a semiconductor device comprising a semiconductor substrate, an intermediate region including a stacked structure in which a first semiconductor region and a second semiconductor region are stacked, a third semiconductor region, a fourth semiconductor region stacked, and a second conductivity type embedded region arranged around the third semiconductor region. The impurity concentration of the second semiconductor region is lower than that of the first and third semiconductor regions. The fourth semiconductor region and the third semiconductor region constitute a Zener diode. The third semiconductor region and the uppermost second semiconductor region of the intermediate region constitute a PIN diode. The first and second semiconductor regions constitute a PIN diode. The lowermost first semiconductor region of the intermediate region constitutes a Zener diode with the semiconductor substrate. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing the configuration of a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view showing an example of the configuration of a semiconductor substrate included in the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating the operation of the semiconductor device according to the first embodiment. [Figure 6] Figure 6 is an equivalent circuit diagram illustrating the current path in the operation of the semiconductor device shown in Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating other operations of the semiconductor device according to the first embodiment. [Figure 8] Figure 8 is an equivalent circuit diagram illustrating the current path in the operation of the semiconductor device shown in Figure 7. [Figure 9] Figure 9 is a schematic diagram showing an example in which the semiconductor device according to the first embodiment is used as an overvoltage protection element. [Figure 10]Figure 10 is a schematic cross-sectional view showing the configuration of a comparative example semiconductor device. [Figure 11] Figure 11 is an equivalent circuit diagram of the comparative example semiconductor device shown in Figure 10. [Figure 12] Figure 12 is a schematic cross-sectional view showing the configuration of a modified example of the semiconductor device of the comparative example. [Figure 13] Figure 13 is the equivalent circuit diagram of the comparative example semiconductor device shown in Figure 12. [Figure 14] Figure 14 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. [Figure 15] Figure 15 is a schematic plan view showing the configuration of a semiconductor device according to the second embodiment. [Figure 16] Figure 16 is a schematic cross-sectional view showing an example of the configuration of a semiconductor substrate included in a semiconductor device according to the second embodiment. [Figure 17] Figure 17 is an equivalent circuit diagram of a semiconductor device according to the second embodiment. [Figure 18] Figure 18 is a schematic cross-sectional view illustrating the operation of a semiconductor device according to the second embodiment. [Figure 19] Figure 19 is a schematic cross-sectional view illustrating other operations of the semiconductor device according to the second embodiment. [Figure 20] Figure 20 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the first modified example of the second embodiment. [Figure 21] Figure 21 is a schematic plan view showing the configuration of a semiconductor device according to the first modified example of the second embodiment. [Figure 22] Figure 22 is an equivalent circuit diagram of a semiconductor device according to the first modified example of the second embodiment. [Figure 23] Figure 23 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second modified example of the second embodiment. [Figure 24] Figure 24 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. [Figure 25] Figure 25 is a schematic plan view showing the configuration of a semiconductor device according to the third embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view illustrating a configuration example of a semiconductor substrate included in a semiconductor device according to a third embodiment. [Figure 27] FIG. 27 is an equivalent circuit diagram of the semiconductor device according to the third embodiment. [Figure 28] FIG. 28 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a first modification of the third embodiment. [Figure 29] FIG. 29 is an equivalent circuit diagram of the semiconductor device according to the first modification of the third embodiment. [Figure 30] FIG. 30 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a second modification of the third embodiment. [Figure 31] FIG. 31 is an equivalent circuit diagram of a semiconductor device according to another embodiment. [Figure 32] FIG. 32 is an equivalent circuit diagram of another semiconductor device according to another embodiment. [Figure 33] FIG. 33 is an equivalent circuit diagram of still another semiconductor device according to another embodiment.

[0007] [Detailed Description] Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar reference numerals are assigned to the same or similar parts. It should be noted, however, that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each part, and the like differ from actual situations. In addition, it goes without saying that the drawings include portions where the dimensional relationship or ratio differs between each other.

[0008] In addition, the embodiments shown below are examples of apparatuses or methods for embodying the technical idea, and do not limit the shape, structure, arrangement, and the like of constituent components to those described below. Various modifications can be made to this embodiment within the scope of the claims.

[0009] (First Embodiment) Figure 1 shows a semiconductor device 1 according to the first embodiment. The semiconductor device 1 comprises a semiconductor substrate 10 of a first conductivity type, a first semiconductor region 20 of a second conductivity type disposed on the upper surface of the semiconductor substrate 10, and a second semiconductor region 30 of a different conductivity type from the first semiconductor region 20, disposed on the semiconductor substrate 10 and covering the first semiconductor region 20. A third semiconductor region 40 of a second conductivity type is disposed on the upper surface of the second semiconductor region 30 so as to face the first semiconductor region 20 via the second semiconductor region 30. A fourth semiconductor region 50 of a first conductivity type is embedded in a part of the upper part of the third semiconductor region 40. The impurity concentration of the second semiconductor region 30 is lower than the impurity concentrations of the first semiconductor region 20 and the third semiconductor region 40. As shown in Figure 1, the third semiconductor region 40 may be embedded in a part of the upper part of the second semiconductor region 30.

[0010] As described above, the semiconductor device 1 has a stacked structure in which a semiconductor substrate 10, a first semiconductor region 20, a second semiconductor region 30, a third semiconductor region 40, and a fourth semiconductor region 50 are stacked in order. Hereinafter, the region consisting of semiconductors including the semiconductor substrate 10, the first semiconductor region 20, the second semiconductor region 30, the third semiconductor region 40, and the fourth semiconductor region 50 will also be referred to as the semiconductor substrate 100.

[0011] The first and second conductivity types are opposite to each other. That is, if the first conductivity type is N-type, the second conductivity type is P-type, and if the first conductivity type is P-type, the second conductivity type is N-type. Therefore, the diode is constructed in the semiconductor substrate 100 as follows: The semiconductor substrate 10 and the first semiconductor region 20 constitute a Zener diode. The first semiconductor region 20 and the second semiconductor region 30 constitute a PIN diode. The second semiconductor region 30 and the third semiconductor region 40 constitute a PIN diode. The third semiconductor region 40 and the fourth semiconductor region 50 constitute a Zener diode. The Zener diode can be used even with high voltages of about 50V, for example, and current flows in both directions.

[0012] The following will provide an illustrative explanation of the case where the first conductivity type is N-type and the second conductivity type is P-type. Furthermore, the semiconductor device 1 will be described assuming that the second semiconductor region 30 has a different conductivity type from the first semiconductor region 20, which is P-type, and is N-type with a lower impurity concentration than the first semiconductor region 20 and the third semiconductor region 40. In this disclosure, in semiconductor regions with P-type and N-type conductivity types, regions with a negative (-) sign indicate a relatively lower impurity concentration than regions without a sign. Conversely, regions with a positive (+) sign indicate a relatively higher impurity concentration than regions without a sign.

[0013] For example, the first semiconductor region 20 and the third semiconductor region 40 have a thickness of approximately 0.5 μm to 10 μm and an impurity concentration of 5E15 / cm³. 3 ~5E18 / cm 3 It is a P-type diffusion layer of a certain degree. The second semiconductor region 30 has a thickness of approximately 3 μm to 15 μm and an impurity concentration of 1 E11 / cm³. 3 ~1E15 / cm 3 It is an N-type semiconductor of a certain degree. Furthermore, the second semiconductor region 30 has an impurity concentration of 1E11 / cm³. 3 It may also be an intrinsic semiconductor (type i) with a lower coefficient of ion.

[0014] As shown in Figure 1, the thickness direction of the semiconductor substrate 10 is defined as the Z direction. In Figure 1, the Z direction is the vertical direction of the paper. The plane perpendicular to the Z direction is defined as the XY plane, which is defined by the X and Y directions. In Figure 1, the X direction is the horizontal direction of the paper, and the Y direction is the depth direction of the paper. In this disclosure, in the Z direction, the direction in which the first semiconductor region 20 is located relative to the semiconductor substrate 10 is defined as the upward direction, and the direction in which the semiconductor substrate 10 is located relative to the first semiconductor region 20 is defined as the downward direction. The surface facing upward is referred to as the top surface, and the surface facing downward is referred to as the bottom surface. For example, the top and bottom surfaces of the semiconductor substrate 10 are parallel to the XY plane.

[0015] A first insulating layer 71 is placed on the upper surface of the semiconductor substrate 100. An upper metal layer 61 is placed on the upper surface of the first insulating layer 71. An opening is formed in a part of the first insulating layer 71, and the fourth semiconductor region 50 and the upper metal layer 61 are electrically connected through this opening. In other words, the semiconductor substrate 100 and the upper metal layer 61 are electrically insulated by the first insulating layer 71, except for the area in which the fourth semiconductor region 50 is exposed at the opening in the first insulating layer 71. A second insulating layer 72 is placed over the first insulating layer 71 and the upper metal layer 61, and a part of the upper metal layer 61 is exposed at an opening formed in the second insulating layer 72. The upper metal layer 61 is electrically connected to the first external terminal 101 of the semiconductor device 1. The first insulating layer 71 and the second insulating layer 72 are interlayer insulating films and play a role in insulating the wirings in the semiconductor device 1 with a multilayer wiring structure.

[0016] For example, an aluminum (Al) film may be used for the upper metal layer 61. Alternatively, a multilayer film may be used for the upper metal layer 61, with a Ti film as the bottom layer, consisting of an aluminum copper (AlCu) film: 0.5 μm to 5 μm, a titanium nitride (TiN) film: 50 nm to 150 nm, and a titanium (Ti) film: 10 nm to 50 nm. The first insulating layer 71 may be a silicon oxide (SiO2) film with a thickness of 0.5 μm to 6 μm. The second insulating layer 72 may be a silicon nitride (SiN) film with a thickness of 0.5 μm to 4 μm.

[0017] A protective layer 80 is placed on the upper surfaces of the first insulating layer 71 and the second insulating layer 72. The protective layer 80 coats the surface of the semiconductor device 1 to prevent influence from the external environment and adhesion of contaminants. The protective layer 80 may be, for example, a polyimide film with a thickness of 2 μm to 10 μm.

[0018] A lower electrode layer 62 is positioned on the lower surface of the semiconductor substrate 10, on which the first semiconductor region 20 is located on the upper surface. The lower electrode layer 62 is made of the same metallic material as the upper metal layer 61. The lower electrode layer 62 is electrically connected to the second external terminal 102 of the semiconductor device 1.

[0019] Figure 2 shows a plan view of the semiconductor device 1 as seen from the Z direction, which is the normal direction to the upper surface of the semiconductor substrate 10 (hereinafter also referred to as the "plan view"). Figure 1 is a cross-sectional view along the II direction in Figure 2. In Figure 2, the protective layer 80, the first insulating layer 71, the second insulating layer 72, and the upper metal layer 61 are not shown, and the upper surface of the semiconductor substrate 100 is shown by passing through these layers (the same applies to the following plan views). It is preferable that the area of ​​the upper metal layer 61 that contacts the fourth semiconductor region 50 is inside the outer edge of the fourth semiconductor region 50. This makes it possible to reduce parasitic capacitance between the upper metal layer 61 and the fourth semiconductor region 50.

[0020] The dashed line shown in Figure 2 indicates the outer edge of the upper metal layer 61 (the same applies to the following plan views). In Figure 2, the X-direction distance Xd1 is the length of the upper metal layer 61 along the X direction, and the Y-direction distance Yd1 is the length of the upper metal layer 61 along the Y direction. In the first embodiment, Xd1 = 140 μm and Yd1 = 140 μm.

[0021] Figure 3 shows a semiconductor substrate 100 when the first conductivity type is N-type and the second conductivity type is P-type. As shown in Figure 3, the first Zener diode Z1 is constructed with the first semiconductor region 20 as the anode and the semiconductor substrate 10 as the cathode. The first PIN diode P1 is constructed with the first semiconductor region 20 as the anode and the second semiconductor region 30 as the cathode. The second PIN diode P2 is constructed with the third semiconductor region 40 as the anode and the second semiconductor region 30 as the cathode. The second Zener diode Z2 is constructed with the third semiconductor region 40 as the anode and the fourth semiconductor region 50 as the cathode.

[0022] In the following, unless otherwise specified, the first PIN diode P1 and the second PIN diode P2 will also be referred to as "PIN diode P". Similarly, unless otherwise specified, the first Zener diode Z1 and the second Zener diode Z2 will also be referred to as "Zener diode Z". Zener diode Z functions as a voltage-clamping type surge protection element.

[0023] Figure 4 shows an equivalent circuit diagram composed of the PIN diode P and Zener diode Z included in the semiconductor device 1. The cathode of the second Zener diode Z2 is connected to the first external terminal 101, and the anode of the second Zener diode Z2 is connected to the anode of the second PIN diode P2. The cathode of the second PIN diode P2 is connected to the cathode of the first PIN diode P1, and the anode of the first PIN diode P1 is connected to the anode of the first Zener diode Z1. The cathode of the first Zener diode Z1 is connected to the second external terminal 102. However, in the semiconductor device 1 shown in Figure 1, the second semiconductor region 30 is connected to the semiconductor substrate 10 outside the first semiconductor region 20. Therefore, the connection point between the cathode of the second PIN diode P2 and the cathode of the first PIN diode P1 is short-circuited to the second external terminal 102.

[0024] As described above, semiconductor device 1 has a structure in which PIN diodes P and Zener diodes Z are stacked in the film thickness direction (Z direction). Hereinafter, stacking PIN diodes P and Zener diodes Z in the film thickness direction will be referred to as "vertical stacking". Also, a structure in which PIN diodes P and Zener diodes Z are vertically stacked will be referred to as a "vertical stacking structure". By using semiconductor device 1 including a vertical stacking structure, the area in a plan view (hereinafter simply referred to as "area") can be reduced.

[0025] Figure 4 shows an example of the capacitance values ​​of the PIN diode P and Zener diode Z in semiconductor device 1. The capacitance value of the PIN diode P is approximately 1 pF, and the capacitance value of the Zener diode Z is approximately 100 pF. Therefore, the combined capacitance value of semiconductor device 1 is approximately 1 pF.

[0026] The basic operation of semiconductor device 1 is described below.

[0027] First, referring to Figure 5, the operation when a positive voltage is applied to the first external terminal 101 will be explained. When a large positive voltage is applied to the first external terminal 101, the NPN transistor composed of the fourth semiconductor region 50, the third semiconductor region 40, and the second semiconductor region 30 undergoes a breakdown operation. As a result, a first current I11 flows from the first external terminal 101 to the second external terminal 102. In addition, a lower depletion layer 91 is formed at the interface between the first semiconductor region 20 and the second semiconductor region 30, and an upper depletion layer 92 is formed at the interface between the second semiconductor region 30 and the third semiconductor region 40. Therefore, a second current I12 flows to the semiconductor substrate 10 directly below the fourth semiconductor region 50, via the second semiconductor region 30 and the first semiconductor region 20. Therefore, as shown in the equivalent circuit diagram of Figure 6, a combined current I1, which is the sum of the first current I11 and the second current I12, flows from the first external terminal 101 to the second external terminal 102.

[0028] Next, referring to Figure 7, the operation when a positive voltage is applied to the second external terminal 102 will be explained. When a large positive voltage is applied to the second external terminal 102, the width of the depletion layer on the first external terminal 101 side of the depletion layer formed at the interface between the second semiconductor region 30 and the P-type semiconductor region widens. In other words, the upper depletion layer 92 formed at the interface between the second semiconductor region 30 and the third semiconductor region 40 extends downward toward the first semiconductor region 20. Then, as shown in Figure 7, the second semiconductor region 30 is completely depleted between the first semiconductor region 20 and the third semiconductor region 40. As a result, the N region of the PNP region composed of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 disappears. Therefore, the entirety of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 becomes electrically equivalent to a P-type region.

[0029] As a result, as shown in Figure 8, the entire semiconductor substrate 100 can be considered as an NPN transistor. Therefore, when a large positive voltage is applied to the second external terminal 102, the NPN transistor undergoes a breakdown operation, and a breakdown current I2 flows from the second external terminal 102 to the first external terminal 101.

[0030] As described above, the semiconductor device 1 can function as a bidirectional TVS. The impurity concentrations of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 are set to enable the above operation. In other words, the impurity concentration of the semiconductor substrate 100 is set such that a depletion layer is formed from the top to the bottom surface of the second semiconductor region 30 when a predetermined voltage is applied between the semiconductor substrate 10 and the fourth semiconductor region 50.

[0031] In order to use the semiconductor device 1 as an overvoltage protection element, the impurity concentration of the semiconductor substrate 100 is set such that the second semiconductor region 30 is completely depleted when a surge voltage is applied to, for example, the first external terminal 101 or the second external terminal 102. For example, the impurity concentrations of the semiconductor substrate 10, the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 may be set assuming a surge voltage (clamp voltage) of approximately 3V to 50V. A Zener diode Z is formed according to the surge voltage and the required withstand voltage. On the other hand, the lower the impurity concentration of the second semiconductor region 30, the lower the capacitance value of the semiconductor device 1 can be. The film thickness of the second semiconductor region 30 does not affect the capacitance value if it is 4μm or more.

[0032] Figure 9 shows an example in which the semiconductor device 1 is used as an overvoltage protection element. The first external terminal 101 of the semiconductor device 1 is connected to the input / output terminal T of the semiconductor integrated circuit 200, and the second external terminal 102 is connected to the ground electrode GND of the semiconductor integrated circuit 200. When a surge voltage or voltage due to electrostatic discharge (ESD) is applied to the input / output terminal T of the semiconductor integrated circuit 200, a current flows between the first external terminal 101 and the second external terminal 102 of the semiconductor device 1, as explained with reference to Figures 5 and 7. As a result, the semiconductor device 1 protects the internal circuit 210 connected to the input / output terminal T from the overvoltage applied to the input / output terminal T.

[0033] Figure 10 shows a comparative semiconductor device (hereinafter referred to as "comparative protection element 300") for comparison with semiconductor device 1. The comparative protection element 300 shown in Figure 10 includes a first protection element 30MA and a second protection element 30MB. The comparative protection element 300 has a structure in which the first protection element 30MA and the second protection element 30MB, which have the same structure, are connected in series in opposite directions. Hereafter, unless limited, the first protection element 30MA and the second protection element 30MB will be referred to as "protection element 30M".

[0034] The protective element 30M has a structure in which a P+ layer 311 and an N- layer 312 are sequentially stacked on the upper surface of a P+SUB substrate 310. A P+ well region 321 is embedded from the upper surface of the N- layer 312 to a part of the upper part of the P+ layer 311. A first N- region 322 is embedded in a part of the upper part of the P+ well region 321, and an N+ electrode region 323 is embedded in a part of the upper part of the first N- region 322. As shown in Figure 10, the first diode PinA is configured with the P+ well region 321 as the anode and the first N- region 322 as the cathode.

[0035] Separated from the P+ well region 321, the embedded P region 331 is positioned across a portion of the upper part of the P+ layer 311 and a portion of the lower part of the N- layer 312. The N+ well region 332 is embedded in the N- layer 312 from the upper surface of the N- layer 312 to the upper surface of the embedded P region 331. A second N- region 333 is embedded in a portion of the upper part of the N+ well region 332, and a P+ electrode region 334 is embedded in a portion of the upper part of the second N- region 333. As shown in Figure 10, the second diode PinB is formed with the P+ electrode region 334 as the anode and the second N- region 333 as the cathode. Furthermore, the Zener diode ZE is formed with the embedded P region 331 as the anode and the N+ well region 332 as the cathode.

[0036] A silicon oxide layer 341 is formed on the upper surface of the N-layer 312, and a metal layer 350 is placed on the upper surface of the silicon oxide layer 341. The metal layer 350 is, for example, an Al film. The metal layer 350 is electrically connected to the N+ electrode region 323 and the P+ electrode region 334 through openings formed in the silicon oxide layer 341. The metal layer 350 is covered by a silicon nitride layer 342. Furthermore, the silicon nitride layer 342 is covered by a polyimide film 360. A portion of the metal layer 350 is exposed to the outside through openings continuously formed in the silicon nitride layer 342 and the polyimide film 360.

[0037] As shown in Figure 10, the first protection element 30MA and the second protection element 30MB are connected in series in opposite directions by short-circuiting their respective metal layers 350 with a conductive wire 370. The P+SUB substrate 310 of the first protection element 30MA is connected to the first terminal 301 of the comparative protection element 300, and the P+SUB substrate 310 of the second protection element 30MB is connected to the second terminal 302 of the comparative protection element 300.

[0038] Figure 11 shows the equivalent circuit diagram of the comparative protection element 300 shown in Figure 10. For example, by connecting the first terminal 301 between the input / output terminal and the internal circuit of a semiconductor integrated circuit and connecting the second terminal 302 to the ground electrode, the comparative protection element 300 can be used as an overvoltage protection element for a semiconductor integrated circuit. By connecting the first protection element 30MA and the second protection element 30MB in series in opposite directions, the comparative protection element 300 functions as a bidirectional TVS. For example, when a positive voltage is applied to the first terminal 301, current flows from the first terminal 301 to the second terminal 302. When a positive voltage is applied to the second terminal 302, current flows from the second terminal 302 to the first terminal 301.

[0039] Figure 12 shows a modified example of the comparative protection element 300. In the comparative protection element 300 shown in Figure 10, the first protection element 30MA and the second protection element 30MB are connected in series in opposite directions by a wire 370. On the other hand, in the comparative protection element 300 shown in Figure 12, the first protection element 30MA and the second protection element 30MB are formed on the same P+SUB substrate 310, P+ layer 311, and N- layer 312. In other words, the comparative protection element 300 shown in Figure 12 has a structure in which the first terminal 301 of the first protection element 30MA and the second terminal 302 of the second protection element 30MB are short-circuited. In the comparative protection element 300 shown in Figure 12, the metal layer 350 of the first protection element 30MA is connected to the first terminal 301, and the metal layer 350 of the second protection element 30MB is connected to the second terminal 302. The other structural aspects of the comparative protection element 300 shown in Figure 12 are the same as those of the comparative protection element 300 shown in Figure 10. Figure 13 shows the equivalent circuit diagram of the comparative protection element 300 shown in Figure 12. In the comparative protection element 300 shown in Figure 12, the comparative protection element 300 functions as a bidirectional TVS by connecting the first protection element 30MA and the second protection element 30MB in series in opposite directions.

[0040] As shown in Figures 11 and 13, when the capacitance values ​​of the first diode PinA and the second diode PinB are 1 pF, and the capacitance value of the Zener diode ZE is 100 pF, the combined capacitance values ​​of the first protection element 30MA and the second protection element 30MB are approximately 2 pF. Therefore, the combined capacitance value of the reference protection element 300, which is formed by connecting the first protection element 30MA and the second protection element 30MB in series, is 1 pF. As previously stated, the combined capacitance value of the semiconductor device 1, including the vertically stacked structure, is approximately 1 pF. Therefore, the combined capacitance values ​​of the reference protection element 300 and the semiconductor device 1 are equivalent.

[0041] However, the protection element 30M of the comparative protection element 300 has a configuration in which the region formed by the first diode PinA and the region in which the second diode PinB and Zener diode ZE are stacked in the film thickness direction are arranged side by side in a plan view. Therefore, the area of ​​the protection element 30M is larger than that of the semiconductor device 1. Furthermore, the comparative protection element 300, which has a configuration in which two protection elements 30M are arranged side by side in a plan view, requires an even larger area.

[0042] In contrast, the semiconductor device 1 according to the first embodiment has a structure in which a PIN diode P and a Zener diode Z are stacked vertically. By stacking the Zener diodes vertically, the area of ​​the Zener diodes is half that of the comparative protection element 300. Therefore, the semiconductor device 1 can have a smaller area than the comparative protection element 300.

[0043] As described above, the semiconductor device 1 according to the first embodiment can reduce the area of ​​the elements compared to the comparative protection element 300 by stacking the PIN diode P and Zener diode Z vertically. As a result, the semiconductor device 1 can reduce the area while maintaining a low capacitance value and ensuring ESD withstand capability and surge withstand capability.

[0044] (Second embodiment) Figure 14 shows a semiconductor device 1A according to the second embodiment. The semiconductor device 1A shown in Figure 14 comprises a semiconductor substrate 10 of a first conductivity type and an intermediate region 25 disposed on the upper surface of the semiconductor substrate 10. The intermediate region 25 includes at least one laminated structure (hereinafter also referred to as "intermediate laminated structure") in which a second semiconductor region 30 having a different conductivity type from the first semiconductor region 20 is laminated on a first semiconductor region 20 having a second conductivity type. The semiconductor device 1 shown in Figure 14 shows the case in which the intermediate region 25 includes one intermediate laminated structure.

[0045] The semiconductor device 1A further comprises a third semiconductor region 40 of a second conductivity type embedded in the upper part of the second semiconductor region 30 of the uppermost layer of the intermediate region 25, and a fourth semiconductor region 50 of a first conductivity type embedded in a part of the upper part of the third semiconductor region 40. The third semiconductor region 40 faces the semiconductor substrate 10 via the intermediate region 25. The impurity concentration of the second semiconductor region 30 is lower than that of the first semiconductor region 20 and the third semiconductor region 40.

[0046] Furthermore, the semiconductor device 1A includes an embedded region 15 that extends from the upper surface of the intermediate region 25 toward the semiconductor substrate 10. The embedded region 15 is arranged surrounding the third semiconductor region 40 without being electrically connected to it, and defines the extent of the second semiconductor region 30 in a plan view. The embedded region 15 is a second-conductivity semiconductor, and its bottom is connected to the first semiconductor region 20.

[0047] The semiconductor device 1A according to the second embodiment differs from the semiconductor device 1 shown in Figure 1 in that it further includes an embedded region 15. Other configurations of the semiconductor device 1A are the same as those of the first embodiment shown in Figure 1.

[0048] As described above, the semiconductor device 1A has a stacked structure in which a semiconductor substrate 10, an intermediate region 25 including a stacked structure of a first semiconductor region 20 and a second semiconductor region 30, a third semiconductor region 40, and a fourth semiconductor region 50 are stacked in order. Furthermore, the semiconductor device 1A includes a second conductivity type embedded region 15 arranged around the third semiconductor region 40. The fourth semiconductor region 50 and the third semiconductor region 40 constitute a Zener diode. The third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25 constitute a PIN diode. The first semiconductor region 20, the lowest layer of the intermediate region 25, constitutes a Zener diode with the semiconductor substrate 10.

[0049] Figure 15 shows a plan view of the semiconductor device 1A shown in Figure 14. Figure 14 is a cross-sectional view along the XIV-XIV direction in Figure 15. In Figure 15, the X-direction distance Xd2 is the length of the upper metal layer 61 along the X direction, and the Y-direction distance Yd2 is the length of the upper metal layer 61 along the Y direction. In the second embodiment, Xd2 = 140 μm and Yd2 = 140 μm.

[0050] Figure 16 shows the semiconductor substrate 100 of semiconductor device 1A when the first conductivity type is N-type and the second conductivity type is P-type. As shown in Figure 16, the first Zener diode Z1 is formed with the first semiconductor region 20 as the anode and the semiconductor substrate 10 as the cathode. The first PIN diode P1 is formed with the first semiconductor region 20 as the anode and the second semiconductor region 30 as the cathode. The second PIN diode P2 is formed with the third semiconductor region 40 as the anode and the second semiconductor region 30 as the cathode. The second Zener diode Z2 is formed with the third semiconductor region 40 as the anode and the fourth semiconductor region 50 as the cathode.

[0051] Figure 17 shows an equivalent circuit diagram consisting of the PIN diode P and Zener diode Z included in the semiconductor device 1A. The cathode of the second Zener diode Z2 is connected to the first external terminal 101, and the anode of the second Zener diode Z2 is connected to the anode of the second PIN diode P2. The cathode of the second PIN diode P2 is connected to the cathode of the first PIN diode P1, and the anode of the first PIN diode P1 is connected to the anode of the first Zener diode Z1. The cathode of the first Zener diode Z1 is connected to the second external terminal 102.

[0052] The capacitance values ​​of the PIN diode P and Zener diode Z included in semiconductor device 1A are as shown in Figure 17. Specifically, the capacitance value of Zener diode Z is approximately 100 pF. The capacitance value of the first PIN diode P1 is approximately 1.8 pF, and the capacitance value of the second PIN diode P2 is approximately 1 pF. Therefore, the combined capacitance value of semiconductor device 1A is approximately 0.64 pF. Because the area of ​​the first PIN diode P1 is larger than that of the second PIN diode P2, the capacitance value of the first PIN diode P1 is greater than that of the second PIN diode P2.

[0053] In the semiconductor device 1A according to the second embodiment, the area of ​​the Zener diodes is half that of the comparative protection element 300 because the Zener diodes are stacked vertically. Furthermore, compared to the comparative protection element 300 which includes four PIN diodes, the semiconductor device 1A can reduce the area and capacitance value of the PIN diodes by half by removing the first diode PinA of the comparative protection element 300. Therefore, the semiconductor device 1A can reduce the area compared to the comparative protection element 300 while maintaining a low capacitance value and ensuring equivalent ESD withstand capability and surge withstand capability. Otherwise, the semiconductor device 1A is substantially the same as that of the first embodiment, and redundant descriptions are omitted.

[0054] In semiconductor device 1A, the third semiconductor region 40 is surrounded by the embedded region 15, and two PIN diodes are connected in series in opposite directions in the current path of the current that flows when a surge voltage is applied. Therefore, with semiconductor device 1A, the capacitance value can be made even smaller than in semiconductor device 1 according to the first embodiment, in which the second semiconductor region 30 is connected to the semiconductor substrate 10 and the PIN diodes included in the current path are one.

[0055] The basic operation of semiconductor device 1A is described below.

[0056] First, referring to Figure 18, the operation of the semiconductor device 1A when a positive voltage is applied to the first external terminal 101 will be explained. When a positive voltage is applied to the first external terminal 101, the width of the depletion layer on the second external terminal 102 side of the depletion layer formed at the interface between the second semiconductor region 30 and the P-type semiconductor region widens. In other words, the lower depletion layer 91 formed at the interface between the first semiconductor region 20 and the second semiconductor region 30 extends upward toward the third semiconductor region 40, as indicated by the arrow. Then, when a large voltage (e.g., surge voltage) is applied to the first external terminal 101, the second semiconductor region 30 is completely depleted between the first semiconductor region 20 and the embedded region 15 and the third semiconductor region 40. In other words, the N region of the PNP region composed of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 disappears. Therefore, the entirety of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 becomes electrically equivalent to a P-type region.

[0057] As a result, the entire semiconductor substrate 100 can be considered as an NPN transistor, similar to Figure 8. Therefore, when a large positive voltage is applied to the first external terminal 101, the NPN transistor breaks down, and a breakdown current flows from the first external terminal 101 to the second external terminal 102. This causes the semiconductor device 1A to function as an overvoltage protection element.

[0058] Next, referring to Figure 19, the operation of the semiconductor device 1A when a positive voltage is applied to the second external terminal 102 will be explained. When a positive voltage is applied to the second external terminal 102, the width of the depletion layer on the first external terminal 101 side of the depletion layer formed at the interface between the second semiconductor region 30 and the P-type semiconductor region widens. In other words, the upper depletion layer 92 formed between the second semiconductor region 30 and the third semiconductor region 40 extends downward toward the first semiconductor region 20, as indicated by the arrow. Then, when a large voltage (e.g., surge voltage) is applied to the second external terminal 102, the second semiconductor region 30 is completely depleted between the first semiconductor region 20 and the embedded region 15 and the third semiconductor region 40. In other words, the N region of the PNP region composed of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 disappears. Therefore, the entirety of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 becomes electrically equivalent to a P-type region.

[0059] As a result, the entire semiconductor substrate 100 can be considered as an NPN transistor, similar to Figure 8. Therefore, when a large positive voltage is applied to the second external terminal 102, the NPN transistor breaks down, and a breakdown current flows from the second external terminal 102 to the first external terminal 101. This causes the semiconductor device 1A to function as an overvoltage protection element.

[0060] As described above, the semiconductor device 1A can operate as a bidirectional TVS. In the semiconductor device 1A, the impurity concentration of the semiconductor substrate 100 may be set in the same way as in the semiconductor device 1 according to the first embodiment. That is, the impurity concentrations of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 may be set such that a depletion layer is formed from the upper surface to the lower surface of the second semiconductor region 30 when a predetermined voltage is applied between the semiconductor substrate 10 and the fourth semiconductor region 50. Furthermore, the second semiconductor region 30 may be an intrinsic semiconductor (type i).

[0061] As described above, according to the semiconductor device 1A of the second embodiment, the area of ​​the element can be reduced compared to the comparative protection element 300 by stacking the PIN diode P and Zener diode Z vertically. As a result, according to the semiconductor device 1A, the area can be reduced compared to the comparative protection element 300 while ensuring ESD withstand capability and surge withstand capability at low capacitance values. Furthermore, since the semiconductor device 1A has a configuration in which two PIN diodes are connected in series, the capacitance value can be reduced compared to the semiconductor device 1 of the first embodiment, which has one PIN diode.

[0062] (First variation) Figure 20 shows a semiconductor device 1A according to the first modification of the second embodiment. The intermediate region 25 of the semiconductor device 1A shown in Figure 20 has multiple intermediate stacked structures in which a second semiconductor region 30 is stacked on a first semiconductor region 20. The semiconductor device 1A in Figure 20 differs from the semiconductor device 1A shown in Figure 14 in that the intermediate stacked structures are arranged in multiple layers in the intermediate region 25. Hereinafter, the intermediate stacked structure on the side closer to the semiconductor substrate 10 will be referred to as the "lower layer," and the intermediate stacked structure on the side closer to the third semiconductor region 40 will be referred to as the "upper layer."

[0063] The semiconductor device 1A shown in Figure 20 includes a plurality of embedded regions 15 that are individually connected to each of the first semiconductor regions 20 included in a plurality of intermediate stacked structures. As shown in Figure 20, the plurality of embedded regions 15 are arranged in multiple layers in a plan view such that the embedded regions 15 connected to the first semiconductor region 20 closer to the semiconductor substrate 10 are on the outside. Figure 21 shows a plan view of the semiconductor device 1A shown in Figure 20. Figure 20 is a cross-sectional view along the XX-XX direction in Figure 21.

[0064] In the semiconductor device 1A shown in Figure 20, in addition to the PIN diode P and Zener diode Z included in the semiconductor device 1A shown in Figure 14, a third PIN diode P3 and a fourth PIN diode P4 are configured inside the intermediate region 25. More specifically, the bottommost first semiconductor region 20 of the intermediate region 25 constitutes the semiconductor substrate 10 and the first Zener diode Z1. The lower first semiconductor region 20 and the lower second semiconductor region 30 constitute the first PIN diode P1. The third semiconductor region 40 constitutes the topmost second semiconductor region 30 of the intermediate region 25 and the second PIN diode P2. The fourth semiconductor region 50 constitutes the third semiconductor region 40 and the second Zener diode Z2. The third PIN diode P3 uses the lower second semiconductor region 30 as its cathode and the upper first semiconductor region 20 as its anode. The fourth PIN diode P4 uses the upper first semiconductor region 20 as its anode and the upper second semiconductor region 30 as its cathode.

[0065] Figure 22 shows an equivalent circuit diagram consisting of the PIN diode P and Zener diode Z included in the semiconductor device 1A shown in Figure 20. The cathode of the second Zener diode Z2 is connected to the first external terminal 101, and the anode of the second Zener diode Z2 is connected to the anode of the second PIN diode P2. The cathode of the second PIN diode P2 is connected to the cathode of the fourth PIN diode P4, and the anode of the fourth PIN diode P4 is connected to the anode of the third PIN diode P3. The cathode of the third PIN diode P3 is connected to the cathode of the first PIN diode P1, and the anode of the first PIN diode P1 is connected to the anode of the first Zener diode Z1. The cathode of the first Zener diode Z1 is connected to the second external terminal 102.

[0066] As shown in Figure 20, the area of ​​the fourth PIN diode P4 is larger than that of the second PIN diode P2. Furthermore, the area of ​​the third PIN diode P3 is larger than that of the fourth PIN diode P4, and the area of ​​the first PIN diode P1 is larger than that of the third PIN diode P3. Therefore, the capacitance value of the fourth PIN diode P4 is larger than that of the second PIN diode P2, the capacitance value of the third PIN diode P3 is larger than that of the fourth PIN diode P4, and the capacitance value of the first PIN diode P1 is larger than that of the third PIN diode P3. The capacitance values ​​of the PIN diodes P and Zener diode Z included in semiconductor device 1A are as shown in Figure 22. That is, the capacitance value of Zener diode Z is approximately 100pF. The capacitance value of the second PIN diode P2 is approximately 1pF, and the capacitance value of the fourth PIN diode P4 is approximately 1.8pF. The capacitance value of the third PIN diode P3 is approximately 2.3pF, and the capacitance value of the first PIN diode P1 is approximately 4.3pF. Therefore, the combined capacitance value of semiconductor device 1A is approximately 0.45pF. In this way, by arranging multiple intermediate stacked structures in the intermediate region 25, the capacity value can be reduced compared to the case where there is only one intermediate stacked structure.

[0067] In the semiconductor device 1A shown in Figure 20, when a voltage is applied to the first external terminal 101 or the second external terminal 102, the second semiconductor region 30 is completely depleted, similar to the operation described with reference to Figures 18 and 19. Specifically, when a positive voltage is applied to the first external terminal 101, the width of the depletion layer on the second external terminal 102 side of the depletion layer formed at the interface between the second semiconductor region 30 and the P-type semiconductor region widens. As the depletion layer formed at the interface between the first semiconductor region 20 and the second semiconductor region 30, which are included in the intermediate region 25, extends upward, the entire second semiconductor region 30 is completely depleted. Furthermore, when a positive voltage is applied to the second external terminal 102, the width of the depletion layer on the first external terminal 101 side of the depletion layer formed at the interface between the second semiconductor region 30 and the P-type semiconductor region widens. As the depletion layers formed at the interface between the third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25, and at the interface between the first semiconductor region 20 and the second semiconductor region 30 of the intermediate region 25, extend downward, all of the second semiconductor regions 30 are completely depleted.

[0068] By completely depleting all of the second semiconductor regions 30, the entire intermediate region 25 and the third semiconductor region 40 become electrically equivalent to a P-type region. As a result, the entire semiconductor substrate 100 can be considered as an NPN transistor. Therefore, when a large positive voltage is applied to the first external terminal 101, the NPN transistor breaks down, and a breakdown current flows from the first external terminal 101 to the second external terminal 102. Similarly, when a large positive voltage is applied to the second external terminal 102, the NPN transistor breaks down, and a breakdown current flows from the second external terminal 102 to the first external terminal 101. Through these operations, the semiconductor device 1A functions as a bidirectional overvoltage protection element.

[0069] As shown in Figure 20, semiconductor device 1A can achieve even lower capacitance values ​​by configuring an intermediate region with multiple intermediate stacked structures. While the above example illustrates a case where the intermediate stacked structure in the intermediate region 25 consists of two stages, the intermediate stacked structure may consist of three or more stages. The more stages the intermediate stacked structure has, the lower the capacitance value can be.

[0070] (Second variation) The semiconductor device 1A according to the first modified example shown in Figure 20 includes a plurality of embedded regions 15 that are individually connected to each of the first semiconductor regions 20 included in the plurality of intermediate stacked structures. On the other hand, the semiconductor device 1A according to the second modified example shown in Figure 23 includes one embedded region 15, and the ends of each of the first semiconductor regions 20 included in the plurality of intermediate stacked structures are connected to the same embedded region 15.

[0071] The semiconductor device 1A shown in Figure 23 allows for a smaller device area than the semiconductor device 1A shown in Figure 20. Other configurations of the semiconductor device 1A shown in Figure 23 are the same as those of the semiconductor device 1A shown in Figure 20, and therefore, redundant explanations are omitted.

[0072] (Third embodiment) Figure 24 shows semiconductor device 1B according to the third embodiment. Semiconductor device 1B differs from semiconductor device 1A shown in Figure 14 in that the embedded region 15 is an insulator and penetrates the intermediate region 25 until the embedded region 15 reaches the semiconductor substrate 10. Other configurations of semiconductor device 1B are the same as those of the second embodiment shown in Figure 14.

[0073] The embedded region 15 may be, for example, an SiO2 film. To form the insulator embedded region 15, for example, a groove may be formed from the upper surface of the semiconductor substrate 100, and the inside of the groove may be filled with an insulator. The depth of this groove may be, for example, 6 μm to 35 μm, and the width may be, for example, 1 μm to 6 μm.

[0074] The semiconductor device 1B has a stacked structure in which a semiconductor substrate 10, an intermediate region 25 including a stacked structure of a first semiconductor region 20 and a second semiconductor region 30, a third semiconductor region 40, and a fourth semiconductor region 50 are stacked in order. Furthermore, the semiconductor device 1B includes an insulator embedding region 15 that surrounds the third semiconductor region 40 and reaches the semiconductor substrate 10. The fourth semiconductor region 50 and the third semiconductor region 40 constitute a Zener diode. The third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25 constitute a PIN diode. The first semiconductor region 20 and the lowermost first semiconductor region 25 constitute a Zener diode with the semiconductor substrate 10.

[0075] Figure 25 shows a plan view of the semiconductor device 1B shown in Figure 24. Figure 24 is a cross-sectional view along the XXIV-XXIV direction in Figure 25. In Figure 25, the X-direction distance Xd3 is the length of the upper metal layer 61 along the X direction, and the Y-direction distance Yd3 is the length of the upper metal layer 61 along the Y direction. In the third embodiment, Xd3 = 140 μm and Yd3 = 140 μm.

[0076] Figure 26 shows the semiconductor substrate 100 of the semiconductor device 1B when the first conductivity type is N-type and the second conductivity type is P-type. As shown in Figure 26, the first Zener diode Z1 is formed with the first semiconductor region 20 as the anode and the semiconductor substrate 10 as the cathode. The first PIN diode P1 is formed with the first semiconductor region 20 as the anode and the second semiconductor region 30 as the cathode. The second PIN diode P2 is formed with the third semiconductor region 40 as the anode and the second semiconductor region 30 as the cathode. The second Zener diode Z2 is formed with the third semiconductor region 40 as the anode and the fourth semiconductor region 50 as the cathode.

[0077] Figure 27 shows an equivalent circuit diagram composed of the PIN diode P and Zener diode Z included in semiconductor device 1B. The cathode of the second Zener diode Z2 is connected to the first external terminal 101, and the anode of the second Zener diode Z2 is connected to the anode of the second PIN diode P2. The cathode of the second PIN diode P2 is connected to the cathode of the first PIN diode P1, and the anode of the first PIN diode P1 is connected to the anode of the first Zener diode Z1. The cathode of the first Zener diode Z1 is connected to the second external terminal 102. The capacitance values ​​of the first Zener diode Z1 and the second Zener diode Z2 are 100pF, and the capacitance values ​​of the first PIN diode P1 and the second PIN diode P2 are 1pF. Therefore, the combined capacitance value of semiconductor device 1B shown in Figure 24 is approximately 0.5pF. Semiconductor device 1B, in which the embedded region 15 is made of an insulator, has a smaller combined capacitance value compared to semiconductor device 1A.

[0078] The basic operation of semiconductor device 1B is the same as that of semiconductor device 1A, as described with reference to Figures 18 and 19. That is, when a positive voltage is applied to the first external terminal 101, the depletion layer formed at the interface between the first semiconductor region 20 and the second semiconductor region 30 contained in the intermediate region 25 extends upward. As a result, all of the second semiconductor region 30 is completely depleted. Also, when a positive voltage is applied to the second external terminal 102, the depletion layer formed at the interface between the third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25 extends downward. As a result, all of the second semiconductor region 30 is completely depleted.

[0079] By completely depleting all of the second semiconductor regions 30, the entire intermediate region 25 and the third semiconductor region 40 become electrically equivalent to a P-type region. As a result, the entire semiconductor substrate 100 can be considered as an NPN transistor. Therefore, when a large positive voltage is applied to the first external terminal 101, the NPN transistor breaks down, and a breakdown current flows from the first external terminal 101 to the second external terminal 102. Similarly, when a large positive voltage is applied to the second external terminal 102, the NPN transistor breaks down, and a breakdown current flows from the second external terminal 102 to the first external terminal 101. Through these operations, the semiconductor device 1B functions as a bidirectional overvoltage protection element.

[0080] As described above, according to the semiconductor device 1B of the third embodiment, by stacking the PIN diode P and Zener diode Z vertically, the area can be reduced while ensuring ESD withstand capability and surge withstand capability at a low capacitance value. Furthermore, in semiconductor device 1B, where the embedded region 15 is an insulator, the area of ​​the P-type region is smaller than in semiconductor device 1A, where the embedded region 15 is a P-type region. For this reason, semiconductor device 1B can achieve an even lower capacitance value than semiconductor device 1A.

[0081] (First variation) Figure 28 shows a semiconductor device 1B according to the first modification of the third embodiment. The intermediate region 25 of the semiconductor device 1B shown in Figure 28 has multiple intermediate stacked structures in which a second semiconductor region 30 is stacked on a first semiconductor region 20. In other words, the semiconductor device 1B shown in Figure 28 differs from the semiconductor device 1B shown in Figure 24 in that the intermediate region 25 has a structure in which multiple intermediate stacked structures are stacked. The embedded region 15 continuously penetrates the multiple intermediate stacked structures.

[0082] In the semiconductor device 1B shown in Figure 28, in addition to the PIN diode P and Zener diode Z included in the semiconductor device 1B shown in Figure 26, a third PIN diode P3 and a fourth PIN diode P4 are configured inside the intermediate region 25. More specifically, the bottommost first semiconductor region 20 of the intermediate region 25 constitutes the semiconductor substrate 10 and the first Zener diode Z1. The lower first semiconductor region 20 and the lower second semiconductor region 30 constitute the first PIN diode P1. The third semiconductor region 40 constitutes the topmost second semiconductor region 30 of the intermediate region 25 and the second PIN diode P2. The fourth semiconductor region 50 constitutes the third semiconductor region 40 and the second Zener diode Z2. The third PIN diode P3 uses the lower second semiconductor region 30 as the cathode and the upper first semiconductor region 20 as the anode. The fourth PIN diode P4 uses the upper first semiconductor region 20 as the anode and the upper second semiconductor region 30 as the cathode.

[0083] Figure 29 shows an equivalent circuit diagram composed of the PIN diode P and Zener diode Z included in the semiconductor device 1B shown in Figure 28. The capacitance values ​​of the first Zener diode Z1 and the second Zener diode Z2 are 100pF, and the capacitance values ​​of the first PIN diode P1, the second PIN diode P2, the third PIN diode P3, and the fourth PIN diode P4 are 1pF. In this case, the combined capacitance value of the semiconductor device 1B is approximately 0.25pF. With the semiconductor device 1B including an intermediate region 25 in which the intermediate stacked structure is arranged in multiple stages, the combined capacitance value can be made even smaller than that of the semiconductor device 1B shown in Figure 24.

[0084] In the semiconductor device 1B shown in Figure 28, when a voltage is applied to the first external terminal 101 or the second external terminal 102, the second semiconductor region 30 is completely depleted, similar to the operation described with reference to Figures 18 and 19. Specifically, when a positive voltage is applied to the first external terminal 101, the depletion layer formed at the interface between the first semiconductor region 20 and the second semiconductor region 30 contained in the intermediate region 25 extends upward. As a result, all of the second semiconductor region 30 is completely depleted. Also, when a positive voltage is applied to the second external terminal 102, the depletion layers formed at the interface between the third semiconductor region 40 and the uppermost second semiconductor region 30 of the intermediate region 25, and at the interface between the first semiconductor region 20 and the second semiconductor region 30 in the intermediate region 25, respectively, extend downward. As a result, all of the second semiconductor region 30 is completely depleted.

[0085] By completely depleting all of the second semiconductor regions 30, the entire intermediate region 25 and the third semiconductor region 40 become electrically equivalent to a P-type region. As a result, the entire semiconductor substrate 100 can be considered as an NPN transistor. Therefore, when a large positive voltage is applied to the first external terminal 101, the NPN transistor breaks down, and a breakdown current flows from the first external terminal 101 to the second external terminal 102. Similarly, when a large positive voltage is applied to the second external terminal 102, the NPN transistor breaks down, and a breakdown current flows from the second external terminal 102 to the first external terminal 101. Through these operations, the semiconductor device 1B functions as a bidirectional overvoltage protection element.

[0086] As shown in Figure 28, semiconductor device 1B can achieve even lower capacitance values ​​by making the embedded region 15 an insulator and arranging the intermediate stacked structure in multiple stages in the intermediate region 25. Furthermore, as shown in Figure 20, the area increases when the intermediate stacked structure is arranged in multiple stages in semiconductor device 1A, but in semiconductor device 1B, the intermediate stacked structure can be arranged in multiple stages without increasing the area. In the above example, the case in which the intermediate stacked structure included in the intermediate region 25 has two stages is shown, but the intermediate stacked structure may have three or more stages.

[0087] (Second variation) Figure 30 shows a semiconductor device 1B according to a second modification of the third embodiment. The semiconductor device 1B shown in Figure 30 has a configuration in which two semiconductor substrates 100, each containing a semiconductor substrate 10, a first semiconductor region 20, a second semiconductor region 30, a third semiconductor region 40, and a fourth semiconductor region 50, are connected in series in opposite directions. In the semiconductor device 1B shown in Figure 30, the semiconductor substrate 10 is common to both semiconductor substrates 100. An upper metal layer 61 located on one semiconductor substrate 100 is connected to a first external terminal 101, and an upper metal layer 61 located on the other semiconductor substrate 100 is connected to a second external terminal 102.

[0088] The semiconductor device 1B shown in Figure 30 does not have a lower electrode layer 62, and two external terminals are connected to the upper metal layer 61. The structure of the semiconductor device 1B shown in Figure 30 is equivalent to the structure of the semiconductor device 1B shown in Figure 24 connected in series. Therefore, the capacitance value is half that of the semiconductor device 1B shown in Figure 24, and an even lower capacitance value can be achieved. For example, if the capacitance value of the semiconductor device 1B shown in Figure 24 is 0.5 pF, the capacitance value of the semiconductor device 1B shown in Figure 30 is 0.25 pF. In addition, in the semiconductor device 1B shown in Figure 30, intermediate stacked structures may be arranged in multiple stages in the intermediate region 25, similar to the semiconductor device 1B shown in Figure 28.

[0089] (Other embodiments) Although embodiments have been described above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the embodiments. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0090] For example, the above description illustrates the case where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In other words, the semiconductor substrate 10 may be a P-type semiconductor, the first semiconductor region 20 may be an N-type semiconductor, the second semiconductor region 30 may be a P-type or intrinsic semiconductor (i-type), the third semiconductor region 40 may be an N-type semiconductor, and the fourth semiconductor region 50 may be a P-type semiconductor.

[0091] Figures 31 to 33 show the equivalent circuit diagrams composed of the PIN diode P and Zener diode Z included in semiconductor devices 1, 1A, and 1B when the first conductivity type is P-type and the second conductivity type is N-type. Figure 31 is the equivalent circuit diagram of semiconductor device 1 shown in Figure 1. Figure 32 is the equivalent circuit diagram of semiconductor device 1A shown in Figure 14. Figure 33 is the equivalent circuit diagram of semiconductor device 1B shown in Figure 24. The capacitance values ​​of the PIN diode P and Zener diode Z are the same when the first conductivity type is N-type and the second conductivity type is P-type, and when the first conductivity type is P-type and the second conductivity type is N-type. Even when the first conductivity type is P-type and the second conductivity type is N-type, the operation of semiconductor devices 1, 1A, and 1B when a large voltage (e.g., surge voltage) is applied to the external terminals is the same as the operation when the first conductivity type is N-type and the second conductivity type is P-type, as described above.

[0092] Although the present disclosure has been described in detail above, it will be clear to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the descriptions in the present disclosure are illustrative and not intended to be restrictive in any way.

[0093] [Note] The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0094] [Note 1] The semiconductor device comprises a semiconductor substrate 10 of a first conductivity type, a first semiconductor region 20 of a second conductivity type disposed on the upper surface of the semiconductor substrate 10, a second semiconductor region 30 of a different conductivity type from the first semiconductor region 20, disposed on the semiconductor substrate 10 covering the first semiconductor region 20, a third semiconductor region 40 of a second conductivity type disposed on the upper surface of the second semiconductor region 30, and a fourth semiconductor region 50 of a first conductivity type embedded in a part of the upper part of the third semiconductor region 40. The first semiconductor region 20 constitutes a Zener diode with the semiconductor substrate 10. The second semiconductor region 30 constitutes a PIN diode with the first semiconductor region 20. The third semiconductor region 40 is disposed on the second semiconductor region 30 so as to face the first semiconductor region 20 via the second semiconductor region 30, and constitutes a PIN diode with the second semiconductor region 30. The fourth semiconductor region 50 constitutes a Zener diode with the third semiconductor region 40. The impurity concentration of the second semiconductor region 30 is lower than the impurity concentrations of the first semiconductor region 20 and the third semiconductor region 40.

[0095] According to the semiconductor device described in Appendix 1, by stacking PIN diodes and Zener diodes vertically, it is possible to reduce the area of ​​the device while maintaining a low capacitance value and ensuring ESD withstand capability and surge withstand capability.

[0096] [Note 2] In the semiconductor device described in Appendix 1, the impurity concentrations of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 are set such that a depletion layer is formed from the top to the bottom surface of the second semiconductor region 30 when a predetermined voltage is applied between the semiconductor substrate 10 and the fourth semiconductor region 50. In the semiconductor device described in Appendix 2, when a surge voltage is applied to the external terminal, the second semiconductor region 30 is completely depleted, so that the entire second semiconductor region 30 and the third semiconductor region 40 become electrically equivalent to a P-type region. For this reason, the entire semiconductor substrate 100 can be considered as an NPN transistor. As a result, when a large voltage is applied to the external terminal, the NPN transistor breaks down and a breakdown current flows.

[0097] [Note 3] The second semiconductor region 30 of the semiconductor device described in Appendix 1 or 2 is of the first conductivity type.

[0098] [Note 4] The second semiconductor region 30 of the semiconductor device described in Appendix 1 or 2 is an intrinsic semiconductor.

[0099] [Note 5] In the semiconductor device described in any of Appendix 1 to 4, the second semiconductor region 30 is connected to the semiconductor substrate 10 outside the first semiconductor region 20. In the semiconductor device described in Appendix 5, when a positive voltage is applied to the first external terminal 101, the NPN transistor composed of the fourth semiconductor region 50, the third semiconductor region 40, and the second semiconductor region 30 can break down and conduct current.

[0100] [Note 6] In the semiconductor device described in any of Appendix 1 to 5, the third semiconductor region 40 is embedded in a part of the upper part of the second semiconductor region 30.

[0101] [Note 7] The semiconductor device comprises a semiconductor substrate 10 of a first conductivity type, an intermediate region 25 located on the upper surface of the semiconductor substrate 10, a third semiconductor region 40 of a second conductivity type embedded in the upper part of the second semiconductor region 30 of the intermediate region 25, a fourth semiconductor region 50 of a first conductivity type embedded in a part of the upper part of the third semiconductor region 40, and an embedded region 15 that surrounds the third semiconductor region 40 without being electrically connected to it, and extends from the upper surface of the intermediate region 25 toward the semiconductor substrate 10 to define the extent of the second semiconductor region 30 in a plan view. The intermediate region 25 includes at least one laminated structure in which a second semiconductor region 30 having a different conductivity type from the first semiconductor region 20 is stacked on a first semiconductor region 20 of a second conductivity type. The bottommost first semiconductor region 20 forms a Zener diode with the semiconductor substrate 10, and the first semiconductor region 20 and the second semiconductor region 30 form a PIN diode. The third semiconductor region 40 faces the semiconductor substrate 10 via the intermediate region 25 and forms a PIN diode with the uppermost second semiconductor region 30 of the intermediate region 25. The fourth semiconductor region 50 forms a Zener diode with the third semiconductor region 40. The impurity concentration of the second semiconductor region 30 is lower than that of the first semiconductor region 20 and the third semiconductor region 40.

[0102] According to the semiconductor device described in Appendix 7, by stacking PIN diodes and Zener diodes vertically, the area of ​​the device can be reduced while maintaining a low capacitance value and ensuring ESD withstand capability and surge withstand capability. Furthermore, according to the semiconductor device including the embedded region 15, the capacitance value can be reduced even further.

[0103] [Note 8] In the semiconductor device described in Appendix 7, the impurity concentrations of the first semiconductor region 20, the second semiconductor region 30, and the third semiconductor region 40 are set such that a depletion layer is formed from the bottom surface to the top surface of the second semiconductor region 30 when a predetermined voltage is applied between the semiconductor substrate 10 and the fourth semiconductor region 50. In the semiconductor device described in Appendix 8, when a surge voltage is applied to the external terminal, the second semiconductor region 30 is completely depleted, so that the entire second semiconductor region 30 and the third semiconductor region 40 become electrically equivalent to a P-type region. For this reason, the entire semiconductor substrate 100 can be considered as an NPN transistor. As a result, when a large voltage is applied to the external terminal, the NPN transistor breaks down and a breakdown current flows.

[0104] [Note 9] The second semiconductor region 30 of the semiconductor device described in Appendix 7 or 8 is of the first conductivity type.

[0105] [Note 10] The second semiconductor region 30 of the semiconductor device described in Appendix 7 or 8 is an intrinsic semiconductor.

[0106] [Note 11] In the semiconductor device described in any of Appendix 7 to 10, the embedded region 15 is a second-conductivity semiconductor, and the embedded region 15 is connected to the first semiconductor region 20.

[0107] [Note 12] In the semiconductor device described in Appendix 7, the intermediate region 25 has a structure in which multiple stacked structures are stacked, and includes multiple embedded regions 15 that are individually connected to each of the first semiconductor regions 20 included in the multiple stacked structures. The multiple embedded regions 15 are arranged in multiple layers in a plan view such that the embedded regions 15 that are connected to the first semiconductor region 20 on the side closer to the semiconductor substrate 10 are on the outside. According to the semiconductor device described in Appendix 12, an even lower capacitance value can be achieved by configuring the intermediate region 25 with multiple layers of stacked structures.

[0108] [Note 13] In the semiconductor device described in any of Appendix 7 to 10, the embedded region 15 is an insulator. The embedded region 15 penetrates the intermediate region 25 until it reaches the semiconductor substrate 10. According to the semiconductor device described in Appendix 13, the combined capacitance value can be reduced by making the embedded region 15 an insulator.

[0109] [Note 14] In the semiconductor device described in Appendix 13, the intermediate region 25 has a structure in which multiple stacked structures are stacked. The embedded region 15 continuously penetrates the multiple stacked structures. [Explanation of Symbols]

[0110] 1, 1A, 1B Semiconductor devices 10 Semiconductor substrates 15. Embedded area 20. First Semiconductor Area 25 Intermediate area 30. Second Semiconductor Area 40 Third Semiconductor Area 50. Fourth Semiconductor Area 61 Upper metal layer 62 Lower electrode layer 71 First insulating layer 72 Second insulating layer 80 protective layer 91 Lower depletion layer 92 Upper depletion layer 100 Semiconductor substrates 101 First external terminal 102 Second external terminal P1 1st PIN diode P2 2nd PIN diode P3 3-PIN diode P4 4th PIN diode Z1 First Zener diode Z2 Second Zener diode

Claims

1. A first-type conductive semiconductor substrate and An intermediate region disposed on the upper surface of the semiconductor substrate, comprising at least one laminated structure in which a second semiconductor region having a different conductivity type than the first semiconductor region is laminated on a first semiconductor region having a second conductivity type, wherein the bottommost first semiconductor region constitutes a Zener diode with the semiconductor substrate, and the first and second semiconductor regions constitute a PIN diode, and the intermediate region, Embedded above the uppermost second semiconductor region of the intermediate region, facing the semiconductor substrate via the intermediate region, and a third semiconductor region of second conductivity type constituting a PIN diode with the uppermost second semiconductor region, A fourth semiconductor region of first conductivity type, embedded in a part of the upper part of the third semiconductor region and constituting a Zener diode with the third semiconductor region, An embedded region is arranged surrounding the third semiconductor region without being electrically connected to it, and extends from the upper surface of the intermediate region toward the semiconductor substrate so as to define the extent of the second semiconductor region in a plan view, Equipped with, The impurity concentration in the second semiconductor region is lower than the impurity concentrations in the first and third semiconductor regions. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the impurity concentrations of the first semiconductor region, the second semiconductor region, and the third semiconductor region are set such that a depletion layer is formed from the lower surface to the upper surface of the second semiconductor region when a predetermined voltage is applied between the semiconductor substrate and the fourth semiconductor region.

3. The semiconductor device according to claim 1, wherein the second semiconductor region is of the first conductivity type.

4. The semiconductor device according to claim 1, wherein the second semiconductor region is an intrinsic semiconductor.

5. The embedded region is a semiconductor of the second conductivity type, The embedded region is connected to the first semiconductor region. The semiconductor device according to any one of claims 1 to 4.

6. The intermediate region has a structure in which multiple stacked structures are stacked, It includes a plurality of embedded regions that are individually connected to each of the first semiconductor regions included in the plurality of stacked structures, Multiple embedded regions are arranged in a plan view in a multi-layered manner such that the embedded region connected to the first semiconductor region on the side closer to the semiconductor substrate is on the outside. The semiconductor device according to claim 5.

7. The aforementioned embedded area is an insulator, The embedded region penetrates the intermediate region until it reaches the semiconductor substrate. The semiconductor device according to any one of claims 1 to 4.

8. The intermediate region has a structure in which multiple stacked structures are stacked, The embedded region continuously penetrates the multiple stacked structures. The semiconductor device according to claim 7.

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