Semiconductor equipment

Abstract

To provide a semiconductor device that can obtain stable characteristics. [Solution] According to the embodiment, the semiconductor device includes a first electrode, a second electrode, and a semiconductor member provided between the first electrode and the second electrode. The semiconductor member includes a diode region including a first region and a second region, and a transistor region. The first region and the second region extend along a first direction. A first position in the second direction of the first region is different from a second position in the second direction of the second region. The second direction intersects the first direction. The semiconductor member is between the first electrode and the second electrode in a third direction that intersects a plane including the first and second directions. At least a portion of the transistor region is around the diode region in the plane.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device. [Background Art]

[0002] For example, in a semiconductor device, stable characteristics are desired. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2023-77119 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An embodiment provides a semiconductor device capable of obtaining stable characteristics. [Means for Solving the Problem]

[0005] According to an embodiment, the semiconductor device includes a first electrode, a second electrode, and a semiconductor member provided between the first electrode and the second electrode. The semiconductor member includes a diode region including a first region and a second region, and a transistor region. The first region and the second region extend along a first direction. A first position of the first region in a second direction is different from a second position of the second region in the second direction. The second direction intersects the first direction. The semiconductor member is located between the first electrode and the second electrode in a third direction that intersects a plane including the first direction and the second direction. At least a part of the transistor region is located around the diode region in the plane. [Brief Description of the Drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view illustrating the semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 6] Figure 6 is a schematic plan view illustrating the characteristics of a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals with respect to previously shown figures, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. Figures 2 to 4 are schematic cross-sectional views illustrating a part of a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along line A1-A2 in Figure 1. Figure 3 is a cross-sectional view taken along line B1-B2 in Figure 1. Figure 4 is a cross-sectional view taken along line C1-C2 in Figure 1.

[0009] As shown in Figures 1 to 4, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, and a semiconductor member 10. The semiconductor device 110 may further include a third electrode 53 and a first insulating member 41.

[0010] The semiconductor component 10 is provided between the first electrode 51 and the second electrode 52.

[0011] The semiconductor component 10 includes a diode region 60 and a transistor region 60T. The transistor region 60T is, for example, a MOS (Metal Oxide Semiconductor) region.

[0012] As shown in Figure 1, the diode region 60 includes multiple regions. For example, the diode region 60 includes a first region 61 and a second region 62, etc. The first region 61 and the second region 62 extend along a first direction D1. The first position of the first region 61 in the second direction D2 is different from the second position of the second region 62 in the second direction D2. The second direction D2 intersects the first direction D1.

[0013] Let the first direction D1 be the Y-axis direction. Let one direction perpendicular to the Y-axis direction be the X-axis direction. Let the direction perpendicular to both the Y-axis and X-axis directions be the Z-axis direction. The second direction D2 is, for example, the X-axis direction.

[0014] The third direction D3 from the first electrode 51 to the second electrode 52 intersects the plane containing the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Z-axis direction. The plane containing the first direction D1 and the second direction D2 corresponds to, for example, the XY plane.

[0015] The semiconductor component 10 is located between the first electrode 51 and the second electrode 52 in the third direction D3. At least a portion of the transistor region 60T lies around the diode region 60 in this plane (XY plane). For example, at least a portion of the transistor region 60T lies around the first region 61 and the second region 62 in the XY plane.

[0016] As shown in Figure 2, the first insulating member 41 includes a first insulating region 41a. The first insulating region 41a is located between the semiconductor member 10 and the third electrode 53. The first insulating member 41 may further include a second insulating region 41b. The second insulating region 41b is located between the third electrode 53 and the second electrode 52.

[0017] A current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be a potential based on the potential of the second electrode 52. The first electrode 51 functions as, for example, a drain electrode. The second electrode 52 functions as, for example, a source electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 110 is, for example, a MOS transistor.

[0018] The diode region 60 has, for example, a function of spreading a surge current. Provision of the diode region 60 enables more stable operation.

[0019] Since a surge current flows through the diode region 60, the temperature is likely to rise in the diode region 60 and the periphery thereof. This may cause damage to various wiring materials, connection members, and the like.

[0020] As described above, in the embodiment, a plurality of regions of the diode region 60 (such as the first region 61 and the second region 62) are provided with shifted positions in the second direction D2. For example, the second region 62 is discontinuous from the first region 61. This allows heat to easily spread in the diode region 60 and the periphery thereof, thereby suppressing local temperature rise, and suppressing excessive temperature rise. For example, damage to wiring materials and the like is suppressed.

[0021] For example, there is a reference example in which the second region 62 is continuous with the first region 61 and the position in the second direction D2 is not shifted. In the reference example, a long continuous diode region 60 is provided. In the reference example, heat is likely to be excessively accumulated in the central portion of the long continuous diode region 60, and local high temperature is likely to occur. This easily causes damage to wiring materials and the like.

[0022] In contrast, in this embodiment, the diode region 60 is divided into multiple regions (such as a first region 61 and a second region 62). In these multiple regions, the position in the second direction D2 is shifted. The second region 62 is discontinuous with the first region 61. This allows heat to spread and suppresses excessive temperature rise. Damage to wiring materials and the like is suppressed. According to this embodiment, a semiconductor device with stable characteristics can be provided.

[0023] For example, the area of ​​the PN region of the diode region 60 per unit area is larger than the area of ​​the PN region of the transistor region 60T per unit area. The contact resistance per unit area between the source electrode (second electrode 52) and the p region (e.g., second semiconductor region 12) in the diode region 60 is smaller than the contact resistance per unit area between the source electrode (second electrode 52) and the body region (e.g., second semiconductor region 12) in the transistor region 60T. For example, the current flowing through the PN junction diode in the diode region 60 is larger than the current flowing through the PN junction diode in the transistor region 60T.

[0024] The resistance in the diode region 60 is lower than the resistance of the diode (body diode) in the MOSFET portion (transistor region 60T).

[0025] For example, when a large current such as a surge is applied, a large current can flow through the diode region 60. The diode region 60 has the effect of concentrating the surge current.

[0026] When a surge current is applied, conductivity modulation occurs more easily in the diode region 60 than in the transistor region 60T, and the effect of conductivity modulation is stronger. The region in the diode region 60 where conductivity is modulated becomes, for example, a "starting point." Carriers generated by conductivity modulation spread to adjacent cells, further increasing the current. As the current increases, the temperature of the diode region 60 rises, and the forward voltage Vf in the diode region 60 decreases. This allows for positive feedback. For example, a large current flowing through a PN diode causes carrier propagation and heat propagation to the adjacent transistor region 60T. This promotes conductivity modulation.

[0027] For example, surge current is concentrated in the diode region 60 (promoting modulation of conductivity), and the large current and heat generation are distributed to adjacent cells or the diode region 60. This improves the surge current.

[0028] For example, the number of diode regions 60 may be the same as the number of bonding wires provided in the source plane. For example, if the number of bonding wires provided in the source plane is 3, it is preferable that the number of diode regions 60 be 3. Multiple diode regions 60 may be arranged along the long direction of the chip.

[0029] As already explained, if the multiple diode regions 60 are not shifted, localized heat generation occurs in the area between the multiple diode regions 60, damaging the cell. This heat generation causes variations in surge withstand capability.

[0030] As shown in Figure 1, the length of the semiconductor member 10 along the first direction D1 is defined as the first semiconductor member length L1. The length of the semiconductor member 10 along the second direction D2 is defined as the second semiconductor member length L2. In this embodiment, the first semiconductor member length L1 may be greater than or equal to the second semiconductor member length L2. For example, each of the multiple diode regions 60 extends along the longer direction of the semiconductor member 10. This makes it easier to spread surge currents, for example.

[0031] As shown in Figure 1, in this example, the first region 61 lies between two regions of the transistor region 60T in the first direction D1. The second region 62 lies between the other two regions of the transistor region 60T in the first direction D1.

[0032] The first region 61 lies between two regions of the transistor region 60T in the second direction D2. The second region 62 lies between the other two regions of the transistor region 60T in the second direction D2.

[0033] As shown in Figure 1, the diode region 60 may further include a third region 63. A portion of the transistor region 60T lies around the third region 63 in the XY plane. The third region 63 extends along the first direction D1. The third position of the third region 63 in the second direction D2 is different from the second position.

[0034] In this example, the position of the second region 62 in the first direction D1 is between the position of the first region 61 in the first direction D1 and the position of the third region 63 in the first direction D1. The transistor region 60T includes a first portion 60Tp. For example, at least a portion of the first portion 60Tp may be located between the first region 61 and the third region 63 in the first direction D1. The direction from the second region 62 to the first portion 60Tp may be along the second direction D2.

[0035] As shown in Figure 1, the first distance d1 is the distance along the second direction D2 between the first position in the first region 61 in the second direction D2 and the second position in the second region 62 in the second direction D2. The first distance d1 corresponds to the shift distance. The length (width) of the first region 61 along the second direction D2 is defined as the first region width w1. The first distance d1 is longer than the first region width w1. For example, the first distance d1 can be five times or more the first region width w1.

[0036] In one example, the first distance d1 may be, for example, between 200 μm and 800 μm. The first region width w1 may be, for example, between 4 μm and 100 μm.

[0037] For example, the length of the first region 61 along the first direction D1 is defined as the first region length Lr1. The first region length Lr1 may be at least five times the first region width w1 along the second direction D2 of the first region 61. In one example, the first region length Lr1 may be, for example, between 1000 μm and 1500 μm.

[0038] As shown in Figure 1, the semiconductor member 10 includes a first end 10ea in a first direction D1 and a second end 10eb in a second direction D2. The first end 10ea is the closest of the multiple ends included in the semiconductor member 10 to the first region 61 in the first direction D1. The second end 10eb is the closest of the multiple ends included in the semiconductor member 10 to the first region 61 in the second direction D2. The distance between the first region 61 and the second end 10eb in the second direction D2 is denoted as the second end distance de2. The distance between the first region 61 and the first end 10ea in the first direction D1 is denoted as the first end distance de1. For example, the second end distance de2 may be longer than the first end distance de1. The first region 61 is far away from the second end 10eb in the second direction D2. This allows for more effective suppression of local temperature rise.

[0039] As shown in Figure 1, the diode region 60 may include several other regions (such as the fourth region 64, the fifth region 65, and the sixth region 66). The configurations of the first region 61, the second region 62, and the third region 63, which have already been described, may be applied to these regions, respectively.

[0040] In this example, multiple third electrodes 53 are provided. The multiple third electrodes 53 extend along the second direction D2. The multiple third electrodes 53 are aligned along the first direction D1. The multiple third electrodes 53 are electrically connected to the third electrode pad 53P.

[0041] Figure 2 illustrates a cross-section in the transistor region 60T. The semiconductor member 10 includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, and a third semiconductor region 13 of a first conductivity type. The first conductivity type is either n-type or p-type. The second conductivity type is the other of n-type and p-type. Hereafter, the first conductivity type will be assumed to be n-type and the second conductivity type to be p-type.

[0042] As shown in Figure 2, the first semiconductor region 11 may include a first subregion 11a, a second subregion 11b, and a third subregion 11c. The direction from the first subregion 11a to the second subregion 11b intersects with the third direction D3. In this example, the direction from the first subregion 11a to the second subregion 11b follows the first direction D1.

[0043] The second partial region 11b lies between the first electrode 51 and the second semiconductor region 12 in the third direction D3. At least a portion of the third semiconductor region 13 lies between the second semiconductor region 12 and the second electrode 52. The third semiconductor region 13 is electrically connected to the second electrode 52.

[0044] In the transistor region 60T, the third subregion 11c lies between the first subregion 11a and the third electrode 53 in the third direction D3. In the transistor region 60T, the direction from the third subregion 11c to the second semiconductor region 12 intersects with the third direction D3. In this example, the direction from the third subregion 11c to the second semiconductor region 12 follows the first direction D1.

[0045] The concentration of the third impurity of the first conductivity type in the third semiconductor region 13 is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11.

[0046] As shown in Figure 2, the semiconductor member 10 may include a fourth semiconductor region 14 of the second conductivity type. The fourth semiconductor region 14 is located between the second semiconductor region 12 and the second electrode 52. The concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region 14 is higher than the concentration of the second impurity of the second conductivity type in the second semiconductor region 12.

[0047] As shown in Figure 2, the semiconductor member 10 may include a fifth semiconductor region 15 of the second conductivity type. The fifth semiconductor region 15 is located between the fourth semiconductor region 14 and the second electrode 52. The concentration of the fifth impurity of the second conductivity type in the fifth semiconductor region 15 is higher than the concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region 14. The fifth semiconductor region 15 may include, for example, a metal silicide. The fifth semiconductor region 15 may include, for example, at least one selected from the group consisting of titanium silicide and nickel silicide.

[0048] The semiconductor device 110 may further include a first electrode portion 52a. The first electrode portion 52a is provided between the first semiconductor region 11 and the second electrode 52. For example, the first electrode portion 52a is in contact with the first semiconductor region 11. A Schottky diode may be formed in the portion including the first electrode portion 52a. The first electrode portion 52a may include, for example, at least one selected from the group consisting of T1 and Al.

[0049] Figure 3 illustrates a cross-section of the diode region 60. In the diode region 60, the third partial region 11c is not provided between the first partial region 11a and the third electrode 53. In the diode region 60, a part of the second semiconductor region 12 is provided between the first partial region 11a and the third electrode 53. A pn ​​junction is formed in the diode region 60.

[0050] As shown in Figure 1, the diode region 60 may include a crossing direction region 68. The crossing direction region 68 extends along the second direction D2.

[0051] Figure 4 illustrates a cross-section in the intersecting region 68. As shown in Figure 4, a pn junction is formed by the first semiconductor region 11 and the second semiconductor region 12.

[0052] (Second Embodiment) Figure 5 is a schematic plan view illustrating a semiconductor device according to the second embodiment. As shown in Figure 5, the semiconductor device 111 according to this embodiment includes a connecting member 70. The configuration of the semiconductor device 111, excluding the connecting member, may be the same as that of the semiconductor device 110.

[0053] The connecting member 70 is, for example, a bonding wire. The connecting member 70 may include a first connecting member 71 and a second connecting member 72. The first connecting member 71 and the second connecting member 72 are electrically connected to the second electrode 52.

[0054] The first connecting member 71 includes a first connection region 71r connected to the second electrode 52. At least a portion of the first connection region 71r overlaps with the first region 61 in the third direction D3. The second connecting member 72 includes a second connection region 72r connected to the second electrode 52. At least a portion of the second connection region 72r overlaps with the second region 62 in the third direction D3. The overlap of these connection regions with the diode region 60 allows, for example, surge current to spread efficiently.

[0055] For example, a larger surge current flows through the diode region 60 compared to the transistor region 60T, resulting in greater heat generation in the diode region 60. The current flowing through the bonding wire also generates heat at the bonding wire connection. The interaction between the heat generated in the diode region 60 and the heat generated at the bonding wire connection further increases the heat generation. These factors lead to a decrease in the forward voltage Vf of the diode region 60 and an enhancement of conductivity modulation.

[0056] In this embodiment, surge current and heat generated from wire bonding can be immediately propagated to the diode region 60. For example, a large current flowing through the diode region 60 causes carrier propagation and heat propagation to the adjacent MOSFET region. Good propagation is achieved. Good heat diffusion is achieved.

[0057] As already explained, a Schottky diode (SBD) may be formed in the portion including the first electrode portion 52a. In this embodiment, by providing the diode region 60, the transistor region 60T, and the SBD region, an even better I is obtained compared to the case where only the transistor region 60T and the SBD region are provided. FSM (Peak Surge Forward Current) is obtained.

[0058] The first region 61 may include a first center 61c in the first direction D1. At least a portion of the first connection region 71r may overlap with the first center 61c in the third direction D3. For example, heat concentration is suppressed. The second region 62 may include a second center 62c in the first direction D1. At least a portion of the second connection region 72r may overlap with the second center 62c in the third direction D3. For example, heat concentration is suppressed.

[0059] As shown in Figure 5, the length (width) of the first connection region 71r in the second direction D2 is defined as the first connection region width Lc2. As already explained, the distance (shift distance) along the second direction D2 between the first position of the first region 61 in the second direction D2 and the second position of the second region 62 in the second direction D2 is the first distance d1. The first connection region width Lc2 may be 1 / 10 or more of the first distance d1. The first connection region width Lc2 may be 5 times or less of the first distance d1.

[0060] The length of the first connection region 71r in the first direction D1 is defined as the first connection region length Lc1. As already explained, the length of the first region 61 along the first direction D1 is the first region length Lr1. In this embodiment, the first region length Lr1 may be four times or less the first connection region length Lc1. The first region length Lr1 may be one time or more the first connection region length Lc1.

[0061] Figure 6 is a schematic plan view illustrating the characteristics of a semiconductor device according to the second embodiment. As shown in Figure 6, in the semiconductor device 111, a first high-temperature region 71h exists corresponding to the first connection region 71r. The length of the first high-temperature region 71h in the second direction D2 is shorter than the length of the first high-temperature region 71h in the first direction D1. A second high-temperature region 72h exists corresponding to the second connection region 72r. The length of the second high-temperature region 72h in the second direction D2 is shorter than the length of the second high-temperature region 72h in the first direction D1. The second high-temperature region 72h is substantially not continuous with the first high-temperature region 71h. Temperature rise is suppressed.

[0062] The semiconductor component 10 may contain SiC or Si. The semiconductor component 10 may contain, for example, at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC. If the semiconductor component 10 contains SiC, the impurity of the first conductivity type may contain, for example, at least one selected from the group consisting of N, P, and As. If the semiconductor component 10 contains SiC, the impurity of the second conductivity type may contain, for example, at least one selected from the group consisting of B, Al, and Ga. The semiconductor component 10 may contain, for example, a compound semiconductor containing Ga.

[0063] At least one of the first electrode 51 and the second electrode 52 may include at least one selected from the group consisting of Al, Cu, Ti, Ni, Ag, and Au. At least one of the first electrode 51 and the second electrode 52 may include at least one selected from the group consisting of titanium silicide and nickel silicide. The third electrode 53 may include, for example, conductive polysilicon.

[0064] In the embodiment, information regarding length and thickness is obtained by electron microscopy observation or the like. Information regarding the material composition is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy) or the like.

[0065] According to the embodiment, a semiconductor device can be provided that can obtain stable characteristics.

[0066] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element such as electrodes, semiconductor members, and insulating members included in a semiconductor device is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.

[0067] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0068] Furthermore, all semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0069] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention.

[0070] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0071] 10: Semiconductor material, 10ea, 10eb: First and second ends, 11-15: First to fifth semiconductor regions, 11a-11c: First to third partial regions, 41: First insulating material, 41a, 41b: First and second insulating regions, 51-53: First to third electrodes, 52a: First electrode portion, 53P: Third electrode pad, 60: Diode region, 60T: Transistor region, 60Tp: First portion, 61-66: First to sixth regions, 61c, 62c: First and second centers, 68: Crossing direction region, 70: Connecting material, 71, 72: First and second connecting material, 71h, 72h: First and second high-temperature regions, 71r, 72r: First and second connecting regions, 110, 111: Semiconductor device, D1~D3: 1st~3rd directions, L1, L2: 1st and 2nd semiconductor member lengths, Lc1, Lc2: 1st and 2nd connection region lengths, Lr1: 1st region length, d1: 1st distance, de1, de2: 1st and 2nd end distances, w1: 1st region width

Claims

1. First electrode and The second electrode and A semiconductor member provided between the first electrode and the second electrode, Equipped with, The semiconductor member includes a diode region including a first region and a second region, and a transistor region. The first region and the second region extend along the first direction, The first position in the second direction of the first region is different from the second position in the second direction of the second region, The second direction intersects the first direction, The semiconductor member is located between the first electrode and the second electrode in a third direction intersecting the plane including the first and second directions. A semiconductor device in which at least a portion of the transistor region is located around the diode region in the plane.

2. The semiconductor device according to claim 1, wherein the second region is discontinuous with the first region.

3. The third electrode and A first insulating member including a first insulating region, Furthermore, The semiconductor device according to claim 1, wherein the first insulating region is located between the semiconductor member and the third electrode.

4. The aforementioned semiconductor member is The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, Includes, The first semiconductor region includes a first subregion, a second subregion, and a third subregion. The direction from the first subregion to the second subregion intersects with the third direction, The second subregion is located between the first electrode and the second semiconductor region in the third direction. At least a portion of the third semiconductor region is located between the second semiconductor region and the second electrode. The third semiconductor region is electrically connected to the second electrode, In the transistor region, the third subregion is located between the first subregion and the third electrode in the third direction. The semiconductor device according to claim 3, wherein in the transistor region, the direction from the third subregion to the second semiconductor region intersects with the third direction.

5. In the diode region, the third subregion is not provided between the first subregion and the third electrode. The semiconductor device according to claim 4, wherein a part of the second semiconductor region is provided between the first partial region and the third electrode in the diode region.

6. The diode region further includes a third region, A portion of the transistor region is located around the third region in the plane, The third region extends along the first direction, The semiconductor device according to claim 1, wherein the third position in the second direction of the third region is different from the second position.

7. The semiconductor device according to claim 6, wherein the position of the second region in the first direction is between the position of the first region in the first direction and the position of the third region in the first direction.

8. The semiconductor device according to claim 1, wherein the first distance along the second direction between the first position and the second position is longer than the width of the first region along the second direction of the first region.

9. First connecting member and The second connecting member and Furthermore, The first connecting member and the second connecting member are electrically connected to the second electrode. The first connecting member includes a first connecting region that is connected to the second electrode, At least a portion of the first connection region overlaps with the first region in the third direction, The second connecting member includes a second connecting region that is connected to the second electrode, The semiconductor device according to any one of claims 1 to 8, wherein at least a portion of the second connection region overlaps with the second region in the third direction.

10. The first region includes the first center in the first direction, At least a portion of the first connection region overlaps with the first center in the third direction, The second region includes the second center in the first direction, The semiconductor device according to claim 9, wherein at least a portion of the second connection region overlaps with the second center in the third direction.

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