Method for manufacturing a semiconductor substrate, and method for manufacturing an epitaxial structure

Abstract

The present invention provides a method for manufacturing a semiconductor substrate that can effectively suppress the formation of an unintended conductive layer near the interface between the substrate and the epitaxial thin film. [Solution] A method for manufacturing a semiconductor substrate used as a base substrate for epitaxial growth of a semiconductor thin film on a substrate, wherein the surface of the substrate is 5 × 10 20 ~5×10 21 cm -3 The process includes an ion implantation step of implanting impurity ions at a specified ion implantation concentration, and an annealing step of annealing the ion-implanted substrate under an inert gas atmosphere.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing an epitaxial structure. Background Art

[0002] As shown in FIG. 1, a lateral high-frequency gallium oxide (Ga₂O₃) transistor 100 is manufactured by homoepitaxially growing a Ga₂O₃ thin film 20 on a Ga₂O₃ substrate 10, and then performing device processing on the thin film portion on the surface of the Ga₂O₃ thin film 20. Here, FIG. 1 is a cross-sectional view schematically showing the configuration of a conventional lateral high-frequency gallium oxide (Ga₂O₃) transistor.

[0003] In the lateral high-frequency gallium oxide transistor 100 shown in FIG. 1, a source electrode 22 is provided in a source region 21 on the surface of the Ga₂O₃ thin film 20, and a drain electrode 24 is provided in a drain region 23 on the surface of the Ga₂O₃ thin film 20. A channel portion 25 is provided between the source region 21 and the drain region 23. Such a lateral high-frequency gallium oxide transistor 100 is designed such that current flows from the source electrode 22, through the channel portion 25, to the drain electrode 24. In FIG. 1, reference numeral 26 indicates a gate insulating film, and reference numeral 27 indicates a gate electrode.

[0004] Here, it is known that in the lateral high-frequency gallium oxide transistor 100, an unintended current path 31, as indicated by the arrow in FIG. 1 passing through the interface between the Ga₂O₃ substrate 10 and the Ga₂O₃ thin film 20, is formed, which adversely affects the operation of the transistor.

[0005] The cause and formation mechanism of the unintended current path 31 as described above are as follows. First, a silicon compound called siloxane exists in the atmosphere, and such siloxane adheres to the surface of the Ga₂O₃ substrate 10. When a thin film is homoepitaxially grown on the Ga₂O₃ substrate 10 with siloxane adhering to the surface, siloxane-derived silicon (Si) is incorporated into the thin film and acts as a donor. For this reason, near the interface between the Ga₂O₃ substrate 10 and the Ga₂O₃ thin film 20, the carrier concentration is 10 19 cm -3 An order of magnitude highly electrically conductive layer (hereinafter also referred to as "conductive layer 30") is formed. Hereinafter, the conductive layer 30 formed near the interface between the Ga₂O₃ substrate 10 and the Ga₂O₃ thin film 20 may be simply referred to as "the conductive layer 30 formed near the interface".

[0006] When a voltage is applied to the source electrode 22 in the presence of the above-described conductive layer 30, in addition to the original designed current passing through the channel portion 25, a current passing through the conductive layer 30 near the interface, such as the current path 31 shown in FIG. 1, flows between the source electrode 22 and the drain electrode 24. For example, the original designed current passing through the channel portion 25 can be controlled to be turned on and off by applying a gate voltage, but the current through the current path 31 as shown in FIG. 1 cannot be controlled by the gate voltage. Therefore, the current passing through the conductive layer 30 via the current path 31 as shown in FIG. 1 becomes a leakage current in the lateral high-frequency gallium oxide transistor 100.

[0007] For the reasons stated above, unless measures are taken to further reduce the influence of the conductive layer 30 unintentionally formed near the interface, or to appropriately separate the current path 31 passing through the conductive layer 30 near the interface from the intended current path, it will be difficult to achieve normal transistor operation. It should be noted that the unintended current path 31 passing through the conductive layer 30, as described above, can occur in cases other than when a Ga2O3 thin film 20 is homoepitaxially grown on a Ga2O3 substrate 10. For example, similar measures regarding the siloxane-derived conductive layer 30 are required in other semiconductor substrates such as gallium nitride (GaN) and gallium arsenide (GaAs).

[0008] Conventionally, various techniques have been proposed to address the siloxane-derived conductive layer 30, as described above (see, for example, Non-Patent Documents 1-5).

[0009] Non-patent document 1 discloses a technique for removing surface contamination by Si oxide by wet etching with chemicals. Specifically, non-patent document 1 discloses a technique for removing surface contamination by Si oxide on a substrate by wet etching with hydrofluoric acid (HF).

[0010] Non-patent document 2 discloses a technique for etching Si-based compounds by plasma-based dry etching. Specifically, non-patent document 2 discloses a technique for etching Si-based compounds on a substrate by plasma-based dry etching using methane tetrafluoride (CF4) in a vacuum chamber.

[0011] Non-patent document 3 discloses a technique for etching Si-based compounds by etching with a Ga beam. Specifically, non-patent document 3 discloses a technique for removing silicon (Si) attached to the substrate surface by etching the substrate surface by irradiating it with a Ga beam used for growing Ga2O3 thin films in an ultra-high vacuum chamber.

[0012] Non-Patent Document 4 discloses a technique for introducing a back barrier layer (not shown) between a Ga2O3 substrate 10 and a Ga2O3 thin film 20, as shown in Figure 1. Specifically, Non-Patent Document 4 discloses introducing a back barrier layer (Al) with a larger band gap than Ga2O3 between the Ga2O3 substrate 10 and the Ga2O3 thin film 20 as a channel layer. x Ga 1-x A technique has been disclosed in which a Ga2O3 layer is inserted as a back barrier layer. According to the technique disclosed in Non-Patent Document 4, Ga2O3 and (Al x Ga 1-x Since a band offset of approximately 0.3 eV is formed between the 2O3 and the interface, it is possible to separate the current path intended by the design from the current path that passes through the conductive layer formed near the interface.

[0013] Non-Patent Document 5 discloses a technique in which iron (Fe), which acts as an acceptor, is pre-implanted into a substrate before epitaxial thin film growth. In the technique described in Non-Patent Document 5, silicon (Si) present near the substrate interface is incorporated into the thin film and acts as a donor. By compensating for this Si donor, the conductive layer formed near the interface is intended to be eliminated. For example, when epitaxial thin film growth is performed on a substrate that has been pre-implanted with iron (Fe), the ion-implanted iron (Fe) diffuses into the thin film during thin film growth. In the technique described in Non-Patent Document 5, as mentioned above, the diffusion of iron (Fe) into the thin film is utilized to compensate for silicon (Si) as a donor and iron (Fe) as an acceptor, thereby eliminating the conductive layer formed near the interface. [Prior art documents] [Non-patent literature]

[0014] [Non-Patent Document 1] JP McCandless et al., Appl. Phys. Lett. 124, 111601 (2024). [Non-Patent Document 2] Makoto Sekine, J. Plasma. Fusion Res. 83, 319 (2007). [Non-Patent Document 3] E. Ahmadi et al., Appl. Phys. Express 10, 071101 (2017). [Non-Patent Document 4] T. Ohtsuki et al., IEEE Electron Device Lett. 44, 1829 (2023). [Non-Patent Document 5] S. Kumar et al., Appl. Phys. Lett. 117, 193502 (2020). [Overview of the project] [Problems that the invention aims to solve]

[0015] However, the technologies described in Non-Patent Documents 1-5 are not sufficient as countermeasures against conductive layers derived from siloxanes, and there is a need for the development of further measures to eliminate conductive layers formed near the substrate interface.

[0016] For example, the technology described in Non-Patent Document 1 had a problem in that even if it was possible to remove Si compounds adhering to the substrate surface by cleaning, when the substrate was lifted out of the cleaning solution into the atmosphere, siloxanes present in the atmosphere would re-adhere to the substrate surface.

[0017] The technology described in Non-Patent Document 2, like that in Non-Patent Document 1 mentioned above, had the problem that siloxane would re-adhere to the substrate surface immediately after the substrate was removed from the process chamber and exposed to the air after dry etching. Furthermore, since the quartz used as a component of the dry etching process apparatus serves as a source of Si compounds, such dry etching process apparatus can sometimes contribute to silicon contamination of the substrate surface.

[0018] Since the technology described in Non-Patent Document 3 is performed in an ultra-high vacuum chamber, implementation of the technology requires an ultra-high vacuum environment, which has the problem of poor versatility. Furthermore, there have been reports that silicon (Si) adhering to the inner wall of an ultra-high vacuum chamber desorbs and re-adheres to the substrate surface (e.g., E. Welser et al., J. Cryst. Growth 310, 4799 (2008).; F. Alema et al., APL Mater 9, 091102 (2021).).

[0019] In the technology described in Non-Patent Document 4, the conductive layer formed near the interface itself does not disappear, and the technology involves inserting an (Al x Ga 1-x )2O3 layer, which has a larger band gap than Ga2O3, as a back barrier layer. However, since the band offset between Ga2O3 and (Al x Ga 1-x )2O3 is as small as approximately 0.3 eV, there has been a problem that current leakage may occur when the function as a back barrier cannot be sufficiently achieved. For example, when the function of (Al x Ga 1-x )2O3 as a back barrier cannot be sufficiently achieved, such as when (Al x Ga 1-x )2O3 is over-etched during device processing, current leakage may occur.

[0020] In the technology described in Non-Patent Document 5, iron (Fe) ion implantation is performed at an implantation concentration of 2×10 19 cm -3 at a depth of approximately 50 nm from the substrate surface. As a result of simulating the depth profile of ion concentration for such implantation conditions, the iron (Fe) ion concentration near the interface was approximately 1×10 18 cm -3 . On the other hand, the silicon (Si) concentration near the interface is approximately 5×10 19 cm -3Therefore, in the technology described in Non-Patent Document 5, the ion concentration of iron (Fe) near the interface is significantly lower than that of silicon (Si), and the donor is not adequately compensated by iron (Fe) ion implantation, requiring further measures.

[0021] The present invention has been made in view of these circumstances, and its object is to provide a method for manufacturing a semiconductor substrate and a method for manufacturing an epitaxial structure that can effectively suppress the formation of an unintended conductive layer near the interface between the substrate and the epitaxial thin film. [Means for solving the problem]

[0022] To achieve the above objective, the present invention provides the following means. [1] A method for manufacturing a semiconductor substrate used as a base substrate for epitaxial growth of a semiconductor thin film on a substrate, On the surface of the substrate, 5 × 10 20 ~5×10 21 cm -3 An ion implantation process in which impurity ions are implanted at the ion implantation concentration, A method for manufacturing a semiconductor substrate, comprising an annealing step of annealing the ion-implanted substrate in an inert gas atmosphere. [2] The method for manufacturing a semiconductor substrate according to [1], wherein the ion implantation step involves ion implanting the impurity ions such that the ion implantation depth from the surface of the substrate is less than 12 nm. [3] The method for manufacturing a semiconductor substrate according to [1] or [2], wherein the ion implantation step involves ion implanting at least one ion selected from the group consisting of iron, magnesium, and nitrogen (N) as the impurity. [4] The method for manufacturing a semiconductor substrate according to any one of [1] to [3], wherein the annealing step involves annealing the ion-implanted substrate under a nitrogen atmosphere at a temperature of 800 to 1100°C. [5] The method for manufacturing a semiconductor substrate according to any one of [1] to [4], wherein the substrate is made of gallium nitride or gallium oxide. [6] A step of manufacturing a semiconductor substrate by a semiconductor substrate manufacturing method described in any one of the items [1] to [5], A method for manufacturing an epitaxial structure, comprising the step of epitaxially growing a semiconductor thin film on the surface of the obtained semiconductor substrate.

[0023] Furthermore, in one embodiment of the present invention, the present invention relates to a method for manufacturing an epitaxial structure, comprising the steps of: manufacturing a semiconductor substrate by the semiconductor substrate manufacturing method described above; and epitaxially growing a semiconductor thin film on the surface of the obtained semiconductor substrate. [Effects of the Invention]

[0024] According to the present invention, the formation of an unintended conductive layer near the interface between the substrate and the epitaxial thin film can be effectively suppressed. [Brief explanation of the drawing]

[0025] [Figure 1] This is a schematic cross-sectional view showing the configuration of a conventional lateral high-frequency gallium oxide (Ga2O3) transistor. [Figure 2] This graph shows the changes in the sheet resistance value of the substrate surface of the semiconductor substrate in the examples and comparative examples. [Figure 3] This image shows a high-angle scattering annular dark-field scanning transmission microscope (HAADF-STEM) image of a Ga2O3 thin film epitaxially grown on a semiconductor substrate in Example 2. [Modes for carrying out the invention]

[0026] (First Embodiment) Hereinafter, preferred embodiments of a method for manufacturing a semiconductor substrate and a method for manufacturing an epitaxial structure according to the first embodiment of the present invention will be described in detail. Note that this embodiment is not limited to the embodiments described below, and includes various modifications and improvements. In other words, the components described below include those that are easily conceivable by those skilled in the art, and those that are substantially the same, and the components described below can be combined as appropriate. Furthermore, this embodiment may include various omissions, substitutions, or modifications of components without departing from the spirit of the present invention.

[0027] (Method of manufacturing semiconductor substrates) The semiconductor substrate manufacturing method of this embodiment is a method for manufacturing a semiconductor substrate used as a base substrate for epitaxial growth of a semiconductor thin film on a substrate. The semiconductor substrate manufacturing method of this embodiment involves forming a 5 × 10 on the surface of the substrate. 20 ~5×10 21 cm -3 The process includes an ion implantation step in which impurity ions are implanted at an ion implantation concentration, and an annealing step in which the ion-implanted substrate is annealed under an inert gas atmosphere. Here, on the surface of the substrate, 5 × 10 20 ~5×10 21 cm -3 Ion implantation of impurities at an ion implantation concentration of 5 × 10⁻¹⁰ means that the ion implantation concentration of the impurities is 5 × 10⁻¹⁰. 20 ~5×10 21 cm -3 This means that ion implantation into the substrate is performed under such conditions.

[0028] Furthermore, the semiconductor substrate manufacturing method of this embodiment may further include a cleaning step to clean the annealed substrate after the annealing step. The steps in the semiconductor substrate manufacturing method of this embodiment will be described in more detail below.

[0029] Here, there are no particular restrictions on the substrate used in the semiconductor substrate manufacturing method of this embodiment; any substrate conventionally used as a base substrate for epitaxial growth of semiconductor thin films is acceptable. For example, substrates composed of gallium oxide (Ga2O3), gallium nitride (GaN), and gallium arsenide (GaAs) can be used. In particular, in the semiconductor substrate manufacturing method of this embodiment, gallium oxide substrates (hereinafter also referred to as "Ga2O3 substrates") and gallium nitride substrates (hereinafter also referred to as "GaN substrates") are preferred, and beta-gallium oxide substrates (hereinafter also referred to as "β-Ga2O3 substrates") are more preferred. The β-Ga2O3 substrate may be, for example, an iron (Fe)-doped β-Ga2O3(010) substrate.

[0030] (Ion implantation process) In the semiconductor substrate manufacturing method of this embodiment, first, as an ion implantation step, 5 × 10 20 ~5×10 21 cm -3 The ion implantation process involves implanting impurities at the specified ion implantation concentration. Hereafter, the process of implanting impurities at the above-mentioned ion implantation concentration will simply be referred to as "ion implanting impurities." The ion implantation process preferably involves implanting impurities into the entire substrate at the above-mentioned ion implantation concentration. The implanted impurities are incorporated into the thin film and act as acceptors. The ion implantation process is not particularly limited, but it can be carried out at room temperature (e.g., 20°C). The ion implantation process may also be carried out while heating the substrate. Here, the ion implantation concentration refers to the concentration at the point where the impurity concentration is maximum in the ion implantation concentration distribution obtained by multiplying the depth distribution of the implanted impurities by the dose amount. For example, the ion implantation concentration can be measured by compositional analysis in the depth direction of the sample using secondary ion mass spectrometry (SIMS).

[0031] Impurities that act as acceptors and are ion-implanted on the substrate surface diffuse into the thin film during thin film growth. Here, silicon (Si) present near the substrate interface is incorporated into the thin film during thin film growth and acts as a donor. Thus, the silicon (Si) as a donor and the impurities as acceptors compensate for each other, effectively suppressing the formation of unintended conductive layers near the interface.

[0032] Ion implantation concentration 5 × 10 20 ~5×10 21 cm -3 In this way, the silicon (Si) donor is sufficiently compensated for by the impurities acting as acceptors. There are no particular limitations, but for example, the ion implantation concentration is 6 × 10⁻⁶. 20 ~3×10 21 cm -3 Preferably, 7 × 10 20 ~2×10 21 cm -3 It is more preferable that it be 8 × 10 20 ~1 × 10 21 cm -3 This configuration is particularly preferable. By configuring it in this way, the formation of an unintended conductive layer near the interface can be more effectively suppressed.

[0033] Furthermore, in the ion implantation process, it is preferable to implant impurity ions such that the ion implantation depth from the substrate surface is shallower than 12 nm. Hereinafter, the ion implantation depth from the substrate surface when impurity ions are implanted in the ion implantation process will also be simply referred to as "ion implantation depth." That is, the ion implantation depth is preferably 12 nm or less from the substrate surface, more preferably 10 nm or less, even more preferably 8 nm or less, and even more preferably 7 nm or less. For example, the ion implantation depth from the substrate surface may be 5 to 12 nm, 5 to 10 nm, 5 to 8 nm, or 5 to 7 nm. The lower limit of the ion implantation depth may be 6 nm. By configuring it in this way, the formation of an unintended conductive layer near the interface can be more effectively suppressed. Here, ion implantation depth refers to the point where the depth distribution of the implanted impurities is maximum. For example, the ion implantation depth can be measured by compositional analysis in the depth direction of the sample using secondary ion mass spectrometry (SIMS).

[0034] In the ion implantation process, the acceleration voltage for ion implantation is preferably set to 8 to 20 keV, more preferably to 9 to 15 keV, and particularly preferably to 10 to 11 keV. By configuring it in this way, ion implantation with the above-mentioned ion implantation concentration and ion implantation depth can be suitably performed.

[0035] In the ion implantation process, the impurities to be implanted should act as acceptors for silicon (Si), which is incorporated into the thin film during thin film growth and acts as a donor. For example, although not particularly limited, at least one ion selected from the group consisting of iron, magnesium, and nitrogen (N) can be used as an impurity to be implanted. By using at least one ion selected from the above group as the impurity to be implanted, the implanted impurities can appropriately compensate for the silicon (Si) that acts as a donor.

[0036] (Annealing process) In the semiconductor substrate manufacturing method of this embodiment, the next step is to perform an annealing treatment on the ion-implanted substrate under an inert gas atmosphere. The annealing treatment is performed to recover from crystal damage to the substrate induced by ion implantation and to activate the implanted impurities.

[0037] There are no particular restrictions on the annealing conditions; it is sufficient as long as the crystal damage to the substrate is restored and the implanted impurities are activated. For example, the annealing process preferably involves annealing the ion-implanted substrate under a nitrogen atmosphere at a temperature of 800 to 1100°C for 10 to 60 minutes. While not particularly limited, the annealing temperature is more preferably 850-1050°C, and particularly preferably 900-1000°C. The annealing time is more preferably 15 to 50 minutes, and particularly preferably 20 to 40 minutes. Furthermore, the annealing process may be carried out under an inert gas atmosphere other than a nitrogen atmosphere.

[0038] (Washing process) In the semiconductor substrate manufacturing method of this embodiment, the substrate that has undergone the annealing process may be subjected to the following cleaning process.

[0039] First, in the cleaning process, the substrate that has undergone the annealing process is cleaned with an organic solvent. Examples of organic solvents include known solvents such as acetone, isopropyl alcohol, methanol, and ethanol. There are no particular restrictions on the cleaning method, and known cleaning methods such as ultrasonic cleaning can be used.

[0040] For example, as a cleaning step, the substrate that has undergone the annealing process may be sequentially wiped with acetone, isopropyl alcohol, methanol, and ethanol, and then ultrasonically cleaned. There are no particular restrictions on the cleaning time with each organic solvent; the cleaning time may be, for example, 2 to 5 minutes.

[0041] In the cleaning process, after cleaning with an organic solvent, the substrate may be further cleaned with a piranha solution. An example of a piranha solution is a solution obtained by mixing concentrated sulfuric acid (H2SO4) and 30% by mass hydrogen peroxide solution (H2O2) in a volume ratio of 4:1. For example, a substrate that has been cleaned with an organic solvent may be cleaned with the piranha solution for 5 minutes, and then further cleaned with pure water for 1 minute. The cleaning with pure water may be repeated multiple times. For example, the cleaning with pure water may be repeated three times. Furthermore, although not particularly limited, cleaning with the piranha solution and pure water (hereinafter simply referred to as "cleaning with piranha solution") may be repeated multiple times.

[0042] Furthermore, in the cleaning process, after cleaning with piranha solution, the substrate may be further cleaned with 50% by mass hydrogen fluoride (HF). For example, a substrate that has been cleaned with piranha solution may be cleaned with the above-mentioned hydrogen fluoride for 30 minutes, and then further cleaned with pure water for 1 minute. The cleaning with pure water may be repeated multiple times. For example, the cleaning with pure water may be repeated three times. In addition, although not particularly limited, cleaning with hydrogen fluoride and pure water (hereinafter simply referred to as "cleaning with hydrogen fluoride") may be repeated multiple times.

[0043] The surface of the ion-implanted and annealed substrate is etched by washing with the piranha solution and hydrogen fluoride as described above. For example, the etching amount is preferably smaller than the implantation depth, while increasing the etching amount allows the ion implantation depth to be brought closer to the substrate surface, making it easier for the effects of the ion-implanted impurities to manifest.

[0044] The semiconductor substrate manufactured by the ion implantation process, the cleaning process, and any additional cleaning process described above is suitably used as a base substrate for epitaxial growth of semiconductor thin films. Furthermore, when a semiconductor thin film is epitaxially grown on this semiconductor substrate, the formation of an unintended conductive layer near the interface between the semiconductor substrate and the epitaxial thin film can be effectively suppressed. In other words, when silicon (Si) present near the interface of the semiconductor substrate is incorporated into the thin film, the incorporated silicon (Si) as a donor and the impurities implanted as acceptors compensate for each other, effectively suppressing the formation of a highly electrically conductive layer.

[0045] (Method for manufacturing epitaxial structures) Next, the method for manufacturing the epitaxial structure of this embodiment will be described. The method for manufacturing the epitaxial structure of this embodiment includes the steps of manufacturing a semiconductor substrate using the semiconductor substrate manufacturing method of this embodiment described above, and epitaxially growing a semiconductor thin film on the surface of the obtained semiconductor substrate. The step of manufacturing the semiconductor substrate in the method for manufacturing the epitaxial structure of this embodiment (hereinafter also referred to as the "semiconductor substrate manufacturing step") can be carried out in the same manner as the semiconductor substrate manufacturing method of this embodiment described above. The step of epitaxial growth in the method for manufacturing the epitaxial structure of this embodiment (hereinafter also referred to as the "epitaxial step") will now be described.

[0046] (Epitaxial process) In the manufacturing method of the epitaxial structure of this embodiment, the epitaxial step can be a thin-film growth process using a conventionally known epitaxial technique. Examples of thin-film growth processes include the vapor phase epitaxy (VPE) method and the chemical solution deposition (CSD) method.

[0047] Examples of VPE methods include physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0048] PVD (Physical Vapor Deposition) is a method that involves injecting physical energy into a single- or multi-element solid material target to cause evaporation, followed by recrystallization as a thin film on a substrate. Examples of PVD methods include sputtering, which uses plasma to evaporate the target; pulsed laser deposition (PLD), which uses laser light; and molecular beam epitaxy (MBE), which uses electron beams or resistance heating.

[0049] On the other hand, the CVD method is a method in which a raw material gas containing the constituent materials of the target thin film is flowed into the space on which the substrate is placed, and a thin film is fabricated through chemical reactions in the gas phase and on the substrate surface through the excitation and decomposition of molecules of the raw material gas.

[0050] When a β-Ga2O3 substrate, such as an iron (Fe)-doped β-Ga2O3(010) substrate, is used as the substrate, it is preferable to grow a Ga2O3 thin film on the surface of the obtained semiconductor substrate by molecular beam epitaxy (MBE). For example, when a Ga2O3 thin film is epitaxially grown by molecular beam epitaxy (MBE), silicon (Si) present near the interface of the semiconductor substrate is incorporated into the Ga2O3 thin film. However, the silicon (Si) incorporated into the Ga2O3 thin film as a donor and the impurities implanted as ion acceptors compensate for each other, effectively suppressing the formation of a highly electrically conductive layer.

[0051] The manufacturing method for epitaxial structures in this embodiment is expected to be more effective in fabricating lateral high-frequency Ga2O3 transistors that do not exhibit drain current leakage. Furthermore, the formation of unintended highly electrically conductive layers can occur in other material systems that do not contain Si. For this reason, the manufacturing methods for semiconductor substrates and epitaxial structures in this embodiment can also be applied to other material systems that do not contain Si.

[0052] Although embodiments of this invention have been described in detail above, the specific configuration is not limited to the embodiments described herein, and includes design changes and the like that do not depart from the gist of this invention. Furthermore, various modifications are possible within the scope of the claims for one aspect of the present invention, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this invention. [Examples]

[0053] The present invention will be described in more detail below with reference to examples and comparative examples, but the present invention is not limited to the following examples.

[0054] (Example 1) (Fabrication of semiconductor substrates) First, a commercially available Fe-doped β-Ga2O3(010) substrate (manufactured by Novel Crystal Technology Co., Ltd., product name (10×15mm) 2 β-Ga2O3(010) substrates were prepared. Next, iron (Fe) ions were implanted as an impurity into the prepared Fe-doped β-Ga2O3(010) substrates. The ion implantation was performed with an ion implantation concentration of 5 × 10⁻¹⁰. 20 cm -3 The ion implantation depth was 6 nm, the acceleration voltage (implantation energy) was 10 keV, and the temperature was room temperature.

[0055] Next, the ion-implanted substrate was annealed at 950°C for 30 minutes under a nitrogen atmosphere.

[0056] Next, the annealed substrate was washed with organic solvents: acetone, isopropyl alcohol, methanol, and ethanol. Specifically, it was washed three times with acetone, followed by washing with isopropyl alcohol, methanol, and ethanol in that order. Each washing step lasted 3 minutes.

[0057] Next, the substrates that had been cleaned with an organic solvent were washed with piranha solution and pure water. Specifically, the substrates were first washed with piranha solution for 5 minutes, and then washed three times with pure water for 1 minute each.

[0058] Next, the substrates that had been washed with the piranha solution were washed with 50% by mass hydrogen fluoride (HF) and pure water. Specifically, the substrates were first washed with the hydrogen fluoride solution for 30 minutes, and then washed with pure water for 1 minute three times.

[0059] As described above, 5 × 10 20 cm -3 A semiconductor substrate was fabricated by ion implanting impurities at the specified ion implantation concentration. The fabricated semiconductor substrate had its surface etched by approximately 2.5 nm by cleaning with the piranha solution and with hydrogen fluoride (HF) as described above. The semiconductor substrate fabricated in this manner was used as the semiconductor substrate for Example 1.

[0060] (Epitaxial growth of Ga2O3 thin films) The semiconductor substrate fabricated in Example 1 was used as a base substrate for epitaxial growth of a Ga2O3 thin film, and the Ga2O3 thin film was grown on the fabricated semiconductor substrate using the following method. Specifically, the fabricated semiconductor substrate was introduced into a molecular beam epitaxy apparatus (for example, Veeco, Inc., product name (GEN930)), and the Ga2O3 thin film was grown by molecular beam epitaxy (MBE). The epitaxial growth of the Ga2O3 thin film was performed with an equivalent Ga beam pressure of 2.53 × 10⁻⁶. -5The experiment was conducted under conditions of Pa, ozone flow rate of 2.0 sccm, and substrate temperature of 630°C. The thickness of the Ga2O3 thin film was approximately 200 nm.

[0061] (Example 2) Ion implantation concentration 1 × 10 21 cm -3 Except for the change made, the semiconductor substrate for Example 2 was fabricated in the same manner as in Example 1. Then, a Ga2O3 thin film was grown on the fabricated semiconductor substrate in the same manner as in Example 1.

[0062] (Comparative Example 1) Ion implantation concentration 1 × 10 20 cm -3 A semiconductor substrate for Comparative Example 1 was fabricated in the same manner as in Example 1, except for one change. Then, a Ga2O3 thin film was grown on the fabricated semiconductor substrate in the same manner as in Example 1.

[0063] (Comparative Example 2) A commercially available Fe-doped β-Ga2O3(010) substrate, the same as the one used to prepare the semiconductor substrate for Example 1, was prepared and used as the semiconductor substrate for Comparative Example 2. The semiconductor substrate of Comparative Example 2 was used as a base substrate for epitaxial growth of a Ga2O3 thin film, and a Ga2O3 thin film was grown on the semiconductor substrate in the same manner as in Example 1.

[0064] (Evaluation of conductivity at the interface between a semiconductor substrate and a Ga2O3 thin film) The conductivity of the interface between the semiconductor substrate and the Ga2O3 thin film was evaluated for the semiconductor substrates of Examples 1 and 2 and Comparative Examples 1 and 2 using the following method.

[0065] Specifically, in Examples 1 and 2 and Comparative Example 1, the sheet resistance values ​​of the substrate surface were measured using an electrostatic coupling sheet resistance meter for substrates before ion implantation, substrates after ion implantation, substrates after annealing, and substrates on which a Ga2O3 thin film was grown. In Comparative Example 2, neither ion implantation nor annealing was performed. Therefore, in Comparative Example 2, the prepared substrate was considered as a substrate before ion implantation, and the sheet resistance values ​​of the substrate surface were measured in the same manner as in Example 1 for the substrate before ion implantation and the substrate on which a Ga2O3 thin film was grown. The measurement results of the sheet resistance values ​​are shown in Figure 2. Figure 2 is a graph showing the changes in the sheet resistance values ​​of the substrate surface of the semiconductor substrates in the Examples and Comparative Examples, where the horizontal axis indicates the measurement time when the sheet resistance value was measured, and the vertical axis indicates the sheet resistance value (kΩ / sq). The meaning of the items on the horizontal axis of the graph shown in Figure 2 is as follows: "Before ion implantation" is written for substrates before ion implantation. "After ion implantation" is written for substrates after ion implantation. Substrates that have undergone annealing treatment are described as "after annealing treatment." Substrates on which a Ga2O3 thin film has been grown are described as "after thin film growth." The measured sheet resistance value after thin film growth is the sheet resistance value at the interface between the semiconductor substrate and the Ga2O3 thin film.

[0066] The semiconductor substrate of Comparative Example 2 is a substrate that has not undergone ion implantation or annealing treatment, and as shown in Figure 2, the sheet resistance value has decreased significantly after thin film growth. Therefore, it is presumed that in the semiconductor substrate of Comparative Example 2, a highly electrically conductive layer is formed at the interface between the semiconductor substrate and the Ga2O3 thin film after thin film growth. In addition, the semiconductor substrate of Comparative Example 1 has an ion implantation concentration of 1 × 10⁻⁶. 20 cm -3 This is a substrate that has undergone ion implantation. As shown in Figure 2, the sheet resistance of the semiconductor substrate of Comparative Example 1 decreases after thin film growth. Therefore, it is presumed that, in the case of the semiconductor substrate of Comparative Example 1 as well, a highly electrically conductive layer is formed at the interface between the semiconductor substrate and the Ga2O3 thin film after thin film growth.

[0067] On the other hand, the semiconductor substrate of Example 1 has an ion implantation concentration of 5 × 10⁻⁶ 20 cm -3 The substrate was ion-implanted as follows: The semiconductor substrate of Example 2 had an ion implantation concentration of 1 × 10⁻⁶. 21 cm -3 This is a substrate that has undergone ion implantation. As shown in Figure 2, the sheet resistance of the semiconductor substrates in Examples 1 and 2 hardly changed after thin film growth. Therefore, the semiconductor substrates in Examples 1 and 2 were able to effectively suppress the formation of a highly electrically conductive layer at the interface between the semiconductor substrate and the Ga2O3 thin film after thin film growth. Comparing Examples 1 and 2 with Comparative Example 1, the sheet resistance of the semiconductor substrate in Comparative Example 1 decreased after thin film growth, suggesting that an ion implantation concentration of 1 × 10⁻⁶, as in Comparative Example 1, is not sufficient. 20 cm -3 However, it was found that the effect of suppressing the formation of the conductive layer was not sufficiently obtained. That is, 5 × 10 on the surface of the substrate 20 cm -3 It is believed that performing ion implantation at the above ion implantation concentrations can effectively suppress the formation of a highly electrically conductive layer.

[0068] In Example 2, 1 × 10⁻¹⁶ ions were implanted near the substrate surface at an ion implantation depth of 6 nm. 21 cm -3 Because ion implantation was performed at such a high concentration, we investigated its effect on the crystallinity of the epitaxially grown Ga2O3 thin film. Specifically, the epitaxially grown Ga2O3 thin film was analyzed using high-angle scattering annular dark-field scanning transmission microscopy (HAADF-STEM). The analysis results are shown in Figure 3. Figure 3 is an image of the high-angle scattering annular dark-field scanning transmission microscopy (HAADF-STEM) of the Ga2O3 thin film epitaxially grown on the semiconductor substrate of Example 2. Hereafter, the high-angle scattering annular dark-field scanning transmission microscopy (HAADF-STEM) image shown in Figure 3 will also be simply referred to as the "HAADF-STEM image".

[0069] As shown in the HAADF-STEM image in Figure 3, 1 × 10 21 cm -3Even when a Ga2O3 thin film was grown on a semiconductor substrate that had undergone ion implantation at such a high concentration, it was confirmed that the Ga2O3 thin film grew without any disorder in its crystal structure. Therefore, 1 × 10 21 cm -3 Even when ion implantation was performed at such a high concentration, it was confirmed that the thin film grew properly without any disruption to the crystal structure, similar to the case where a Ga2O3 thin film was grown on a semiconductor substrate without ion implantation, as in Comparative Example 2. [Explanation of Symbols]

[0070] 10 Ga2O3 substrates 20 Ga2O3 thin film 21 Source Area 22 Source electrodes 23 Drain area 24 Drain electrodes 25 Channel Section 26 Gate insulating film 27 Shuttle gate 30 Conduction layer 31 Current Path 100 Horizontal High-Frequency Gallium Oxide Transistors

Claims

1. A method for manufacturing a semiconductor substrate used as a base substrate for epitaxial growth of a semiconductor thin film on a substrate, On the surface of the substrate, 5 x 10 ２０ ~5 x 10 ２１ cm －３ An ion implantation process in which impurity ions are implanted at the ion implantation concentration, A method for manufacturing a semiconductor substrate, comprising an annealing step of annealing the ion-implanted substrate in an inert gas atmosphere.

2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the ion implantation step involves implanting the impurity ions such that the ion implantation depth from the surface of the substrate is less than 12 nm.

3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the ion implantation step involves ion implanting at least one ion selected from the group consisting of iron, magnesium, and nitrogen (N) as the impurity.

4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the annealing step involves annealing the ion-implanted substrate under a nitrogen atmosphere at a temperature of 800 to 1100°C.

5. The method for manufacturing a semiconductor substrate according to claim 1, wherein the substrate is made of gallium nitride or gallium oxide.

6. A step of manufacturing a semiconductor substrate by the semiconductor substrate manufacturing method described in any one of claims 1 to 5, A method for manufacturing an epitaxial structure, comprising the step of epitaxially growing a semiconductor thin film on the surface of the obtained semiconductor substrate.

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