Semiconductor equipment

Abstract

To provide a semiconductor device with improved characteristics. [Solution] According to the embodiment, the semiconductor device includes first to third electrodes, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type. The first semiconductor region includes first to third subregions. The second subregion is located between the first electrode and the second semiconductor region. At least a portion of the third semiconductor region is located between the second semiconductor region and the second electrode. The semiconductor member includes a diode portion and a transistor portion. In the transistor portion, the third subregion is located between the first subregion and the third electrode in a first direction. In the diode portion, the third subregion is not provided between the first subregion and the third electrode, and a portion of the second semiconductor region is provided between the first subregion and the third electrode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device. [Background Art]

[0002] For example, improvement of characteristics is desired in semiconductor devices. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Laying-Open No.2023-77119 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An embodiment provides a semiconductor device capable of improving characteristics. [Means for Solving the Problem]

[0005] According to the embodiment, the semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first insulating member. The semiconductor member is provided between the first electrode and the second electrode. The third electrode extends along a second direction intersecting a first direction from the first electrode to the second electrode. The first insulating member includes a first insulating region. The first insulating region is located between the semiconductor member and the third electrode. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type. The first semiconductor region includes a first partial region, a second partial region, and a third partial region. The third direction from the first partial region to the second partial region intersects a plane including the first and second directions. The second partial region is located between the first electrode and the second semiconductor region in the first direction. At least a portion of the third semiconductor region is located between the second semiconductor region and the second electrode. The third semiconductor region is electrically connected to the second electrode. The semiconductor member includes a diode portion and a transistor portion. In the transistor portion, the third sub-region is located between the first sub-region and the third electrode in the first direction. In the transistor portion, the direction from the third sub-region to the second semiconductor region is along the third direction. In the diode portion, the third sub-region is not provided between the first sub-region and the third electrode. In the diode portion, a part of the second semiconductor region is provided between the first sub-region and the third electrode. The diode portion includes a first diode region. The transistor portion includes a first transistor region. The direction from the first diode region to the first transistor region is along the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 3]Figure 3 is a schematic cross-sectional view illustrating a part of a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a schematic perspective view illustrating a part of the semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view illustrating a part of the semiconductor device according to the first embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals with respect to previously shown figures, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. Figures 2 and 3 are schematic cross-sectional views illustrating a part of a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view taken along line A1-A2 in Figure 1. Figure 3 is a cross-sectional view taken along line B1-B2 in Figure 1. Figure 4 is a schematic perspective view illustrating a part of the semiconductor device according to the first embodiment. Figure 5 is a schematic plan view illustrating a part of the semiconductor device according to the first embodiment.

[0009] As shown in Figures 1 to 4, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a semiconductor member 10, and a first insulating member 41.

[0010] The semiconductor component 10 is provided between the first electrode 51 and the second electrode 52. The first direction D1 from the first electrode 51 to the second electrode 52 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to both the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0011] The third electrode 53 extends along the second direction D2. The second direction D2 intersects the first direction D1 from the first electrode 51 to the second electrode 52. The second direction D2 may be, for example, the X-axis direction.

[0012] As shown in Figure 2, the first insulating member 41 includes a first insulating region 41a. The first insulating region 41a is located between the semiconductor member 10 and the third electrode 53. The first insulating member 41 may further include a second insulating region 41b. At least a portion of the second insulating region 41b is located between the third electrode 53 and the second electrode 52.

[0013] As shown in Figure 2, the semiconductor member 10 includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, and a third semiconductor region 13 of the first conductivity type. The first conductivity type is either n-type or p-type. The second conductivity type is the other of n-type and p-type. Hereafter, the first conductivity type will be assumed to be n-type and the second conductivity type will be assumed to be p-type.

[0014] The first semiconductor region 11 includes a first subregion 11a, a second subregion 11b, and a third subregion 11c. The third direction D3 from the first subregion 11a to the second subregion 11b intersects a plane (e.g., the ZX plane) that includes the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0015] The second partial region 11b lies between the first electrode 51 and the second semiconductor region 12 in the first direction D1. At least a portion of the third semiconductor region 13 lies between the second semiconductor region 12 and the second electrode 52. The third semiconductor region 13 is electrically connected to the second electrode 52.

[0016] As shown in FIG. 1, the semiconductor member 10 includes a diode portion 60 and a transistor portion 70. FIG. 2 exemplifies a cross-section of the transistor portion 70. FIG. 3 exemplifies a cross-section of the diode portion 60.

[0017] As shown in FIG. 2, in the transistor portion 70, the third partial region 11c is located between the first partial region 11a and the third electrode 53 in the first direction D1. In the transistor portion 70, the direction from the third partial region 11c to the second semiconductor region 12 is along the third direction D3.

[0018] As shown in FIG. 3, in the diode portion 60, the third partial region 11c is not provided between the first partial region 11a and the third electrode 53. In the diode portion 60, a part of the second semiconductor region 12 is provided between the first partial region 11a and the third electrode 53. For example, the second semiconductor region 12 and the first semiconductor region 11 form a pn diode.

[0019] As shown in FIG. 1, the diode portion 60 includes a first diode region 61. The transistor portion 70 includes a first transistor region 71. The direction from the first diode region 61 to the first transistor region 71 is along the second direction D2.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the second electrode 52. The first electrode 51 functions as, for example, a drain electrode. The second electrode 52 functions as, for example, a source electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 110 is, for example, a transistor. The transistor portion 70 is, for example, a MOS (Metal Oxide Semiconductor) region.

[0021] In the embodiment, providing the diode portion 60 suppresses adverse effects caused by, for example, surge current. For example, destruction caused by surge current is suppressed.

[0022] As shown in Figure 4, in this embodiment, the direction from the first diode region 61 to the first transistor region 71 is along the second direction D2 (see Figure 1). The first transistor region 71 is provided next to the first diode region 61. When in ON operation, the carrier c1 flowing through the first diode region 61 can flow towards the first electrode 51 via the first transistor region 71. This suppresses the reduction in ON current caused by the diode portion 60 (e.g., the first diode region 61). The first transistor region 71 becomes a current path. In this embodiment, a low ON resistance can be obtained. According to this embodiment, a semiconductor device with improved characteristics can be provided.

[0023] For example, the area of ​​the PN region of the diode portion 60 per unit area is larger than the area of ​​the PN region of the transistor portion 70 per unit area. The current flowing through the PN junction diode included in the diode portion 60 is larger than the current flowing through the PN junction diode included in the transistor portion 70.

[0024] The resistance in the diode portion 60 is lower than the resistance in the diode (body diode) included in the transistor portion 70 (MOSFET portion). For example, when a large current such as a surge is applied, the current preferentially flows through the diode portion 60. For example, the diode portion 60 has the effect of concentrating the surge current.

[0025] When a surge current is applied, conductivity modulation occurs more easily in the diode portion 60 than in the MOSFET portion, and the effect of conductivity modulation is stronger. For example, this region where conductivity is modulated becomes the "starting point." Carriers generated based on conductivity modulation spread to adjacent cells, further increasing the current. As the current increases, heat is generated in the diode portion 60, and the forward voltage Vf of the diode portion 60 decreases. This provides positive feedback. Surge current concentrates in the diode portion 60. The diode portion 60 becomes the starting point for conductivity modulation. For example, large currents and heat can be distributed to adjacent diode portions 60.

[0026] As shown in Figures 1 and 5, the diode portion 60 may further include a second diode region 62. The first transistor region 71 is located between the first diode region 61 and the second diode region 62 in the second direction D2.

[0027] As shown in Figures 1 and 5, the transistor portion 70 may further include a second transistor region 72. The direction from at least a portion of the second transistor region 72 to the first diode region 61 is along the third direction D3.

[0028] The transistor region 70 may further include a third transistor region 73. The first diode region 61 is located between the second transistor region 72 and the third transistor region 73 in the third direction D3. The second diode region 62 is located between the second transistor region 72 and the third transistor region 73 in the third direction D3.

[0029] Thus, transistor portions 70 may be provided next to the first diode region 61 and the second diode region 62, respectively. The transistor portions 70, which function as current paths, provide low on-resistance.

[0030] For example, as described above, by providing the first transistor region 71 between the first diode region 61 and the second diode region 62, a low on-resistance can be obtained. The diode region suppresses the adverse effects of surge current. On the other hand, since the diode region does not operate during ON operation, it may worsen the on-resistance. In this case, the first transistor region 71 functions as a current bypass region, which can mitigate the deterioration of the on-resistance. As a result, a low on-resistance can be obtained.

[0031] As shown in Figure 5, a plurality of first diode regions 61 and a plurality of second diode regions 62 may be provided between the second transistor region 72 and the third transistor region 73. A first transistor region 71 may be provided between one of the plurality of first diode regions 61 and one of the plurality of second diode regions 62.

[0032] In one example, the first length L1 of the first diode region 61 in the second direction D2 may be longer than the third length L3 of the first transistor region 71 in the second direction D2. In one example, the second length L2 of the second diode region 62 in the second direction D2 may be longer than the third length L3 of the first transistor region 71 in the second direction D2.

[0033] In one example, the first length L1 may be at least 1x and up to 10x the third length L3. The first length L1 may also be at least 4x and up to 6x the third length L3. The second length L2 may also be at least 1x and up to 10x the third length L3. The second length L2 may also be at least 4x and up to 6x the third length L3. In one example, the third length L3 may be at least 5μm and up to 30μm.

[0034] The length (width) of the first diode region 61 in the first direction D1 may be 0.9 times or more and 1.1 times or less the length (width) of the first transistor region 71 in the first direction D1. For example, the length (width) of the first transistor region 71 in the first direction D1 may be 5 μm or more and 30 μm or less.

[0035] As shown in Figure 1, for example, the length L1 along the third direction D3 of the semiconductor member 10 may be greater than or equal to the length L2 along the second direction D2 of the semiconductor member 10.

[0036] As shown in Figures 1 to 3, multiple third electrodes 53 may be provided. The multiple third electrodes 53 are arranged along the third direction D3. As shown in Figures 2 and 3, the diode portion 60 and the transistor portion 70 are provided corresponding to the multiple third electrodes 53.

[0037] In this embodiment, the concentration of the third impurity of the first conductivity type in the third semiconductor region 13 is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11.

[0038] As shown in Figures 2 and 3, the semiconductor member 10 may further include a fourth semiconductor region 14 of the second conductivity type. The fourth semiconductor region 14 is located between the second semiconductor region 12 and the second electrode 52. The concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region 14 is higher than the concentration of the second impurity of the second conductivity type in the second semiconductor region 12.

[0039] As shown in Figures 2 and 3, the semiconductor member 10 may further include a fifth semiconductor region 15 of the second conductivity type. The fifth semiconductor region 15 is located between the fourth semiconductor region 14 and the second electrode 52. The concentration of the fifth impurity of the second conductivity type in the fifth semiconductor region 15 is higher than the concentration of the fourth impurity.

[0040] As shown in Figures 2 and 3, the semiconductor device 110 may further include a first electrode portion 52a. The first electrode portion 52a is located between the first semiconductor region 11 and the second electrode 52. For example, a Schottky diode may be formed in the portion including the first electrode portion 52a. The first electrode portion 52a may include, for example, at least one selected from the group consisting of Ti and Al.

[0041] As shown in Figures 2 and 3, the position of the first electrode portion 52a along the third direction D3 is between the position of one of the multiple third electrodes 53 in the third direction D3 and the position of another of the multiple third electrodes 53 in the third direction D3.

[0042] The semiconductor component 10 may contain SiC or Si. The semiconductor component 10 may contain, for example, at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC. If the semiconductor component 10 contains SiC, the impurity of the first conductivity type may contain, for example, at least one selected from the group consisting of N, P, and As. If the semiconductor component 10 contains SiC, the impurity of the second conductivity type may contain, for example, at least one selected from the group consisting of B, Al, and Ga. The semiconductor component 10 may contain, for example, a compound semiconductor containing Ga.

[0043] At least one of the first electrode 51 and the second electrode 52 may include at least one selected from the group consisting of Al, Cu, Ti, Ni, Ag, and Au. At least one of the first electrode 51 and the second electrode 52 may include at least one selected from the group consisting of titanium silicide and nickel silicide. The third electrode 53 may include, for example, conductive polysilicon.

[0044] In the embodiment, information regarding length and thickness is obtained by electron microscopy observation or the like. Information regarding the material composition is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy) or the like.

[0045] According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0046] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element such as electrodes, semiconductor members, and insulating members included in a semiconductor device is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.

[0047] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0048] Furthermore, all semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0049] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention.

[0050] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0051] 10: Semiconductor material, 11-15: 1st-5th semiconductor regions, 11a-11c: 1st-3rd partial regions, 41: 1st insulating material, 41a, 41b: 1st and 2nd insulating regions, 51-53: 1st-3rd electrodes, 52a: 1st electrode portion, 60: Diode portion, 61, 62: 1st and 2nd diode regions, 70: Transistor portion, 71-73: 1st-3rd transistor regions, 110: Semiconductor device, D1-D3: 1st-3rd directions, L1-L3: 1st-3rd lengths, c1: Carrier

Claims

1. First electrode and The second electrode and A semiconductor member provided between the first electrode and the second electrode, A third electrode extending along a second direction intersecting the first direction from the first electrode to the second electrode, A first insulating member including a first insulating region, wherein the first insulating region is located between the semiconductor member and the third electrode, Equipped with, The aforementioned semiconductor member is The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, Includes, The first semiconductor region includes a first subregion, a second subregion, and a third subregion. The third direction from the first subregion to the second subregion intersects the plane containing the first and second directions. The second subregion is located between the first electrode and the second semiconductor region in the first direction. At least a portion of the third semiconductor region is located between the second semiconductor region and the second electrode. The third semiconductor region is electrically connected to the second electrode, The semiconductor component includes a diode portion and a transistor portion. In the transistor portion, the third subregion is located between the first subregion and the third electrode in the first direction. In the transistor portion, the direction from the third subregion to the second semiconductor region is along the third direction, In the diode portion, the third partial region is not provided between the first partial region and the third electrode. In the diode portion, a part of the second semiconductor region is provided between the first partial region and the third electrode. The diode portion includes a first diode region, The transistor portion includes a first transistor region, A semiconductor device in which the direction from the first diode region to the first transistor region is along the second direction.

2. The diode portion further includes a second diode region, The semiconductor device according to claim 1, wherein the first transistor region is located between the first diode region and the second diode region in the second direction.

3. The transistor region further includes a second transistor region, The semiconductor device according to claim 2, wherein the direction from at least a portion of the second transistor region to the first diode region is along the third direction.

4. The transistor region further includes a third transistor region, The semiconductor device according to claim 3, wherein the first diode region is located between the second transistor region and the third transistor region in the third direction.

5. The semiconductor device according to claim 4, wherein the second diode region is located between the second transistor region and the third transistor region in the third direction.

6. The semiconductor device according to claim 4, wherein a plurality of first diode regions and a plurality of second diode regions are provided between the second transistor region and the third transistor region.

7. Multiple third electrodes are provided, The plurality of third electrodes are arranged along the third direction, The semiconductor device according to any one of claims 1 to 6, wherein the diode portion and the transistor portion are provided in correspondence with the plurality of third electrodes.

8. The semiconductor device according to any one of claims 1 to 6, wherein the first length of the first diode region in the second direction is longer than the third length of the first transistor region in the second direction.

9. The semiconductor device according to claim 2, wherein the first length of the first diode region in the second direction and the second length of the second diode region in the second direction are each longer than the third length of the first transistor region in the second direction.

10. Further comprising the first electrode portion, The first electrode portion is located between the first semiconductor region and the second electrode. A semiconductor device according to any one of claims 1 to 6, wherein a Schottky diode is formed in the portion including the first electrode portion.

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