Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device having a cantilever structure that can reduce sound leakage and suppress the decrease in sound pressure in the low-frequency range, as well as a method for manufacturing the same. [Solution] The semiconductor device 100 comprises a diaphragm 10d having a first main surface 10h, a first support portion 10f connected to the diaphragm via a connection portion 10g, a peripheral member 10i arranged around the diaphragm excluding the connection portion via a slit 10e, a first laminated film 10 including a piezoelectric layer 18 arranged on the first main surface, and an additional film 20 arranged on at least the upper surface of the first laminated film and extending toward the slit. Viewed from the direction normal to the first main surface, at least a portion of the outer edge of the additional film is located on the slit side of the boundary line between the diaphragm and the slit, and is also located on the slit side of the boundary line between the peripheral member and the slit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Conventionally, micro electro mechanical system (MEMS) technology for fabricating mechanical structures on semiconductor substrates such as silicon using semiconductor manufacturing technology has been provided. In MEMS devices to which MEMS technology is applied, for example, there is a piezoelectric element in which a transducer that drives a vibration membrane with a piezoelectric body and a subframe that forms a frame surrounding the vibration membrane are respectively formed on a silicon substrate and bonded to be stacked, as disclosed in Patent Document 1. Some of these devices have a structure called a cantilever and are applied to speakers and the like.

[0003] Further, piezoelectric elements for MEMS devices have sometimes been fabricated using a silicon on insulator (SOI) wafer in which a buried layer consisting of a buried oxide (BOX) layer and an active layer is formed on the surface of a silicon substrate, as disclosed in Patent Document 2.

Prior Art Literature

Patent Literature

[0004]

Patent Document 1

Patent Document 2

[0005] [Summary] One of the indicators of speaker performance is the frequency response of sound pressure. In speakers with a cantilever structure, the diaphragm is constrained only at the connection point between the diaphragm and the support, making it easy to increase the amplitude of vibration and thus the sound pressure. On the other hand, sound leaks in the opposite direction to the direction of sound emission through slits provided in addition to the connection point between the diaphragm and the support, which presents a problem in that the sounds cancel each other out, especially in the low-frequency range, resulting in a decrease in sound pressure.

[0006] The purpose of this disclosure is to provide a semiconductor device having a cantilever structure that can reduce sound leakage and suppress the decrease in sound pressure in the low-frequency range, and a method for manufacturing the same.

[0007] A semiconductor device according to one aspect of the present disclosure comprises a diaphragm having a first main surface, a first support portion connected to the diaphragm via a connection point, and a peripheral member disposed around the diaphragm, excluding the connection point, via a slit. The semiconductor device further comprises a first laminated film including a piezoelectric layer disposed on the first main surface, and an additional film disposed on at least the upper surface of the first laminated film and extending toward the slit. Viewed from the direction normal to the first main surface, at least a portion of the outer edge of the additional film is located on the slit side of the boundary line between the diaphragm and the slit, and is located on the slit side of the boundary line between the peripheral member and the slit.

[0008] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of forming a first laminated film including a piezoelectric layer on a first main surface of a substrate, and forming a slit between the first laminated film and the substrate in a region of the first laminated film that does not include the piezoelectric layer when viewed from the direction normal to the first main surface. The method for manufacturing a semiconductor device further includes the steps of forming an additional film on the upper surface of the first laminated film and the upper part of the slit, and removing a portion of the additional film disposed above the slit. The step of removing a portion of the additional film is performed such that the outer edge of the additional film protrudes above the slit and a portion of the upper part of the slit is exposed.

[0009] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the steps of forming a first laminated film including a piezoelectric layer on a first main surface of a substrate, and forming a slit between the first laminated film and the substrate in a region of the first laminated film that does not include the piezoelectric layer when viewed from the direction normal to the first main surface. The method for manufacturing a semiconductor device further includes the steps of forming an additional film on the upper surface of the first laminated film and on the side surface of the slit. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a plan view of the semiconductor device according to the first embodiment, as seen from the top surface. [Figure 2] Figure 2 is a cross-sectional view of the semiconductor device according to the first embodiment, along line II-II. [Figure 3] Figure 3 is an enlarged cross-sectional view of the main part of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view of the semiconductor device according to the first embodiment, along line IV-IV. [Figure 5A] Figure 5A is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (Part 1). [Figure 5B] Figure 5B is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 2). [Figure 5C] Figure 5C is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 3). [Figure 5D] Figure 5D is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 4). [Figure 5E] Figure 5E is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 5). [Figure 5F] Figure 5F is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 6). [Figure 5G] Figure 5G is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 7). [Figure 5H] Figure 5H is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment (part 8). [Figure 6] FIG. 6 is a diagram showing characteristics of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is an enlarged cross-sectional view of main parts of the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is an enlarged cross-sectional view of main parts of the semiconductor device according to the third embodiment. [Figure 11A] FIG. 11A is a diagram (Part 1) for explaining the manufacturing steps of the semiconductor device according to the third embodiment. [Figure 11B] FIG. 11B is a diagram (Part 2) for explaining the manufacturing steps of the semiconductor device according to the third embodiment. [Figure 11C] FIG. 11C is a diagram (Part 3) for explaining the manufacturing steps of the semiconductor device according to the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to a modification of the third embodiment. [Figure 13] FIG. 13 is a cross-sectional view of the semiconductor device according to the fourth embodiment. [Figure 14] FIG. 14 is an enlarged cross-sectional view of main parts of the semiconductor device according to the fourth embodiment. [Figure 15A] FIG. 15A is a diagram (Part 1) for explaining the manufacturing steps of the semiconductor device according to the fourth embodiment. [Figure 15B] FIG. 15B is a diagram (Part 2) for explaining the manufacturing steps of the semiconductor device according to the fourth embodiment. [Figure 15C] FIG. 15C is a diagram (Part 3) for explaining the manufacturing steps of the semiconductor device according to the fourth embodiment. [Figure 16] FIG. 16 is a cross-sectional view of the semiconductor device according to the fifth embodiment. [Figure 17] FIG. 17 is an enlarged cross-sectional view of main parts of the semiconductor device according to the fifth embodiment. [Figure 18A]Figure 18A is a diagram illustrating the manufacturing process of a semiconductor device according to the fifth embodiment (Part 1). [Figure 18B] Figure 18B is a diagram illustrating the manufacturing process of a semiconductor device according to the fifth embodiment (part 2). [Figure 18C] Figure 18C is a diagram illustrating the manufacturing process of a semiconductor device according to the fifth embodiment (part 3).

[0011] [Detailed explanation] The semiconductor device and its manufacturing method described herein will be explained in detail below, with reference to the drawings, using a piezoelectric element as an example. It goes without saying that the semiconductor device and its manufacturing method described herein are applicable not only to piezoelectric elements but also to other types of semiconductor devices and their manufacturing methods.

[0012] The embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, components, installation locations of components, and connection configurations shown in the embodiments below are examples and are not intended to limit the scope of this disclosure. Furthermore, components in the embodiments below that are not described in the independent claim representing the highest-level concept are described as optional components. In addition, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from actual ratios. Furthermore, the embodiments and their modifications below may include similar components, and similar components are given the same reference numerals, and redundant descriptions are omitted.

[0013] [First Embodiment] (Configuration of a semiconductor device) Figure 1 is a plan view of the semiconductor device 100 according to the first embodiment, viewed from the direction normal to the top surface. The semiconductor device 100 according to the first embodiment is a piezoelectric element. Figure 2 is a cross-sectional view of the semiconductor device 100 according to the first embodiment, along the line II-II in Figure 1.

[0014] The semiconductor device 100 is a MEMS device utilizing semiconductor manufacturing technology, and is constructed by bonding the top surface 10b of a first laminate 10 including a first semiconductor substrate 11 and the bottom surface 31a of a second semiconductor substrate 31 with an adhesive layer 45. In the semiconductor device 100, the first laminate 10, on which the additional film 20 described later is laminated, constitutes a transducer, and the second semiconductor substrate 31 constitutes a subframe. For ease of understanding, the electrodes 21 placed on the main surface of the diaphragm 10d are omitted from the illustration in Figure 1.

[0015] In the following explanation, we will use the XYZ coordinate system, which is an example of a Cartesian coordinate system. Specifically, the plane parallel to the first principal surface 10h, which is the principal surface of the diaphragm 10d constituting the semiconductor device 100, will be defined as the XY plane, and the normal direction perpendicular to the XY plane will be defined as the Z direction. Furthermore, the X and Y axes will be two orthogonal directions within the XY plane.

[0016] The first laminate 10 is constructed by stacking, in order, a first semiconductor substrate 11, a first insulating layer 12, a semiconductor layer 13, a second insulating layer 14, a first metal layer 17, a piezoelectric layer 18, a second metal layer 19, a first protective layer 15, and a second protective layer 16. A first cavity 10c is formed on the bottom surface 10a of the first laminate 10, reaching the semiconductor layer 13 so that the semiconductor layer 13 forms a diaphragm 10d. On the top surface 10b of the first laminate 10, a slit 10e is formed around the diaphragm 10d, leaving a connection point 10g, and reaching the first cavity 10c so that the diaphragm 10d forms a rectangular cantilever structure in plan view. In addition, electrode pads 25 are formed at a pair of corners of the rectangular first laminate 10 that sandwich the connection point 10g of the diaphragm 10d, with the second protective layer 16 opening to connect to the first metal layer 17 and the second metal layer 19.

[0017] The diaphragm 10d is connected to a first support portion 10f formed by a semiconductor layer 13 via a connection point 10g. Viewed from the direction normal to the first main surface 10h, the connection point 10g coincides with the line segment connecting both ends of the slit 10e. Here, the direction in which the line segment of the connection point 10g extends is defined as the X direction, and the direction perpendicular to the line segment of the connection point 10g and directed from the first support portion 10f toward the diaphragm 10d is defined as the Y direction. In this embodiment, the length of the diaphragm 10d in the Y direction is L. Furthermore, the portion of the semiconductor layer 13 arranged around the diaphragm 10d excluding the connection point 10g via the slit 10e will be referred to as the peripheral member 10i.

[0018] The additional film 20 is located on the upper part of the first main surface 10h of the diaphragm 10d and on a portion of the upper part of the slit 10e. Viewed from the direction normal to the first main surface 10h, at least a portion of the outer edge of the additional film 20 is located on the slit 10e side of the boundary line between the diaphragm 10d and the slit 10e, and also on the slit 10e side of the boundary line between the peripheral member 10i and the slit 10e.

[0019] The first metal layer 17, piezoelectric layer 18, and second metal layer 19, which are laminated on the semiconductor layer 13 forming the diaphragm 10d, constitute a driving means that vibrates the diaphragm 10d according to the applied voltage.

[0020] In the first laminate 10, the first semiconductor substrate 11, the first insulating layer 12, and the semiconductor layer 13 are made of SOI wafers. Specifically, the first semiconductor substrate 11 corresponds to the support layer of the SOI wafer and is made of silicon (Si), the first insulating layer 12 corresponds to the BOX layer and is made of silicon dioxide (SiO2), and the semiconductor layer 13 corresponds to the active layer and is made of Si.

[0021] The second insulating layer 14 may consist of SiO2 and aluminum oxide (Al2O3) laminated in sequence. The first metal layer 17 may consist of titanium oxide (TiO2) and platinum (Pt) laminated in sequence. The TiO2 is interposed between the upper Pt layer and the lower second insulating layer 14 to ensure close adhesion. The piezoelectric layer 18 may consist of zinc zirconate titanate (PZT) or aluminum nitride (AlN). The second metal layer 19 may consist of iridium oxide (IrO2) and iridium (Ir) laminated in sequence. The first protective layer 15 may consist of Al2O3 and SiO2 laminated in sequence. Here, SiO2 acts as an interlayer insulating film, and Al2O3 acts as a hydrogen barrier film. The second protective layer 16 may consist of SiO2. The electrode 21 may consist of aluminum (Al) copper (Cu) alloy and titanium nitride (TiN) laminated in sequence. TiN is a barrier metal.

[0022] The additional film 20 may be composed of SiO2, silicon nitride (SiN), Al2O3, parylene, or a film. The film may contain polymers or organic materials. The film may be a photosensitive film such as a dry film resist, or it may be a non-photosensitive film. In this embodiment, an example is shown in which the additional film 20 is composed of a photosensitive film.

[0023] The second semiconductor substrate 31 has a frame-like shape surrounding the diaphragm 10d, and a second cavity 31c is formed on the upper part of the diaphragm 10d, connecting the bottom surface 31a to the top surface 31b. Notches 31f are formed at a pair of opposing corners on the outer circumference of the second semiconductor substrate 31 so as to expose the electrode pads 25 formed on the first laminate 10. The bottom surface 31a of the second semiconductor substrate 31 is bonded to the top surface 10b of the first laminate 10 by an adhesive layer 45 interposed between them. The second semiconductor substrate 31 may be made of Si.

[0024] Figure 3 is an enlarged cross-sectional view of the main part 50 near the slit 10e of the semiconductor device 100 shown in Figure 2. The same parts as in Figure 2 are denoted by the same reference numerals and their descriptions are omitted.

[0025] Here, the second insulating layer 14, first metal layer 17, piezoelectric layer 18, second metal layer 19, first protective layer 15, and second protective layer 16, which are laminated on the first main surface 10h of the diaphragm 10d, will be referred to as the first laminated film 22, and the same will apply hereafter. The additional film 20 is positioned at least on the upper surface of the first laminated film 22 and extends toward the slit 10e. In this embodiment, as shown in Figure 3, the additional film 20, which is made of film, is positioned on the upper surface of the first laminated film 22, more specifically on the upper surface of the second protective layer 16 positioned on the upper part of the diaphragm 10d, and has a shape that protrudes toward the upper part of the slit 10e in a direction parallel to the top surface of the outer edge of the second protective layer 16.

[0026] As mentioned above, in transducers with a cantilever structure, sound leakage through the slit 10e reduces sound pressure, especially in the low-frequency range, i.e., the low-frequency range. However, the minimum width of the slit 10e is determined by the lithography resolution based on the performance of the exposure equipment and resist in the manufacturing process, making it difficult to make it narrower.

[0027] As will be described later with reference to Figures 5E to 5F, in this embodiment, the additional film 20 is formed to cover the second protective layer 16 and the first groove 46, which will later become the slit 10e. The additional film 20 is then formed by removing a portion of the upper part of the first groove 46 and the portions formed on the upper parts of the peripheral member 10i and the first support portion 10f by lithography. In this lithography, the high resolution required to form a slit in the additional film 20 is not necessary; only accuracy in positioning the portion of the additional film 20 to be removed is required.

[0028] As described above, the additional film 20 is formed to cover approximately 50% of the width of the slit 10e, as shown in Figure 3. However, the proportion of the additional film 20 that covers the upper part of the slit 10e is not limited to this; it should be a proportion that protrudes above the slit 10e, substantially narrowing the slit width, and does not collide with the side of the surrounding member 10i when the diaphragm 10d vibrates. In this embodiment, the additional film 20 has a hardness such that the portion that protrudes above the slit 10e is maintained in a direction parallel to the portion formed on the upper surface of the second protective layer 16. In this embodiment, by having the additional film 20 cover approximately 50% of the width of the slit 10e, the width of the slit 10e can be substantially narrowed by approximately 50%, and sound leakage can be reduced to the same extent as when the width of the slit 10e is narrowed by approximately 50%.

[0029] Figure 4 is a cross-sectional view of the semiconductor device 100 according to the first embodiment, along the line IV-IV in Figure 1. The same reference numerals are used for parts identical to those in Figure 2, and their descriptions are omitted. In this embodiment, the width of the diaphragm 10d in the X direction is W.

[0030] As previously mentioned with reference to Figure 1, in Figure 4, peripheral members 10i are arranged on both sides of the diaphragm 10d in the X direction via slits 10e. The additional membrane 20, positioned on the upper part of the diaphragm 10d, protrudes from the top of the slits 10e so as to cover approximately 50% of the width of each slit 10e located on both sides of the diaphragm 10d in the X direction.

[0031] In addition, in the plan view of Figure 1, the diaphragm 10d and the additional membrane 20 at the corners that sandwich the free end opposite the connection point 10g of the diaphragm 10d may be formed with curves having a radius of curvature. Specifically, the radius of curvature of the corner of the diaphragm 10d, i.e., the inner diameter, and the radius of curvature of the corner of the surrounding member 10i, i.e., the outer diameter, are set so that the width of the slit 10e and the width of the portion not covered by the additional membrane 20 at the corner are the same as their respective widths at other parts of the body. This prevents the additional membrane 20 from colliding with the surrounding member 10i at the corner on the free end side of the diaphragm 10d when the diaphragm 10d vibrates.

[0032] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. First, using Figures 5A to 5F, the process of fabricating the first laminate 10, which consists of additional films 20 that will constitute the transducer, will be described.

[0033] The first semiconductor substrate 11, first insulating layer 12, and semiconductor layer 13 shown in Figure 5A are composed of an SOI wafer. Specifically, the first semiconductor substrate 11 corresponds to the support layer of the SOI wafer, the first insulating layer 12 corresponds to the BOX layer, and the semiconductor layer 13 corresponds to the active layer. A third insulating layer 27 is laminated on the bottom surface of the SOI wafer, and a second insulating layer 14, a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 are laminated in order on the top surface of the SOI wafer.

[0034] As shown in Figure 5B, unnecessary portions are removed by etching so that the first metal layer 17, piezoelectric layer 18, and second metal layer 19, which are sequentially laminated on the second insulating layer 14, are formed into the appropriate shape.

[0035] As shown in Figure 5C, the first protective layer 15 is formed to cover the second insulating layer 14, which is made up of a first metal layer 17, a piezoelectric layer 18, and a second metal layer 19 that have been processed into an appropriate shape by etching.

[0036] As shown in Figure 5D, a first opening 15a is formed in the first protective layer 15 so that electrodes can be connected to the first metal layer 17 and the second metal layer 19, respectively, thereby forming an electrode 21 and wiring (not shown) connected to the electrode 21. The electrode 21 and wiring may be laminated with aluminum (Al) copper (Cu) alloy and titanium nitride (TiN). A second opening 15c is also formed in the first protective layer 15 at the position where a slit 10e is formed in the first laminate 10. After covering the first protective layer 15 with the electrode 21 and the second opening 15c with the second protective layer 16, the second protective layer 16 covering the second opening 15c is removed by etching. Then, by etching down the second opening 15c, a first groove 46 is formed that reaches the top surface of the first semiconductor substrate 11.

[0037] As shown in Figure 5E, the first groove 46 is formed by attaching an additional film 20 to the upper surface of the second protective layer 16. In this embodiment, the additional film 20 is made of a photosensitive film, and the portion of the additional film 20 formed above the first groove 46 has a hardness such that it is maintained in a direction parallel to the portion formed on the upper surface of the second protective layer 16.

[0038] As shown in Figure 5F, the second protective layer 16 on the upper part of the peripheral member 10i and the additional film 20 placed on the second protective layer 16 on the upper part of the first groove 46, on the side of the peripheral member 10i and on the side of the first support part 10f from the center in the width direction of the first groove 46 are removed. When a negative type film is used as the additional film 20, a method can be used in which a mask material is placed on the upper surface of the part of the additional film 20 to be removed, exposed, and developed to remove the unexposed part of the additional film 20.

[0039] Here, a positive film may be used as the additional film 20, and a mask material may be placed on the upper surface of the portion of the additional film 20 that is not to be removed, and the same process may be carried out. Alternatively, if a non-photosensitive film is used as the additional film 20, a method may be used in which a mask material with a desired pattern is formed on the upper surface of the additional film 20 by lithography, and the additional film 20 is etched using the mask material as a mask to remove the unwanted portion.

[0040] As described above with reference to Figure 3, in this embodiment, the additional film 20 is processed to cover approximately 50% of the width of the first groove 46. The additional film 20 has a hardness such that the portion protruding above the first groove 46 is maintained in a direction parallel to the portion formed on the upper surface of the second protective layer 16.

[0041] As a result, a first laminate 10 with the additional film 20 is obtained. A third insulating layer 27 is further laminated on the bottom surface 10a of the first laminate 10.

[0042] Next, using Figures 5G and 5H, the process of processing the semiconductor device 100 according to the first embodiment, which includes the first laminated body 10 with the additional film 20 and the second semiconductor substrate 31, will be described. Here, the process of processing the second semiconductor substrate 31, which will constitute the subframe, will be omitted from the explanation.

[0043] As shown in Figure 5G, the first laminate 10, on which the additional film 20 shown in Figure 5F is laminated, and the second semiconductor substrate 31 are bonded together with an adhesive layer 45 in between, such that the top surface 10b of the first laminate 10 and the bottom surface 31a of the second semiconductor substrate 31 face each other.

[0044] As shown in Figure 5H, the third insulating layer 27 laminated on the bottom surface 10a of the first laminate 10 and the portion from the bottom surface of the first laminate 10 up to a predetermined height are removed by grinding and polishing so that the first laminate 10 has a predetermined thickness. After that, the portion directly below the diaphragm 10d in the first laminate 10, which has been processed to the predetermined thickness, is removed by etching to form a first cavity 10c between the bottom surface 10a of the first laminate 10 and the diaphragm 10d. At this time, the first groove 46 formed in Figure 5G penetrates to the side of the first cavity 10c, becoming a slit 10e.

[0045] In this embodiment, the additional film 20 is not affected by the manufacturing process shown in Figures 5G and 5H. Therefore, even after going through the manufacturing process shown in Figures 5G and 5H, the additional film 20 remains in a shape that covers approximately 50% of the width of the slit 10e. Thus, the semiconductor device 100 is obtained.

[0046] (Characteristics of semiconductor devices) Figure 6 shows the frequency characteristics of the sound pressure of the semiconductor device 100 according to the first embodiment. The horizontal axis in Figure 6 represents frequency, particularly the low-frequency range of approximately 10 Hz to 100 Hz, i.e., the low-frequency range. The vertical axis represents sound pressure level (SPL). In Figure 6, the sound pressure of the semiconductor device 100 according to the first embodiment is shown by a solid line. As a comparative example, the sound pressure when the additional film 20 is not placed and the slit width is varied in three ways is shown in order from narrow to wide slit widths, with a long dashed line, a dotted line, and a short dashed line.

[0047] In the semiconductor device 100, as described above with reference to Figure 3, the additional film 20 is formed to cover approximately 50% of the width of the slit 10e, thereby reducing sound leakage to the same extent as when the width of the slit 10e is narrowed by approximately 50%. As a result, as shown by the solid line in Figure 6, the decrease in sound pressure in the low-frequency range can be suppressed compared to a comparative example in which the additional film 20 is not provided.

[0048] (Effects of the first embodiment) According to the semiconductor device 100, in a piezoelectric element having a cantilever structure, the additional film 20 is formed to cover approximately 50% of the width of the slit 10e, thereby narrowing the effective width of the slit 10e by approximately 50%, and reducing sound leakage through the slit 10e. This makes it possible to suppress the decrease in sound pressure in the low-frequency range.

[0049] According to the manufacturing method of the semiconductor device 100, the width of the portion of the upper part of the slit 10e that is not covered by the additional film 20 can be set by alignment accuracy that is lower than the required accuracy of the exposure apparatus necessary to form the slit 10e. As a result, even when using the same exposure apparatus, the effective width of the slit 10e can be narrowed to reduce sound leakage and suppress the decrease in sound pressure in the low-frequency range. In other words, the manufacturing cost required to suppress the decrease in sound pressure in the low-frequency range due to sound leakage through the slit 10e can be reduced.

[0050] [Second Embodiment] (Configuration of a semiconductor device) Figure 7 is a cross-sectional view of the semiconductor device 101 according to the second embodiment, along the line corresponding to line II-II in Figure 1. The semiconductor device 101 is a piezoelectric element. The same reference numerals are used for parts identical to those in Figure 2, and their descriptions are omitted. The plan view of the semiconductor device 101, viewed from the direction normal to the top surface, is the same as the plan view of the semiconductor device 100 in Figure 1, except for the detailed position of the outer edge of the additional film 20, and therefore its description is omitted. Figure 8 is an enlarged cross-sectional view of the main part 51 near the slit 10e in Figure 7. The same reference numerals are used for parts identical to those in Figure 3, and their descriptions are omitted.

[0051] The semiconductor device 101 according to the second embodiment shown in Figures 7 and 8 differs from the semiconductor device 100 according to the first embodiment shown in Figures 2 and 3 in the following respects. In Figures 2 and 3, the portion of the additional film 20 that protrudes above the slit 10e is maintained in a direction parallel to the portion formed on the upper surface of the second protective layer 16. In contrast, in Figures 7 and 8, the portion of the additional film 20 that protrudes above the slit 10e is bent along the side surface of the slit 10e on the diaphragm 10d side and adheres to the side surfaces of the second protective layer 16, the first protective layer 15, etc., which are laminated on the upper surface of the diaphragm 10d.

[0052] In the semiconductor device 101 shown in Figures 7 and 8, the additional film 20 does not have the hardness necessary for the portion of the additional film 20 that protrudes above the slit 10e to be maintained in a direction parallel to the portion formed on the upper surface of the second protective layer 16. Therefore, the additional film 20 bends along the outer edge of the second protective layer 16 laminated on the upper surface of the diaphragm 10d due to its own weight and adheres to the side surface of the second protective layer 16, etc. After adhering to the side surface of the slit 10e, the additional film 20 has the hardness necessary to maintain its position and shape.

[0053] The length in the Z direction along which the additional film 20 adheres to the side surface of the slit 10e on the diaphragm 10d side is not limited to Figure 8, and may adhere only to the side surface of the second protective layer 16, or it may adhere to the side surfaces of the second protective layer 16, the first protective layer 15, the second insulating layer 14, and the diaphragm 10d. That is, in this embodiment, the additional film 20 is positioned on the top surface of the outer edge of the first laminated film 22, and further positioned on at least a portion of the side surface of the outer edge of the first laminated film 22. In the semiconductor device 101, the width of the upper part of the slit 10e is narrowed by a width substantially equal to the thickness of the additional film 20. This reduces the effective width of the slit 10e and reduces sound leakage through the slit 10e.

[0054] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 101 according to the second embodiment will be described. The method for manufacturing the semiconductor device 101 is the same as the method for manufacturing the semiconductor device 100 according to the first embodiment, as described above with reference to Figures 5A to 5H, except for the material of the additional film 20 used.

[0055] In the semiconductor device 101, the additional film 20 is made of a film that does not have the hardness such that the portion of the additional film 20 protruding above the slit 10e is maintained in a direction parallel to the portion deposited on the upper surface of the second protective layer 16. As a result, the portion of the additional film 20 protruding above the slit 10e bends and adheres along the side surface of the slit 10e on the diaphragm 10d side. Because the degree of freedom in the hardness of the film that can be used as the additional film 20 is increased, it is possible to reduce manufacturing costs or improve manufacturing throughput by using inexpensive, readily available, or easy-to-handle materials.

[0056] (Effects of the second embodiment) According to the semiconductor device 101, in a piezoelectric element having a cantilever structure, sound leakage through the slit 10e can be reduced by narrowing the width of the slit 10e by a width substantially equal to the thickness of the additional film 20. This makes it possible to suppress the decrease in sound pressure in the low-frequency range.

[0057] According to the manufacturing method for the semiconductor device 101, even when using the same exposure apparatus, the effective width of the slit 10e can be narrowed, thereby reducing sound leakage through the slit 10e. Furthermore, since there is greater flexibility in the hardness of the film that can be used as the additional film 20, it is possible to reduce manufacturing costs or improve manufacturing throughput by using inexpensive, readily available, or easy-to-handle materials.

[0058] [Third Embodiment] (Configuration of a semiconductor device) Figure 9 is a cross-sectional view of the semiconductor device 102 according to the third embodiment, along the line corresponding to line II-II in Figure 1. The semiconductor device 102 is a piezoelectric element. The same reference numerals are used for parts identical to those in Figure 7, and their descriptions are omitted. The plan view of the semiconductor device 102, viewed from the direction normal to the top surface, is the same as the plan view of the semiconductor device 100 in Figure 1, except for the shape of the additional film 20, and therefore its description is omitted. Figure 10 is an enlarged cross-sectional view of the main part 52 near the slit 10e in Figure 9. The same reference numerals are used for parts identical to those in Figure 8, and their descriptions are omitted.

[0059] The semiconductor device 102 according to the third embodiment shown in Figures 9 and 10 differs from the semiconductor device 101 according to the second embodiment shown in Figures 7 and 8 in the following respects. In Figures 7 and 8, the additional film 20 is a film, and the additional film 20 is formed on the side of the slit 10e on the diaphragm 10d side, starting from the top surface of the second protective layer 16 and extending to a predetermined height. In contrast, in Figures 9 and 10, the additional film 20 is SiO2, SiN, Al2O3, or parylene. The additional film 20 is formed on both the side of the slit 10e on the diaphragm 10d side and the side of the peripheral member 10i, extending from the top surface of the second protective layer 16 to the bottom surface of the diaphragm 10d.

[0060] In the semiconductor device 102, the width of the slit 10e is narrowed by the thickness of the additional film 20 formed on both sides of the slit 10e. As will be described later with reference to Figure 11A, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film deposition time or film deposition rate during the deposition of the additional film 20.

[0061] Figure 10 shows an example where the thickness of the additional film 20 formed on one side of the slit 10e is set to approximately 30% of the width of the slit 10e. Since the additional film 20 is formed on both sides of the slit 10e, the width of the hole in the slit 10e where the additional film 20 is not formed is narrowed to approximately 40% of the width of the slit 10e. However, the thickness of the additional film 20 formed on the side of the slit 10e is not limited to this; any thickness that narrows the effective width of the slit and prevents the additional film 20 on the diaphragm 10d side from colliding with the surrounding member 10i side when the diaphragm 10d vibrates is acceptable. As described above, in the semiconductor device 102, sound leakage through the slit 10e can be reduced by narrowing the effective width of the slit 10e.

[0062] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 102 according to the third embodiment will be described. Of the manufacturing methods for the semiconductor device 102, the method before forming the additional film 20 is the same as the method for manufacturing the semiconductor device 100 according to the first embodiment, as described above with reference to Figures 5A to 5D.

[0063] Figure 11A shows the manufacturing process for depositing the additional film 20 on the cross-section shown in Figure 5D. In this embodiment, examples are shown where the additional film 20 is one of SiO2, SiN, Al2O3, or parylene. When the additional film 20 is SiO2 or SiN, chemical vapor deposition (CVD) can be used as the method for depositing the additional film 20. When the additional film 20 is Al2O3, atomic layer deposition (ALD) or sputtering can be used as the method for depositing the additional film 20. When the additional film 20 is parylene, vapor deposition or CVD can be used as the method for depositing the additional film 20. Using the film deposition method described above, the additional film 20 is deposited on the top and side surfaces of the second protective layer 16 and on the side and bottom surfaces of the first groove 46, as shown in Figure 11A.

[0064] In the manufacturing process shown in Figure 11A, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film deposition time or deposition rate during the deposition of the additional film 20. This makes it possible to narrow the effective width of the slit 10e to a desired width even when using the same exposure apparatus. When ALD is used as the film deposition method for the additional film 20, the thickness of the additional film 20 formed on both sides of the slit 10e can be made uniform and precisely controlled to be the same thickness as the additional film 20 formed on the upper surface of the second protective layer 16.

[0065] As shown in Figure 11B, the first laminate 10, on which the additional film 20 shown in Figure 11A is laminated, is bonded to the second semiconductor substrate 31. Specifically, on the top surface of the first laminate 10 shown in Figure 11A, the additional film 20 formed on the top surface of the second protective layer 16 above the first support portion 10f and peripheral member 10i is removed by etching to expose the top surface of the second protective layer 16. Then, the top surface of the second protective layer 16 and the bottom surface 31a of the second semiconductor substrate 31 are bonded together with an adhesive layer 45 interposed so that they face each other.

[0066] As shown in Figure 11C, the third insulating layer 27 and the area from the bottom surface of the first laminate 10 to a predetermined height are removed by grinding and polishing so that the first laminate 10 has a predetermined thickness. Then, the portion directly below the diaphragm 10d is removed by etching to form the first cavity 10c. At this time, the first groove 46 formed in Figure 11B penetrates through to the side of the first cavity 10c, becoming a slit 10e. Thus, the semiconductor device 102 is obtained.

[0067] (Effects of the third embodiment) In semiconductor device 102, an additional film 20 is placed on both sides of the slit 10e in a piezoelectric element having a cantilever structure. According to semiconductor device 102, by narrowing the effective width of the slit 10e, sound leakage through the slit 10e can be reduced, and the decrease in sound pressure in the low-frequency range can be suppressed.

[0068] According to the manufacturing method of the semiconductor device 102, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film deposition time or deposition rate during the deposition of the additional film 20. This makes it possible to narrow the effective width of the slit 10e to a desired width even when using the same exposure apparatus. When ALD is used as the film deposition method for the additional film 20, the thickness of the additional film 20 formed on both sides of the slit 10e can be made uniform with high precision.

[0069] [Modified example of the third embodiment] (Configuration of a semiconductor device) Figure 12 is a cross-sectional view of a semiconductor device 103 according to a modified example of the third embodiment, along the line II-II in Figure 1. The semiconductor device 103 is a piezoelectric element. The same reference numerals are used for parts identical to those in Figure 9, and their descriptions are omitted. The plan view of the semiconductor device 103 as seen from the direction normal to the top surface is the same as the plan view of the semiconductor device 102, and therefore its description is omitted.

[0070] The semiconductor device 103, a modified example of the third embodiment shown in Figure 12, differs from the semiconductor device 102 of the third embodiment shown in Figure 9 in the following respects. In Figure 9, the additional film 20 formed on the top surface of the second protective layer 16 above the first support portion 10f and peripheral member 10i is removed. In contrast, in Figure 12, the additional film 20 formed on the top surface of the second protective layer 16 above the first support portion 10f and peripheral member 10i is left without etching, and the top surface of the additional film 20 and the bottom surface 31a of the second semiconductor substrate 31 are bonded together with an adhesive layer 45 in between.

[0071] Thus, the additional film 20 formed on the surface where the first laminate 10 and the second semiconductor substrate 31 are bonded together, or on the top surface of the second semiconductor substrate 31, does not need to be removed if it does not affect the manufacturing process or the assembly of the semiconductor device. By omitting the step of removing the additional film 20, manufacturing costs can be reduced.

[0072] (Effects of the modified version of the third embodiment) In semiconductor device 103, an additional film 20 is placed on both sides of the slit 10e in a piezoelectric element having a cantilever structure. According to semiconductor device 103, by narrowing the effective width of the slit 10e, sound leakage through the slit 10e can be reduced, and the decrease in sound pressure in the low-frequency range can be suppressed. According to semiconductor device 103, manufacturing costs can be reduced by omitting the step of removing the additional film 20 formed on the surface where the first laminate 10 and the second semiconductor substrate 31 are bonded together.

[0073] [Fourth Embodiment] (Configuration of a semiconductor device) Figure 13 is a cross-sectional view of the semiconductor device 104 according to the fourth embodiment, along the line corresponding to line II-II in Figure 1. The semiconductor device 104 is a piezoelectric element. The same reference numerals are used for parts identical to those in Figure 9, and their descriptions are omitted. The plan view of the semiconductor device 104, viewed from the direction normal to the top surface, is the same as the plan view of the semiconductor device 100 in Figure 1, except for the shape of the additional film 20, and therefore its description is omitted. Figure 14 is an enlarged cross-sectional view of the main part 54 near the slit 10e in Figure 13. The same reference numerals are used for parts identical to those in Figure 10, and their descriptions are omitted.

[0074] The semiconductor device 104 according to the fourth embodiment shown in Figures 13 and 14 differs from the semiconductor device 102 according to the third embodiment shown in Figures 9 and 10 in the following respects. In Figures 9 and 10, the additional film 20 is formed from the top surface of the second protective layer 16 on both sides of the slit 10e to the bottom surface of the diaphragm 10d. In contrast, in Figures 13 and 14, the additional film 20 is formed not only on both sides of the slit 10e, but also on the side of the adhesive layer 45 on the slit 10e side, and on the side and top surface of the second semiconductor substrate 31 on the second cavity 31c side. Note that, as will be described later with reference to Figure 15C, the additional film 20 on the top surface of the second semiconductor substrate 31 may be removed.

[0075] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 104 according to the fourth embodiment will be described. Of the manufacturing methods for the semiconductor device 104, the method up to forming the first laminate 10 and the first groove 46 is the same as the method for manufacturing the semiconductor device 100 according to the first embodiment described above with reference to Figures 5A to 5D.

[0076] As shown in Figure 15A, the second semiconductor substrate 31 is bonded to the structure shown in Figure 5D by interposing an adhesive layer 45 on the upper surface of the second protective layer 16 above the first support portion 10f and the peripheral member 10i.

[0077] As shown in Figure 15B, an additional film 20 is formed. The manufacturing method of the semiconductor device 104 according to this embodiment differs from the manufacturing method of the semiconductor device 102 according to the third embodiment in that the additional film 20 is formed after the first laminate 10 and the second semiconductor substrate 31 are bonded together. The material and method of forming the additional film 20 in this embodiment are the same as those used in the manufacturing method of the semiconductor device 102 according to the third embodiment described above with reference to Figure 11A, so a detailed explanation is omitted. In this embodiment as well, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film formation time or film formation rate during the formation of the additional film 20.

[0078] As shown in Figure 15C, the third insulating layer 27 and the bottom surface of the first laminate 10 are removed by grinding and polishing up to a predetermined height, and then the first cavity 10c is formed. Note that, as described above with reference to Figure 12, the additional film 20 formed on the top surface of the second semiconductor substrate 31 may be left as shown in Figure 15C if it does not affect the manufacturing process or the assembly of the semiconductor device. However, the additional film 20 on the top surface of the second semiconductor substrate 31 may also be removed from the cross-sectional view shown in Figure 15C. Thus, the semiconductor device 104 is obtained.

[0079] (Effects of the fourth embodiment) In the semiconductor device 104, an additional film 20 is placed on both sides of the slit 10e in a piezoelectric element having a cantilever structure. According to the semiconductor device 104, by narrowing the effective width of the slit 10e, sound leakage through the slit 10e can be reduced, and the decrease in sound pressure in the low-frequency range can be suppressed. According to the manufacturing method of the semiconductor device 104, the additional film 20 can be formed after bonding the first laminate 10 and the second semiconductor substrate 31, which increases the degree of freedom in the manufacturing process sequence.

[0080] [Fifth Embodiment] (Configuration of a semiconductor device) Figure 16 is a cross-sectional view of the semiconductor device 105 according to the fifth embodiment, along the line corresponding to line II-II in Figure 1. The semiconductor device 105 is a piezoelectric element. The same reference numerals are used for parts identical to those in Figure 13, and their descriptions are omitted. The plan view of the semiconductor device 105, viewed from the direction normal to the top surface, is the same as the plan view of the semiconductor device 100 in Figure 1, except for the shape of the additional film 20, and therefore its description is omitted. Figure 17 is an enlarged cross-sectional view of the main part 55 near the slit 10e in Figure 16. The same reference numerals are used for parts identical to those in Figure 10, and their descriptions are omitted.

[0081] The semiconductor device 105 according to the fifth embodiment shown in Figures 16 and 17 differs from the semiconductor device 104 according to the fourth embodiment shown in Figures 13 and 14 in the following respects. In Figures 13 and 14, the additional film 20 is formed on both sides of the slit 10e, on the side of the adhesive layer 45 on the slit 10e side, and on the side and top surface of the second semiconductor substrate 31 on the second cavity 31c side. In contrast, in Figures 16 and 17, the additional film 20 is further formed on the bottom surface of the diaphragm 10d, on the first insulating layer 12 below the first support portion 10f and peripheral member 10i, on the side of the first semiconductor substrate 11 on the first cavity 10c side, and on the bottom surface of the first semiconductor substrate 11. Note that the additional film 20 does not need to be placed on the top surface of the second semiconductor substrate 31 and the bottom surface of the first semiconductor substrate 11.

[0082] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 105 according to the fifth embodiment will be described. Of the manufacturing methods for the semiconductor device 105, the method up to forming the first laminate 10 and the first groove 46 is the same as the method for manufacturing the semiconductor device 100 according to the first embodiment, as described above with reference to Figures 5A to 5D.

[0083] As shown in Figure 18A, the second semiconductor substrate 31 is bonded to the structure shown in Figure 5D by interposing an adhesive layer 45 on the upper surface of the second protective layer 16 above the first support portion 10f and the peripheral member 10i.

[0084] As shown in Figure 18B, the third insulating layer 27 and the bottom surface of the first laminate 10 are removed by grinding and polishing up to a predetermined height, and then the first cavity 10c is formed.

[0085] As shown in Figure 18C, an additional film 20 is formed. The manufacturing method of the semiconductor device 105 according to this embodiment differs from the manufacturing method of the semiconductor device 104 according to the fourth embodiment in that the additional film 20 is formed after the first cavity 10c is formed.

[0086] The material and deposition method for the additional film 20 in this embodiment are the same as those for the manufacturing method of the semiconductor device 102 according to the third embodiment described above with reference to Figure 11A. When Al2O3 is used as the additional film 20 and ALD is used as the deposition method for the additional film 20, the additional film 20 can be formed simultaneously on the side of the slit 10e, the surface on the second cavity 31c side, and the surface on the first cavity 10c side. On the other hand, when CVD, sputtering, or evaporation is used as the deposition method for the additional film 20, since deposition is directional, the additional film 20 may be formed separately on the surface on the second cavity 31c side and the surface on the first cavity 10c side to ensure that the thickness of the additional film 20 is uniform.

[0087] In this embodiment as well, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film deposition time or deposition rate during the deposition of the additional film 20. As described above with reference to Figure 12, the additional film 20 formed on the top surface of the second semiconductor substrate 31 and the bottom surface of the first semiconductor substrate 11 does not need to be removed if it does not affect the manufacturing process or the assembly of the semiconductor device. However, the additional film 20 formed on the top surface of the second semiconductor substrate 31 and the bottom surface of the first semiconductor substrate 11 may be removed with respect to the cross-sectional view shown in Figure 18C. Thus, the semiconductor device 105 is obtained.

[0088] (Effects of the fifth embodiment) In semiconductor device 105, an additional film 20 is placed on both sides of the slit 10e in a piezoelectric element having a cantilever structure. According to semiconductor device 105, by narrowing the effective width of the slit 10e, sound leakage through the slit 10e can be reduced, and the decrease in sound pressure in the low-frequency range can be suppressed. According to the manufacturing method of semiconductor device 105, the additional film 20 can be formed after the first cavity 10c is formed, which increases the degree of freedom in the manufacturing process sequence.

[0089] [Other embodiments] While several embodiments of this disclosure have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. One or more elements of one embodiment may be combined with one or more elements of another embodiment. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications are permitted without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and in the scope of the invention and its equivalents as described in the claims.

[0090] For example, in the embodiments of this disclosure, PZT may be used as the piezoelectric layer 18 and a polymer film as the additional film 20. By laminating these materials as in the embodiments of this disclosure, not only can sound leakage through the slit 10e be reduced, but acoustic characteristics can also be improved.

[0091] (Note) The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0092] (Note 1) The semiconductor devices 100 to 105 each include a diaphragm 10d having a first main surface 10h, a first support portion 10f connected to the diaphragm 10d via a connection portion 10g, and a peripheral member 10i arranged around the diaphragm 10d excluding the connection portion 10g via a slit 10e. The semiconductor devices 100 to 105 further include a first laminated film 22 including a piezoelectric layer 18 disposed on the first main surface 10h, and an additional film 20 disposed on the upper surface of the first laminated film 22. Viewed from the direction normal to the first main surface 10h, at least a portion of the outer edge of the additional film 20 is located on the side of the slit 10e rather than the boundary line between the diaphragm 10d and the slit 10e, and is located on the side of the slit 10e rather than the boundary line between the peripheral member 10i and the slit 10e.

[0093] According to semiconductor devices 100 to 105, in a piezoelectric element having a cantilever structure, the effective width of the slit 10e can be narrowed by arranging the additional film 20, thereby reducing sound leakage through the slit 10e. This makes it possible to suppress the decrease in sound pressure in the low-frequency range.

[0094] (Note 2) In the semiconductor device 100 described in Appendix 1, the outer edge of the additional film 20 has a shape that protrudes above the slit 10e in a direction parallel to the plane forming the top surface of the outer edge of the first laminated film 22. With the semiconductor device 100, by forming the additional film 20 so as to cover the slit 10e, the effective width of the slit 10e can be narrowed, thereby reducing sound leakage through the slit 10e.

[0095] (Note 3) In the semiconductor device 101 described in Appendix 1, the additional film 20 is arranged on the top surface of the outer edge of the first laminated film 22, and is also arranged on at least a portion of the side surface of the outer edge of the first laminated film 22. According to the semiconductor device 101, sound leakage through the slit 10e can be reduced by narrowing the width of the slit 10e by a width substantially equal to the thickness of the additional film 20.

[0096] (Note 4) In semiconductor devices 102, 103, 104, and 105 described in Appendix 1, the additional film 20 is also placed on the side of the slit 10e on the diaphragm 10d side and on the side of the slit 10e on the peripheral member 10i side. According to semiconductor devices 102 to 105, by placing the additional film 20 on both sides of the slit 10e and narrowing the effective width of the slit 10e, sound leakage through the slit 10e can be reduced, and the decrease in sound pressure in the low-frequency range can be suppressed.

[0097] (Note 5) In the semiconductor device 105 described in Appendix 4, the additional film 20 is also placed on the bottom surface of the diaphragm 10d, facing in the opposite direction to the first main surface 10h.

[0098] (Note 6) In the semiconductor devices 100 to 105 described in any one of the appendices 1 to 5, the first laminated film 22 includes a structure in which metal layers 17, 19 and a piezoelectric layer 18 are laminated. This makes it possible to configure a driving means for vibrating the diaphragm 10d according to the applied voltage.

[0099] (Note 7) In the semiconductor devices 100 and 101 described in any one of the appendices 1 to 3 or 6, the additional film 20 includes a film.

[0100] (Note 8) In the semiconductor devices 102 to 105 described in any one of the appendices 1, 4 to 6, the additional film 20 contains SiO2.

[0101] (Note 9) In the semiconductor devices 102 to 105 described in any one of the appendices 1, 4 to 6, the additional film 20 contains SiN.

[0102] (Note 10) In semiconductor devices 102 to 105 described in any one of the appendices 1, 4 to 6, the additional film 20 contains Al2O3.

[0103] (Note 11) In the semiconductor devices 102 to 105 described in any one of the appendices 1, 4 to 6, the additional film 20 contains parylene.

[0104] (Note 12) In the semiconductor devices 100 to 105 described in any one of the appendices 1 to 11, the diaphragm 10d, the first support portion 10f, and the peripheral member 10i contain Si.

[0105] (Note 13) A method for manufacturing semiconductor devices 100 and 101 includes the step of forming a first laminated film 22 including a piezoelectric layer 18 on a first main surface 10h of substrates 11 to 13. The method for manufacturing semiconductor devices 100 and 101 further includes the step of forming a slit in the first laminated film 22 and the substrates 11 to 13 in a region of the first laminated film 22 that does not include the piezoelectric layer 18 when viewed from the direction normal to the first main surface 10h. The method for manufacturing semiconductor devices 100 and 101 further includes the step of forming an additional film 20 on the upper surface of the first laminated film 22 and the upper part of the slit 10e, and the step of removing a portion of the additional film 20 that is positioned on the upper part of the slit 10e. The step of removing a portion of the additional film 20 is performed such that the outer edge of the additional film 20 protrudes above the upper part of the slit 10e and a portion of the upper part of the slit 10e is exposed.

[0106] According to the manufacturing method for semiconductor devices 100 and 101, the width of the portion of the upper part of the slit 10e that is not covered by the additional film 20 can be set by alignment accuracy that is lower than the required accuracy of the exposure apparatus necessary to form the slit 10e. As a result, even when using the same exposure apparatus, the effective width of the slit 10e can be narrowed to reduce sound leakage and suppress the decrease in sound pressure in the low-frequency range.

[0107] (Note 14) In the method for manufacturing semiconductor devices 100 and 101 described in Appendix 13, the additional film 20 includes a film resist. The step of forming the additional film 20 is performed by attaching a film resist, and the step of removing a portion of the additional film 20 is performed by exposing and developing the film resist.

[0108] (Note 15) In the method for manufacturing semiconductor devices 100 and 101 described in Appendix 13, the additional film 20 includes a film. The step of forming the additional film 20 is performed by attaching a film, and the step of removing a portion of the additional film 20 is performed by etching the film using a mask placed on the upper surface of the film.

[0109] (Note 16) A method for manufacturing semiconductor devices 102 to 105 includes the step of forming a first laminated film 22 including a piezoelectric layer 18 on a first main surface 10h of substrates 11 to 13. A method for manufacturing semiconductor devices 102 to 105 further includes the step of forming a slit 10e in the first laminated film 22 and substrates 11 to 13 in a region of the first laminated film 22 that does not include the piezoelectric layer 18 when viewed from the normal direction of the first main surface 10h. A method for manufacturing semiconductor devices 102 to 105 further includes the step of forming an additional film on the upper surface of the first laminated film 22 and on the side surface of the slit 10e.

[0110] According to the manufacturing method for semiconductor devices 102 to 105, the thickness of the additional film 20 formed on both sides of the slit 10e can be controlled by the film formation time or film formation rate during the formation of the additional film 20. This makes it possible to narrow the effective width of the slit 10e to a desired width, even when using the same exposure apparatus.

[0111] (Note 17) The method for manufacturing the semiconductor device 104 described in Appendix 16 further includes the step of bonding a second substrate 31 to the upper part of the substrates 11 to 13 arranged around the slit 10e, and after bonding the second substrate 31, an additional film 20 is formed. The method for manufacturing the semiconductor device 104 allows for increased flexibility in the order of processes during manufacturing.

[0112] (Note 18) The method for manufacturing the semiconductor device 105 described in Appendix 16 further includes a step of grinding the bottom surface of the substrates 11-13 that faces in the opposite direction to the first main surface 10h. The step of forming the additional film 20 is performed after the step of grinding the bottom surface, and the additional film 20 is also formed on the bottom surface side of the substrates 11-13. According to the method for manufacturing the semiconductor device 105, the additional film 20 can be formed after the first cavity 10c is formed, which increases the degree of freedom in the order of processes in manufacturing.

[0113] (Note 19) In the method for manufacturing semiconductor devices 102 to 105 as described in any one of appendices 16 to 18, the additional film 20 comprises SiO2, SiN, or parylene, and the step of forming the additional film 20 is carried out by CVD.

[0114] (Note 20) In the method for manufacturing semiconductor devices 102 to 105 described in any one of appendices 16 to 18, the additional film 20 contains Al2O3, and the step of forming the additional film 20 is performed by ALD or sputtering. When ALD is used as the method for forming the additional film 20, the thickness of the additional film 20 formed on both sides of the slit 10e can be made uniform with high precision.

[0115] (Note 21) In the method for manufacturing semiconductor devices 102 to 105 as described in any one of appendices 16 to 18, the additional film 20 contains parylene, and the step of forming the additional film 20 is carried out by vapor deposition.

[0116] (Note 22) In the method for manufacturing semiconductor devices 101 to 105 described in any one of appendices 13 to 21, the substrates 11 to 13 include SOI substrates. [Explanation of Symbols]

[0117] 10. First layer 10c First Cavity 10d diaphragm 10e slit 10f 1st support part 10g connection point 10h Main field 1 10i Peripheral components 11. First Semiconductor Substrate 12. First insulating layer 13 Semiconductor layer 14. Second insulating layer 15 1st protective layer 16 Second protective layer 17 1st metal layer 18 Piezoelectric layer 19 Second metal layer 20 Additional film 21 electrodes 22 First layered film 25 electrode pads 27 Third insulating layer 31. Second Semiconductor Substrate 31c Second Cavity 31f Notch 45 Adhesive layer 46 First groove 100, 101, 102, 103, 104, 105 Semiconductor

Claims

1. A diaphragm having a first main surface, A first support portion connected to the diaphragm via a connection point, A peripheral member is arranged around the diaphragm, excluding the connection point, via a slit. A first laminated film including a piezoelectric layer disposed on the first main surface, An additional film disposed at least on the upper surface of the first laminated film and extending toward the slit, Equipped with, Viewed from the direction normal to the first main surface, at least a portion of the outer edge of the additional film is located on the slit side of the boundary line between the diaphragm and the slit, and is located on the slit side of the boundary line between the peripheral member and the slit. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the outer edge of the additional film has a shape that protrudes above the slit in a direction parallel to the plane forming the top surface of the outer edge of the first laminated film.

3. The semiconductor device according to claim 1, wherein the additional film is disposed on the top surface of the outer edge of the first laminated film and is also disposed on at least a portion of the side surface of the outer edge of the first laminated film.

4. The semiconductor device according to claim 1, wherein the additional film is further disposed on the side surface of the slit on the diaphragm side and on the side surface of the slit on the peripheral member side.

5. The additional film is also positioned on the bottom surface of the diaphragm, facing in the opposite direction to the first main surface. The semiconductor device according to claim 4.

6. The semiconductor device according to claim 1, wherein the first laminated film includes a structure in which a metal layer and a piezoelectric layer are laminated.

7. The semiconductor device according to claim 1, wherein the additional film includes a film.

8. The additional film is SiO ２ A semiconductor device according to claim 1, including the above.

9. The semiconductor device according to claim 1, wherein the additional film contains SiN.

10. The additional film is Al ２ O ３ A semiconductor device according to claim 1, including the above.

11. The semiconductor device according to claim 1, wherein the additional film contains parylene.

12. The semiconductor device according to claim 1, wherein the diaphragm, the first support portion, and the peripheral member contain Si.

13. A step of forming a first laminated film including a piezoelectric layer on the first main surface of a substrate, A step of forming a slit in the first laminated film and the substrate in a region of the first laminated film that does not include the piezoelectric layer when viewed from the direction normal to the first main surface, A step of forming an additional film on the upper surface of the first laminated film and the upper part of the slit, A step of removing a portion of the additional film positioned above the slit, Includes, The step of removing a portion of the additional film is performed such that the outer edge of the additional film protrudes above the slit and a portion of the upper part of the slit is exposed. A method for manufacturing a semiconductor device.

14. The additional film includes a film resist. The step of forming the additional film is carried out by attaching a film resist. The step of removing a portion of the additional film is performed by exposing and developing the film resist. The method for manufacturing a semiconductor device according to claim 13.

15. A step of forming a first laminated film including a piezoelectric layer on the first main surface of a substrate, A step of forming a slit in the first laminated film and the substrate in a region of the first laminated film that does not include the piezoelectric layer when viewed from the direction normal to the first main surface, A step of forming an additional film on the upper surface of the first laminated film and on the side surface of the slit, including, A method for manufacturing a semiconductor device.

16. The process further includes grinding the bottom surface of the substrate that faces in the opposite direction to the first main surface, The step of forming the additional film is performed after the step of grinding the bottom surface, and the additional film is also formed on the bottom surface side of the substrate. The method for manufacturing a semiconductor device according to claim 15.

17. The aforementioned additional film is SiO ２ Contains either SiN or parylene, The step of forming the additional film is carried out by CVD. The method for manufacturing a semiconductor device according to claim 15.

18. The aforementioned additional film is Al ２ O ３ Includes, The step of forming the additional film is carried out by ALD or sputtering. The method for manufacturing a semiconductor device according to claim 15.

19. The additional film contains parylene, The step of forming the additional film is carried out by vapor deposition. The method for manufacturing a semiconductor device according to claim 15.

20. The method for manufacturing a semiconductor device according to claim 13 or 15, wherein the substrate includes an SOI substrate.

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