Insulated gate semiconductor device

Abstract

The present invention provides an insulated gate semiconductor device that can reduce on-resistance. [Solution] The insulated gate semiconductor device comprises a drift layer of a first conductivity type, a base region of a second conductivity type provided on the upper surface side of the drift layer, a main region 6 of the first conductivity type provided on the upper surface side of the base region, and a gate electrode 10 embedded in a trench 8 dug downward from the upper surface of the main region 6 via a gate insulating film 9. Multiple mesa portions 15 sandwiched between adjacent trenches 8 are arranged in a matrix, and the width W1 of each of the multiple mesa portions 15 in at least one direction is 600 nm or less.

Description

Technical Field

[0001] The present disclosure relates to an insulated gate semiconductor device.

Background Art

[0002] Patent Document 1 discloses a silicon carbide MOSFET (SiC-MOSFET) including a matrix-type cell structure in which rectangles are two-dimensionally arranged and a Fin Field Effect Transistor (FinFET) structure. Patent Document 2 discloses a SiC-MOSFET including a matrix-type cell structure. Non-Patent Document 1 discloses a SiC-MOSFET with a FinFET structure.

Prior Art Literature

Patent Literature

[0003]

Patent Document 1

Patent Document 2

Non-Patent Literature

[0004]

Non-Patent Document 1

Summary of Invention

Problem to be Solved by the Invention

[0005] In insulated gate semiconductor devices, there is a demand for reducing on-resistance.

[0006] An object of the present disclosure is to provide an insulated gate semiconductor device capable of reducing on-resistance. [Means for solving the problem]

[0007] To achieve the above objective, one aspect of the present disclosure is an insulated gate semiconductor device comprising: a drift layer of a first conductivity type; a base region of a second conductivity type provided on the upper surface side of the drift layer; a main region of the first conductivity type provided on the upper surface side of the base region; and a gate electrode embedded in a trench dug downward from the upper surface of the main region via a gate insulating film, wherein a plurality of mesa portions sandwiched between adjacent trenches are arranged in a matrix, and the width of each of the plurality of mesa portions in at least one direction is 0.6 μm or less. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide an insulated gate semiconductor device that can reduce on-resistance. [Brief explanation of the drawing]

[0009] [Figure 1] This is a vertical cross-sectional view of an insulated gate type semiconductor device according to the first embodiment. [Figure 2] This is a horizontal cross-sectional view taken from direction aa in Figure 1. [Figure 3] This is a cross-sectional view taken perpendicular to line BB' in Figure 2. [Figure 4] This is a schematic diagram of a hexagonal crystal. [Figure 5] This is a schematic diagram illustrating the side orientation of the trench. [Figure 6] This is a schematic diagram illustrating the side orientation of the trench. [Figure 7] This graph shows the relationship between the surface orientation of the trench side, the gate voltage, and the mobility. [Figure 8] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to a comparative example. [Figure 9] This graph shows the relationship between fin width and channel resistance. [Figure 10]This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the second embodiment. [Figure 11] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the third embodiment. [Figure 12] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the fourth embodiment. [Figure 13] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the fifth embodiment. [Figure 14] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the sixth embodiment. [Figure 15] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the seventh embodiment. [Figure 16] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the eighth embodiment. [Figure 17] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the ninth embodiment. [Figure 18] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the tenth embodiment. [Figure 19] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the 11th embodiment. [Figure 20] This is a horizontal cross-sectional view of an insulated gate type semiconductor device according to the 12th embodiment. [Modes for carrying out the invention]

[0010] The first to twelfth embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to twelfth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below.

[0011] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0013] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without "+" and "-" markings. However, even if two semiconductor regions are marked with the same "n," this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0014] Furthermore, in the following explanation, "identical" impurity concentration, width, depth, or thickness, etc., includes not only cases where they are strictly identical, but also tolerances due to process variations, etc., that can be considered substantially identical. The tolerance range is, for example, ±10% compared to the case where they are strictly identical.

[0015] In addition, in the following description, the "-" in the notation of Miller indices means a bar attached to the index immediately after it, and adding "-" before an index represents a negative index.

[0016] (First Embodiment) An example is described where the insulated gate semiconductor device according to the first embodiment is a trench gate structure vertical MOSFET made of silicon carbide (SiC) (SiC-MOSFET). An example is described where the SiC is hexagonal crystal structure SiC (4H-SiC). Although FIG. 1 illustrates three unit cells C of the insulated gate semiconductor device according to the first embodiment, a larger number of unit cells C may be further arranged in parallel to form a multi-channel structure.

[0017] As shown in FIG. 1, the insulated gate semiconductor device according to the first embodiment has a first conductivity type (n - -type) drift layer 2 which is a semiconductor region made of SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less approximately.

[0018] On the upper surface side of the drift layer 2, a current spreading layer (CSL) 3, which is a semiconductor region made of first conductivity type (n-type) SiC having a higher impurity concentration than the drift layer 2, is provided. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less approximately. Note that the current spreading layer 3 is not necessarily required to be provided.

[0019] In each of the unit cells C, a base region 5, which is a semiconductor region made of second conductivity type (p-type) SiC, is provided on the upper surface side of the current spreading layer 3. The impurity concentration of the base region 5 is, for example, 1×10 17 cm -3 or more and 1×10 18 cm -3The extent is as follows. Note that if the current diffusion layer 3 is not provided, the lower surface of the base region 5 may be in contact with the upper surface of the drift layer 2.

[0020] In each unit cell C, the upper surface of the base region 5 has a first conductivity type (n) with a higher impurity concentration than the drift layer 2. + A first main region (source region) 6, which is a semiconductor region made of SiC of type 6, is provided. The impurity concentration of the source region 6 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 5 x 10 18 cm -3 It is approximately as follows.

[0021] At the boundary between adjacent unit cells C, a trench 8 is provided, which is excavated downward (in the depth direction) from the upper surface of the source region 6 and penetrates both the source region 6 and the base region 5. The lower surface of the trench 8 reaches the current diffusion layer 3. The sides (side walls) of the trench 8 are in contact with the source region 6, the base region 5, and the current diffusion layer 3. If the current diffusion layer 3 is not provided, the lower surface of the trench 8 reaches the drift layer 2, and the sides of the trench 8 are in contact with the source region 6, the base region 5, and the drift layer 2.

[0022] The depth of the trench 8 is, for example, 0.7 m or more and 1.3 μm or less, and may be, for example, about 1 μm. Figure 1 illustrates the case where the side surface of the trench 8 is a vertical plane, but the side surface of the trench 8 may have a trapezoidal or inverted trapezoidal tapered cross-section, or it may be a curved surface that is convex outward. Also, Figure 1 illustrates the case where the bottom surface of the trench 8 is a plane, but the bottom surface of the trench 8 may be a curved surface that is convex downward. Furthermore, the corner formed by the bottom surface and the side surface of the trench 8 may have curvature.

[0023] The insulated gate semiconductor device according to the first embodiment includes a mesa portion 15 in each unit cell C, which is a semiconductor region partitioned by adjacent trenches 8. The side surface of the mesa portion 15 corresponds to the side surface of the trenches 8. The mesa portion 15 includes the source region 6, the base region 5, and the upper part of the current diffusion layer 3. The upper part of the current diffusion layer 3 is the portion of the current diffusion layer 3 sandwiched between adjacent trenches 8. If the current diffusion layer 3 is not provided, the mesa portion 15 includes the source region 6, the base region 5, and the upper part of the drift layer 2. The upper part of the drift layer 2 is the portion of the drift layer 2 sandwiched between adjacent trenches 8.

[0024] The width W1 of the mesa portion 15 corresponds to the spacing between adjacent trenches 8. The width W1 of the mesa portion 15 may be narrower than the width W2 of the trench 8, the same as the width W2 of the trench 8, or wider than the width W2 of the trench 8. The width W2 of the trench 8 is, for example, about 200 nm or more and 1 μm or less. The width W1 of the mesa portion 15 is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 of the mesa portion 15 may be, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0025] A gate insulating film 9 is provided along the lower surface and sides of the trench 8. A gate electrode 10 is embedded inside the trench 8 via the gate insulating film 9. The gate insulating film 9 and the gate electrode 10 constitute a trench gate type insulated gate electrode structure (9,10).

[0026] The thickness of the gate insulating film 9 is, for example, approximately 30 nm or more and 100 nm or less. As the gate insulating film 9, a single layer film of any one of the following can be used: silicon oxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these. As the material for the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities added, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0027] Figure 2 shows a horizontal cross-section viewed from direction aa in Figure 1. The vertical cross-section viewed from the bottom to the top of Figure 2 along line AA' in Figure 2 corresponds to Figure 1. As shown in Figure 2, the unit cell C has a rectangular planar pattern. The trench 8 has a grid-like (mesh-like) planar pattern. The trench 8 includes a plurality of first straight sections (first stripe sections) extending parallel to each other in a first direction (left-right direction in Figure 2), which is one direction, and a plurality of second straight sections (second stripe sections) extending parallel to each other in a second direction (up-down direction in Figure 2), which is perpendicular to the first direction, and intersecting the plurality of first straight sections.

[0028] As shown in Figure 2, the mesa portion 15 is arranged in a matrix (matrix-like) pattern along a first direction (left-right direction in Figure 2) and a second direction (up-down direction in Figure 2). In this example, the entire active region is shown to have the same pattern, but this configuration is not essential. The mesa portion 15 may include portions with different patterns, as long as it is arranged along the first and second directions. The gate insulating film 9 has a frame-shaped planar pattern surrounding the mesa portion 15. The gate electrode 10 is embedded in the trench 8 via the gate insulating film 9. The gate electrode 10 has a grid-like (mesh-like) planar pattern similar to that of the trench 8. The corners formed by the sides of the trench 8 may have curvature. The sides of the trench 8 may be curved surfaces that are convex outwards.

[0029] The width of the mesa portion 15 in at least one direction is 600 nm or less. The width of the mesa portion 15 in one direction may be narrower than the width of the trench 8 in one direction. The planar pattern of the mesa portion 15 may be a polygon, circle, or ellipse. Polygons include, for example, rectangles (squares) such as squares or rectangles, triangles, pentagons, hexagons, and octagons. The corners of the polygon may be rounded to have curvature. If the mesa portion 15 has a polygonal planar pattern, one of the sides of the mesa portion 15 may be an m-face or an a-face.

[0030] In the insulated gate type semiconductor device according to the first embodiment, an example is given where the mesa portion 15 has a rectangular square planar pattern and a rectangular prism shape. Since the mesa portion 15 has a square planar pattern, the width W3 of the mesa portion 15 in the second direction (up and down direction in Figure 2) is the same as the width W1 of the mesa portion 15 in the first direction. If the mesa portion 15 has a rectangular planar pattern, the width W3 of the mesa portion 15 in the second direction (up and down direction in Figure 2) may be wider than or narrower than the width W1 of the mesa portion 15 in the first direction. The width W4 of the trench 8 between adjacent mesa portions 15 in the second direction (up and down direction in Figure 2) may be the same as the width W2 of the trench 8 between adjacent mesa portions 15 in the first direction (left and right direction in Figure 2), may be narrower than or wider than the width W2.

[0031] The mesa portion 15 has two source regions 6 located at both ends in the second direction (up and down direction in Figure 2) within the planar pattern, and a second conductive type (p) located between the two source regions 6 and in contact with the two source regions 6. + It includes a base contact region 7 which is a semiconductor region made of SiC (type). In the second direction (up and down direction in Figure 2), the widths W11 and W13 of the source region 6 and the width W12 of the base contact region 7 may be the same or different from each other. The base region 5 hidden beneath the two source regions 6 and base contact region 7 has a square planar pattern which is a rectangle similar to the mesa portion 15.

[0032] Figure 3 shows a vertical cross-section of Figure 2, viewed from the bottom to the top along the BB line in Figure 2. As shown in Figure 3, in each unit cell C, the base contact region 7 is located on the upper side of the base region 5. The depth of the base contact region 7 may be the same as the depth of the source region 6 shown in Figure 1, or it may be deeper or shallower than the depth of the source region 6. The lower surface of the base contact region 7 is in contact with the upper surface of the base region 5. The side surface of the base contact region 7 is in contact with the trench 8. The impurity concentration of the base contact region 7 is higher than the impurity concentration of the base region 5. The impurity concentration of the base contact region 7 is, for example, 5 × 10⁻⁶. 19 cm -3 The above 5 x 10 20 cm -3 It is approximately as follows.

[0033] In the cross-section shown in Figure 3, the mesa portion 15 includes the base contact region 7, the base region 5, and the upper part of the current diffusion layer 3. If the current diffusion layer 3 is not provided, the mesa portion 15 includes the base contact region 7, the base region 5, and the upper part of the drift layer 2.

[0034] Here, we will explain the plane orientation used for the side surface of the mesa portion 15. Figure 4 shows a schematic diagram of a hexagonal crystal. A hexagonal crystal is represented by coordinate axes consisting of a1, a2, and a3 axes that intersect each other at 120°, and a c axis that passes through the intersection of the a1, a2, and a3 axes and is perpendicular to the a1, a2, and a3 axes. The six side surfaces of the hexagonal crystal parallel to the c axis are the m planes. The planes of the hexagonal crystal parallel to the a1, a2, and a3 axes and perpendicular to the c axis are the c planes. The planes of the hexagonal crystal parallel to the c axis and perpendicular to the a1 axis are the a planes.

[0035] The semiconductor substrate used in the insulated gate type semiconductor device according to the first embodiment is, as shown in Figure 5, for example, <0001> The semiconductor substrate has an off-angle θ1 of approximately 4° to 8° in the <11-20> direction with respect to the (c-axis) direction. In Figure 5, the semiconductor substrate is shown as a rectangular parallelepiped, and the multiple straight lines L1 shown as solid lines on the side surface schematically represent the Si plane. Consider providing a trench T1 and a trench T2 perpendicular to trench T1 on this semiconductor substrate. The side surfaces S1 and S2 of trench T1 use the m plane, which is the (1-100) plane perpendicular to the (0001) plane. The side surfaces S1 and S2 of trench T1 are formed in a tapered shape, and both side surfaces S1 and S2 of trench T1 are m planes inclined at approximately 9° toward the Si plane.

[0036] Figure 6 shows the case where a trench T2 is provided in a semiconductor substrate. As shown in Figure 6, both opposing sides S3 and S4 of the trench T2 use the (11-20) plane, which is the a-plane. In Figure 6, dashed lines L2 and L3 parallel to the a-plane are schematically shown. In this case, because the semiconductor substrate has an off-angle θ1, the inclination angle θ2 of one side S3 of the trench T2 with respect to the a-plane is different from the inclination angle θ3 of the other side S4 with respect to the a-plane. For example, if the off-angle θ1 is 4° and the taper angle of the side of the trench T2 is 9°, then the inclination angle θ2 of the side S3 of the trench T2 on the Si-plane side with respect to the a-plane is 5°, and the inclination angle θ4 of the side S4 of the trench T2 on the Si-plane side with respect to the a-plane is 13°.

[0037] Figure 7 shows the relationship between gate voltage and electron mobility for the m-plane tilted 9° towards the Si-plane, the a-plane tilted 5° towards the Si-plane, and the a-plane tilted 13° towards the Si-plane. From Figure 7, the electron mobility is highest for the a-plane tilted 5° towards the Si-plane, followed by the m-plane tilted 9° towards the Si-plane, and then the a-plane tilted 13° towards the Si-plane. That is, if the a-plane is used as the opposing sides S3 and S4 of the trench T2, the electron mobility of one side S3 is higher than that of the other side S4.

[0038] Any of the four sides perpendicular to the four sides of the square formed by the planar pattern of the mesa portion 15 shown in Figure 2 may be either the m-plane or the a-plane. For example, the side that touches the two sides parallel to the first direction (left-right direction in Figure 2) of the mesa portion 15 may be the m-plane, and the side that touches the two sides parallel to the second direction (up-down direction in Figure 2) of the mesa portion 15 may be the a-plane. That is, by making the side composed only of the source region 6 the m-plane, and the side composed of the source region 6 and the base contact region 7 the a-plane, the base contact region 7 may touch the a-plane.

[0039] As shown in Figures 1 and 3, the interior of the current diffusion layer 3 contains a second conductivity type (p + A gate bottom protection region 4, which is a semiconductor region made of SiC (type), is provided. The gate bottom protection region 4 has the function of mitigating the electric field applied to the gate insulating film 9 on the lower surface of the trench 8. The impurity concentration of the gate bottom protection region 4 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 The extent is as follows: In Figures 1 and 3, the gate bottom protection area 4 may be electrically connected to the base area 5 on the front or back side.

[0040] Figures 1 and 3 illustrate the case where the gate bottom protection area 4 is in contact with the lower surface of the trench 8, but the gate bottom protection area 4 may be separated from the lower surface of the trench 8. Figures 1 and 3 illustrate the case where the width of the gate bottom protection area 4 is the same as the width W2 of the trench 8, but the width of the gate bottom protection area 4 may be narrower or wider than the width W2 of the trench 8. If the current diffusion layer 3 is not provided, the gate bottom protection area 4 may be provided inside the drift layer 2. The gate bottom protection area 4 is not necessarily provided.

[0041] An insulating film 11, which is an interlayer insulating film, is provided on the upper surface of the gate electrode 10. As the insulating film 11, for example, a single layer of a silicon oxide film (SiO2 film) free of impurities, referred to as an "NSG film," a silicon oxide film with phosphorus added (PSG film), a silicon oxide film with boron added (BSG film), a silicon oxide film with phosphorus and boron added (BPSG film), or a silicon nitride film (Si3N4 film) can be used, or a composite film made by selecting and combining several of these.

[0042] The insulating film 11 is provided with an opening (contact hole) 11a that exposes at least a portion of the upper surface of the source region 6 and the base contact region 7. A contact electrode 12 is embedded inside the contact hole 11a. The contact electrode 12 makes low-resistance ohmic contact with the source region 6 and the base contact region 7.

[0043] The contact electrode 12 has a barrier metal layer 12a that is in direct contact with the upper surfaces of the source region 6 and the base contact region 7, and a plug layer 12b whose lower surface is in contact with the upper surface of the barrier metal layer 12a. The barrier metal layer 12a is made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminated structure with Ti as the lower layer. The barrier metal layer 12a may cover the insulating film 11. Between the source region 6 and the base contact region 7 and the barrier metal layer 12a, nickel silicide (NiSi) is used for ohmic contact. xA silicide layer consisting of the following may be provided. The plug layer 12b is made of a metal such as tungsten (W).

[0044] A first main electrode (source electrode) 13 is provided so as to cover the upper surface of the insulating film 11 and the contact electrode 12. The source electrode 13 is provided separately from the gate wiring layer (not shown) which is electrically connected to the gate electrode 10. The source electrode 13 is made of a metal such as aluminum (Al) or copper (Cu), or an alloy such as aluminum-silicon (Al-Si) or aluminum-copper (Al-Cu).

[0045] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A second main region (drain region) 1, which is a semiconductor region made of SiC (type), is provided. Drain region 1 is made of a semiconductor substrate (SiC substrate), for example, made of SiC. The impurity concentration of drain region 1 is, for example, 1 × 10⁻⁶. 19 cm -3 The above is 3 x 10 20 cm -3 The extent is as follows. Furthermore, a buffer layer, dislocation conversion layer, or recombination promotion layer, etc., which is an n-type semiconductor region with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0046] A second main electrode (drain electrode) 14 is provided on the lower side of the drain region 1. For the drain electrode 14, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Between the drain region 1 and the drain electrode 14, nickel silicide (NiSi) is provided for ohmic contact. x A silicide layer consisting of the following may be provided.

[0047] During the switching operation of the insulated-gate semiconductor device according to the first embodiment, the source electrode 13 is set to ground potential, a positive voltage is applied to the drain electrode 14, and a positive voltage above a threshold is applied to the gate electrode 10. As a result, an inversion layer (channel) is formed in the portion of each base region 5 of the unit cell C that is in contact with the gate insulating film 9, and the vertical MOSFET turns on. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, the drift layer 2, the inversion layer of the base region 5, and the source region 6. On the other hand, if the voltage applied to the gate electrode 10 is below the threshold, an inversion layer is not formed in the portion of the base region 5 that is in contact with the gate insulating film 9, so the vertical MOSFET turns off, and no current flows from the drain electrode 14 to the source electrode 13.

[0048] In the insulated-gate semiconductor device according to the first embodiment, the vertical MOSFET has a FinFET structure. A FinFET structure is a so-called double-gate structure in which the width W1 of the mesa portion 15 sandwiched between adjacent trenches 8 is narrowed by a predetermined width, and an inversion layer (channel) is formed in the base region 5 sandwiched between adjacent trenches 8. In a FinFET structure, when a gate voltage above a threshold is applied to the gate electrode 10, the voltage from both of the pair (two) gate electrodes 10 that sandwich the base region 5 is applied to the entire base region 5.

[0049] Here, if the width of the mesa portion 15 is 600 nm or less, an inversion layer is formed in each unit cell C in a region (bulk region) away from the interface between the base region 5 and the gate insulating film 9 (this effect is also called the "FinFET effect"). As a result, electrons moving within the inversion layer are less affected by the interface state density at the interface between the gate insulating film 9 and the base region 5, increasing electron mobility and reducing on-resistance. In particular, since SiC is a compound, its interface state density is about an order of magnitude higher than that of Si, and electron mobility is easily affected by the interface state density, the FinFET effect is especially effective for insulated gate semiconductor devices using SiC. The narrower the width of the mesa portion 15, the greater the FinFET effect. The lower limit of the width of the mesa portion 15 is, for example, about 50 nm, but it is not particularly limited.

[0050] Here, an insulated gate semiconductor device according to a comparative example will be described. Figure 8 shows a horizontal cross-section of the insulated gate semiconductor device according to the comparative example, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 8, the insulated gate semiconductor device according to the comparative example has a linear (stripe-shaped) planar pattern in which the trenches 8 extend parallel to each other in one direction (up and down direction in Figure 8). The mesa portion 15x has a linear (stripe-shaped) planar pattern that extends parallel to the extension direction of the trenches 8. In the mesa portion 15x, in the extension direction of the trenches 8, n + Source area 6 and p of type + The base contact regions 7 of the type are arranged alternately and periodically.

[0051] In the comparative example of an insulated gate semiconductor device, the mesa portion 15x has a linear (striped) planar pattern. Therefore, even if the width of the mesa portion 15x is narrowed in the direction perpendicular to the extension direction of the trench 8 (left-right direction in Figure 8), the FinFET effect can only be obtained on a pair of sides of the mesa portion 15x in the direction perpendicular to the extension direction of the trench 8. In contrast, according to the insulated gate semiconductor device of the first embodiment, as shown in Figure 2, the mesa portions 15 are arranged in a matrix, and the widths W1 and W2 of the rectangles formed by the planar patterns of the mesa portions 15 are narrowed to 600 nm or less. As a result, the FinFET effect can be obtained on the sides of the rectangles of the mesa portion 15 that are in contact with each side, thereby reducing the on-resistance.

[0052] Figure 9 is a graph of simulation results showing the relationship between mesa width (FIN width) and channel resistance (R_Ch) when the trenches have a linear (striped) planar pattern, similar to the insulated gate semiconductor device in the comparative example. The horizontal axis of Figure 9 is the mesa width (FIN width), and the vertical axis is the channel resistance (R_Ch). In Figure 9, the straight line fitted to the plot is shown as a dashed line. As shown in Figure 9, as the mesa width (FIN width) is narrowed to just under 200 nm, the channel resistance decreases monotonically due to the increase in channel density. However, when the mesa width (FIN width) is 200 nm or less, the channel resistance is significantly reduced due to the FinFET effect.

[0053] Furthermore, when the mesa portions are arranged in a matrix, the direction in which the FinFET effect can be obtained on the side surface of the mesa portions increases, so if the mesa width (FIN width) is 600 nm or less, the FinFET effect can be obtained. Also, when the mesa portions are arranged in a matrix and the mesa portions have a rectangular planar pattern, if the mesa width (FIN width) is 400 nm or less, the FinFET effect is easily obtained. Also, when the mesa portions are arranged in a matrix and the mesa portions have a hexagonal, circular, or elliptical planar pattern, if the mesa width (FIN width) is 600 nm or less, the FinFET effect is easily obtained.

[0054] (Second Embodiment) Figure 10 shows a horizontal cross-section of the insulated gate semiconductor device according to the second embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 10, the configuration of the matrix-likely arranged mesa portions 15 in the insulated gate semiconductor device according to the second embodiment differs from that of the insulated gate semiconductor device according to the first embodiment shown in Figure 2.

[0055] In the insulated gate semiconductor device according to the second embodiment, the mesa portion 15 has a rectangular planar pattern and a rectangular prism shape. The mesa portion 15 has a first direction (left-right direction in Figure 10) as its short side and a second direction (up-down direction in Figure 10) perpendicular to the first direction as its long side. The width W1 of the mesa portion 15 in the short side is narrower than the width W3 of the mesa portion 15 in the long side.

[0056] The width W1 in the short direction of the mesa portion 15 is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portion 15 is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0057] The longitudinal width W3 of the mesa portion 15 is, for example, about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the longitudinal width W3 of the mesa portion 15 is, for example, about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0058] The mesa portion 15 is located within the planar pattern and has two n provided on both ends in the longitudinal direction of the mesa portion 15. + A source region 6 of type and a p provided between the two source regions 6 and adjacent to the two source regions 6 + The base contact region 7 of the type is included. In the longitudinal direction of the mesa portion 15, the widths W11 and W13 of the source region 6 and the width W12 of the base contact region 7 may be the same as or different from each other.

[0059] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa portion 15 may be either the m-face or the a-face. For example, the side touching the two sides (long sides) parallel to the longitudinal direction of the mesa portion 15 may be the m-face, and the side touching the two sides (short sides) parallel to the short direction of the mesa portion 15 may be the a-face.

[0060] Other configurations of the insulated gate semiconductor device according to the second embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0061] According to the insulated gate semiconductor device of the second embodiment, the mesa portions 15 are arranged in a matrix, and the width W1 in the short-side direction of the rectangle formed by the planar pattern of the mesa portions 15 is narrowed to 600 nm or less. As a result, the FinFET effect can be obtained on the side surface of the mesa portions 15, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long-side direction of the rectangle formed by the planar pattern of the mesa portions 15 to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be reduced even further.

[0062] (Third embodiment) Figure 11 shows a horizontal cross-section of the insulated gate semiconductor device according to the third embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 11, the insulated gate semiconductor device according to the third embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 2 in the configuration of the mesa portions 15 arranged in a matrix (honeycomb) shape.

[0063] In the insulated gate semiconductor device according to the third embodiment, the mesa portion 15 has a polygonal hexagonal planar pattern and has a hexagonal prism shape. Figure 11 illustrates the case where the hexagon formed by the planar pattern of the mesa portion 15 is a regular hexagon, but it may also be a flattened hexagon other than a regular hexagon. The width W5 of two opposing sides of the mesa portion 15 may be wider than the width W6 of the trench 8, the same as the width W6 of the trench 8, or narrower than the width W6 of the trench 8. In addition, each side surface of the hexagonal prism may be a curved surface that is convex outward. In addition, the corners where the sides of the hexagonal prism meet may have curvature.

[0064] The width W5 of the mesa portion 15 is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W5 of the mesa portion 15 may be, for example, 50 nm or more and 600 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less.

[0065] Any of the six faces perpendicular to each side of the hexagon formed by the planar pattern of the mesa portion 15 may be an m-face or an a-face. For example, all six faces perpendicular to each side of the hexagon formed by the planar pattern of the mesa portion 15 may be m-faces.

[0066] The mesa portion 15 is located within the planar pattern, p + A base contact region 7 of type n is provided to surround the base contact region 7. + It includes a source region 6 of the type. The base contact region 7 has a hexagonal planar pattern. The source region 6 is annular (frame-shaped) and has a hexagonal planar pattern on its inner and outer circumferences.

[0067] Other configurations of the insulated gate semiconductor device according to the third embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0068] According to the insulated gate semiconductor device of the third embodiment, the mesa portions 15 are arranged in a matrix, and the width W5 between any two opposing sides of the hexagon formed by the planar pattern of the mesa portions 15 is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the side surface of the mesa portions 15, thereby reducing the on-resistance.

[0069] (Fourth Embodiment) Figure 12 shows a horizontal cross-section of the insulated gate semiconductor device according to the fourth embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 12, the insulated gate semiconductor device according to the fourth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 2 in the configuration of the mesa portions 15a and 15b arranged in a matrix (honeycomb) shape.

[0070] The insulated gate semiconductor device according to the fourth embodiment has two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + It includes a source region 6 of the type. The mesa portion 15b is located inside the planar pattern, p + It includes a base contact region 7 of the type. Mesa portions 15a and 15b are provided adjacent to each other. In this example, six mesa portions 15a are provided so as to surround one mesa portion 15b.

[0071] Mesa sections 15a and 15b have the same external shape. Mesa sections 15a and 15b have a hexagonal planar pattern, which is a polygon. The width W5 of two opposing sides of mesa sections 15a and 15b may be wider than the width W6 of trench 8, the same as the width W6 of trench 8, or narrower than the width W6 of trench 8.

[0072] The width W5 of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W5 of the mesa portions 15a and 15b may be, for example, 50 nm or more and 600 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less.

[0073] Any of the six faces perpendicular to each side of the hexagon formed by the planar patterns of the mesa sections 15a and 15b may be either an m-face or an a-face. For example, all six faces perpendicular to each side of the hexagon formed by the planar patterns of the mesa sections 15a and 15b may be m-faces.

[0074] Other configurations of the insulated gate semiconductor device according to the fourth embodiment are substantially the same as those of the insulated gate semiconductor device according to the third embodiment, so redundant explanations will be omitted.

[0075] According to the insulated gate semiconductor device of the fourth embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W5 between any two opposing sides of the hexagon formed by the planar pattern of the mesa portions 15a and 15b is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance.

[0076] (Fifth embodiment) Figure 13 shows a horizontal cross-section of the insulated gate semiconductor device according to the fifth embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 13, the configuration of the mesa portions 15 arranged in a matrix (honeycomb) pattern in the insulated gate semiconductor device according to the fifth embodiment differs from that of the insulated gate semiconductor device according to the first embodiment shown in Figure 2.

[0077] In the insulated gate semiconductor device according to the fifth embodiment, the mesa portion 15 has a circular planar pattern and a cylindrical three-dimensional shape. The width W5, which is the diameter of the mesa portion 15, may be wider than the width W6 of the trench 8, may be the same as the width W6 of the trench 8, or may be narrower than the width W6 of the trench 8.

[0078] The width W5 of the mesa portion 15 is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W5 of the mesa portion 15 may be, for example, 50 nm or more and 600 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less.

[0079] The mesa portion 15 is located within the planar pattern, p + A base contact region 7 of type n is provided to surround the base contact region 7. + It includes a source region 6 of the type. The base contact region 7 has a circular planar pattern. The source region 6 is annular (frame-shaped) and has a circular planar pattern on its inner and outer circumferences.

[0080] Although Figure 13 illustrates the case where the mesa portion 15 has a circular planar pattern, the mesa portion 15 may also have an elliptical planar pattern. The other configurations of the insulated gate type semiconductor device according to the fifth embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0081] According to the insulated gate semiconductor device of the fifth embodiment, the mesa portions 15 are arranged in a matrix, and the width W5, which is the diameter of the circle formed by the planar pattern of the mesa portions 15, is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the side surface of the mesa portions 15, and thus the on-resistance can be reduced.

[0082] (Sixth Embodiment) Figure 14 shows a horizontal cross-section of the insulated gate semiconductor device according to the sixth embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 14, the configuration of the matrix-likely arranged mesa portions 15a and 15b in the insulated gate semiconductor device according to the sixth embodiment differs from that of the insulated gate semiconductor device according to the first embodiment shown in Figure 2.

[0083] The insulated gate semiconductor device according to the sixth embodiment includes two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + It includes a source region 6 of the type. The mesa portion 15b is located inside the planar pattern, p + It includes a base contact region 7 of the type. Mesa portions 15a and 15b are provided adjacent to each other. In this example, six mesa portions 15a are provided so as to surround one mesa portion 15b.

[0084] The mesa sections 15a and 15b have a circular planar pattern. The mesa sections 15a and 15b have the same outer shape. The width W5, which is the diameter of the mesa sections 15a and 15b, may be wider than the width W6 of the trench 8, the same as the width W6 of the trench 8, or narrower than the width W6 of the trench 8.

[0085] The width W5 of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W5 of the mesa portions 15a and 15b may be, for example, 50 nm or more and 600 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less.

[0086] Although Figure 14 illustrates the case where the mesa portions 15a and 15b have a circular planar pattern, the mesa portions 15a and 15b may also have an elliptical planar pattern. The other configurations of the insulated gate type semiconductor device according to the sixth embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0087] According to the insulated gate semiconductor device of the sixth embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W5, which is the diameter of the circle formed by the planar pattern of the mesa portions 15a and 15b, is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance.

[0088] (Seventh Embodiment) Figure 15 shows a horizontal cross-section of the insulated gate semiconductor device according to the seventh embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 15, the configuration of the mesa portions 15 arranged in a matrix (matrix-like) pattern in the insulated gate semiconductor device according to the seventh embodiment differs from that of the insulated gate semiconductor device according to the first embodiment shown in Figure 2.

[0089] In the insulated gate type semiconductor device according to the seventh embodiment, the mesa portion 15 is located inside the planar pattern, n + The source region 6 of the type and the p provided in contact with the source region 6 in the longitudinal direction of the mesa portion 15 + The base contact region 7 of the type is included. In the longitudinal direction of the mesa portion 15, the width W21 of the source region 6 is wider than the width W22 of the base contact region 7.

[0090] In the first direction (left-right direction in Figure 15), the source regions 6 of adjacent mesa portions 15 face each other, and the base contact regions 7 of adjacent mesa portions 15 face each other. In the second direction (up-down direction in Figure 15), which is perpendicular to the first direction, the source regions 6 of adjacent mesa portions 15 face each other, and the base contact regions 7 of adjacent mesa portions 15 face each other. That is, in the second direction (up-down direction in Figure 15), the mesa portions 15 are arranged one by one in opposite directions.

[0091] The mesa section 15 has a rectangular planar pattern. The mesa section 15 has a first direction (left-right direction in Figure 15) as its short side and a second direction (up-down direction in Figure 15) as its long side. The width W1 of the mesa section 15 in the short side is narrower than the width W3 of the mesa section 15 in the long side.

[0092] The width W1 in the short direction of the mesa portion 15 is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portion 15 is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0093] The longitudinal width W3 of the mesa portion 15 is, for example, about 2 μm or less, may be about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. In addition, the longitudinal width W3 of the mesa portion 15 is, for example, about 50 nm or more and 2 μm or less, may be about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0094] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa portion 15 may be either the m-face or the a-face. For example, the side adjacent to two sides in the longitudinal direction of the mesa portion 15 may be the m-face, and the side adjacent to two sides in the short direction of the mesa portion 15 may be the a-face.

[0095] In Figure 15, the outer shape of the mesa portion 15 is shown as an example where it is rectangular, but the outer shape of the mesa portion 15 may be a polygon such as a square or hexagon, or it may be circular or elliptical. Furthermore, a mesa portion 15 having only a source region 6 may be added between two mesa portions 15 where the source regions 6 are adjacent on the short side. Similarly, a mesa portion 15 having only a base contact region 7 may be added between two mesa portions 15 where the base contact regions 7 are adjacent on the short side. The other configurations of the insulated gate type semiconductor device according to the seventh embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0096] According to the insulated gate semiconductor device of the seventh embodiment, the mesa portions 15 are arranged in a matrix, and the width W1 in the short-side direction of the rectangle formed by the planar pattern of the mesa portions 15 is narrowed to 600 nm or less. As a result, the FinFET effect can be obtained on the side surface of the mesa portions 15, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long-side direction of the rectangle formed by the planar pattern of the mesa portions 15 to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be reduced even further.

[0097] Furthermore, in the second direction (up and down direction in Figure 15), the source regions 6 of adjacent mesa portions 15 face each other, and the base contact regions 7 of adjacent mesa portions 15 face each other. As a result, in the ion implantation process for forming the source regions 6 and base contact regions 7 during the manufacturing of the insulated gate type semiconductor device according to the seventh embodiment, the opening of the ion implantation mask can be formed to open multiple regions at once. In other words, the opening width of the mask opening can be made wider.

[0098] (Eighth embodiment) Figure 16 shows a horizontal cross-section of the insulated gate semiconductor device according to the eighth embodiment, corresponding to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 16, the insulated gate semiconductor device according to the eighth embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 2 in the configuration of the mesa portions 15a and 15b arranged in a matrix (matrix-like) pattern.

[0099] The insulated gate semiconductor device according to the eighth embodiment includes two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + It includes a source region 6 of the type. The mesa portion 15b is located inside the planar pattern, p + It includes a base contact region 7 of the type. Two types of mesa portions 15a and 15b are provided adjacent to each other.

[0100] In the first direction (left-right direction in Figure 16), one or more mesa sections 15a and one or more mesa sections 15b are provided alternately and periodically. In this example, multiple (two) mesa sections 15a and one mesa section 15b are provided alternately and periodically. In the second direction (up-down direction in Figure 16) perpendicular to the first direction, mesa sections 15a and mesa sections 15b are provided continuously. Mesa sections 15a and mesa 15b may be provided periodically in the second direction and continuously in the first direction.

[0101] Mesa sections 15a and 15b have the same external shape. Mesa sections 15a and 15b have a rectangular planar pattern. Mesa sections 15a and 15b have a first direction (left-right direction in Figure 16) as the short side and a second direction (up-down direction in Figure 16) as the long side. The width W1 in the short side direction of mesa sections 15a and 15b is narrower than the width W3 in the long side direction of mesa sections 15a and 15b.

[0102] The width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0103] The longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 2 μm or less, may be about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 50 nm or more and 2 μm or less, may be about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0104] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa sections 15a and 15b may be either the m-face or the a-face. For example, the sides of the mesa sections 15a and 15b that are adjacent to two sides in the longitudinal direction may be the m-face, and the sides adjacent to two sides in the short direction may be the a-face.

[0105] In Figure 16, the outer shape of the mesa portions 15a and 15b is shown as an example where the outer shape is rectangular, but the outer shape of the mesa portions 15a and 15b may be a polygon such as a square or hexagon, or it may be circular or elliptical. The other configurations of the insulated gate type semiconductor device according to the eighth embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0106] According to the insulated gate semiconductor device of the eighth embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W1 in the short direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long direction of the rectangle formed by the planar pattern of the mesa portion 15 to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be further reduced.

[0107] Furthermore, in a second direction perpendicular to the first direction (the vertical direction in Figure 16), mesa portions 15a and 15b are provided continuously. This allows the opening of the ion implantation mask to be formed in a manner that opens multiple regions simultaneously during the ion implantation process for forming the source region 6 and base contact region 7 during the manufacturing of the insulated gate type semiconductor device according to the 10th embodiment.

[0108] (Ninth Embodiment) Figure 17 shows a horizontal cross-section of the insulated gate semiconductor device according to the ninth embodiment, corresponding to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 17, the insulated gate semiconductor device according to the ninth embodiment differs from the insulated gate semiconductor device according to the seventh embodiment shown in Figure 15 in the configuration of the matrix-like (matrix-like) arrangement of mesa portions 15a and 15b. Specifically, in Figure 15, an example is shown in which a mesa portion having only a source region 6 is added between two mesa portions 15 where the source regions 6 are adjacent on the short side.

[0109] The insulated gate semiconductor device according to the ninth embodiment includes two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + The source region 6 of the type and the p provided in contact with the source region 6 in the longitudinal direction of the mesa portion 15 +It includes a base contact region 7 of the type. In the longitudinal direction of the mesa portion 15a, the width W21 of the source region 6 is wider than the width W22 of the base contact region 7. The mesa portion 15b is located inside the planar pattern, n + Includes source area 6 of type.

[0110] In the first direction (left-right direction in Figure 17), mesa sections 15a and 15b are provided periodically. In the second direction (up-down direction in Figure 17), which is perpendicular to the first direction, a configuration in which two mesa sections 15a sandwich one mesa section 15b is provided periodically. In the second direction (up-down direction in Figure 17), the source region 6 of mesa section 15a faces the source region 6 of the adjacent mesa section 15b. Although not shown in Figure 17, in the second direction (up-down direction in Figure 17), the base contact regions 7 of adjacent mesa sections 15a face each other.

[0111] Mesa sections 15a and 15b have the same external shape. Mesa sections 15a and 15b have a rectangular planar pattern. Mesa sections 15a and 15b have a first direction (left-right direction in Figure 17) as the short side and a second direction (up-down direction in Figure 17) as the long side. The width W1 in the short side direction of mesa sections 15a and 15b is narrower than the width W3 in the long side direction of mesa sections 15a and 15b.

[0112] The width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0113] The longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 2 μm or less, may be about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 50 nm or more and 2 μm or less, may be about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0114] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa sections 15a and 15b may be either the m-face or the a-face. For example, the sides of the mesa sections 15a and 15b that are adjacent to two sides in the longitudinal direction may be the m-face, and the sides adjacent to two sides in the short direction may be the a-face.

[0115] In Figure 17, the outer shape of the mesa portions 15a and 15b is shown as an example where the outer shape is rectangular, but the outer shape of the mesa portions 15a and 15b may be a polygon such as a square or hexagon, or it may be circular or elliptical. The other configurations of the insulated gate type semiconductor device according to the ninth embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0116] According to the insulated gate semiconductor device of the ninth embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W1 in the short direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b is narrowed to 600 nm or less. As a result, the FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be further reduced.

[0117] Furthermore, in the second direction (up and down direction in Figure 17), the source region 6 of mesa portion 15a faces the source region 6 of mesa portion 15b, and the base contact regions 7 of adjacent mesa portions 15a face each other. As a result, in the ion implantation process for forming the source region 6 and base contact region 7 during the manufacturing of the insulated gate type semiconductor device according to the ninth embodiment, the opening of the ion implantation mask can be formed to open multiple regions at once.

[0118] (Tenth embodiment) Figure 18 shows a horizontal cross-section of the insulated gate semiconductor device according to the 10th embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the 1st embodiment shown in Figure 2. As shown in Figure 18, the insulated gate semiconductor device according to the 10th embodiment differs from the insulated gate semiconductor device according to the 7th embodiment shown in Figure 15 in the configuration of the matrix-like (matrix-like) arrangement of mesa portions 15a and 15b. Specifically, in Figure 15, an example is shown in which a mesa portion having only a base contact region 7 is added between two mesa portions 15 where the base contact regions 7 are adjacent on the short side.

[0119] The insulated gate semiconductor device according to the tenth embodiment includes two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + The source region 6 of the type and the p provided in contact with the source region 6 in the longitudinal direction of the mesa portion 15 + It includes a base contact region 7 of the type. In the longitudinal direction of the mesa portion 15a, the width W21 of the source region 6 is wider than the width W22 of the base contact region 7. The mesa portion 15b is located inside the planar pattern, p + Includes a base contact area 7 of the type.

[0120] In the first direction (left-right direction in Figure 18), mesa sections 15a and 15b are provided periodically. In the second direction (up-down direction in Figure 18), which is perpendicular to the first direction, a configuration in which two mesa sections 15a sandwich one mesa section 15b is provided periodically. In the second direction (up-down direction in Figure 18), the base contact region 7 of mesa section 15a faces the base contact region 7 of the adjacent mesa section 15b. Although not shown in Figure 18, in the second direction (up-down direction in Figure 18), the source regions 6 of adjacent mesa sections 15a face each other.

[0121] Mesa sections 15a and 15b have the same external shape. Mesa sections 15a and 15b have a rectangular planar pattern. Mesa sections 15a and 15b have a first direction (left-right direction in Figure 18) as the short side and a second direction (up-down direction in Figure 18) as the long side. The width W1 in the short side direction of mesa sections 15a and 15b is narrower than the width W3 in the long side direction of mesa sections 15a and 15b.

[0122] The width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0123] The longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 2 μm or less, may be about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 50 nm or more and 2 μm or less, may be about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0124] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa sections 15a and 15b may be either the m-face or the a-face. For example, the sides of the mesa sections 15a and 15b that are adjacent to two sides in the longitudinal direction may be the m-face, and the sides adjacent to two sides in the short direction may be the a-face.

[0125] In Figure 18, the outer shape of the mesa portions 15a and 15b is shown as an example where the outer shape is rectangular, but the outer shape of the mesa portions 15a and 15b may be a polygon such as a square or hexagon, or it may be circular or elliptical. The other configurations of the insulated gate type semiconductor device according to the 10th embodiment are substantially the same as those of the insulated gate type semiconductor device according to the 1st embodiment, so redundant explanations will be omitted.

[0126] According to the insulated gate semiconductor device of the 10th embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W1 in the short direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be further reduced.

[0127] Furthermore, in the second direction (up and down direction in Figure 18), the base contact region 7 of the mesa portion 15a faces the base contact region 7 of the mesa portion 15b, and the source regions 6 of adjacent mesa portions 15a face each other. As a result, in the ion implantation process for forming the source region 6 and base contact region 7 during the manufacturing of the insulated gate type semiconductor device according to the 10th embodiment, the opening of the ion implantation mask can be formed to open multiple regions at once.

[0128] (11th embodiment) Figure 19 shows a horizontal cross-section of the insulated gate semiconductor device according to the 11th embodiment, corresponding to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 19, the insulated gate semiconductor device according to the 11th embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 2 in the configuration of the mesa portions 15a and 15b arranged in a matrix (matrix-like) pattern.

[0129] The insulated gate semiconductor device according to the 11th embodiment includes two types of mesa portions 15a and 15b. The mesa portion 15a is located inside the planar pattern, n + It includes a source region 6 of the type. The mesa portion 15b is located inside the planar pattern, p + Includes a base contact area 7 of the type.

[0130] In the first direction (left-right direction in Figure 19), multiple (four) mesa sections 15b are arranged. In Figure 19, four mesa sections 15b are arranged, but the number of mesa sections 15b is not particularly limited and may be three or fewer, or five or more. Multiple mesa sections 15a are provided so as to surround the multiple mesa sections 15b. Although not shown in Figure 19, the configuration in which multiple mesa sections 15a surround the multiple mesa sections 15b shown in Figure 19 may be provided periodically in the first direction (left-right direction in Figure 19) and in a direction perpendicular to the first direction (left-right direction in Figure 19).

[0131] Mesa sections 15a and 15b have the same external shape. Mesa sections 15a and 15b have a rectangular planar pattern. Mesa sections 15a and 15b have a first direction (left-right direction in Figure 19) as the short side and a second direction (up-down direction in Figure 19) as the long side. The width W1 in the short side direction of mesa sections 15a and 15b is narrower than the width W3 in the long side direction of mesa sections 15a and 15b.

[0132] The width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short direction of the mesa portions 15a and 15b is, for example, about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0133] The longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 2 μm or less, may be about 1 μm or less, may be about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the longitudinal width W3 of the mesa portions 15a and 15b is, for example, about 50 nm or more and 2 μm or less, may be about 50 nm or more and 1 μm or less, may be about 50 nm or more and 600 nm or less, may be about 50 nm or more and 400 nm or less, may be about 50 nm or more and 200 nm or less, or may be about 50 nm or more and 100 nm or less.

[0134] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa sections 15a and 15b may be either the m-face or the a-face. For example, the sides of the mesa sections 15a and 15b that are adjacent to two sides in the longitudinal direction may be the m-face, and the sides adjacent to two sides in the short direction may be the a-face.

[0135] In Figure 19, the outer shape of the mesa portions 15a and 15b is shown as an example where it is rectangular, but the outer shape of the mesa portions 15a and 15b may be a polygon such as a square or hexagon, or it may be circular or elliptical. The other configurations of the insulated gate type semiconductor device according to the 11th embodiment are substantially the same as those of the insulated gate type semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0136] According to the insulated gate semiconductor device of the 11th embodiment, the mesa portions 15a and 15b are arranged in a matrix, and the width W1 in the short direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b is narrowed to 600 nm or less. As a result, a FinFET effect can be obtained on the sides of the mesa portions 15a and 15b, thereby reducing the on-resistance. Furthermore, by narrowing the width W3 in the long direction of the rectangle formed by the planar pattern of the mesa portions 15a and 15b to 600 nm or less, the FinFET effect is further increased, and the on-resistance can be further reduced.

[0137] Furthermore, since multiple mesa portions 15a surround multiple mesa portions 15b, in the ion implantation process for forming the source region 6 and base contact region 7, respectively, during the manufacturing of the insulated gate type semiconductor device according to the 11th embodiment, the opening of the ion implantation mask can be formed to open multiple regions at once.

[0138] (12th embodiment) Figure 20 shows a horizontal cross-section of the insulated gate semiconductor device according to the 12th embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. As shown in Figure 20, the insulated gate semiconductor device according to the 12th embodiment differs from the insulated gate semiconductor device according to the first embodiment shown in Figure 2 in the configuration of the matrix-likely arranged mesa portions 15.

[0139] In the insulated gate semiconductor device according to the 12th embodiment, the mesa portion 15 has a rectangular planar pattern. Alternatively, the mesa portion 15 may have a rectangular planar pattern with the first direction (left-right direction in Figure 20) as the short side and the second direction (up-down direction in Figure 20) perpendicular to the first direction as the long side.

[0140] The mesa portion 15 is located within the planar pattern, n + A type source region 6 and a p provided in contact with the source region 6 in the second direction (up and down direction in Figure 20) +The base contact area 7 of the type is included. In the second direction (up and down direction in Figure 20), the width W11 of the source area 6 and the width W12 of the base contact area 7 may be the same or different from each other.

[0141] The width W1 of the mesa portion 15 in the first direction (left-right direction in Figure 20) and the width W3 in the second direction (up-down direction in Figure 20) are, for example, about 600 nm or less, may be about 400 nm or less, may be about 200 nm or less, or may be about 100 nm or less. Also, the width W1 in the short-side direction of the mesa portion 15 may be, for example, 50 nm or more and 600 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less.

[0142] Any of the four sides perpendicular to the four sides of the rectangle formed by the planar pattern of the mesa portion 15 may be either an m-plane or an a-plane. For example, the sides of the mesa portion 15 that are in contact with the two sides parallel in the vertical direction in Figure 20 are m-planes, and the sides of the mesa portion 15 that are in contact with the two sides parallel in the horizontal direction in Figure 20 are a-planes. In this case, the side of the mesa portion 15 that is in contact with the upper source region 6 in Figure 20 uses the a-plane, which has relatively high mobility. On the other hand, the side of the mesa portion 15 that is in contact with the lower base contact region 7 in Figure 20 uses the a-plane, which has relatively low mobility. This allows the m-plane and the a-plane, which has relatively high mobility, to be used as channels without using the a-plane, which has relatively low mobility, thereby reducing on-resistance.

[0143] Furthermore, the width W1 of the mesa portion 15 in the first direction (left-right direction in Figure 20) and the width W11 of the source region 6 in the second direction (up-down direction in Figure 20) may be set such that the degree of movement of the m-face, which is the side surface of the mesa portion 15 that is in contact with the source region 6 parallel to the vertical direction in Figure 20, and the a-face, which is the upper side surface of the mesa portion 15 that is in contact with the source region 6 in Figure 20, are close to each other. For example, the width W11 of the source region 6 may be set to be approximately 1.2 times or more and 1.5 times or less the width W1 of the mesa portion 15.

[0144] Other configurations of the insulated gate semiconductor device according to the 12th embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0145] According to the insulated gate semiconductor device of the 12th embodiment, the mesa portions 15 are arranged in a matrix, and the widths W1 and W3 of the rectangles formed by the planar patterns of the mesa portions 15 are narrowed to 600 nm or less. As a result, the FinFET effect can be obtained on the side surface of the mesa portions 15, thereby reducing the on-resistance.

[0146] (Other embodiments) As described above, the first to twelfth embodiments of this disclosure have been described, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples and operational techniques will become apparent to those skilled in the art from this disclosure.

[0147] For example, as an insulated gate type semiconductor device according to the first to twelfth embodiments, a trench gate type vertical MOSFET was given as an example, but the n of the MOSFET + Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0148] Furthermore, while the first to twelfth embodiments illustrate the case where the insulated gate semiconductor device is composed of silicon carbide (SiC), it is not limited to this. For example, the insulated gate semiconductor device may be composed of silicon (Si), or it may be composed of a semiconductor with a wider band gap than Si (wide bandgap semiconductor), such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN).

[0149] Furthermore, the configurations disclosed in the first to twelfth embodiments can be combined as appropriate, within the bounds of consistency. For example, the matrix does not need to have the same pattern throughout; it may be a combination of multiple regions with different patterns. Also, there may be parts where the repeating pitch of the pattern is changed or the starting position of the repeating pattern is shifted. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of Symbols]

[0150] 1...Drain area 2…Drift layer 3…Current diffusion layer 4…Gate bottom protection area 5…Base area 6…Source area 7…Base contact area 8…Trench 9…Gate insulating film 10… Guard Stop 11… Insulating film 11a... Contact hole 12… Contact electrodes 12a... Barrier metal layer 12b... Plug layer 13…Source electrode 14…Drain electrode 15, 15a, 15b, 15x... Mesa section C...Unit cell L1, L2, L3... dashed lines S1,S2,S3,S4...side T1, T2... Trench W1~W6,W11~W13,W21,W22...width θ1…Off-angle θ2~θ4…Inclination angle

Claims

1. A first conductive drift layer, A second conductivity type base region provided on the upper surface side of the drift layer, A first conductivity type main region provided on the upper surface side of the base region, A gate electrode embedded in a trench dug downward from the upper surface of the main region via a gate insulating film, Equipped with, Multiple mesa sections sandwiched between adjacent trenches are arranged in a matrix. The width of each of the plurality of mesa portions in at least one direction is 600 nm or less. Insulated gate semiconductor device.

2. Each of the aforementioned mesa portions has a polygonal planar pattern. The insulated gate semiconductor device according to claim 1.

3. One of the sides of each of the aforementioned multiple mesa portions is either the m-face or the a-face. The insulated gate semiconductor device according to claim 2.

4. In the aforementioned direction, the width of each of the multiple mesa portions is narrower than the width of the trench. The insulated gate semiconductor device according to claim 2.

5. Each of the plurality of mesa portions has a rectangular planar pattern The insulated gate semiconductor device according to claim 2.

6. Each of the aforementioned multiple mesa sections is A second conductive base contact region is provided on the upper surface side of the base region, Two main regions are provided adjacent to the base contact region so as to sandwich the base contact region, including The insulated gate semiconductor device according to claim 5.

7. The aforementioned rectangle is a rectangle, The side surface adjacent to the longer side of the rectangle is the m-face. The side of the rectangle that is in contact with the shorter side is face a. The insulated gate semiconductor device according to claim 5.

8. Each of the aforementioned mesa portions has a hexagonal planar pattern. The insulated gate semiconductor device according to claim 2.

9. The side surfaces that are adjacent to each side of the aforementioned hexagon are the m-faces. The insulated gate semiconductor device according to claim 8.

10. Each of the aforementioned multiple mesa sections is A second conductive base contact region is provided on the upper surface side of the base region, The main region is provided so as to surround the base contact region, including The insulated gate semiconductor device according to claim 8.

11. The plurality of mesa portions comprises a first mesa portion and a plurality of second mesa portions provided so as to surround the first mesa portion. The first mesa portion includes a second conductive base contact region provided on the upper surface side of the base region, Each of the plurality of second mesa portions includes the main region The insulated gate semiconductor device according to claim 8.

12. Each of the aforementioned mesa sections has a circular or elliptical planar pattern. The insulated gate semiconductor device according to claim 1.

13. Each of the aforementioned mesa portions has a rectangular planar pattern. The insulated gate semiconductor device according to claim 2.

14. Each of the aforementioned multiple mesa sections is A second conductive base contact region is provided on the upper surface side of the base region, The main region is provided in contact with the base contact region in the longitudinal direction of the rectangle, Includes, In the longitudinal and transverse directions of the rectangle, the base contact regions of adjacent mesa portions face each other. The insulated gate semiconductor device according to claim 13.

15. The plurality of mesa sections have a first mesa section and a second mesa section, The first mesa portion includes a second conductive base contact region provided on the upper surface side of the base region, The second mesa portion includes the main region, In the direction of the shorter side of the rectangle, one first mesa portion and two second mesa portions are provided alternately and periodically. In the direction of the longer side of the rectangle, the first mesa portion and the second mesa portion are provided periodically. The insulated gate semiconductor device according to claim 13.

16. The plurality of mesa sections have a first mesa section and a second mesa section, The first mesa portion includes the main region, The second mesa portion includes a second conductive base contact region provided on the upper surface side of the base region and the main region provided in contact with the base contact region in the longitudinal direction of the rectangle, In the direction of the shorter side of the rectangle, the first mesa portion and the second mesa portion are provided periodically. In the direction of the longer side of the rectangle, the main region of the second mesa portion faces the main region of the first mesa portion. The insulated gate semiconductor device according to claim 13.

17. The plurality of mesa sections have a first mesa section and a second mesa section, The first mesa portion includes a second conductive base contact region provided on the upper surface side of the base region, The second mesa portion includes the base contact region and the main region provided in contact with the base contact region in the longitudinal direction of the rectangle, In the direction of the shorter side of the rectangle, the first mesa portion and the second mesa portion are provided periodically. In the direction of the longer side of the rectangle, the base contact region of the second mesa portion faces the base contact region of the first mesa portion. The insulated gate semiconductor device according to claim 13.

18. The plurality of mesa sections have a first mesa section and a second mesa section, The first mesa portion includes a second conductive base contact region provided on the upper surface side of the base region, Each of the second mesa portions includes the main region, Multiple first mesa portions are provided in the direction of the shorter side of the rectangle. Multiple second mesa portions are provided so as to surround the multiple first mesa portions. The insulated gate semiconductor device according to claim 13.

19. The width of each of the plurality of mesa portions in at least one direction is 400 nm or less. The insulated gate semiconductor device according to claim 1.

20. The width of each of the plurality of mesa portions in at least one direction is 200 nm or less. The insulated gate semiconductor device according to claim 1.

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