electronic machines

Abstract

To provide electronic devices that function properly. [Solution] The electronic device comprises a semiconductor element having a first circuit and a second circuit, a wiring board on which the semiconductor element is mounted, a flexible wiring unit connected to the wiring board, a power unit connected to the flexible wiring unit, and a plurality of conductive members connecting the wiring board and the semiconductor element. Power is supplied from the power unit to the first circuit via the flexible wiring unit, a first power wiring provided on the wiring board, and at least four conductive members among the plurality of conductive members, and power is supplied to the second circuit via the flexible wiring unit, a second power wiring provided on the wiring board, and at least one conductive member among the plurality of conductive members.

Description

[Technical Field]

[0001] The present disclosure relates to an electronic device. [Background Art]

[0002] In an electronic device, power is supplied to a semiconductor element using a plurality of conductive members that connect a wiring board and the semiconductor element. Patent Document 1 discloses an electronic device including: a plurality of connection wirings that mutually connect a power supply wiring and an image pickup device; at least two power supply sources connected to the power supply wiring; and at least one power supply source connected to the power supply wiring. A fifth embodiment of Patent Document 2 discloses an image pickup element unit in which a wiring part that supplies power from a connector (power supply connection part) to a left end side of an image pickup substrate and a wiring part that supplies power to a right end side of the image pickup substrate are routed. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2023-53806 [Summary of Invention] [Problem to be Solved by the Invention]

[0004] When there are a plurality of systems of power supplied to a semiconductor element, potential fluctuation of a power wiring in one system may propagate to a power wiring in the other system, thereby affecting the operation of the semiconductor element. [Means for Solving the Problem]

[0005] One object of the present disclosure is to provide an electronic device that operates satisfactorily.

[0006] One aspect of the present disclosure comprises a semiconductor element having a first circuit and a second circuit, a wiring board on which the semiconductor element is mounted, a flexible wiring unit connected to the wiring board, a power unit connected to the flexible wiring unit, and a plurality of conductive members connecting the wiring board and the semiconductor element, wherein the power unit supplies power to the first circuit via the flexible wiring unit, a first power wiring provided on the wiring board, and at least four of the plurality of conductive members, and the flexible wiring unit, a second power wiring provided on the wiring board, and at least four of the plurality of conductive members An electronic device that supplies power to the second circuit via at least one conductive member, wherein the four conductive members include a first conductive member, a second conductive member, a third conductive member, and a fourth conductive member, wherein a first connection part of a plurality of connection parts connecting the flexible wiring unit and the wiring board is arranged on the wiring path connecting the first conductive member and the second conductive member in the first power wiring, and a second connection part of a plurality of connection parts connecting the flexible wiring unit and the wiring board is arranged on the wiring path connecting the third conductive member and the fourth conductive member in the first power wiring. [Effects of the Invention]

[0007] According to one aspect of this disclosure, it is possible to provide electronically operated electronic equipment that functions well. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view of the electronic device according to the first embodiment. [Figure 2] This is a block diagram of the electronic device according to the first embodiment. [Figure 3] This diagram shows the wiring connected to the pixels according to the first embodiment. [Figure 4] This is a perspective view of the wiring board according to the first embodiment. [Figure 5] This is a bottom view of the wiring board, connection part, and flexible wiring unit according to the first embodiment. [Figure 6]This is a cross-sectional view of a wiring board according to the first embodiment. [Figure 7] This is a plan view of the wiring layer according to the first embodiment. [Figure 8] This is a plan view of the wiring layer according to the first embodiment. [Figure 9] This is a schematic diagram showing the current in a digital power wiring pattern according to the first embodiment. [Figure 10] This is a schematic diagram showing the current in a modified digital power wiring pattern. [Figure 11] This is a plan view of the wiring layer according to the second embodiment. [Figure 12] This is a plan view of the wiring layer according to the third embodiment. [Figure 13] This is a plan view of the wiring layer according to the fourth embodiment. [Figure 14] This is a plan view of the wiring layer according to the fifth embodiment. [Figure 15] This is a plan view of the wiring layer according to the sixth embodiment. [Figure 16] This is a plan view of the wiring layer according to the seventh embodiment. [Figure 17] This is a plan view of the wiring layer according to the seventh embodiment. [Modes for carrying out the invention]

[0009] [First Embodiment] Figure 1 is a schematic cross-sectional view of the electronic device according to this embodiment. The electronic device according to this embodiment is a digital camera, such as a digital still camera or a digital video camera. Although Figure 1 shows a lens-interchangeable digital single-lens reflex camera as an example of the electronic device according to this embodiment, it is not limited to this. For example, the electronic device may be an information terminal with a camera, such as a smartphone or a personal computer. Here, the Z axis is the imaging direction of the electronic device, and the X and Y axes are two different directions perpendicular to the Z axis.

[0010] The electronic device includes a camera body 1, a lens unit 2, a semiconductor element 3, a connection portion 4, a flexible wiring unit 5, a processing module 6, a display 7, and a wiring board 10.

[0011] The lens unit 2 is attached to the camera body 1. The lens unit 2 may be detachable from the camera body 1, or may be formed integrally with the camera body 1. The lens unit 2 includes a lens 21. Although three lenses 21 are shown in Fig. 1, the number of lenses 21 is not limited.

[0012] Inside the camera body 1, the semiconductor element 3, the connection portion 4, the flexible wiring unit 5, the processing module 6, and the wiring board 10 are provided.

[0013] The semiconductor element 3 is mounted on the wiring board 10. The semiconductor element 3 is, for example, an image pickup element. The semiconductor element 3 can be configured by a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, a SPAD (Single Photon Avalanche Diode) image sensor, or the like. The semiconductor element 3 converts an optical image formed by the lens 21 into an electrical signal through photoelectric conversion, and outputs an image signal. Note that the semiconductor element 3 is not limited to an image pickup element. The semiconductor element 3 may be a display element, an acoustic element, or another sensor element.

[0014] The wiring board 10 is, for example, a printed wiring board. The connection portion 4 is provided on the wiring board 10. The flexible wiring unit 5 is, for example, a flexible printed wiring board or a flexible flat cable. One end of the flexible wiring unit 5 is connected to the connection portion 4, and the other end of the flexible wiring unit 5 is connected to a connection portion 62. The flexible wiring unit 5 is provided with wiring for inputting and outputting signals between the wiring board 10 and the processing module 6.

[0015] The processing module 6 includes a wiring board 61, a connection section 62, and an image processing unit 63. The wiring board 61 is, for example, a printed circuit board. The wiring board 61 is provided with a connection section 62. The image processing unit 63 is mounted on the wiring board 61 and may be a digital signal processor that processes image signals output from the semiconductor element 3. The image processing unit 63 may be an integrated circuit made up of a semiconductor package.

[0016] The image processing unit 63 receives image signals from the semiconductor element 3 via the wiring board 10, connection unit 4, flexible wiring unit 5, and connection unit 62. The image processing unit 63 performs image processing such as noise reduction, demosaicing, and color balancing on the image signal and outputs image data.

[0017] The display 7 is attached to the camera body 1. The display 7 is a display device that consists of a liquid crystal panel, an organic light-emitting panel, etc., and displays an image based on the image data from the image processing unit 63.

[0018] The camera body 1 may also be provided with a memory device for storing the output signals from the semiconductor element 3. The memory device may be composed of, for example, semiconductor memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0019] Figure 2 is a block diagram of an electronic device according to this embodiment. The electronic device includes a semiconductor element 3, a flexible wiring unit 5, and a power unit 8. The semiconductor element 3 includes a pixel 31, an analog circuit 32, and a digital circuit 33. The digital circuit 33 is an example of a first circuit, and the analog circuit 32 is an example of a second circuit.

[0020] The analog circuit 32 of the semiconductor element 3 has a plurality of pixels 31 arranged in a matrix. The pixels 31 include photodiodes, floating diffusion capacitance elements, transfer transistors, etc. The analog circuit 32 may further include a readout circuit, a clock generation circuit, and a bias generation circuit. The analog circuit 32 processes continuously changing charge or voltage and may include an amplification circuit, a filter circuit, etc. The digital circuit 33 of the semiconductor element 3 includes an A / D conversion circuit, a digital control circuit, an ISP (Image Signal Processor), a data buffering circuit, a communication circuit, etc.

[0021] The power unit 8 may be mounted on an external board (not shown) and may consist of a DC-DC converter, a regulator circuit, etc. The power unit 8 generates power to drive the analog circuit 32 and the digital circuit 33 of the semiconductor element 3 via the flexible wiring unit 5. In Figure 2, the power unit 8 is provided in common to the analog circuit 32 and the digital circuit 33, but different power units 8 may be provided for each of the analog circuit 32 and the digital circuit 33. The power unit 8 may consist of a single element or multiple elements.

[0022] The flexible wiring unit 5 includes a digital power wire 51, a ground wire 52, an analog power wire 53, and a ground wire 54. The digital power wire 51 and the ground wire 52 are connected to the digital circuit 33. Power is supplied to the digital circuit 33 from the power unit 8 through the digital power wire 51. Return current from the digital circuit 33 flows through the ground wire 52. The analog power wire 53 and the ground wire 54 are connected to the analog circuit 32. Power is supplied to the analog circuit 32 from the power unit 8 through the analog power wire 53. Return current from the analog circuit 32 flows through the ground wire 54. Although separate ground wires 52 and 54 are provided for the digital power wire 51 and the analog power wire 53, respectively, the unit is not limited to this. A common ground wire may be provided for the digital power wire 51 and the analog power wire 53. In addition, although not shown, the flexible wiring unit 5 may include signal wires for transmitting image signals, control signals, etc.

[0023] Figure 3 shows the wiring connected to pixel 31. Analog power wiring 34, ground wiring 35, control wiring 36, and signal wiring 37 are connected to pixel 31. Note that the wiring connected to pixel 31 is not limited to that shown in Figure 31. For example, reset wiring (not shown) is connected to pixel 31.

[0024] The analog power wiring 34 supplies power from the analog power wiring 53 to the pixel 31, and the ground wiring 35 returns the return current from the pixel 31 to the ground wiring 54. The control wiring 36 supplies control signals for row reading and row selection, a reset signal for resetting the stored charge, etc., from a scanning circuit (not shown) to the pixel 31. An optical image is formed on the pixel 31 by the lens 21. The pixel 31 generates a pixel signal by photoelectric conversion and outputs the pixel signal to the column signal wiring 38 via the signal wiring 37. Furthermore, the pixel signal is output to the digital circuit 33 via the column signal wiring 38. The digital circuit 33 converts the pixel signal into a digital image signal and outputs the image signal to the image processing unit 63.

[0025] Figure 4 is a perspective view of the wiring board 10 according to this embodiment. The wiring board 10 is a plate-shaped hexahedron and forms a quadrilateral in a plan view in the Z direction. A semiconductor element 3 is mounted on the upper surface of the wiring board 10. The semiconductor element 3 is a plate-shaped hexahedron and, like the wiring board 10, forms a quadrilateral in a plan view in the Z direction. Of the six faces of the hexahedron of the semiconductor element 3, the widest face is called the main face of the semiconductor 3. The main face of the semiconductor element 3 may be the interface between the functional surface of the semiconductor element 3 and the insulator. For example, if the semiconductor element 3 is a CMOS sensor, the main face of the semiconductor element 3 may be the light incident surface from the insulator to the semiconductor or the interface between the oxide film of an MOS (Metal Oxide Semiconductor) transistor and the semiconductor.

[0026] On the upper surface of the wiring board 10, a plurality of pads 101 are provided around the semiconductor element 3. Each of the plurality of pads 101 is connected to the semiconductor element 3 via bonding wires (conductive members) 102. The plurality of pads 101 are connected to the analog circuit 32 and the digital circuit 33. Preferably, the plurality of pads 101 are provided distributed along the outer circumference of the semiconductor element 3. For example, in a plurality of pixels 31, the difference in wiring length from the pads 101 to the pixels 31 of the semiconductor element 3 becomes smaller, and the variation in power supplied to each pixel 31 of the semiconductor element 3 can be reduced. Similarly, in a plurality of digital circuits 33, the difference in wiring length from the pads 101 to the digital circuits 33 can be reduced.

[0027] Connection parts 4a and 4b are connected to the underside of the wiring board 10. One end of the flexible wiring unit 5a is connected to connection part 4a, and the other end of the flexible wiring unit 5a is connected to connection part 62. Similarly, one end of the flexible wiring unit 5b is connected to connection part 4b, and the other end of the flexible wiring unit 5b is connected to connection part 62.

[0028] Figure 5 is a bottom view of the wiring board 10, connection parts 4a and 4b, and flexible wiring units 5a and 5b according to this embodiment. Connection part 4a is provided on the right side of the bottom surface of the wiring board 10, and connection part 4b is provided on the left side of the bottom surface of the wiring board 10. Flexible wiring unit 5a is provided with digital power wiring 51a, ground wiring 52a, analog power wiring 53a, and ground wiring 54a. Flexible wiring unit 5b is provided with digital power wiring 51b and ground wiring 52b.

[0029] In a plan view of the flexible wiring unit 5a, the digital power wiring 51a is provided alongside the ground wiring 52a, and the analog power wiring 53a is provided alongside the ground wiring 54a. In a plan view of the flexible wiring unit 5b, the digital power wiring 51b is provided alongside the ground wiring 52b.

[0030] Figure 6 is a cross-sectional view of the wiring board 10 according to this embodiment, and is a cross-sectional view of the wiring board 10 along the line A-A' in Figure 4. As shown in Figure 5, the wiring board 10 is a multilayer substrate having a plurality of wiring layers 11 to 18 formed on an insulating substrate. Although eight wiring layers 11 to 18 are shown in Figure 6, the number of wiring layers is not limited.

[0031] The wiring layer 11 is formed on the lower surface of the wiring board 10, and the wiring layer 11 is provided with connection parts 4a, 4b and circuit components 9. The connection parts 4a, 4b may be, for example, connector components. The connection part (first connector component) 4a has conductive leads 41a, 43a provided in a resin substrate. One end of lead 41a is connected to the digital power wiring 51a of the flexible wiring unit 5a, and the other end of lead 41a is connected to the digital power wiring pattern of the wiring layer 11. One end of lead 43a is connected to the analog power wiring 53a of the flexible wiring unit 5a, and the other end of lead 43a is connected to the analog power wiring pattern of the wiring layer 11. Although not shown in Figure 6, the connection part 4a further includes two leads connected to the ground wiring 52a, 54a of the flexible wiring unit 5a, and these leads are connected to different ground patterns of the wiring layer 11. The connector part (second connector component) 4b similarly has a lead 41b, which connects the digital power wiring 51b to the digital power wiring pattern of the wiring layer 11. Although not shown in Figure 6, the connector part 4b also connects the ground wiring 52b of the flexible wiring unit 5b to the ground pattern of the wiring layer 11. Note that the connector parts 4a and 4b may be separate joining members such as solder. The circuit component 9 may be, for example, a capacitor or a linear regulator.

[0032] A wiring layer 12 is provided above the wiring layer 11. The wiring layer 12 has a digital power wiring pattern (first power wiring pattern) 121. The digital power wiring pattern 121 of the wiring layer 12 has the largest area among the multiple digital power wiring patterns that constitute the digital power wiring (first power wiring) provided on the wiring board 10. Therefore, the digital power wiring pattern 121 can radiate the largest amount of noise among the multiple digital power wiring patterns. The digital power wiring pattern 121 of the wiring layer 12 is connected to the digital power wiring pattern of the wiring layer 11 via a via 103. The digital power wiring pattern 121 is also connected to the pad 101 via a via 104.

[0033] A wiring layer 13 is provided above the wiring layer 12. The wiring layer 13 is provided with, for example, a ground wiring pattern. The ground wiring pattern may be connected to the ground wiring patterns of other wiring layers, pads 101, connectors 4a, 4b, etc., via vias (not shown).

[0034] Above wiring layer 13, wiring layer 14 is provided. Analog power wiring patterns are provided on wiring layer 14. The analog power wiring patterns on wiring layer 14 are connected to the analog power wiring patterns on wiring layer 11 via via 105. Above wiring layer 14, wiring layer 15 is provided. For example, power wiring patterns are provided on wiring layer 15. Note that wiring layer 14 may also include signal wiring patterns.

[0035] A wiring layer 16 is provided above the wiring layer 15. The wiring layer 16 has an analog power wiring pattern (second power wiring pattern) 161. The analog power wiring pattern 161 of the wiring layer 16 has the largest area among the multiple analog power wiring patterns that constitute the analog power wiring (second power wiring) provided on the wiring board 10. For this reason, the analog power wiring pattern 161 is most strongly affected by noise from the digital power wiring pattern among the multiple analog power wiring patterns 161. The analog power wiring pattern 161 of the wiring layer 16 is connected to the analog power wiring pattern of the wiring layer 14 via a via 106. The analog power wiring pattern 161 is also connected to the pad 101 via a via 107.

[0036] A wiring layer 17 is provided above the wiring layer 16. A ground wiring pattern is provided on the wiring layer 17. For example, the ground wiring pattern may be formed over substantially the entire area of ​​the wiring layer 17. By providing a large area ground wiring pattern, the impedance of the ground wiring pattern can be lowered and noise generated in other wiring layers can be shielded. The ground wiring pattern can be connected to the ground wiring patterns of other wiring layers, pads 101, connectors 4a, 4b, etc., via vias (not shown).

[0037] A wiring layer 18 is provided above the wiring layer 17, on the upper surface of the wiring board 10. Multiple pads 101 are formed on the wiring layer 18. As described above, the multiple pads 101 may include pads 101 connected to the digital power wiring pattern 121, pads 101 connected to the analog power wiring pattern 161, pads 101 connected to the ground wiring pattern, and pads 101 connected to the signal wiring pattern. The pads 101 are connected to the analog circuit 32 and the digital circuit 33 in the semiconductor element 3 via bonding wires 102. The analog circuit 32 and the digital circuit 33 may be connected to a common ground wiring pattern on the wiring board 10, or they may be connected to different ground wiring patterns on the wiring layers 13 and 17. By connecting the analog circuit 32 and the digital circuit 33 to a ground pattern with a large area, potential fluctuations due to noise in the ground wiring pattern can be reduced.

[0038] In Figure 6, power is supplied to the analog power wiring pattern 161 via the flexible wiring unit 5b and the connection part 4b, but this is not limited to this. For example, power may be supplied to the analog power wiring pattern 161 via the linear regulator included in the circuit component 9. By performing a step-down process with the linear regulator of the circuit component 9, a low-noise voltage can be supplied to the analog power wiring pattern 161.

[0039] Figure 7 is a plan view of the wiring layer 12 according to this embodiment. The digital power wiring pattern 121 has a predetermined width and is bent to form a quadrilateral with long and short sides. In a plan view, the digital power wiring pattern 121 does not overlap with the semiconductor element 3. This reduces noise propagating from the digital power wiring pattern 121 to the semiconductor element 3. Although one digital power wiring pattern 121 is shown in Figure 7, the digital power wiring pattern 121 may be divided into multiple patterns. Also, in Figure 7, parts of the connection portions 4a and 4b are arranged to overlap with the semiconductor element 3 in a direction perpendicular to the main surface of the semiconductor element 3, but at least one of the connection portions 4a and 4b may be arranged so as not to overlap with the semiconductor element 3 in a direction perpendicular to the main surface of the semiconductor element 3. Furthermore, in a direction perpendicular to the main surface of the semiconductor element 3, the distance between the connection portion 4a and the connection portion 4b may be greater than the length of at least one side of the quadrilateral of the semiconductor element 3.

[0040] The digital power wiring pattern 121 is arranged to overlap multiple pads 101 in a plan view. This shortens the wiring path of the digital power wiring, enabling low impedance and stable operation of the digital circuit 33. In the wiring layer 12, the area enclosed by the digital power wiring pattern 121 is provided with other power wiring patterns, signal wiring patterns, ground wiring patterns, lands, etc. Note that the digital power wiring pattern 121 may be arranged outside the multiple pads 101 in a plan view.

[0041] In a plan view of the wiring layer 12, the connection points 4a and 4b are positioned to overlap the centers of two opposing sides of the digital power wiring pattern 121, for example, two short sides. The bonding wires 102 are connected to the digital power wiring pattern 121 via pads 101 and vias 104. Although 12 bonding wires 102 are shown in Figure 7, the number of bonding wires 102 is not limited to that shown in Figure 7.

[0042] The digital power wiring pattern 121 has a gap 122 in the center of one of its longer sides. The gap 122 forms the end of the digital power wiring pattern 121. This prevents the formation of a closed loop in the digital power wiring pattern 121 and suppresses the occurrence of potential fluctuations associated with the induced magnetic field in the digital power wiring pattern 121. Note that the gap 122 is not necessarily required in the digital power wiring pattern 121.

[0043] Figure 8 is a plan view of the wiring layer 16 according to this embodiment. In a plan view, the analog power wiring pattern 161 has a quadrilateral shape with long and short sides, similar to the digital power wiring pattern 121. In a plan view, the analog power wiring pattern 161 overlaps with the digital power wiring pattern 121. In a plan view, the analog power wiring pattern 161 does not overlap with the semiconductor element 3. This reduces noise propagating from the analog power wiring pattern 161 to the semiconductor element 3. Although one analog power wiring pattern 161 is shown in Figure 8, the analog power wiring pattern 161 may be divided into multiple patterns.

[0044] The analog power wiring pattern 161 is positioned to overlap multiple pads 101 in a plan view. This shortens the wiring path of the analog power wiring, enabling low impedance and stable operation of the analog circuit 32. In the wiring layer 16, the area enclosed by the analog power wiring pattern 161 is provided with other power wiring patterns, signal wiring patterns, ground wiring patterns, lands, etc. Note that the analog power wiring pattern 161 may be positioned outside the multiple pads 101 in a plan view.

[0045] In a plan view of the wiring layer 16, the connection points 4a and 4b are positioned to overlap the midpoints of the two short sides of the analog power wiring pattern 161, respectively. The bonding wires 102 are connected to the analog power wiring pattern 161 via pads 101 and vias 107. Although 10 bonding wires 102 are shown in Figure 8, the number of bonding wires 102 is not limited to that shown in Figure 8.

[0046] A gap 162 is provided at one corner of the quadrilateral analog power wiring pattern 161. In a plan view, it is preferable that the gap 122 and the gap 162 do not overlap. That is, in a plan view (the stacking direction of the multilayer substrate), it is preferable that the digital power wiring pattern 121 has a portion that does not overlap with the analog power wiring pattern 161, and the analog power wiring pattern 161 has a portion that does not overlap with the digital power wiring pattern 121.

[0047] As described above, the increased processing power due to the enhanced functionality of the digital circuit 33 increases the amount of current flowing from the digital power wiring pattern 121 to the digital circuit 33, and thus increases the noise generated in the digital circuit 33. For example, the amount of current supplied to the digital circuit 33 increases with an increase in the number of pixels or an increase in the signal transfer speed. A large amount of current flowing through the digital power wiring pattern 121 can increase the noise radiated from the digital power wiring pattern 121. When the potential of the analog power wiring pattern 161 fluctuates, the output of the analog circuit 32 changes. For example, if the potential fluctuation of the analog power wiring pattern 161 that supplies power to the pixels 31 of the analog circuit 32 is large, distortion may occur in the image generated by the semiconductor element 3. In addition, since the digital power wiring pattern 121 overlaps with the analog power wiring pattern 161, the current generated in the digital power wiring pattern 121 by the operation of the digital circuit 33 induces a current in the analog power wiring pattern 161. As a result, potential fluctuations in the analog power wiring pattern 161 cause the operation of the analog circuit 32 to become unstable, resulting in distortions such as streaks in the image generated by the multiple pixels 50. According to this embodiment, as detailed below, it is possible to reduce the maximum current of the digital power wiring pattern 121 and reduce noise in the analog power wiring pattern 161.

[0048] Figure 9 is a schematic diagram showing the current in the digital power wiring pattern 121 according to this embodiment. In plan view, the digital power wiring pattern 121 has two connection parts 4a and 4b. Also, 12 bonding wires 102A to 102L are connected to the digital power wiring pattern 121. In plan view, of the four sides of the quadrilateral of the main surface of the semiconductor element 3, the two long sides are designated as the first and third sides, and the two short sides are designated as the second and fourth sides. Bonding wires 102A to 102D face the first side, bonding wires 102E and 102F face the fourth side, bonding wires 102G to 102J face the third side, and bonding wires 102K and 102L face the second side. The arrows in Figure 9 represent the current supplied from connection parts 4a and 4b, respectively. The length of the arrows represents the magnitude of the current value, with longer arrows indicating a larger current value. It should be assumed that the current values ​​for bonding wires 102A to 102L are equal.

[0049] The current flowing through the digital power wiring pattern 121 is added towards the connection points 4a and 4b, so the current is larger closer to the connection points 4a and 4b. The digital power wiring pattern 121 has three bonding wires, connection point 4a, six bonding wires, connection point 4b, and three bonding wires connected to it in a clockwise direction starting from the gap 122. Near connection points 4a and 4b, the current equivalent to that of three bonding wires flows, so the maximum current flowing through the digital power wiring pattern 121 is equal to the current of three bonding wires. In this way, by providing multiple connection points 4a and 4b, the maximum current of the digital power wiring pattern 121 can be reduced. Therefore, it is possible to reduce the potential fluctuation of the analog power wiring pattern 161 caused by current changes in the digital power wiring pattern 121 and suppress the deterioration of image quality.

[0050] Figure 10 is a schematic diagram showing the current in a modified digital power wiring pattern 121. In plan view, the modified digital power wiring pattern 121 has only one connection part 4a. Six bonding wires, a connection part 4a, and six bonding wires are connected to the digital power wiring pattern 121 in a clockwise direction starting from the gap 122. Since the current equivalent to that of six bonding wires flows near the connection part 4a, the maximum value of the current in the digital power wiring pattern 121 is the current value equivalent to that of six bonding wires.

[0051] As described above, by providing multiple connection points 4a and 4b, the maximum value of the current in the digital power wiring pattern 121 can be reduced by half. This also reduces the maximum value of the current induced in the analog power wiring pattern 161 that overlaps with the digital power wiring pattern 121 in a plan view. According to this embodiment, by lowering the maximum value of the current in the digital power wiring pattern 121, the potential fluctuations of the analog power wiring pattern 161 caused by current changes in the digital power wiring pattern 121 can be reduced. This makes it possible to suppress a decrease in image quality.

[0052] In Figure 9, the current values ​​of bonding wires 102A to 102L are assumed to be equal, but this is not the case. If the current values ​​of bonding wires 102A to 102L are different, it is preferable that connection parts 4a and 4b be provided such that the sum of the currents of the bonding wires 102 connected to connection parts 4a and 4b is approximately equal. This effectively reduces the maximum current value in the digital power wiring pattern 121.

[0053] As described above, in this embodiment, by supplying power from the connection part 4 to the digital power wiring pattern 121, the impedance of the power supply source can be lowered regardless of the frequency band, and a well-functioning electronic device can be provided.

[0054] Furthermore, in this embodiment, the connection part 4 is located on the wiring path connecting the two bonding wires 102, and at least one bonding wire 102 is located on the wiring path connecting the two connection parts 4 in the digital power wiring pattern 121. This makes it possible to lower the maximum current of the digital power wiring pattern 121 and improve the operation of the electronic equipment.

[0055] Here, let M be the number of bonding wires 102, N be the number of connection points 4, and X be a natural number obtained by rounding down the value of M / (2N) to the nearest integer. However, M and N are both natural numbers of 2 or greater. When a gap 122 is provided to form the end of the digital power wiring pattern 121, it is preferable that 2 × X or (2 × X + 1) bonding wires 102 are provided between any one end and the nearest connection point 4. This arrangement makes it possible to lower the maximum current of the digital power wiring pattern 121.

[0056] [Second Embodiment] Next, the electronic device according to the second embodiment will be described. In this embodiment, the positions of the connection parts 4a and 4b differ from those of the first embodiment. The following description will focus on the configuration that differs from the first embodiment.

[0057] Figure 11 is a plan view of the wiring layer 12 according to this embodiment. The connection parts 4a and 4b are arranged to overlap the centers of the two long sides of the digital power wiring pattern 121, respectively. In addition, a gap 122 is provided in the center of one of the short sides of the digital power wiring pattern 121.

[0058] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and electronic equipment that operates well can be provided. In a plan view, the configuration in this embodiment can be effective when the connection parts 4a and 4b are arranged to overlap the two long sides of the digital power wiring pattern 121.

[0059] [Third Embodiment] Next, an electronic device according to the third embodiment will be described. In this embodiment, the position of the gap 122 differs from that of the first embodiment. The following description will focus on the configuration that differs from the first embodiment.

[0060] Figure 12 is a plan view of the wiring layer 12 according to this embodiment. A gap 122 is provided at one corner of the quadrilateral digital power wiring pattern 121. The connection parts 4a and 4b are positioned offset by a predetermined distance from the center of the two opposing long sides of the digital power wiring pattern 121.

[0061] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and an electronic device that operates well can be provided.

[0062] [Fourth Embodiment] Next, an electronic device according to the fourth embodiment will be described. The electronic device according to this embodiment differs from the first embodiment in that it is provided with three connection parts 4a to 4c. The following description will focus on the configuration that differs from the first embodiment.

[0063] Figure 13 is a plan view of the wiring layer 12 according to this embodiment. A gap 122 is formed in the center of one long side of the digital power wiring pattern 121, and a connection part 4b is provided in the center of the other long side. In addition, connection parts 4a and 4b are provided at positions offset by a predetermined distance from the center of two opposing short sides of the digital power wiring pattern 121. In a plan view of the wiring layer 12, connection parts 4a to 4c overlap the digital power wiring pattern 121. Two bonding wires, connection part 4a, four bonding wires, connection part 4b, four bonding wires, connection part 4c, and two bonding wires are connected to the digital power wiring pattern 121 in a clockwise direction starting from the gap 122. Since the current equivalent to that of two bonding wires flows in the vicinity of connection parts 4a to 4c, the maximum current value of the digital power wiring pattern 121 is the current value equivalent to that of two bonding wires.

[0064] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and a well-functioning electronic device can be provided. In particular, in this embodiment, the more connection parts are increased, the lower the maximum current can be, and the better the operation of the electronic device can be.

[0065] [Fifth Embodiment] Next, an electronic device according to the fifth embodiment will be described. The electronic device according to this embodiment differs from the first embodiment in that it is provided with two gaps 122. The following description will focus on the configuration that differs from the first embodiment.

[0066] Figure 14 is a plan view of the wiring layer 12 according to this embodiment. The positions of the connection parts 4a and 4b are the same as in the second embodiment. The gap 122 is provided in the center of the two long sides of the digital power wiring pattern 121, and the digital power wiring pattern 121 is divided by the two gaps 122. As a result, the number of wiring paths between the two bonding wires 102 is different from that of the first embodiment. For example, in the first embodiment, in the digital power wiring pattern 121 of the wiring layer 12 which constitutes the most digital power wiring, the number of wiring paths between the bonding wire 102B (first conductive member) facing one long side of the digital power wiring pattern 121 and the bonding wire 102E (fourth conductive member) facing one short side of the digital power wiring pattern 121 is 1. On the other hand, in the digital power wiring pattern 121 of this embodiment, the number of wiring paths between the bonding wire 102B and the bonding wire 102E is 0.

[0067] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and an electronic device that operates well can be provided.

[0068] [Sixth Embodiment] Next, an electronic device according to the sixth embodiment will be described. The electronic device according to this embodiment differs from the first embodiment in that it has digital power wiring patterns 121a and 121b. The following description will focus on the configuration that differs from the first embodiment.

[0069] Figure 15 is a plan view of the wiring layer 12 according to this embodiment. The wiring layer 12 has two digital power wiring patterns 121a and 121b. In plan view, the digital power wiring patterns 121a and 121b form a quadrilateral, with the digital power wiring pattern 121b surrounding the semiconductor element 3, and the digital power wiring pattern 121a further surrounding the digital power wiring pattern 121b. Note that the configuration in which the digital power wiring pattern 121a surrounds the digital power wiring pattern 121b is not limited to the example in Figure 15. For example, if one of the four sides of each of the digital power wiring patterns 121a and 121b is missing, the two opposing sides of the digital power wiring pattern 121b may be placed between the two opposing sides of the digital power wiring pattern 121a. Alternatively, only one side of the digital power wiring pattern 121b may be placed between the two opposing sides of the digital power wiring pattern 121a. In any of the above arrangements, parts of each of the two opposing sides of the digital power wiring pattern 121a (the first and second parts) and parts of each of the two opposing sides of the digital power wiring pattern 121b (the third and fourth parts) can be located on the same straight line.

[0070] The digital power wiring patterns 121a and 121b have approximately the same width. The digital power wiring pattern (first wiring pattern) 121a has the largest area among the multiple layers of digital power wiring patterns connected to the connection part 4a, and the digital power wiring pattern 121b (second wiring pattern) has the largest area among the multiple layers of digital power wiring patterns connected to the connection part 4b. Similarly, the analog power wiring pattern (third wiring pattern) 161 has the largest area among the multiple layers of analog power wiring patterns.

[0071] The connection part 4a is positioned so as to overlap the center of one short side of the digital power wiring pattern 121a. A gap 122a is provided in the center of the other short side of the digital power wiring pattern 121a. The connection part 4b is positioned opposite the connection part 4a and so as to overlap the center of one short side of the digital power wiring pattern 121b. A gap 122b is provided in the center of the other short side of the digital power wiring pattern 121b so as to be opposite the gap 122a. The digital power wiring patterns 121a and 121b may be supplied with power from both the connection parts 4a and 4b.

[0072] Digital power wiring pattern 121a has three bonding wires, a connector 4a, and three bonding wires connected clockwise starting from gap 122a. Digital power wiring pattern 121b has three bonding wires, a connector 4b, and three bonding wires connected clockwise starting from gap 122b. Bonding wire 102 is also connected alternately to digital power wiring patterns 121a and 121b in a clockwise direction.

[0073] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and electronic equipment that operates well can be provided. In particular, in this embodiment, since the digital power wiring patterns 121a and 121b receive power from the connection parts 4a and 4b which are located opposite each other, currents flow in opposite directions through the digital power wiring patterns 121a and 121b. As a result, the induced magnetic fields in each of the digital power wiring patterns 121a and 121b cancel each other out, further effectively reducing noise from the digital power wiring pattern 121 to the analog power wiring pattern 161, and improving the operation of the electronic equipment.

[0074] [Seventh Embodiment] Next, an electronic device according to the seventh embodiment will be described. The electronic device according to this embodiment differs from the sixth embodiment in that the two digital power wiring patterns are provided on different wiring layers 12 and 13. The following description will focus on the configuration that differs from the sixth embodiment.

[0075] Figure 16 is a plan view of the wiring layer 12 according to this embodiment, and Figure 17 is a plan view of the wiring layer 13 according to this embodiment. The digital power wiring pattern 121 is formed on the wiring layer 12 and is configured substantially the same as the digital power wiring pattern 121a of the sixth embodiment. The digital power wiring pattern 131 is formed on the wiring layer 13 and is configured substantially the same as the digital power wiring pattern 121b of the sixth embodiment. In a plan view, the digital power wiring patterns 121 and 131 overlap, but the gaps 122 and 132, and the connection parts 4a and 4b are located opposite each other. The bonding wires 102 are alternately connected to the digital power wiring patterns 121 and 131 in a clockwise direction.

[0076] In this embodiment as well, since power is supplied from the connection part 4 to the digital power wiring pattern 121, noise can be reduced regardless of the frequency band, and a well-functioning electronic device can be provided. Also, similar to the sixth embodiment, currents flow in opposite directions through the digital power wiring patterns 121 and 131. As a result, the induced magnetic fields from the digital power wiring patterns 121 and 131 cancel each other out, effectively reducing noise from the digital power wiring patterns 121 and 131 to the analog power wiring pattern 161, and improving the operation of the electronic device.

[0077] Although the two digital power wiring patterns 121 and 131 are provided on wiring layers 12 and 13, the invention is not limited to this arrangement. However, it is more preferable that the two digital power wiring patterns 121 and 131 are provided on two adjacent wiring layers. This allows the induced magnetic fields of the digital power wiring patterns 121 and 131 to be canceled out more effectively, thereby reducing noise more effectively.

[0078] [Modified Embodiment] The present invention is not limited to the embodiments described above, and many modifications are possible within the technical concept of the present invention. Furthermore, the effects described in the embodiments are merely a list of the most preferred effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0079] The combination of the first and second circuits that separate the power supply system is not limited to the case where the first circuit is a digital circuit and the second circuit is an analog circuit. For example, the first circuit may be an analog circuit and the second circuit may be a digital circuit, or the first circuit may be a first digital circuit and the second circuit may be a second digital circuit, or the first circuit may be a first analog circuit and the second circuit may be a second analog circuit.

[0080] The embodiments described above have focused on applications to electronic devices such as imaging devices, but are not limited to these. The module described above is also applicable to mobile devices such as smartphones, tablet computers, laptop computers, and portable game consoles, as well as wearable devices. Furthermore, the module is also applicable to image forming apparatuses, such as printers, copiers, facsimile machines, and multifunction devices equipped with these functions. In addition, the module is applicable to communication equipment such as modems and routers, medical equipment such as X-ray machines and endoscopes, industrial equipment such as robots and semiconductor manufacturing equipment, and transportation equipment such as vehicles, airplanes, and ships.

[0081] The disclosures in this specification include not only what is explicitly stated herein, but also all matters that can be inferred from this specification and the drawings attached thereto. Furthermore, the disclosures in this specification include the complement of the individual concepts described herein. That is, if this specification states, for example, "A is B," then even if it omits the statement "A is not B," it can be said that this specification discloses "A is not B." This is because the statement "A is B" presupposes that the case "A is not B" is being considered.

[0082] This disclosure includes the following components: (Composition 1) A semiconductor device having a first circuit and a second circuit, A wiring board on which the aforementioned semiconductor element is mounted, A flexible wiring unit connected to the aforementioned wiring board, A power unit connected to the aforementioned flexible wiring unit, The circuit board and the semiconductor element are connected by a plurality of conductive members, An electronic device that supplies power from the power unit to the first circuit via the flexible wiring unit, the first power wiring provided on the wiring board, and at least four conductive members from the plurality of conductive members, and supplies power to the second circuit via the flexible wiring unit, the second power wiring provided on the wiring board, and at least one conductive member from the plurality of conductive members, The four conductive members include a first conductive member, a second conductive member, a third conductive member, and a fourth conductive member. In the first power wiring, the first connection part, one of a plurality of connection parts connecting the flexible wiring unit and the wiring board, is arranged on the wiring path connecting the first conductive member and the second conductive member. An electronic device characterized in that, in the first power wiring, a second connection part among a plurality of connection parts connecting the flexible wiring unit and the wiring board is arranged on the wiring path connecting the third conductive member and the fourth conductive member. (Configuration 2) The electronic device according to configuration 1, characterized in that at least one of the first connecting portion and the second connecting portion is arranged so as not to overlap the semiconductor element in a direction perpendicular to the main surface of the semiconductor element. (Composition 3) The main surface of the aforementioned semiconductor element is quadrilateral, The electronic device according to configuration 1 or 2, characterized in that the distance between the first connection part and the second connection part is greater than the length of at least one side of the four sides of the quadrilateral. (Composition 4) The electronic device according to any one of configurations 1 to 3, characterized in that the second conductive member is arranged on the wiring path connecting the first connection part and the second connection part in the first power wiring. (Composition 5) The first circuit is a digital circuit, The electronic device according to any one of configurations 1 to 4, characterized in that the second circuit is an analog circuit. (Composition 6) The main surface of the aforementioned semiconductor element is quadrilateral, The first conductive member is positioned opposite the first side of the four sides of the quadrilateral, The second conductive member is positioned opposite the second side of the quadrilateral, The third conductive member is positioned opposite the third side of the quadrilateral, The electronic device according to any one of configurations 1 to 5, characterized in that the fourth conductive member faces the fourth side of the quadrilateral. (Composition 7) The main surface of the aforementioned semiconductor element is quadrilateral, The electronic device according to configuration 6, characterized in that two of the four sides that face each other are located between at least one of the first conductive member and the second conductive member and at least one of the third conductive member and the fourth conductive member. (Composition 8) The aforementioned wiring board is a multilayer circuit board, The electronic device according to any one of configurations 1 to 7, characterized in that, among the plurality of wiring layers of the multilayer substrate, the first wiring layer that constitutes the largest number of the first power wiring is arranged such that the number of wiring paths between the first conductive member and the fourth conductive member in the first wiring layer is 1 or 0. (Composition 9) The aforementioned wiring board is a multilayer circuit board, The electronic device according to any one of configurations 1 to 8, characterized in that the wiring layer on which the first power wiring pattern having the largest area among the plurality of wiring patterns constituting the first power wiring is provided is different from the wiring layer on which the second power wiring pattern having the largest area among the plurality of wiring patterns constituting the second power wiring is provided. (Composition 10) The electronic device according to configuration 9, characterized in that the first power wiring pattern overlaps the second power wiring pattern in the stacking direction of the multilayer substrate. (Composition 11) The electronic device according to configuration 10, characterized in that the first power wiring pattern has a portion that does not overlap with the second power wiring pattern in the stacking direction, and the second power wiring pattern has a portion that does not overlap with the first power wiring pattern in the stacking direction. (Composition 12) The electronic device according to any one of configurations 1 to 11, characterized in that, when the number of the plurality of conductive members is M, the number of the plurality of connection parts is N, and X is a natural number obtained by dividing M by 2N and truncating the decimal part, there are X or (X+1) conductive members between any end of the first power wiring and the connection part closest to any end of the first power wiring among the N connection parts, and there are 2 × X or (2 × X+1) conductive members between each of the N connection parts. (Composition 13) The electronic device according to any one of configurations 1 to 12, characterized in that the plurality of conductive members are bonding wires. (Composition 14) The first connection portion is composed of a first connector component, The electronic device according to any one of configurations 1 to 13, characterized in that the second connection portion is composed of a second connector component. (Composition 15) The electronic device according to any one of configurations 1 to 14, characterized in that the first connection and the second connection are made of solder that is separated from each other. (Composition 16) The electronic device according to any one of configurations 1 to 15, characterized in that the first power wiring includes a first wiring pattern having the largest area among a plurality of wiring patterns connected to the first connection and a second wiring pattern having the largest area among a plurality of wiring patterns connected to the second connection, and the second power wiring includes a third wiring pattern having the largest area among a plurality of wiring patterns connected to a third connection among a plurality of connection points connecting the flexible wiring unit and the wiring board. (Composition 17) The electronic device according to configuration 16, characterized in that, in a plan view with respect to the main surface of the semiconductor element, the first and second portions of the first wiring pattern and the third and fourth portions of the second wiring pattern are located on the same straight line. (Composition 18) The electronic device according to configuration 16, characterized in that the wiring layer on which the first wiring pattern is provided is provided between the wiring layer on which the third wiring pattern is provided and the wiring layer on which the second wiring pattern is provided. (Composition 19) The electronic device according to any one of configurations 1 to 18, characterized in that the semiconductor element is an image sensor. (Composition 20) The electronic device according to any one of configurations 1 to 18, further comprising a processing device for processing the signal output from the semiconductor element. (Composition 21) The electronic device according to any one of configurations 1 to 18, further comprising a memory device for storing signals output from the semiconductor element. [Explanation of symbols]

[0083] 1: Camera body 2: Lens Unit 3: Semiconductor elements 4: Connection part 5: Flexible Wiring Unit 6: Processing Module 7: Display 8: Power Unit 10: Wiring board 11, 12, 13, 14, 15, 16, 17, 18: Wiring layer 31: Pixels 32: Analog Circuits 33: Digital Circuits

Claims

1. A semiconductor element having a first circuit and a second circuit, A wiring board on which the aforementioned semiconductor element is mounted, A flexible wiring unit connected to the aforementioned wiring board, A power unit connected to the aforementioned flexible wiring unit, The circuit board and the semiconductor element are connected by a plurality of conductive members, An electronic device that supplies power from the power unit to the first circuit via the flexible wiring unit, the first power wiring provided on the wiring board, and at least four conductive members among the plurality of conductive members, and supplies power to the second circuit via the flexible wiring unit, the second power wiring provided on the wiring board, and at least one conductive member among the plurality of conductive members, The four conductive members include a first conductive member, a second conductive member, a third conductive member, and a fourth conductive member. In the first power wiring, the first connection part, one of a plurality of connection parts connecting the flexible wiring unit and the wiring board, is arranged on the wiring path connecting the first conductive member and the second conductive member. An electronic device characterized in that, in the first power wiring, a second connection part among a plurality of connection parts connecting the flexible wiring unit and the wiring board is arranged on the wiring path connecting the third conductive member and the fourth conductive member.

2. The electronic device according to claim 1, characterized in that at least one of the first connecting portion and the second connecting portion is arranged so as not to overlap the semiconductor element in a direction perpendicular to the main surface of the semiconductor element.

3. The main surface of the aforementioned semiconductor element is quadrilateral, The electronic device according to claim 1, characterized in that the distance between the first connection part and the second connection part is greater than the length of at least one side of the four sides of the quadrilateral.

4. The electronic device according to claim 1, characterized in that the second conductive member is arranged on the wiring path connecting the first connection part and the second connection part in the first power wiring.

5. The first circuit is a digital circuit, The electronic device according to claim 1, characterized in that the second circuit is an analog circuit.

6. The main surface of the aforementioned semiconductor element is quadrilateral, The first conductive member is positioned opposite the first side of the four sides of the quadrilateral, The second conductive member is positioned opposite the second side of the quadrilateral, The third conductive member is positioned opposite the third side of the quadrilateral, The electronic device according to claim 1, characterized in that the fourth conductive member faces the fourth side of the quadrilateral.

7. The main surface of the aforementioned semiconductor element is quadrilateral, The electronic device according to claim 6, characterized in that two of the four sides that face each other are located between at least one of the first conductive member and the second conductive member and at least one of the third conductive member and the fourth conductive member.

8. The aforementioned wiring board is a multilayer circuit board, The electronic device according to claim 1, characterized in that, among the plurality of wiring layers of the multilayer substrate, the first wiring layer that constitutes the largest number of the first power wiring is arranged such that the number of wiring paths between the first conductive member and the fourth conductive member in the first wiring layer is 1 or 0.

9. The aforementioned wiring board is a multilayer circuit board, The electronic device according to claim 1, characterized in that the wiring layer on which the first power wiring pattern having the largest area among the plurality of wiring patterns constituting the first power wiring is provided is different from the wiring layer on which the second power wiring pattern having the largest area among the plurality of wiring patterns constituting the second power wiring is provided.

10. The electronic device according to claim 9, characterized in that the first power wiring pattern overlaps the second power wiring pattern in the stacking direction of the multilayer substrate.

11. The electronic device according to claim 10, characterized in that the first power wiring pattern has a portion that does not overlap with the second power wiring pattern in the stacking direction, and the second power wiring pattern has a portion that does not overlap with the first power wiring pattern in the stacking direction.

12. The electronic device according to claim 1, characterized in that, when the number of the plurality of conductive members is M, the number of the plurality of connection parts is N, and X is a natural number obtained by dividing M by 2N and truncating the decimal part, there are X or (X+1) conductive members between any end of the first power wiring and the connection part that is closest to any end of the first power wiring among the N connection parts, and there are 2 × X or (2 × X+1) conductive members between each of the N connection parts.

13. The electronic device according to claim 1, characterized in that the plurality of conductive members are bonding wires.

14. The first connection part and the first connector component constitute the first connection part, The electronic device according to claim 1, characterized in that the second connection portion is composed of a second connector component.

15. The electronic device according to claim 1, characterized in that the first connection and the second connection are made of solder that is separated from each other.

16. The electronic device according to claim 1, wherein the first power wiring includes a first wiring pattern having the largest area among a plurality of wiring patterns connected to the first connection and a second wiring pattern having the largest area among a plurality of wiring patterns connected to the second connection, and the second power wiring includes a third wiring pattern having the largest area among a plurality of wiring patterns connected to a third connection among a plurality of connection points connecting the flexible wiring unit and the wiring board.

17. The electronic device according to claim 16, characterized in that, in a plan view with respect to the main surface of the semiconductor element, the first and second portions of the first wiring pattern and the third and fourth portions of the second wiring pattern are located on the same straight line.

18. The electronic device according to claim 16, characterized in that the wiring layer on which the first wiring pattern is provided is provided between the wiring layer on which the third wiring pattern is provided and the wiring layer on which the second wiring pattern is provided.

19. The electronic device according to any one of claims 1 to 18, characterized in that the semiconductor element is an image sensor.

20. The electronic device according to any one of claims 1 to 18, further comprising a processing device for processing the signal output from the semiconductor element.

21. The electronic device according to any one of claims 1 to 18, further comprising a memory device for storing signals output from the semiconductor element.

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