Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, which enable the suitable bonding of multiple substrates to each other. [Solution] According to one embodiment, the semiconductor device includes a lower substrate comprising a first substrate, a first insulating film provided on the first substrate, a first pad provided within the first insulating film on the upper surface side of the first insulating film, and a first recess provided within the first insulating film on the upper surface side of the first insulating film. The device further comprises an upper substrate disposed on the lower substrate and in contact with the lower substrate, the upper substrate comprising a second substrate, a second insulating film provided below the second substrate, a second pad provided within the second insulating film on the lower surface side of the second insulating film, and a second recess provided within the second insulating film on the lower surface side of the second insulating film and facing the first recess. The device further comprises a first member housed within the first recess and the second recess.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a case where a semiconductor device is manufactured by bonding a plurality of wafers to each other, it is required to bond these wafers with high accuracy.

Prior Art Literature

Patent Literature

[0003]

Patent Literature 1

Patent Literature 2

Patent Literature 3

Summary of the Invention

Problem to be Solved by the Invention

[0004] Provided are a semiconductor device capable of suitably bonding a plurality of substrates to each other and a method for manufacturing the same.

Means for Solving the Problem

[0005] According to one embodiment, the semiconductor device includes a lower substrate comprising a first substrate, a first insulating film provided on the first substrate, a first pad provided within the first insulating film on the upper surface side of the first insulating film, and a first recess provided within the first insulating film on the upper surface side of the first insulating film. The device further comprises an upper substrate disposed on and in contact with the lower substrate, the upper substrate comprising a second substrate, a second insulating film provided below the second substrate, a second pad provided within the second insulating film on the lower surface side of the second insulating film, and a second recess provided within the second insulating film on the lower surface side of the second insulating film and facing the first recess. The device further comprises a first member housed within the first recess and the second recess. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is a plan view showing the structure of the first embodiment of the semiconductor device. [Figure 3] This is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a perspective view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a perspective view showing another example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view showing a first modified example of the first embodiment of a method for manufacturing a semiconductor device. [Figure 8] This is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a second modified example of the first embodiment. [Figure 9] This is a cross-sectional view (2 / 3) showing the manufacturing method of the semiconductor device of the second modified example described above. [Figure 10] This is a cross-sectional view (3 / 3) showing the manufacturing method of the semiconductor device of the second modified example described above. [Figure 11]It is a cross-sectional view for explaining the method of manufacturing a semiconductor device according to the third to fifth modified examples of the first embodiment. [Figure 12] It is a plan view for explaining the method of manufacturing a semiconductor device according to the sixth modified example of the first embodiment. [Figure 13] It is a perspective view showing the method of manufacturing a semiconductor device according to the seventh modified example of the first embodiment. [Figure 14] It is a plan view showing the structure of a semiconductor device according to the eighth modified example of the first embodiment. [Figure 15] It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 16] It is an enlarged cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 17] It is a cross-sectional view (1 / 2) showing the method of manufacturing a semiconductor device according to the second embodiment. [Figure 18] It is a cross-sectional view (2 / 2) showing the method of manufacturing a semiconductor device according to the second embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 18, the same components are denoted by the same reference numerals, and overlapping descriptions will be omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] The semiconductor device of the present embodiment includes an upper substrate 1, a lower substrate 2, and a plurality of spherical members 3 which are examples of a first member. The upper substrate 1 is bonded to the lower substrate 2. Therefore, the upper substrate 1 is disposed on the lower substrate 2 and is in contact with the lower substrate 2. The semiconductor device of the present embodiment is, for example, a semiconductor chip including a three-dimensional semiconductor memory.

[0010] The upper substrate 1 includes a substrate 1a, which is an example of a second substrate, an interlayer insulating film 1b, which is an example of a second insulating film and a second film, and a plurality of metal pads 1c, which is an example of a second pad. The lower substrate 2 includes a substrate 2a, which is an example of a first substrate, an interlayer insulating film 2b, which is an example of a first insulating film and a first film, and a plurality of metal pads 2c, which is an example of a first pad. When the semiconductor device of the present embodiment is a semiconductor chip, the upper substrate 1 is an upper chip within the semiconductor chip, and the lower substrate 2 is a lower chip within the semiconductor chip.

[0011] Each of the substrates 1a and 2a is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows a lower surface A1 and an upper surface B1 of the substrate 1a, and an upper surface A2 and a lower surface B2 of the substrate 2a. FIG. 1 further shows an X direction and a Y direction that are parallel to these surfaces A1, B1, A2, and B2 and perpendicular to each other, and a Z direction that is perpendicular to these surfaces A1, B1, A2, and B2. In the present specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may coincide with the direction of gravity, or may not coincide with the direction of gravity.

[0012] The interlayer insulating film 1b is provided under the substrate 1a, and the interlayer insulating film 2b is provided on the substrate 2a. Each of the interlayer insulating films 1b and 2b is, for example, a laminated insulating film including a SiO₂ film (silicon oxide film) and another insulating film. In the present embodiment, the lower surface of the interlayer insulating film 1b and the upper surface of the interlayer insulating film 2b are formed of SiO₂. The interlayer insulating film 1b of the present embodiment is bonded to the interlayer insulating film 2b. Therefore, the interlayer insulating film 1b is disposed on the interlayer insulating film 2b, and the lower surface of the interlayer insulating film 1b is in contact with the upper surface of the interlayer insulating film 2b.

[0013] Each metal pad 1c is provided within the interlayer insulating film 1b on the lower side of the interlayer insulating film 1b, and each metal pad 2c is provided within the interlayer insulating film 2b on the upper side of the interlayer insulating film 2b. Each of the metal pads 1c and 2c is, for example, a metal layer containing a Cu (copper) layer. In this embodiment, each metal pad 1c is bonded to the corresponding metal pad 2c. Therefore, each metal pad 1c is positioned on the corresponding metal pad 2c, and the lower surface of each metal pad 1c is in contact with the upper surface of the corresponding metal pad 2c. The semiconductor device of this embodiment may also include metal pads (dummy pads) 1c that do not come into contact with the metal pads 2c, and metal pads (dummy pads) 2c that do not come into contact with the metal pads 1c.

[0014] The upper substrate 1 further includes a plurality of recesses C1 provided within the interlayer insulating film 1b on the lower surface side of the interlayer insulating film 1b. These recesses C1 are holes formed within the interlayer insulating film 1b. The shape of each recess C1 is, for example, conical or pyramidal. Therefore, the surface of each recess C1 has a tapered shape inclined with respect to the XY plane. In this embodiment, the shape of each recess C1 is a cone or pyramidal shape extending in the Z direction, and the shape of each recess C1 in plan view is a circle or polygon (for example, a quadrilateral such as a square or rectangle). In Figure 1, the surface of each recess C1 is formed of the interlayer insulating film 1b. Each recess C1 is an example of a second recess.

[0015] The lower substrate 2 further includes a plurality of recesses C2 provided within the interlayer insulating film 2b on the upper surface side of the interlayer insulating film 2b. These recesses C2 are holes formed within the interlayer insulating film 2b. The shape of each recess C2 is, for example, conical or pyramidal. Therefore, the surface of each recess C2 has a tapered shape inclined with respect to the XY plane. In this embodiment, the shape of each recess C2 is a cone or pyramidal shape extending in the Z direction, and the shape of each recess C2 in plan view is a circle or polygon (for example, a quadrilateral such as a square or rectangle). In Figure 1, the surface of each recess C2 is formed of the interlayer insulating film 2b. Each recess C2 is an example of a first recess.

[0016] In Figure 1, each recess C1 is positioned on a corresponding recess C2 and faces the corresponding recess C2. As a result, a pair of recesses C1 and C2 form a single cavity within the interlayer insulating films 2a and 2b. Figure 1 shows three cavities formed by three pairs of recesses C1 and C2. In this embodiment, the shapes of the multiple recesses C1 and C2 are identical, and furthermore, the shape of recess C1 in plan view and the shape of recess C2 in plan view are congruent. Therefore, if the shapes of recesses C1 and C2 are, for example, triangular pyramids (tetrahedrons), and recesses C1 and C2 overlap without misalignment, the shape of each cavity will be a hexahedron. Also, if the shapes of recesses C1 and C2 are, for example, square pyramids (pentahedrons), and recesses C1 and C2 overlap without misalignment, the shape of each cavity will be an octahedron.

[0017] Each spherical member 3 is housed within a cavity formed by a pair of recesses C1 and C2. Figure 1 shows three spherical members 3 housed within three cavities. Each spherical member 3 is spherical in shape. The shape of each spherical member 3 may be close to a perfect sphere or may be a sphere with a large deviation from a perfect sphere. Each spherical member 3 is made of, for example, glass or metal. Examples of each spherical member 3 include glass beads made of glass and metal balls made of metal. Each spherical member 3 may also be an elastic member made of an elastic material. In each cavity of this embodiment, the spherical member 3 is housed within the recesses C1 and C2 in contact with both the surface of recess C1 and the surface of recess C2, that is, in contact with both the interlayer insulating film 2a and the interlayer insulating film 2b.

[0018] In this embodiment, the upper substrate 1 and the lower substrate 2 are bonded together such that one or more spherical members 3 are each housed in one or more pairs of recesses C1 and C2. Therefore, alignment of the upper substrate 1 and the lower substrate 2 can be achieved using these spherical members 3. This makes it possible to bond the upper substrate 1 and the lower substrate 2 with high precision, improving the yield caused by the bonding process between the upper substrate 1 and the lower substrate 2, and reducing the costs associated with the bonding process.

[0019] For example, the alignment of the upper substrate 1 and the lower substrate 2 can be performed by optical measurement. However, when employing optical measurement, the small size of the metal pads 1c and 2c, the transmission of light through the upper substrate 1 and lower substrate 2, and the possibility of distortion occurring in the upper substrate 1 and lower substrate 2 all hinder the successful performance of optical measurement. As a result, highly precise and difficult adjustments become necessary for optical measurement. Furthermore, if optical measurement is performed using, for example, X-rays, the high cost of X-ray equipment is also a problem.

[0020] On the other hand, according to this embodiment, such problems can be suppressed by aligning the upper substrate 1 and the lower substrate 2 without using optical measurement. This makes it possible to suitably bond the upper substrate 1 and the lower substrate 2 together.

[0021] The size, shape, and material of each spherical member 3 in this embodiment may be any, but it is desirable that they be suitable for alignment. For example, in order to fix the positional relationship between the upper substrate 1 and the lower substrate 2, it is desirable that the size of each spherical member 3 be such that it does not move as much as possible within the cavity. Therefore, it is desirable that the size of each spherical member 3 be such that it is housed in the recesses C1 and C2 while in contact with both the interlayer insulating films 2a and 2b. Furthermore, each spherical member 3 may be replaced with a member of any shape, but it is desirable that the shape of the member be spherical rather than non-spherical so that the orientation of the member does not change easily within the cavity. In other words, it is desirable that the member be a sphere (a spherical object). Also, the shape of the member may be non-spherical, but it is desirable that it be a shape with high symmetry, similar to a sphere.

[0022] Each spherical member 3 may be made of a highly rigid material or an elastic material. An example of a highly rigid material is glass (SiO2). In this case, both the material of each spherical member 3 and the material of the interlayer insulating films 2a and 2b that form the recesses C1 and C2 can be made of SiO2. On the other hand, when each spherical member 3 is made of an elastic material, the size of each spherical member 3 may be made larger than the size that each spherical member 3 fits into the cavity when no external force is applied to each spherical member 3. This makes it possible to house each spherical member 3 in the cavity so that each spherical member 3 is compressed within the cavity, and the positional relationship between the upper substrate 1 and the lower substrate 2 can be fixed by elastic force.

[0023] Figure 1 further shows the pitch P1 between metal pads 1c and 2c, the width D1 of each recess C1 and each recess C2 in a plan view, and the width D2 of each spherical member 3 in a plan view. In this embodiment, the shape of each spherical member 3 is spherical, and the width D2 is the diameter of the sphere. Also, if the shape of each recess C1 and C2 is conical, the width D1 is the diameter of the base of the cone.

[0024] The pitch P1 is, for example, 1.0 to 2.0 μm. The width D1 is, for example, 10 to 50 μm. The width D2 is, for example, 20 μm or less. When employing a hybrid bonding method, as in this embodiment, in which the interlayer insulating film 1b is bonded to the interlayer insulating film 2b and the metal pad 1c is bonded to the metal pad 2c, it is desirable to ensure an accuracy of alignment between the upper substrate 1 and the lower substrate 2 of about 1 / 10 of the pitch P1. In this case, it is desirable that the width D2 be 10 times or less of the pitch P1, and therefore, as described above, it is desirable to set it to 20 μm or less. This makes it possible to suitably align the upper substrate 1 and the lower substrate 2 by self-alignment.

[0025] Furthermore, the method of this embodiment is applicable not only when bonding two substrates (upper substrate 1 and lower substrate 2), but also when bonding three or more substrates. In addition, the upper substrate 1 and lower substrate 2 may be an array substrate including a memory cell array and a circuit substrate including its control circuit, or both may be array substrates. Also, although the size of the upper substrate 1 and the size of the lower substrate 2 in a plan view are the same in this embodiment, they may be different.

[0026] Figure 2 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0027] Figure 2(a) shows the interlayer insulating film 1b and multiple recesses C1 within the upper substrate 1, and further shows multiple spherical members 3 within these recesses C1. Figure 1 shows a cross-section along the straight line L1 shown in Figure 2(a).

[0028] The semiconductor device of this embodiment is a semiconductor chip, and the shape of the substrate 1a and interlayer insulating film 1b in a plan view is a quadrilateral, such as a square or rectangle, as shown in Figure 2(a). Figure 2(a) shows the four sides F1 and four corners K1 of the quadrilateral. In Figure 2(a), the plurality of recesses C1 include 12 recesses C1 provided near the upper right corner K1 and 12 recesses C1 provided near the lower left corner K1. The lower left corner K1 is located on the diagonal of the quadrilateral with respect to the upper right corner K1. The upper right corner K1 is an example of a first corner, and the lower left corner K1 is an example of a second corner.

[0029] Figure 2(a) shows ten spherical members 3. These spherical members 3 are housed in a portion of the recess C1 located near the upper right corner K1 and in a portion of the recess C1 located near the lower left corner K1. In Figure 2(a), all of the spherical members 3 may be housed in all of the recess C1.

[0030] Figure 2(b) shows the interlayer insulating film 2b and multiple recesses C2 within the lower substrate 2, and further shows multiple spherical members 3 within these recesses C2. Figure 1 shows a cross-section along the straight line L2 shown in Figure 2(b).

[0031] As described above, the semiconductor device of this embodiment is a semiconductor chip, and the shape of the substrate 2a and interlayer insulating film 2b in a plan view is a quadrilateral, such as a square or rectangle, as shown in Figure 2(b). Figure 2(b) shows the four sides F2 and four corners K2 of the quadrilateral. The quadrilateral shown in Figure 2(b) is congruent to the quadrilateral shown in Figure 2(a). In Figure 2(b), the plurality of recesses C2 include 12 recesses C2 provided near the upper right corner K2 and 12 recesses C2 provided near the lower left corner K2. The lower left corner K2 is located on the diagonal of the quadrilateral with respect to the upper right corner K2. The upper right corner K2 is an example of a first corner, and the lower left corner K2 is an example of a second corner.

[0032] Figure 2(b) shows ten spherical members 3. These spherical members 3 are housed in a portion of the recess C2 located near the upper right corner K2 and in a portion of the recess C2 located near the lower left corner K2. In Figure 2(b), all of the spherical members 3 may be housed in the recess C2.

[0033] The semiconductor device of this embodiment includes spherical members 3 in recesses C1 and C2 provided near the upper right corners K1 and K2, and spherical members 3 in recesses C1 and C2 provided near the lower left corners K1 and K2. This makes it possible to fix the positional relationship between the upper substrate 1 and the lower substrate 2 using the spherical members 3 at the upper right corners K1 and K2 and the spherical members 3 at the lower left corners K1 and K2. Furthermore, by positioning the upper right corners K1 and K2 and the lower left corners K1 and K2 diagonally, it is possible to fix the positional relationship between the upper substrate 1 and the lower substrate 2 in such a way that rotation of the upper substrate 1 relative to the lower substrate 2 is suppressed.

[0034] In the vicinity of the upper right corner K1 shown in Figure 2(a), the pitch between the recesses C1 in the X and Y directions is constant. Similarly, in the vicinity of the lower left corner K1 shown in Figure 2(a), the pitch between the recesses C1 in the X and Y directions is constant. However, these pitches do not have to be constant. The same applies to the recesses C2 shown in Figure 2(b). In this embodiment, the pitch between the recesses C2 is the same as the pitch between the recesses C1.

[0035] Note that the arrangement of the multiple recesses C1 within the interlayer insulating film 1b may differ from the arrangement shown in Figure 2(a). For example, these recesses C1 may be located not only near the upper right corner K1 and the lower left corner K1 of the rectangle, but also near the lower right corner K1 and the upper left corner K1 of the rectangle. However, it is desirable that these recesses C1 be located in positions that do not interfere with the arrangement of the metal pad 1c, for example, near one or more sides F1 of the rectangle. The same applies to the recesses C2 shown in Figure 2(b).

[0036] Figure 3 is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0037] Figure 3 shows the process of bonding the upper substrate 1 and the lower substrate 2. More specifically, Figure 3 shows one chip region within the wafer-shaped upper substrate 1 (upper wafer) and one chip region within the wafer-shaped lower substrate 2 (lower wafer). In this embodiment, each of the upper and lower wafers includes multiple chip regions and scribe regions. In this embodiment, as shown in Figure 3, the upper and lower wafers are bonded together such that each chip region in the upper wafer is positioned on the corresponding chip region in the lower wafer. Subsequently, the upper and lower wafers are cut along the scribe regions, and multiple semiconductor devices (semiconductor chips) are manufactured from the upper and lower wafers. Each semiconductor device has the structure shown in Figure 1 and includes one chip region cut from the upper wafer and one chip region cut from the lower wafer.

[0038] Figure 3 further shows a plurality of recesses C1 provided on the lower surface of the upper substrate 1, a plurality of recesses C2 provided on the upper surface of the lower substrate 2, and a plurality of spherical members 3 arranged within these recesses C2. In Figure 3, the upper substrate 1 and the lower substrate 2 are bonded together such that each recess C1 faces the corresponding recess C2, and each spherical member 3 is housed within a pair of recesses C1 and C2. This makes it possible to align the upper substrate 1 and the lower substrate 2 using the plurality of spherical members 3.

[0039] In this embodiment, an upper substrate 1 (upper wafer) is formed by forming an interlayer insulating film 1b on a wafer-shaped substrate 1a, and forming a plurality of metal pads 1c and a plurality of recesses C1 within the interlayer insulating film 1b on the upper surface side of the interlayer insulating film 1b. Similarly, an interlayer insulating film 2b is formed on a wafer-shaped substrate 2a, and forming a plurality of metal pads 2c and a plurality of recesses C2 within the interlayer insulating film 2b on the upper surface side of the interlayer insulating film 2b, thereby forming a lower substrate 2 (lower wafer). Next, the upper wafer and the lower wafer are bonded together such that the interlayer insulating film 1b is placed on the interlayer insulating film 2b and the plurality of recesses C1 are placed on the plurality of recesses C2, and then the upper wafer and the lower wafer are cut. As a result, a plurality of semiconductor devices (semiconductor chips) are manufactured from the upper wafer and the lower wafer. The structure and manufacturing method of the semiconductor devices in this embodiment will be described in the second embodiment (Figures 15 to 18) described later.

[0040] Each recess C1 in this embodiment may be formed within any chip region of the upper wafer, or within the scribe region of the upper wafer (i.e., outside the chip region). Similarly, each recess C2 in this embodiment may be formed within any chip region of the lower wafer, or within the scribe region of the lower wafer (i.e., outside the chip region). When recesses C1 and C2 are formed within the scribe region, they will not remain in the semiconductor device after the upper and lower wafers are cut. In this case, since the upper substrate 1 has already been bonded to the lower substrate 2 after cutting, the positional relationship between the upper substrate 1 and the lower substrate 2 can be maintained even if the recesses C1 and C2 and the spherical members 3 do not remain in the semiconductor device.

[0041] In this embodiment, the number of recesses C2 that accommodate the multiple spherical members 3 may be determined randomly or intentionally. For example, the spherical members 3 can be randomly accommodated in the multiple recesses C2 by scattering them on the lower substrate 2 and sweeping them off the lower substrate 2 with a brush. Alternatively, the spherical members 3 can be accommodated in the multiple recesses C2 according to a predetermined rule by arranging each spherical member 3 in a predetermined recess C2, similar to how ball bumps are formed. In the former case, the spherical members 3 can be easily arranged in the recesses C2. In the latter case, for example, the spherical members 3 can be arranged in the recesses C2 in a way that enhances the alignment effect between the upper substrate 1 and the lower substrate 2.

[0042] Figure 4 is a perspective view showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0043] Figures 4(a) and 4(b) show the process of housing a single spherical member 3 in a pair of recesses C1 and C2. In Figures 4(a) and 4(b), the shape of recess C1 is a cone, where the area of ​​the XY cross-section of recess C1 decreases in the +Z direction, and the shape of recess C2 is a cone, where the area of ​​the XY cross-section of recess C2 decreases in the -Z direction. The diameter of the base of these cones is, for example, 10 to 50 μm.

[0044] Figure 5 is a perspective view showing another example of the method for manufacturing a semiconductor device according to the first embodiment.

[0045] Figures 5(a) and 5(b) also show the process of housing a single spherical member 3 within a pair of recesses C1 and C2. In Figures 5(a) and 5(b), the shape of recess C1 is a pyramidal shape in which the area of ​​the XY cross-section of recess C1 decreases in the +Z direction, and the shape of recess C2 is a pyramidal shape in which the area of ​​the XY cross-section of recess C2 decreases in the -Z direction. The shape of the base of these pyramidal shapes is, for example, a square. The length of one side of the square is, for example, 10 to 50 μm.

[0046] Figure 6 is a perspective view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0047] Figure 6 shows the process of forming a single recess C2 in the interlayer insulating film 2b of the lower substrate 2 using a drill 4. This makes it possible to easily form a conical recess C2 in the interlayer insulating film 2b. In this embodiment, each recess C2 may be formed in the interlayer insulating film 2b of the lower substrate 2 using other tools. An example of such a tool is a reamer.

[0048] Each recess C1 in this embodiment can be formed in the same way as recess C2. Each recess C1 may be formed, for example, within the interlayer insulating film 1b of the upper substrate 1 using a drill 4 or a reamer.

[0049] (1) First variation Figure 7 is a cross-sectional view showing a first modification of the first embodiment for the manufacturing method of a semiconductor device. Figure 7 shows a process of forming a recess C2 in the interlayer insulating film 2b of the lower substrate 2 by etching. This process can be similarly applied to recess C1.

[0050] First, a resist layer 5 is formed on the interlayer insulating film 2b, and an opening 5a is formed within the resist layer 5 (Figure 7(a)). If the recess C2 is conical, the shape of the opening 5a in plan view is set to a circle. If the recess C2 is pyramidal, the shape of the opening 5a in plan view is set to a polygon. However, the shape of the opening 5a may be set taking into account errors in lithography and etching.

[0051] Next, the resist layer 5 is used as a mask to process the interlayer insulating film 2b below the opening 5a by etching (Figures 7(b) and 7(c)). Figures 7(b) and 7(c) show the etching process. This etching is, for example, tapered etching by RIE (Reactive Ion Etching).

[0052] In this way, a recess C2 is formed within the interlayer insulating film 2b (Figure 7(d)). The resist layer 5 may disappear during etching or be removed after etching.

[0053] According to this modified example, it becomes possible to form a recess C2 within the interlayer insulating film 2b using semiconductor process technology. This makes it possible to form the recess C2 easily and with high precision within the process of manufacturing semiconductor devices.

[0054] (2) Second variation Figures 8 to 10 are cross-sectional views showing a second modified example of the first embodiment for manufacturing a semiconductor device. Figures 8 to 10 show a process for forming a recess C2 within the laminated film 11 contained in the interlayer insulating film 2b of the lower substrate 2. This process can also be applied to a recess C1.

[0055] First, multiple insulating films 11a and multiple sacrificial layers 11b are alternately formed on the substrate 2a (Figure 8). As a result, a laminated film 11 containing multiple insulating films 11a and multiple sacrificial layers 11b alternately is formed on the substrate 2a. Each insulating film 11a is, for example, an SiO2 film. Each sacrificial layer 11b is, for example, a SiN film (silicon nitride film). Each sacrificial layer 11b may be an insulating film other than an SiO2 film or a SiN film, or it may be a semiconductor layer such as a polysilicon layer or an amorphous silicon layer. The laminated film 11 is an example of a first insulating film and a first film, similar to the interlayer insulating film 2b.

[0056] Next, the shape of the laminated film 11 is processed (Figure 9). As a result, one or more staircase structures 12 and one or more recesses C2 are formed within the laminated film 11. Figure 9 shows a staircase structure 12 formed at the right end of the laminated film 11 and a staircase structure 12 formed at the left end of the laminated film 11. Each staircase structure 12 shown in Figure 9 forms a staircase extending in the X direction, and a pair of insulating films 11a and sacrificial layers 11b within each staircase structure 12 form one step of the staircase. Figure 9 further shows a recess C2 formed between the staircase structures 12 within the laminated film 11. The surface of the recess C2 shown in Figure 9 has a staircase shape, similar to each staircase structure 12. The processing of the laminated film 11 in Figure 9 is performed by etching, for example, RIE. In this etching process, the staircase structures 12 and recesses C2 are formed, for example, by slimming.

[0057] Next, an interlayer insulating film 2b is formed on the substrate 2a so as to cover the laminated film 11 (Figure 10). As a result, the interlayer insulating film 2b is formed on the stepped structure 12 and in the recesses C2.

[0058] Next, the interlayer insulating film 2b is processed by etching so that it is removed from the recess C2 of the laminated film 11 (Figure 10). As a result, the recess C2 is processed into a shape that extends within the laminated film 11 and the interlayer insulating film 2b. Note that the recess C2 may not be formed at the stage shown in Figure 9 before the formation of the interlayer insulating film 2b, but rather at the stage shown in Figure 10 after the formation of the interlayer insulating film 2b.

[0059] Subsequently, a replacement process is performed in which multiple slits are formed within the laminated film 11, and each sacrificial layer 12 is replaced with an electrode layer using these slits. This forms a memory cell array including the laminated film 11. An example of a memory cell array is shown in Figure 15 of the second embodiment described later.

[0060] In the replacement process, only a portion of each sacrificial layer 12 may be replaced with an electrode layer. In this case, the multiple sacrificial layers 12 will remain in each semiconductor device of this embodiment. These sacrificial layers 12 will remain, for example, in locations far from the multiple slits or in locations close to any of the staircase structures 12. In this case, each staircase structure 12 in each semiconductor device may be formed by these sacrificial layers 12. Also, if the recess C2 is formed in a location far from the multiple slits or in a location close to any of the staircase structures 12, the recess C2 in each semiconductor device may also be formed by these sacrificial layers 12.

[0061] According to this modified example, it becomes possible to form recesses C2 within the interlayer insulating film 2b and the laminated film 11 using semiconductor process technology. As a result, similar to the second modified example, it becomes possible to form recesses C2 easily and with high precision within the process of manufacturing semiconductor devices.

[0062] (3) Variations of the 3rd to 5th Figure 11 is a cross-sectional view illustrating the manufacturing method of the third to fifth modified semiconductor device according to the first embodiment.

[0063] Figure 11(a) shows the laminated film 11 within the interlayer insulating film 2b of the lower substrate 2, one or more stepped structures 12 included in the laminated film 11, and the laminated film 13 within the interlayer insulating film 1b of the upper substrate 1, and one or more stepped structures 14 included in the laminated film 13. As described above, the laminated film 11 is an example of the first insulating film and the first film, similar to the interlayer insulating film 2b. Similarly, the laminated film 13 is an example of the second insulating film and the second film, similar to the interlayer insulating film 1b.

[0064] The structure and formation method of the laminated film 11 and the staircase structure 12 shown in Figure 11(a) are the same as those of the laminated film 11 and the staircase structure 12 shown in Figures 8 to 10. Similarly, the structure and formation method of the laminated film 13 and the staircase structure 14 shown in Figure 11(a) are the same as those of the laminated film 11 and the staircase structure 12 shown in Figures 8 to 10.

[0065] In Figure 11(a), the XZ cross-sectional shape of the laminated film 11 is generally a trapezoid where the side on the top surface of the laminated film 11 is shorter than the side on the bottom surface of the laminated film 11. In this case, the top surface of the laminated film 11 is called the "Face" and the bottom surface of the laminated film 11 is called the "Back". Also in Figure 11(a), the XZ cross-sectional shape of the laminated film 13 is generally a trapezoid where the side on the bottom surface of the laminated film 13 is shorter than the side on the top surface of the laminated film 13. In this case, the bottom surface of the laminated film 13 is called the "Face" and the top surface of the laminated film 13 is called the "Back". The laminated films 11 and 13 shown in Figure 11(a) have a "Face to Face structure".

[0066] Figure 11(b) also shows the laminated film 11, one or more stepped structures 12, the laminated film 13, and one or more stepped structures 14. However, in Figure 11(b), the XZ cross-sectional shape of the laminated film 11 is generally a trapezoid where the side on the lower surface of the laminated film 11 is shorter than the side on the upper surface of the laminated film 11. Also in Figure 11(b), the XZ cross-sectional shape of the laminated film 13 is generally a trapezoid where the side on the upper surface of the laminated film 13 is shorter than the side on the lower surface of the laminated film 13. The laminated films 11 and 13 shown in Figure 11(b) have a "Back to Back structure".

[0067] Figure 11(c) also shows the laminated film 11, one or more stepped structures 12, the laminated film 13, and one or more stepped structures 14. However, in Figure 11(c), the XZ cross-sectional shape of the laminated film 11 is generally a trapezoid where the lower side of the laminated film 11 is shorter than the upper side. Also in Figure 11(c), the XZ cross-sectional shape of the laminated film 13 is generally a trapezoid where the lower side of the laminated film 13 is shorter than the upper side. The laminated films 11 and 13 shown in Figure 11(c) have a "Face to Back structure".

[0068] In each of Figures 11(a) to 11(c), similar to the second modified example, one or more recesses C2 may be formed within the laminated film 11 and one or more recesses C1 may be formed within the laminated film 13. This makes it possible to form the recesses C1 and C2 using semiconductor process technology.

[0069] In addition, as shown in Figure 11(a), recesses C1 and C2 may be formed using the staircase structures 12 and 14. In this case, two laminated films 11 are formed in the lower substrate 2, and the region between the staircase structure 12 of one laminated film 11 and the staircase structure 12 of the other laminated film 11 is used as recess C2. Similarly, two laminated films 13 are formed in the upper substrate 1, and the region between the staircase structure 14 of one laminated film 13 and the staircase structure 14 of the other laminated film 13 is used as recess C1. In this case, the surface of each staircase structure 12 becomes the surface of recess C2, and the surface of each staircase structure 14 becomes the surface of recess C1.

[0070] This method can also be applied to the upper substrate 1 in Figure 11(c). In Figure 11(c), the recess C1 of the upper substrate 1 is formed between two stepped structures 14, and the recess C2 of the lower substrate 2 is formed within the laminated film 11.

[0071] (4) Sixth variation Figure 12 is a plan view illustrating a method for manufacturing a semiconductor device according to a sixth modified example of the first embodiment.

[0072] Figure 12(a) shows a plurality of recesses C1 provided within the upper substrate 1. These recesses C1 include five recesses C1a to C1e arranged in a row along the Y direction. Figure 12(a) further shows the pitch T1 between the recesses C1a to C1e.

[0073] Figure 12(b) shows a plurality of recesses C2 provided within the lower substrate 2. These recesses C1 include five recesses C2a to C2e arranged in a row along the Y direction. Figure 12(b) further shows the pitch T2 between recesses C2a to C2e. In this modified example, the pitch T2 is different from the pitch T1.

[0074] In this modified example, the bonding position between the upper substrate 1 and the lower substrate 2 is adjusted by bonding them together so that the spherical member 3 is housed in a predetermined recess C1 among recesses C1a to C1e and in a predetermined recess C2 among recesses C2a to C2e. In one case, the upper substrate 1 and the lower substrate 2 are bonded together so that recess C1c faces recess C2c and the spherical member 3 is housed in recesses C1c and C2c. In another case, the upper substrate 1 and the lower substrate 2 are bonded together so that recess C1a faces recess C2a and the spherical member 3 is housed in recesses C1a and C2a.

[0075] In this modified example, recesses C1 and C2 are formed within the upper substrate 1 and lower substrate 2, assuming that warping occurs in at least one of the upper substrate 1 and lower substrate 2, or that distortion occurs in at least one of the upper substrate 1 and lower substrate 2.

[0076] For example, if there is no warping or distortion in the upper substrate 1 and the lower substrate 2, recesses C1 and C2 are formed such that recess C1c faces recess C2c. Therefore, if there is no warping or distortion in the upper substrate 1 and the lower substrate 2, the upper substrate 1 and the lower substrate 2 are bonded together such that the spherical member 3 is housed in recesses C1c and C2c. This makes it possible to suitably bond the upper substrate 1 and the lower substrate 2 when there is no warping or distortion.

[0077] On the other hand, if the upper substrate 1 and / or the lower substrate 2 are warped and / or distorted, the upper substrate 1 and the lower substrate 2 are bonded together so that the spherical member 3 is housed in the recess C1 other than recess C1c and in the recess C2 other than recess C2c. For example, the upper substrate 1 and the lower substrate 2 are bonded together so that the spherical member 3 is housed in the recesses C1a, C2a, or recesses C1b, C2b, or recesses C1d, C2d, or recesses C1e, C2e. This makes it possible to suitably bond the upper substrate 1 and the lower substrate 2 even when warping and / or distortion occurs.

[0078] In this modified example, instead of making the pitch T2 different from the pitch T1, the sizes of the recesses C1a to C1e may be made different from each other, and the sizes of the recesses C2a to C2e may also be made different from each other. This makes it possible to adjust the bonding position between the upper substrate 1 and the lower substrate 2 by utilizing these size differences.

[0079] For example, consider a case where recesses C1a to C1e include a large recess C1 and a small recess C1, and recesses C2a to C2e include a large recess C2 and a small recess C2, and the difference between the sizes of the large recesses C1 and C2 and the sizes of the small recesses C1 and C2 is sufficiently large.

[0080] In this case, the spherical member 3, which is as large as the large recesses C1 and C2, can fit into the large recesses C1 and C2, but cannot fit into the small recesses C1 and C2. Therefore, by using the large recesses C1 and C2 and the large spherical member 3, it becomes possible to adjust the bonding position between the upper substrate 1 and the lower substrate 2.

[0081] On the other hand, a spherical member 3 that is as small as the small recesses C1 and C2 can fit into both the small and large recesses C1 and C2. However, a small spherical member 3 that fits into the large recesses C1 and C2 can move around considerably within those recesses and therefore cannot adequately contribute to adjusting the bonding position. Consequently, only a small spherical member 3 that fits into the small recesses C1 and C2 can adequately contribute to adjusting the bonding position. Therefore, by using the small recesses C1 and C2 and the small spherical member 3, it becomes possible to adjust the bonding position between the upper substrate 1 and the lower substrate 2.

[0082] This is also true when recesses C1a to C1e include recesses C1 of size Na (where Na is an integer greater than or equal to 2), and recesses C2a to C2e include recesses C2 of size Nb (where Nb is an integer greater than or equal to 2). Here, Nb is generally the same value as Na, but it may be a different value from Na.

[0083] (5) Seventh variation Figure 13 is a perspective view showing a seventh modified example of the first embodiment for the manufacturing method of a semiconductor device.

[0084] Figure 13 shows an upper wafer V1, which is a wafer-shaped upper substrate 1, and a lower wafer V2, which is a wafer-shaped lower substrate 2. Figure 13 further shows a plurality of recesses C1 formed outside the chip region of the upper wafer V1 on the lower surface of the upper wafer V1, and a plurality of recesses C2 formed outside the chip region of the lower wafer V2 on the upper surface of the lower wafer V2. In Figure 13, the upper substrate 1 and the lower substrate 2 are bonded together so that a spherical member 3 is housed in the recesses C1 and C2. Each of the recesses C1 and C2 is formed, for example, using a drill 4 (Figure 6) or a reamer.

[0085] According to this modified example, by forming recesses C1 and C2 outside the chip region of the upper wafer V1 and lower wafer V2, it becomes possible to form, for example, large recesses C1 and C2. This makes it possible to easily form the recesses C1 and C2 and to easily handle the spherical member 3.

[0086] (6) Variation 8 Figure 14 is a plan view showing the structure of a semiconductor device of the eighth modified example of the first embodiment.

[0087] The semiconductor device of this modified example includes an upper substrate 2' in addition to the upper substrate 1 and lower substrate 2. The upper substrate 2' is bonded to the upper substrate 1. Therefore, the upper substrate 2' is positioned on the upper substrate 1 and is in contact with the upper substrate 1. The upper substrate 1 corresponds to the "lower substrate" for the upper substrate 2'.

[0088] In this modified example, substrate 1a (see Figure 1) is removed from upper substrate 1 in order to bond upper substrate 2' to upper substrate 1. Instead, upper substrate 1 has a plurality of metal pads 1c' and a plurality of recesses C1' provided within the interlayer insulating film 1b (see Figure 1) on the upper surface side of upper substrate 1. Furthermore, upper substrate 2' has a plurality of metal pads 2c' and a plurality of recesses C2' disposed on these metal pads 1c' and recesses C1' on the lower surface side of upper substrate 2'. The semiconductor device of this modified example further comprises a plurality of spherical members 3', each spherical member 3' housed in a pair of recesses C1', C2'.

[0089] According to this modified example, when bonding three or more substrates (upper substrate 1, lower substrate 2, and upper substrate 2'), it becomes possible to align these substrates using multiple components (spherical components 3, 3').

[0090] As described above, the semiconductor device of this embodiment includes a spherical member 3 housed in recesses C1 and C2 of the upper substrate 1 and the lower substrate 2, as shown in Figure 1. Therefore, according to this embodiment, for example, by using the spherical member 3 to align the upper substrate 1 and the lower substrate 2, it becomes possible to suitably bond the upper substrate 1 and the lower substrate 2 together.

[0091] Note that the semiconductor device shown in Figure 1 does not necessarily have to include at least one of the substrates 1a and 2a. Examples of such structures are the structure shown in Figure 14, which was mentioned above, and the structure shown in Figure 15, which will be described later. Also, each recess C1 shown in Figure 1 may be formed in substrate 1a and / or in interlayer insulating film 1b, and each recess C2 shown in Figure 1 may be formed in substrate 2a and / or in interlayer insulating film 2b. For example, the recess C2 shown in Figure 7(d) may reach substrate 2a.

[0092] (Second Embodiment) Figure 15 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0093] The semiconductor device of this embodiment comprises an array chip 21 and a circuit chip 22 bonded together. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer containing the array chip 21 and a circuit wafer containing the circuit chip 22. The array chip 21 and the circuit chip 22 of this embodiment correspond to the upper substrate 1 and lower substrate 2 of the first embodiment, respectively.

[0094] The array chip 21 comprises a memory cell array 31 containing a plurality of memory cells, an insulating film 32 on the memory cell array 31, and an interlayer insulating film 33 below the memory cell array 31. The insulating film 32 is, for example, an SiO2 film. The interlayer insulating film 33 is, for example, a laminated film containing an SiO2 film and other insulating films. A portion of the memory cell array 31 in this embodiment corresponds to the laminated film 11 or 13 of the first embodiment, and the interlayer insulating film 33 in this embodiment corresponds to the interlayer insulating film 1b of the first embodiment.

[0095] The circuit chip 22 is located beneath the array chip 21. The symbol S indicates the bonding surface between the array chip 21 and the circuit chip 22. The circuit chip 22 comprises an interlayer insulating film 34 beneath the interlayer insulating film 33 and a substrate 35 beneath the interlayer insulating film 34. The interlayer insulating film 34 is, for example, a laminated film including an SiO2 film and other insulating films. The substrate 35 is, for example, a semiconductor substrate such as a Si substrate. The interlayer insulating film 34 and the substrate 35 in this embodiment correspond to the interlayer insulating film 2b and the substrate 2a in the first embodiment, respectively.

[0096] Figure 15 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 35, and the Z direction, which is perpendicular to the surface of the substrate 35. The X, Y, and Z directions intersect each other. In this embodiment, as in the first embodiment, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0097] The array chip 21 includes multiple word lines WL as multiple electrode layers within the memory cell array 31. Figure 15 shows a stepped structure 41 within the memory cell array 31 and multiple beam sections 42 provided within the stepped structure 41. Each word line WL extends in the X direction and is electrically connected to the word wiring layer 44 via a contact plug 43. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 45 and is also electrically connected to the source line SL. The bit line BL extends in the Y direction and is located below the multiple word lines WL. The source line SL extends in the X direction and is located above the multiple word lines WL. The stepped structure 41 in this embodiment corresponds to the stepped structure 12 or 14 in the first embodiment.

[0098] The circuit chip 22 comprises a plurality of transistors 51. Each transistor 51 includes a gate insulating film 51a and a gate electrode 51b, which are sequentially provided on the substrate 35, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 35. The circuit chip 22 also comprises a plurality of contact plugs 52 provided on the gate electrode 51b, source diffusion layer, or drain diffusion layer of the plurality of transistors 51. The circuit chip 22 also comprises a wiring layer 53, a wiring layer 54, and a wiring layer 55. The wiring layer 53 contains a plurality of wires and is provided on the plurality of contact plugs 52. The wiring layer 54 contains a plurality of wires and is provided on the wiring layer 53. The wiring layer 55 contains a plurality of wires and is provided on the wiring layer 54.

[0099] The circuit chip 22 further comprises a plurality of via plugs 56 provided on the wiring layer 55 and a plurality of metal pads 57 provided on the plurality of via plugs 56. The metal pads 57 are, for example, metal layers including a Cu layer. The circuit chip 22 functions as a logic circuit that controls the operation of the array chip 21. This logic circuit is composed of transistors 51 and the like and is electrically connected to the metal pads 57. The metal pads 57 in this embodiment correspond to the metal pads 2c in the first embodiment.

[0100] The array chip 21 comprises a plurality of metal pads 61 provided on the plurality of metal pads 57, and a plurality of via plugs 62 provided on the plurality of metal pads 61. The metal pads 61 are, for example, metal layers including a Cu layer. The array chip 21 also comprises a wiring layer 63 and a wiring layer 64. The wiring layer 63 includes a plurality of wires and is provided on the plurality of via plugs 62. The wiring layer 64 includes a plurality of wires and is provided on the wiring layer 63. The bit line BL is contained within the wiring layer 64. The logic circuit is electrically connected to the memory cell array 31 via the metal pads 61, 57, etc., and controls the operation of the memory cell array 31 via the metal pads 61, 57, etc. The metal pad 61 in this embodiment corresponds to the metal pad 1c in the first embodiment.

[0101] The array chip 21 further comprises a plurality of via plugs 65 provided on the wiring layer 64, and metal pads 66 provided on the plurality of via plugs 65 and on the insulating film 32. The array chip 21 also comprises a passivation insulating film 67 provided on the metal pads 66 and on the insulating film 32. The metal pads 66 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device in this embodiment. The passivation insulating film 67 is, for example, a multilayer film including an SiO2 film and a SiN film, and has an opening P that exposes the upper surface of the metal pads 66. The metal pads 66 can be electrically connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc. through the opening P.

[0102] Figure 16 is an enlarged cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0103] Figure 16 shows the memory cell array 31 shown in Figure 15. The memory cell array 31 comprises a laminated film 71 including a plurality of electrode layers 71a and a plurality of insulating films 71b that are alternately stacked in the Z direction. The plurality of electrode layers 71a function, for example, as the word lines WL described above. Each electrode layer 71a is, for example, a metal layer including a Cu layer. Each insulating film 71b is, for example, an SiO2 film. The laminated film 71 in this embodiment corresponds to the laminated film 11 or 13 of the first embodiment, respectively.

[0104] Figure 16 further shows one of the multiple columnar sections CL shown in Figure 15. Each columnar section CL includes a memory insulating film 72, a channel semiconductor layer 73, and a core insulating film 74, arranged sequentially on the side surface of the laminated film 71. The memory insulating film 72 includes a block insulating film 72a, a charge storage layer 72b, and a tunnel insulating film 72c, arranged sequentially on the side surface of the laminated film 71. The block insulating film 72a is, for example, an SiO2 film. The charge storage layer 72b is, for example, an insulating film such as a SiN film. The charge storage layer 72b may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 72b is capable of storing signal charges in a three-dimensional semiconductor memory. The tunnel insulating film 72c is, for example, an SiO2 film. The channel semiconductor layer 73 is, for example, a polysilicon layer. The channel semiconductor layer 73 functions as a channel in the three-dimensional semiconductor memory. The core insulating film 74 is, for example, an SiO2 film.

[0105] Figures 17 and 18 are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.

[0106] Figure 17 shows an array wafer W1 containing multiple array chips 21 and a circuit wafer W2 containing multiple circuit chips 22. The orientation of the array wafer W1 in Figure 17 is the opposite of the orientation of the array chips 21 in Figure 15. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 17 shows the array wafer W1 before its orientation is reversed for bonding, and Figure 15 shows the array chips 21 after their orientation has been reversed for bonding, and after bonding and dicing.

[0107] In Figure 17, reference numeral S1 indicates the upper surface of the array wafer W1, and reference numeral S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 36 provided beneath the insulating film 32. The substrate 36 is, for example, a semiconductor substrate such as a Si substrate. The substrate 36 in this embodiment corresponds to the substrate 1a in the first embodiment.

[0108] In this embodiment, first, as shown in Figure 17, a memory cell array 31, an insulating film 32, an interlayer insulating film 33, a metal pad 61, a via plug 65, etc. are formed on the substrate 36 of the array wafer W1, and an interlayer insulating film 34, a transistor 51, a metal pad 57, etc. are formed on the substrate 35 of the circuit wafer W2. Next, as shown in Figure 18, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that surfaces S1 and S2 face each other. This bonds the interlayer insulating film 33 and the interlayer insulating film 34. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 61 and the metal pad 57. In this way, the substrate 36 and the substrate 35 are bonded together via the interlayer insulating films 33 and 34.

[0109] Subsequently, the substrate 36 is removed by CMP (Chemical Mechanical Polishing), and the substrate 35 is thinned by CMP. Then, the array wafer W1 and the circuit wafer W2 are cut into multiple chips (dicing). In this way, the semiconductor device shown in Figure 15 is manufactured. The metal pad 66 and the passivation insulating film 67 are formed on the insulating film 32 after the removal of the substrate 36 and the thinning of the substrate 35.

[0110] Figure 15 shows the interface between the interlayer insulating film 33 and the interlayer insulating film 34, and the interface between the metal pad 61 and the metal pad 57. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated, for example, by detecting the inclination of the side surfaces of the metal pad 61 and the metal pad 57, or by detecting the positional displacement between the side surfaces of the metal pad 61 and the metal pad 57.

[0111] In this embodiment, similar to the first embodiment, a plurality of recesses C1 are formed in the interlayer insulating film 33, and a plurality of recesses C2 are formed in the interlayer insulating film 34, and the spherical members 3 in the recesses C1 and C2 are used for alignment during bonding. This makes it possible to suitably bond the array wafer W1 and the circuit wafer W2.

[0112] According to this embodiment, the semiconductor device and its manufacturing method of the first embodiment can be applied to this embodiment.

[0113] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of symbols]

[0114] 1: Upper circuit board, 1a: Circuit board, 1b: Interlayer insulating film, 1c: Metal pad, 1c': Metal pad, 2: Lower board, 2': Upper board, 2a: Board, 2b: Interlayer insulating film, 2c: Metal pad, 2c': Metal pad, 3: Spherical member, 3': Spherical member, 4: Drill, 5: Resist layer, 5a: Opening, 11: Multilayer film, 11a: Insulating film, 11b: Sacrificial layer, 12: Stepped structure, 13: Laminated film, 14: Stair structure, 21: Array chip, 22: Circuit chip, 31: Memory cell array, 32: Insulating film, 33: Interlayer insulating film, 34: Interlayer insulating film, 35: Substrate, 36: Substrate, 41: Staircase structure, 42: Beam section, 43: Contact plug, 44: Word wiring layer, 45: Via plug, 51: Transistor, 51a: Gate insulating film, 51b: Gate electrode, 52: Contact plug, 53: Wiring layer, 54: Wiring layer, 55: Wiring layer, 56: Via plug, 57: Metal pad, 61: Metal pad, 62: Via plug, 63: Wiring layer, 64: Wiring layer, 65: Via plug, 66: Metal pad, 67: Passivation insulating film, 71: Multilayer film, 71a: Electrode layer, 71b: Insulating film, 72: Memory insulating film, 72a: Block insulating film, 72b: Charge storage layer, 72c: Tunnel insulating film, 73: Channel semiconductor layer, 74: Core insulating film

Claims

1. A lower substrate comprising a first substrate, a first insulating film provided on the first substrate, a first pad provided within the first insulating film on the upper surface side of the first insulating film, and a first recess provided within the first insulating film on the upper surface side of the first insulating film, An upper substrate disposed on and in contact with the lower substrate, comprising: a second substrate; a second insulating film provided below the second substrate; a second pad provided within the second insulating film on the lower surface side of the second insulating film; and a second recess provided within the second insulating film on the lower surface side of the second insulating film and facing the first recess; The first member housed in the first recess and the second recess, A semiconductor device equipped with a semiconductor device.

2. The second insulating film is disposed on the first insulating film, The second pad is located on the first pad. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1, wherein the shape of the first member is spherical.

4. The semiconductor device according to claim 1, wherein the first member is formed of glass or metal.

5. The semiconductor device according to claim 1, wherein the first member is housed in the first recess and the second recess in contact with the first insulating film and the second insulating film.

6. The semiconductor device according to claim 1, wherein the shape of at least one of the first recess and the second recess is conical or pyramidal.

7. The semiconductor device according to claim 1, wherein at least one of the surfaces of the first recess and the second recess has a tapered shape.

8. The semiconductor device according to claim 1, wherein the shape of the first recess in a plan view and the shape of the second recess in a plan view are congruent.

9. The lower substrate includes a plurality of first recesses as the first recesses, The upper substrate includes a plurality of second recesses as the second recesses, Each of the plurality of second recesses faces one or more of the plurality of first recesses. The semiconductor device according to claim 1.

10. Each of the first and second substrates has a rectangular shape in plan view. Each of the plurality of first recesses and the plurality of second recesses includes a first recess and a second recess provided near the first corner of the rectangle and a first recess and a second recess provided near the second corner of the rectangle, The second corner is located on the diagonal of the quadrilateral with respect to the first corner, The semiconductor device according to claim 9.

11. The semiconductor device according to claim 9, wherein the pitch between the plurality of second recesses is different from the pitch between the plurality of first recesses, or the plurality of first recesses include first recesses of multiple sizes, and the plurality of second recesses include second recesses of multiple sizes.

12. A lower substrate is formed, comprising a first substrate, a first insulating film provided on the first substrate, a first pad provided within the first insulating film on the upper surface side of the first insulating film, and a first recess provided within the first insulating film on the upper surface side of the first insulating film. An upper substrate is formed, comprising a second substrate, a second insulating film provided on the second substrate, a second pad provided within the second insulating film on the upper surface side of the second insulating film, and a second recess provided within the second insulating film on the upper surface side of the second insulating film. The lower substrate and the upper substrate are bonded together such that the second recess faces the first recess and the first member is housed within the first recess and the second recess. A method for manufacturing a semiconductor device, including the following.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the lower substrate and the upper substrate are bonded together such that the second insulating film is placed on the first insulating film and the second pad is placed on the first pad.

14. The first recess is provided within the chip region of the lower substrate, The second recess is provided within the chip region of the upper substrate, The method for manufacturing a semiconductor device according to claim 12.

15. The first recess is provided outside the chip area of ​​the lower substrate, The second recess is provided outside the chip area of ​​the upper substrate. The method for manufacturing a semiconductor device according to claim 12.

16. The method for manufacturing a semiconductor device according to claim 12, wherein the first recess or the second recess is formed in the first insulating film or the second insulating film using a drill or reamer, or is formed in the first insulating film or the second insulating film by etching.

17. The method for manufacturing a semiconductor device according to claim 12, wherein the first recess or the second recess is formed within a laminated film included in the first insulating film or the second insulating film, or is formed using a stepped structure within the laminated film.

18. The lower substrate is formed to include a plurality of first recesses as the first recesses, The upper substrate is formed to include a plurality of second recesses as the second recesses, The method for manufacturing a semiconductor device according to claim 12, wherein the lower substrate and the upper substrate are bonded together such that one or more of the plurality of second recesses face one or more of the plurality of first recesses.

19. The pitch between the plurality of second recesses is different from the pitch between the plurality of first recesses, or the plurality of first recesses include first recesses of multiple sizes, and the plurality of second recesses include second recesses of multiple sizes. A method for manufacturing a semiconductor device according to claim 18, further comprising adjusting the bonding position between the lower substrate and the upper substrate by bonding them together such that the first member is housed in a predetermined first recess among the plurality of first recesses and in a predetermined second recess among the plurality of second recesses.

20. A lower chip comprising a first substrate and / or a first film, and a first recess provided within the first substrate and / or the first film, An upper chip disposed on and in contact with the lower chip, comprising a second substrate and / or a second film, and a second recess provided within the second substrate and / or the second film and facing the first recess, The first member housed in the first recess and the second recess, A semiconductor device equipped with a semiconductor device.

Images