Semiconductor device and method for manufacturing the same

Abstract

This invention provides a semiconductor device in which JFET resistance is suppressed. [Solution] The device comprises a drift layer 2 of a first conductivity type, a base region 5 of a second conductivity type provided on the upper surface side of the drift layer, a main region 6 of the first conductivity type provided on the upper surface side of the base region, a first trench 81 sandwiching the main region and the base region from the side, a second trench 82 deeper than the first trench, insulated gate type electrode structures (9, 10) embedded in the first trench and the second trench respectively, and a gate bottom protection region 4 of the second conductivity type provided at the bottom of the insulated gate type electrode structure, wherein the gate bottom protection region is provided relative to the second trench.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Non-patent document 1 and patent document 1 below describe a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with a trench gate structure in which FinFET unit cells (functional units of the element) are arranged. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6631632 specification [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in Non-Patent Document 1 and Patent Document 1 mentioned above, the fin width (the width between adjacent gate trenches) is narrow. Therefore, carriers may be affected by the JFET resistance.

[0006] The present disclosure has been made in view of such circumstances, and an object thereof is to provide a semiconductor device in which JFET resistance is suppressed. [Means for Solving the Problems]

[0007] In order to solve the above problem, a semiconductor device according to one aspect of the present disclosure includes: a drift layer of a first conductivity type; a base region of a second conductivity type provided on an upper surface side of the drift layer; a main region of the first conductivity type provided on an upper surface side of the base region; a first trench sandwiching the main region and the base region from a lateral side, and a second trench deeper than the first trench; an insulated gate electrode structure embedded in each of the first trench and the second trench; and a gate bottom protection region of the second conductivity type provided at a bottom portion of the insulated gate electrode structure, wherein the gate bottom protection region is provided for the second trench. The gist of the present invention is as follows.

[0008] Furthermore, a width of the base region may be 0.2 μm or less.

[0009] Furthermore, the gate bottom protection region may be provided only for the second trench. Alternatively, the gate bottom protection region is provided for both the first trench and the second trench, and a width of the gate bottom protection region provided for the first trench may be smaller than a width of the first trench.

[0010] Furthermore, a depth of the second trench may be 1.4 times or more and 5 times or less a depth of the first trench.

[0011] Furthermore, the semiconductor device may include a plurality of each of the first trenches and the second trenches, and the first trenches and the second trenches may be alternately arranged along an arrangement direction.

[0012] Furthermore, the semiconductor device may include a plurality of each of the first trenches and the second trenches, and the plurality of first trenches may be provided between two i-th (i is a positive integer) and (i+1)-th second trenches along an arrangement direction.

[0013] Furthermore, the array may have multiple first trenches and second trenches, and the depth of the i-th (where i is a positive integer) second trench may be different from the depth of the i+1th second trench along the array direction.

[0014] Furthermore, the first semiconductor region of a second conductivity type may be provided, connecting the gate bottom protection region provided for the second trench to the base region.

[0015] Furthermore, the method may include forming a drift layer of a first conductivity type, forming a base region of a second conductivity type on the upper side of the drift layer, providing a main region of the first conductivity type on the upper side of the base region, forming a first trench and a second trench deeper than the first trench that sandwich the main region and the base region from the side, embedding an insulated gate type electrode structure in each of the first and second trenches, and forming a gate bottom protection region of the second conductivity type at the bottom of the insulated gate type electrode structure, wherein the gate bottom protection region may be formed relative to the second trench.

[0016] Furthermore, the width of the base region sandwiched between the first trench and the second trench may be formed to be 0.2 μm or less.

[0017] Furthermore, the depth of the second trench may be formed to be 1.4 times or more and 5 times or less the depth of the first trench.

[0018] Furthermore, multiple first trenches and second trenches may be formed so that they are alternately arranged along the alignment direction. Also, the gate bottom protection area may be formed only for the second trench. Alternatively, the gate bottom protection area may be formed for both the first and second trenches, and the width of the gate bottom protection area formed for the first trench may be smaller than the width of the first trench.

[0019] It should be noted that the above summary of disclosures does not enumerate all the necessary features of this disclosure. Furthermore, subcombinations of these features may also constitute a disclosure. [Effects of the Invention]

[0020] According to this disclosure, it is possible to provide a semiconductor device in which JFET resistance is suppressed. [Brief explanation of the drawing]

[0021] [Figure 1] This is a cross-sectional view showing a vertical cross-section of the semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view showing the horizontal cross-section as seen from the top side along line AA in Figure 1. [Figure 3] This is a cross-sectional view showing the vertical cross-section of Figure 2, viewed from the bottom to the top along line BB in Figure 2. [Figure 4] This is a cross-sectional view showing a vertical cross-section of a semiconductor device relating to a comparative example. [Figure 5] This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view of the process following Figure 5, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view of the process following Figure 5, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view of the process following Figures 6 and 7, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view of the process following Figures 6 and 7, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view of the process following Figures 8 and 9, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view of the process following Figures 8 and 9, illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a process cross-sectional view following Figures 10 and 11 illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a process cross-sectional view following Figures 10 and 11 illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] This is a process cross-sectional view following Figures 12 and 13 illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] This is a process cross-sectional view following Figures 12 and 13 illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] This is a cross-sectional view showing a vertical cross-section of the semiconductor device according to the second embodiment. [Figure 17] This is a cross-sectional view showing a vertical cross-section of the semiconductor device according to the third embodiment. [Figure 18] This is a cross-sectional view showing a vertical cross-section of the semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0022] The first to fourth embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to fourth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0023] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region that is reasonable according to the common technical knowledge of those skilled in the art.

[0024] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0025] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0026] Furthermore, in the following explanation, "approximately identical" or "approximately the same" for impurity concentration, width, depth, or thickness means not only that they are exactly identical, but also that they include a range that includes tolerances due to process variations. The range that includes tolerances is, for example, ±10%.

[0027] [First Embodiment] <Configuration of semiconductor device> FIGS. 1 to 3 are diagrams showing configuration examples of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device according to the first embodiment is an insulated gate semiconductor device. As shown in FIG. 1, in the semiconductor device according to the first embodiment, a case where an active element that is a power switching element is a vertical MOSFET (SiC-MOSFET) having a trench gate structure is illustrated as an example. The semiconductor device according to the first embodiment includes unit cells C1 to C4 which are functional units of the active element. The unit cells C1 to C4 are arranged in the left-right direction in FIG. 1. Although four unit cells C1 to C4 are shown in FIG. 1, a multi-channel structure in which more cells are similarly arranged may be configured.

[0028] The semiconductor device according to the first embodiment includes a first conductivity type (n - type) semiconductor region which is a drift layer 2. The drift layer 2 is formed of, for example, an epitaxial growth layer made of silicon carbide (SiC). The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to breakdown voltage specifications and the like. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less.

[0029] In each of the unit cells C1 to C4, a base region 5 which is a second conductivity type (p-type) semiconductor region is provided on an upper surface side of the drift layer 2. The base region 5 is formed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the base region 5 is, for example, 1×10 17 cm -3 or more and 1×10 18 cm -3 or less.

[0030] In each of the unit cells C1 to C4, a first conductivity type (n + type) semiconductor region having a higher impurity concentration than the drift layer 2, which is a first main region (source region) 6, is provided on an upper surface side of the base region 5. The source region 6 is formed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the source region 6 is, for example, 1×1017 cm -3 The above 5 x 10 18 cm -3 It is approximately as follows.

[0031] A trench 8 is provided in the direction normal to the upper surface of the source region 6 (depth direction), excavated downward from the upper surface of the source region 6 and penetrating the source region 6 and the base region 5. The trench 8 includes two types of trenches with different depths: a first trench 81 and a second trench 82 which is deeper than the first trench 81. When the first trench 81 and the second trench 82 are not distinguished, they are simply referred to as trench 8. The lower surface of trench 8 reaches the drift layer 2. The sides of trench 8 are in contact with the sides of the source region 6, the base region 5, and the drift layer 2.

[0032] As shown in Figure 1, each of the unit cells C1 to C4 has a mesa portion, which is a semiconductor region sandwiched between adjacent trenches 8, as a fin portion 15. More specifically, each of the unit cells C1 to C4 has a mesa portion, which is a semiconductor region sandwiched between adjacent first trenches 81 and second trenches 82, as a fin portion 15. The fin portion 15 includes the source region 6, the base region 5, and the portion of the drift layer 2 sandwiched between adjacent first trenches 81 and second trenches 82.

[0033] The width w1 of the fin portion 15 corresponds to the width of the portion sandwiched between the source region 6, the base region 5, and adjacent trenches 8 of the drift layer 2. The width w1 of the fin portion 15 is narrower than the width w2 of the trench 8. The width w1 of the fin portion 15 is, for example, about 0.2 μm or less. The width w1 of the fin portion 15 is, for example, about 0.05 μm or more and 0.2 μm or less. The width w1 of the fin portion 15 may be about 0.1 μm or more and 0.2 μm or less, or about 0.05 μm or more and 0.1 μm or less. By setting the width w1 of the fin portion 15 to about 0.2 μm or less, the FinFET structure described later can be realized.

[0034] Figure 2 shows a horizontal cross-section viewed from the top side along line AA in Figure 1. The vertical cross-section viewed from the bottom to the top of Figure 2 along line AA in Figure 2 corresponds to Figure 1. As shown in Figure 2, each of the trenches 8, gate insulating film 9, and gate electrode 10 has a planar pattern that extends linearly (striped) in one direction (up and down direction in Figure 2) parallel to each other. The trenches 8 are arranged parallel to each other with a gap (first gap) along a direction perpendicular to one direction (left and right direction in Figure 2, the arrangement direction). Between the trenches 8, in one direction (up and down direction in Figure 2), there is a source region 6 and a second conductivity type (p + The source region 6 and the base contact region 7, which are semiconductor regions of type (type), are arranged alternately and periodically. The source region 6 and the base contact region 7 may be in contact with each other.

[0035] As shown in Figure 1, the semiconductor device according to this embodiment has multiple first trenches 81 and multiple second trenches 82, and the first trenches 81 and the second trenches 82 are arranged alternately and periodically with a gap (first interval) between them along the left-right direction (arrangement direction) of the paper in Figure 1.

[0036] Figure 3 shows a vertical cross-section of Figure 2, viewed from the bottom to the top along the BB line in Figure 2. As shown in Figure 3, in each of the unit cells C1 to C4, the base contact region 7 is provided on the upper side of the base region 5. The depth of the base contact region 7 may be the same as the depth of the source region 6 shown in Figure 1, it may be deeper than the depth of the source region 6, or it may be shallower than the depth of the source region 6. The lower surface of the base contact region 7 is in contact with the upper surface of the base region 5. The side surface of the base contact region 7 is in contact with the side surface of the trench 8. The base contact region 7 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the base contact region 7 is higher than the impurity concentration of the base region 5. The impurity concentration of the base contact region 7 is, for example, 5 × 10⁻⁶. 19 cm -3 The above 5 x 10 20 cm -3The extent is as follows: In the cross-section shown in Figure 3, the fin portion 15 includes the portion sandwiched between the base contact region 7, the base region 5, and the adjacent trenches 8 of the drift layer 2.

[0037] A gate insulating film 9 is provided along the bottom and sides of the trench 8. A gate electrode 10 is embedded inside the trench 8 with the gate insulating film 9 interposed between them. The gate insulating film 9 and the gate electrode 10 constitute a trench-gate type insulated gate electrode structure (9,10). The insulated gate electrode structure (9,10) is embedded in both the first trench 81 and the second trench 82. In this example, neither the first trench 81 nor the second trench 82 are dummy trenches. The second trench 82 may be a dummy trench.

[0038] The thickness of the gate insulating film 9 is, for example, approximately 30 nm or more and 100 nm or less. As the gate insulating film 9, a single layer film of any one of the following can be used: silicon oxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these. As the material for the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities added, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0039] An insulating film 11, which is an interlayer insulating film, is provided on the upper surface of the gate electrode 10. As the insulating film 11, for example, a single layer of a silicon oxide film (SiO2 film) free of impurities, referred to as an "NSG film," a silicon oxide film with phosphorus added (PSG film), a silicon oxide film with boron added (BSG film), a silicon oxide film with phosphorus and boron added (BPSG film), or a silicon nitride film (Si3N4 film) can be used, or a composite film made by selecting and combining several of these.

[0040] As shown in Figures 1 and 3, the insulating film 11 is provided with an opening (contact hole) 11a that exposes at least a portion of the upper surface of the source region 6 and the base contact region 7. Inside the opening 11a, a silicide layer 12 is provided that is in direct contact with the upper surface of the source region 6 and the base contact region 7. The silicide layer 12 is made of nickel silicide (NiSi x It consists of the above and is provided for ohmic contact. Alternatively, 3C-SiC may be formed instead of the silicide layer 12.

[0041] A first main electrode (source electrode) 13 is provided so as to cover the upper surfaces of the insulating film 11 and the silicide layer 12. The source electrode 13 is provided separately from the gate wiring layer (not shown) which is electrically connected to the gate electrode 10. The source electrode 13 is made of a metal such as aluminum (Al) or copper (Cu), or an alloy such as aluminum-silicon (Al-Si) or aluminum-copper (Al-Cu). A contact plug that fills the opening 11a may be provided inside the opening 11a and on the upper surface of the silicide layer 12. The contact plug is made of a metal material such as tungsten (W), and its upper surface is in contact with the lower surface of the source electrode 13. Although not shown, a barrier metal layer may be provided on the lower side of the source electrode 13. The barrier metal layer is made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminated structure with Ti as the lower layer. The barrier metal layer may cover the insulating film 11.

[0042] As shown in Figure 1, the interior of the drift layer 2 contains a second conductivity type (p +A gate bottom protection region 4, which is a semiconductor region of type 82, is provided. The gate bottom protection region 4 is provided for the second trench 82. The statement that "the gate bottom protection region 4 is provided for the second trench 82" means that "the gate bottom protection region 4 is provided at the bottom of the insulated gate type electrode structure (9,10) embedded in the second trench 82." The gate bottom protection region 4 is provided only for the second trench 82 of the two trenches 82, the first trench 81. The gate bottom protection region 4 has the function of mitigating the electric field applied to the gate insulating film 9 on the lower surface of the second trench 82. The impurity concentration of the gate bottom protection region 4 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 The following applies: In Figure 1, the gate bottom protection region 4 may be electrically connected to the base region 5 on the front or back side. For example, as shown in Figure 3, the gate bottom protection region 4 may be electrically connected to the base region 5 by a first semiconductor region 3 of the second conductivity type (p-type) below the base contact region 7. The first semiconductor region 3 is long in the vertical direction of the paper in Figure 3, with its lower end connected to the gate bottom protection region 4 and its upper end connected to the base region 5. The impurity concentration of the first semiconductor region 3 is 1 × 10⁻⁶ 17 cm -3 The above is 1 x 10 19 cm -3 The following is an example. Note that the first semiconductor region 3 only needs to be located below at least a portion of the base contact region 7.

[0043] Figure 1 illustrates a case where the gate bottom protection area 4 is in contact with the lower surface of the trench 8, but the gate bottom protection area 4 may be separated from the lower surface of the trench 8. Figure 1 illustrates a case where the width of the gate bottom protection area 4 provided for the second trench 82 is approximately the same as the width w2 of the second trench 82, but the width of the gate bottom protection area 4 may be narrower or wider than the width w2 of the second trench 82, as long as electric field concentration is suppressed.

[0044] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. +A second main region (drain region) 1, which is a semiconductor region of type 1, is provided. Drain region 1 is made of a semiconductor substrate (SiC substrate), for example, SiC. The impurity concentration of drain region 1 is, for example, 1 × 10⁻⁶. 19 cm -3 The above is 3 x 10 20 cm -3 The extent is as follows. Furthermore, a buffer layer, dislocation conversion layer, or recombination promotion layer, etc., which is an n-type semiconductor region with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0045] A second main electrode (drain electrode) 14 is provided on the lower side of the drain region 1. For the drain electrode 14, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Between the drain region 1 and the drain electrode 14, nickel silicide (NiSi) is provided for ohmic contact. x A silicide layer consisting of the following may be provided.

[0046] During the switching operation of the semiconductor device according to the first embodiment, the source electrode 13 is set to ground potential, and a positive voltage is applied to the drain electrode 14. In this state, when a positive voltage above a threshold is applied to the gate electrode 10, an inversion layer (channel) is formed in the base region 5 of each unit cell C1 to C4, and the vertical MOSFET turns on. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, drift layer 2, the inversion layer of the base region 5, and the source region 6. On the other hand, when the voltage applied to the gate electrode 10 is below the threshold, an inversion layer is not formed in the base region 5, so the vertical MOSFET turns off, and no current flows from the drain electrode 14 to the source electrode 13.

[0047] In the semiconductor device according to the first embodiment, the vertical MOSFET has a FinFET structure. A FinFET structure is a so-called double-gate structure in which the width w1 of the fin portion 15 sandwiched between adjacent trenches 8 is narrowed by a predetermined width, and an inversion layer (channel) is formed in the base region 5 sandwiched between adjacent trenches 8. In a FinFET, when a gate voltage of a threshold value or higher is applied to the gate electrode 10, the voltage from both of the pair (two) gate electrodes 10 sandwiching the base region 5 is applied to the entire base region 5. Here, since the width w1 of the fin portion 15 has the above value, in each of the unit cells C1 to C4, one inversion layer is formed not near the interface between the base region 5 and the left and right gate insulating films 9, but in a region (bulk region) away from the interface between the base region 5 and the left and right gate insulating films 9. The inversion layer is formed in a region that is, for example, 0.05 μm or more and 0.1 μm or less from the interface between the base region 5 and the left and right gate insulating films 9. The inversion layer is formed in the horizontal central part of the base region 5.

[0048] Therefore, in the semiconductor device according to the first embodiment, compared to the case where an inversion layer is formed near the interface between the base region 5 and the gate insulating film 9, electrons moving within the inversion layer are less affected by the interface state density at the interface between the gate insulating film 9 and the base region 5. This allows for higher electron mobility and suppression of on-resistance.

[0049] In particular, SiC is a compound, and its interface state density is about an order of magnitude higher than that of Si. Therefore, the electron mobility of semiconductor devices using SiC is more susceptible to the influence of the interface state density than that of semiconductor devices using Si. For this reason, the FinFET structure is particularly effective for semiconductor devices using SiC.

[0050] The following describes the overview of this technology and the first trench 81 and the second trench 82 in more detail. In the following description, "having a first trench 81" means having a first trench 81 in addition to having an insulated gate type electrode structure (9,10) embedded in the first trench 81. Similarly, "having a second trench 82" means having a second trench 82 in addition to having an insulated gate type electrode structure (9,10) embedded in the second trench 82. First, the overview will be explained. Figure 4 is a diagram showing the longitudinal cross-sectional structure of a semiconductor device according to the comparative example. As shown in Figure 4, in the unit cells C1 to C4 of the semiconductor device according to the comparative example, the depth of the trenches 8a is approximately the same. The gate bottom protection region 4 is provided at the bottom of all trenches 8a in the unit cells C1 to C4. As a result, in the left-right direction of Figure 4, the distance between adjacent gate bottom protection regions 4 is approximately the same as the width w1 of the fin portion 15, increasing the JFET resistance and increasing the on-resistance. However, if the gate bottom protection region 4 is not provided, the electric field will concentrate at the bottom of the trench 8a. Since the band gap of SiC is wide, the electric field applied to the gate insulating film tends to be strong, making it important to protect the gate bottom.

[0051] In the semiconductor device according to this embodiment, as shown in Figure 1, the depth d2 of the second trench 82 is made greater than the depth d1 of the first trench 81. By making the trenches 8 have different depths in this way, the electric field tends to concentrate at the bottom of the deeper trench (second trench 82), and does not tend to concentrate at the bottom of the shallower trench (first trench 81). Therefore, in this embodiment, a gate bottom protection region 4 is provided at the bottom of the second trench 82 where the electric field tends to concentrate, and a gate bottom protection region 4 is not provided at the bottom of the first trench 81 where the electric field does not tend to concentrate. Furthermore, since the gate bottom protection regions 4 are provided every other trench 8, the spacing d3 (JFET width) between adjacent gate bottom protection regions 4 can be widened, and the JFET resistance can be suppressed.

[0052] The depth d2 of the second trench 82 is set to be, for example, 1.4 times or more and 5 times or less the depth d1 of the first trench 81. By setting the depth d2 of the second trench 82 to be 1.4 times or more the depth d1 of the first trench 81, it is possible to suppress the concentration of the electric field at the bottom of the first trench 81 and to secure a current path, which is the path through which the current flows. In other words, by setting the distance d4 from the bottom surface of the first trench 81 to the top surface of the gate bottom protection region 4 to be 0.4 times or more the depth d1 of the first trench 81, it is possible to suppress the concentration of the electric field at the bottom of the first trench 81 and to secure a certain area of ​​the drift layer 2 as a current path on the underside of the first trench 81. Figure 1 illustrates the flow of current (electrons). Note that the distance d4 corresponds to, for example, the difference between the depth d2 of the second trench 82 and the depth d1 of the first trench 81. Furthermore, by setting the depth d2 of the second trench 82 to approximately five times or less the depth d1 of the first trench 81, it is possible to prevent the difficulty of forming the second trench 82 from becoming too high. Also, the height (vertical dimension) of the fin section 15 is determined by the depth d1 of the first trench 81. Therefore, by designing all the first trenches 81 to have the same depth d1 as much as possible, it is possible to make the heights of multiple fin sections 15 as uniform as possible, although manufacturing tolerances will occur.

[0053] The width w2 of the trench 8 (Figure 2) is, for example, approximately 0.3 μm or more and 1.0 μm or less. The widths of the first trench 81 and the second trench 82 may be the same or different. Also, as shown in Figure 1, the depth d1 of the first trench 81 is, for example, approximately 0.7 μm or more and 1.3 μm or less. The spacing d3 between adjacent gate bottom protection regions 4 is, for example, approximately 0.8 μm or more and 2.0 μm or less. The distance d4 from the bottom surface of the first trench 81 to the top surface of the gate bottom protection region 4 is, for example, approximately 0.4 μm or more and 4.0 μm or less. The aspect ratio between the spacing d3 between adjacent gate bottom protection regions 4 and the difference between the depth d2 of the second trench 82 and the depth d1 of the first trench 81 (distance d4) may be approximately 2:1 or more and 1:2 or less.

[0054] According to the semiconductor device of the first embodiment, a first trench 81 and a second trench 82 which are deeper than the first trench 81 are provided, sandwiching the source region 6 and the base region 5 from the side, so that the electric field is less likely to concentrate in the first trench 81. Therefore, the electric field concentration in the first trench 81 can be mitigated without providing a gate bottom protection region 4 for the first trench 81. Furthermore, the gate bottom protection region 4 is provided only for the second trench 82, which is more prone to electric field concentration than the first trench 81. Since the gate bottom protection region 4 is selectively provided only in the area where the electric field is prone to concentration, the spacing d3 between the gate bottom protection regions 4 can be widened, and the JFET resistance can be suppressed. This suppresses the on-resistance.

[0055] Furthermore, according to the semiconductor device of the first embodiment, the width w1 of the base region 5 is 0.2 μm or less. In a FinFET structure with a narrow width w1, the gate bottom protection region 4 is not provided at the bottom of the first trench 81, and the gate bottom protection region 4 provided at the bottom of the second trench 82 is located at a position away from the lower base of the fin portion 15. Therefore, even when the width of the fin portion 15 is narrow, it is possible to reduce the influence of JFET resistance.

[0056] Furthermore, according to the semiconductor device of the first embodiment, the depth of the second trench 82 is 1.4 times or more and 5 times or less the depth of the first trench 81. Therefore, a certain area of ​​the drift layer 2 as a current path can be secured below the first trench 81, and on-resistance can be suppressed. In addition, it is possible to prevent the difficulty of forming the second trench 82 from becoming too high.

[0057] Furthermore, according to the semiconductor device of the first embodiment, the first trench 81 and the second trench 82 are arranged alternately along the arrangement direction. Therefore, since gate bottom protection areas 4 are provided every other trench 8, the spacing d3 (JFET width) between adjacent gate bottom protection areas 4 can be widened, and JFET resistance can be suppressed.

[0058] Furthermore, according to the semiconductor device of the first embodiment, since it includes a first semiconductor region 3 of a second conductivity type that connects the gate bottom protection region 4 provided with respect to the second trench 82 to the base region 5, the potential of the gate bottom protection region 4 can be fixed.

[0059] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing a semiconductor device according to the first embodiment shown in Figure 1 will be described with reference to Figures 1 and 5 to 15. Figures 6, 8, 10, 12, and 14 show vertical cross-sections of Figure 2 viewed from the bottom to the top along line AA. Figures 5, 7, 9, 11, 13, and 15 show vertical cross-sections of Figure 2 viewed from the bottom to the top along line BB.

[0060] As shown in Figure 5, first, n-type impurities such as nitrogen (N) are added to n + A semiconductor substrate (SiC substrate) 1 made of type 1 SiC is prepared. The upper surface of the SiC substrate 1 has an off-angle of approximately 3 degrees to 8 degrees from the {0001} plane. Next, a drift layer 2 is epitaxially grown on the upper surface of the SiC substrate 1. Then, a mask pattern M1 for ion implantation, made of a photoresist film or the like, is formed on the upper surface of the drift layer 2 using photolithography technology. Note that the mask pattern M1 may be a hard mask made of an insulating film or the like. An opening M1a is formed in the mask pattern M1 in the area where the first semiconductor region 3 will be provided. The opening M1a is provided in a position that overlaps with the area where the base contact region 7 will be formed in the future, and is positioned so as not to overlap as much as possible with the area where the source region 6 will be formed in the future. Then, using the mask pattern M1 as an ion implantation mask, ion implantation of p-type impurities such as aluminum (Al) is performed under predetermined ion implantation conditions to selectively form the first semiconductor region 3. After that, the mask pattern M1 is removed. Note that the mask pattern M1 may be a hard mask made of an insulating film or the like.

[0061] Next, as shown in Figures 6 and 7, p-type impurities such as aluminum (Al) are ion-implanted on the upper surface of the drift layer 2 under predetermined ion-implantation conditions to selectively form the base region 5. The lower surface of the formed base region 5 is in contact with the upper surface of the first semiconductor region 3. Subsequently, a source region 6, shown in Figure 6, and a base contact region 7, shown in Figure 7, are selectively formed on the upper surface of the base region 5. The source region 6 is selectively formed by ion-implanting n-type impurities such as nitrogen (N) on the upper surface of the base region 5 under predetermined ion-implantation conditions. The base contact region 7 is selectively formed by ion-implanting p-type impurities such as aluminum (Al) on the upper surface of the base region 5 under predetermined ion-implantation conditions.

[0062] Then, as shown in Figures 8 and 9, an etching mask pattern M2 made of a photoresist film or the like is formed on the upper surface of the source region 6 and the base contact region 7 using photolithography technology. The mask pattern M2 may also be a hard mask made of an insulating film or the like. The mask pattern M2 has a plurality of openings M2a that are spaced apart and periodically arranged in the left-right direction of the paper in Figures 8 and 9. Then, using the mask pattern M2 as an etching mask, a second trench 82 with a depth d2 is selectively formed in the depth direction from the upper surface of the source region 6 and the base contact region 7 by dry etching technology such as reactive ion etching (RIE). Multiple second trenches 82 are spaced apart and periodically arranged in the left-right direction of the paper in Figures 8 and 9. As shown in Figure 9, the openings M2a of the mask pattern M2 are located offset from the first semiconductor region 3 in the left-right direction of the paper in Figure 9. Therefore, the right side portion of the first semiconductor region 3 remains unetched and is in contact with the right side wall of the second trench 82.

[0063] Subsequently, as shown in Figures 8 and 9, p-type impurities such as aluminum (Al) are ion-implanted into the drift layer 2 from the lower surface of the second trench 82 under predetermined ion implantation conditions to selectively form the gate bottom protection region 4. As shown in Figure 9, the side surface of the formed gate bottom protection region 4 is in contact with the side surface of the first semiconductor region 3.

[0064] Next, by performing heat treatment (activation annealing), the p-type or n-type impurities ion-implanted in the first semiconductor region 3, gate bottom protection region 4, base region 5, source region 6, and base contact region 7, respectively, are simultaneously activated. Here, we illustrate a case where activation annealing is performed all at once after all ion implantation steps, but multiple activation annealing steps may be performed individually after each ion implantation step.

[0065] Next, as shown in Figures 10 and 11, a gate insulating film 9 is formed on the lower and side surfaces of the second trench 82 by thermal oxidation or CVD. Then, a polysilicon layer (doped polysilicon layer) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited to fill the inside of the second trench 82 using CVD technology or the like. After that, a portion of the polysilicon layer is selectively removed by dry etching or the like. As a result, as shown in Figures 10 and 11, an insulated gate electrode structure (9,10) consisting of the gate insulating film 9 and the gate electrode 10 is formed inside the second trench 82. After that, the mask pattern M2 is removed.

[0066] Then, as shown in Figures 12 and 13, an etching mask pattern M3 made of a photoresist film or the like is formed on the upper surface of the source region 6 and the base contact region 7 using photolithography technology. Note that the mask pattern M3 may be a hard mask made of an insulating film or the like. The mask pattern M3 has a plurality of openings M3a that are spaced apart and arranged periodically in the left-right direction of the paper in Figures 12 and 13. Each of the openings M3a is located between adjacent second trenches 82 in the left-right direction of the paper in Figures 12 and 13. Then, using the mask pattern M3 as an etching mask, first trenches 81 with a depth of d1 are selectively formed in the depth direction from the upper surface of the source region 6 and the base contact region 7 by dry etching technology such as reactive ion etching (RIE). As a result, first trenches 81 with a depth of d1 and second trenches 82 with a depth of d2 are formed alternately in the left-right direction of the paper in Figures 12 and 13. Note that depth d2 is formed to be deeper than depth d1. More specifically, the depth d2 of the second trench 82 is formed to be approximately 1.4 times or more and 5 times or less the depth d1 of the first trench 81. Since the first trench 81 and the second trench 82 are formed separately, the second trench 82 can be formed deeper than the first trench 81. In addition, the width w2 of the first trench 81 and the second trench 82 and the arrangement pitch of the first trench 81 and the second trench 82 are adjusted so that the width of the base region 5 sandwiched between the first trench 81 and the second trench 82 is approximately 0.2 μm or less. A gate bottom protection region 4 is not formed at the bottom of the first trench 81.

[0067] Subsequently, a gate insulating film 9 is formed on the lower and side surfaces of the first trench 81 by thermal oxidation or CVD. Next, a polysilicon layer (doped polysilicon layer) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited to fill the inside of the first trench 81 using CVD technology or the like. Then, a portion of the polysilicon layer is selectively removed by dry etching or the like. As a result, as shown in Figures 12 and 13, an insulated gate electrode structure (9,10) consisting of the gate insulating film 9 and the gate electrode 10 is formed inside the first trench 81. The semiconductor region remaining between the first trench 81 and the second trench 82 constitutes the fin portion 15. After that, the mask pattern M3 is removed. The gate insulating films 9 and gate electrode 10 of the first trench 81 and the second trench 81 may be formed simultaneously.

[0068] Next, as shown in Figures 14 and 15, an insulating film 11, which is an interlayer insulating film, is deposited on the upper surface of the insulated gate electrode structure (9,10) using CVD technology or the like. Then, a portion of the insulating film 11 is selectively removed using photolithography technology and dry etching technology or the like to create openings (contact holes) 11a in the insulating film 11 that expose the upper surfaces of the source region 6 and the base contact region 7. After that, heat treatment (reflow) may be performed to flatten the insulating film 11.

[0069] Next, a silicide layer 12 and a source electrode 13 (see Figure 1) are sequentially formed on the upper surfaces of the source region 6 and base contact region 7 using sputtering technology or vapor deposition. A barrier metal layer may also be formed on the lower surface of the source electrode 13.

[0070] Next, the SiC substrate 1 is thinned from the bottom side by grinding or chemical mechanical polishing (CMP) to adjust its thickness, thereby creating the drain region 1. Then, a drain electrode 14 (see Figure 1) made of titanium (Ti), nickel (Ni), gold (Au), etc. is formed on the entire bottom surface of the drain region 1 by sputtering or vapor deposition. In this way, the silicon carbide semiconductor device shown in Figure 1 is completed.

[0071] In the method for forming the first semiconductor region 3 described above, p-type impurities were ion-implanted first as shown in Figure 5, and then the second trench 82 was formed as shown in Figure 9. However, this technology is not limited to this. The second trench 82 may be formed first, and then p-type impurities may be ion-implanted to form the first semiconductor region 3. In this case, the p-type impurities are ion-implanted obliquely toward one side wall of the second trench 82.

[0072] Furthermore, in the semiconductor device manufacturing method described above, the second trench 82 is formed first and then the first trench 81 is formed, but the first trench 81 may be formed first and then the second trench 82 may be formed.

[0073] According to the semiconductor device manufacturing method of the first embodiment, a first trench 81 and a second trench 82, which are deeper than the first trench 81, are formed sandwiching the source region 6 and the base region 5 from the side. This makes it difficult for the electric field to concentrate at the bottom of the shallower first trench 81. Therefore, the electric field concentration in the first trench 81 can be mitigated without forming a gate bottom protection region 4 in the first trench 81. Furthermore, the gate bottom protection region 4 is formed only in the second trench 82, which is more prone to electric field concentration than the first trench 81. Since the gate bottom protection region 4 is selectively formed only in the area prone to electric field concentration, the spacing d3 between the gate bottom protection regions 4 can be widened, and the JFET resistance can be suppressed. This suppresses the on-resistance.

[0074] Furthermore, according to the semiconductor device manufacturing method of the first embodiment, the width w1 of the base region 5 is formed to 0.2 μm or less by adjusting the distance between the first trench 81 and the second trench 82. In a FinFET structure with a narrow width w1, the gate bottom protection region 4 is not formed at the bottom of the first trench 81, and the gate bottom protection region 4 formed at the bottom of the second trench 82 is located at a position lower than the lower base of the fin portion 15. Therefore, even if the width of the fin portion 15 is formed narrowly, it can be made less susceptible to the influence of JFET resistance.

[0075] Furthermore, according to the semiconductor device manufacturing method of the first embodiment, the depth of the second trench 82 is formed to be 1.4 times or more and 5 times or less the depth of the first trench 81. Therefore, a certain area of ​​the drift layer 2 as a current path can be secured below the first trench 81, and on-resistance can be suppressed. In addition, it is possible to prevent the difficulty of forming the second trench 82 from becoming too high.

[0076] Furthermore, according to the semiconductor device manufacturing method of the first embodiment, first trenches 81 and second trenches 82 are formed alternately along the arrangement direction. Therefore, since gate bottom protection regions 4 are formed every other trench 8 in the arranged trenches 8, the spacing d3 (JFET width) between adjacent gate bottom protection regions 4 can be widened, and JFET resistance can be suppressed.

[0077] [Second Embodiment] The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figure 1, in that, as shown in Figure 16, a plurality of first trenches 81 are provided between the i-th (where i is a positive integer) and i+1-th second trenches 82 along the array direction.

[0078] To distinguish between the two second trenches 82 shown in Figure 16, the second trench 82 on the left side in the left-right direction of the paper is called second trench 82a, and the second trench 82 on the right side in the left-right direction of the paper is called second trench 82b. When second trenches 82a and 82b are not distinguished from each other, they are simply called second trench 82. For example, second trench 82a corresponds to the i-th second trench 82 along the array direction, and second trench 82b corresponds to the (i+1)-th second trench 82 along the array direction. Two first trenches 81 are provided between second trench 82a and second trench 82b. The number of first trenches 81 provided between second trench 82a and second trench 82b is not limited to 2. The number of first trenches 81 (positive integer) provided between second trench 82a and second trench 82b may be, for example, 2 or more and 5 or less, or it may be, for example, 2 or 3. The wider the gap between the second trench 82a and the second trench 82b, the more likely the electric field is to concentrate at the bottom of the first trench 81. Therefore, the number of first trenches 81 provided between the second trench 82a and the second trench 82b may be determined according to the gap between the second trench 82a and the second trench 82b and the difference in trench depth. The arrangement of first trenches 81 and second trenches 82 is repeated along the direction of arrangement, such as one second trench 82, two first trenches 81, one second trench 82, two first trenches 81, and so on.

[0079] According to the semiconductor device of the second embodiment, since the number of second trenches 82 is reduced, the gap d3 between adjacent gate bottom protection regions 4 can be further widened, and the JFET resistance can be further suppressed.

[0080] [Third Embodiment] The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Figure 1, in that, as shown in Figure 17, the depth of the i-th (where i is a positive integer) second trench 82 and the (i+1)th second trench 82 are different along the array direction.

[0081] As shown in Figure 17, the second trench 82 includes a second trench 82 having a depth d2c and a second trench 82 having a depth d2d that is different from the depth d2c. The second trench 82 having a depth d2c is called the second trench 82c, and the second trench 82 having a depth d2d is called the second trench 82d, and they are distinguished from each other. When the second trench 82c and the second trench 82d are not distinguished from each other, they are simply called the second trench 82. For example, the second trench 82c corresponds to the i-th second trench 82 along the array direction, and the second trench 82d corresponds to the (i+1)th second trench 82 along the array direction. The depth d2c of the second trench 82c and the depth d2d of the second trench 82d are set to be approximately 1.4 times or more and 5 times or less the depth d1 of the first trench 81. Within that range, the depth d2c of the second trench 82c is greater than the depth d2d of the second trench 82d. Therefore, the gate bottom protection area 4 provided at the bottom of the second trench 82c is located at a deeper position than the gate bottom protection area 4 provided at the bottom of the second trench 82d. In other words, adjacent gate bottom protection areas 4 are provided along the diagonal direction of the paper in Figure 17.

[0082] In the semiconductor device according to the third embodiment, since the depths of the second trench 82c and the second trench 82d are different, the spacing d3 between adjacent gate bottom protection regions 4 becomes the spacing in the diagonal direction of the paper in Figure 17. As a result, the spacing d3 can be widened compared to the first embodiment shown in Figure 1, and the JFET resistance can be further suppressed.

[0083] [Fourth Embodiment] The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 1 in that, as shown in Figure 18, the gate bottom protection area 4 is provided for both the first trench 81 and the second trench 82.

[0084] The gate bottom protection region 4 provided at the bottom of the first trench 81 is called the gate bottom protection region 4a, and is distinguished from the gate bottom protection region 4 provided at the bottom of the second trench 82. When the gate bottom protection region 4a and the gate bottom protection region 4 are not distinguished, it is simply called the gate bottom protection region 4. In the left-right direction of Figure 18, the width of the gate bottom protection region 4a is made smaller than the width of the first trench 81. Note that "the gate bottom protection region 4a is provided at the first trench 81" means "the gate bottom protection region 4a is provided at the bottom of the insulated gate type electrode structure (9,10) embedded in the first trench 81". The gate bottom protection region 4a may be electrically connected to the base region 5 or it may be at a floating potential. The gate bottom protection region 4a can be fabricated, for example, by injecting p-type impurities at the same timing as the first semiconductor region 3.

[0085] According to the semiconductor device of the fourth embodiment, since a gate bottom protection region 4a is provided at the bottom of the first trench 81, the electric field is less likely to concentrate at the bottom of the first trench 81. Furthermore, since the width of the gate bottom protection region 4a is made smaller than the width of the first trench 81, it is possible to suppress the p-type gate bottom protection region 4a from entering between the p-type region at the lower base of the fin portion 15 and the drift layer 2 below it, thereby suppressing an increase in on-resistance.

[0086] [Other embodiments] As described above, the first to fourth embodiments of this disclosure have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0087] For example, although a MOSFET was given as an example of a semiconductor device according to the first to fourth embodiments, n + Instead of drain region 1 of type p +This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0088] A current diffusion layer (CSL) of type 1 conductivity (n-type) with a higher impurity concentration than that of the drift layer 2 may be selectively provided on the upper surface of the drift layer 2. The configuration when a current diffusion layer is provided will be described below. The lower surface of the current diffusion layer is in contact with the upper surface of the drift layer 2. The current diffusion layer is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the current diffusion layer is, for example, 5 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3 The following is the extent of the configuration: The lower surface of the base region 5 is in contact with the upper surface of the current diffusion layer. The left and right sides of the trench 8 are in contact with the current diffusion layer instead of the drift layer 2, and the lower surface of the trench 8 reaches the current diffusion layer. The current diffusion layer is located between adjacent trenches 8. The gate bottom protection region 4 is provided within the current diffusion layer.

[0089] Furthermore, although the semiconductor layer of the semiconductor device according to the first to fourth embodiments was made of silicon carbide (SiC), it may also be made of silicon (Si). The fact that the semiconductor layer of the semiconductor device is made of SiC or Si may include being mainly composed of SiC or Si.

[0090] Furthermore, the configurations disclosed in the first to fourth embodiments can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of symbols]

[0091] 1…Drain region (SiC substrate) 2…Drift layer 3…First Semiconductor Area 4,4a…Gate bottom protection area 5…Base area 6…Source area 7…Base contact area 8,8a...Trench 9…Gate insulating film 10… Guard Stop 11… Insulating film 11a...Opening (contact hole) 12…Silicide layer 13…First main electrode (source electrode) 14…Second main electrode (drain electrode) 15…Fin section 81... Trench No. 1 82, 82a, 82b, 82c, 82d... Second trench C1, C2, C3, C4... Unit cells d3...interval d4… distance M1, M2, M3… Mask Patterns M1a,M2a,M3a…opening w1, w2... width

Claims

1. A first conductive drift layer, A second conductivity type base region provided on the upper surface side of the drift layer, A first conductivity type main region provided on the upper surface side of the base region, A first trench sandwiches the main region and the base region from the side, and a second trench is deeper than the first trench. An insulated gate type electrode structure embedded in the first trench and the second trench, A gate bottom protection region of the second conductivity type provided at the bottom of the insulated gate type electrode structure, Equipped with, The gate bottom protection area is provided with respect to the second trench. Semiconductor equipment.

2. The width of the base region is 0.2 μm or less. The semiconductor device according to claim 1.

3. The gate bottom protection area is provided only for the second trench. The semiconductor device according to claim 1 or 2.

4. The gate bottom protection area is provided for both the first trench and the second trench. The width of the gate bottom protection area provided for the first trench is smaller than the width of the first trench. The semiconductor device according to claim 1 or 2.

5. The depth of the second trench is 1.4 times or more and 5 times or less the depth of the first trench. The semiconductor device according to claim 1 or 2.

6. The first trench and the second trench each have a plurality of, The first trench and the second trench are arranged alternately along the direction of arrangement. The semiconductor device according to claim 1 or 2.

7. The first trench and the second trench each have multiple trenches, A plurality of the first trenches are provided between the i-th (where i is a positive integer) and i+1-th second trenches along the array direction. The semiconductor device according to claim 1 or 2.

8. The first trench and the second trench each have multiple trenches, The depth of the i-th (where i is a positive integer) second trench is different from the depth of the i+1th second trench along the array direction. The semiconductor device according to claim 1 or 2.

9. The first semiconductor region of a second conductivity type connects the gate bottom protection region provided in the second trench to the base region. The semiconductor device according to claim 1 or 2.

10. To form a first-type conductive drift layer, A base region of the second conductivity type is formed on the upper surface side of the drift layer, The first conductivity type main region is provided on the upper surface side of the base region, A first trench and a second trench deeper than the first trench are formed, sandwiching the main region and the base region from the side. The first trench and the second trench are each embedded with an insulated gate type electrode structure, A gate bottom protection region of the second conductivity type is formed at the bottom of the insulated gate type electrode structure, Includes, The gate bottom protection area is formed with respect to the second trench. A method for manufacturing a semiconductor device.

11. The width of the base region sandwiched between the first trench and the second trench is formed to be 0.2 μm or less. A method for manufacturing a semiconductor device according to claim 10.

12. The depth of the second trench is formed to be 1.4 times or more and 5 times or less the depth of the first trench. A method for manufacturing a semiconductor device according to claim 10 or 11.

13. Multiple first trenches and second trenches are formed such that the first trenches and second trenches are arranged alternately along the direction of arrangement. A method for manufacturing a semiconductor device according to claim 10 or 11.

14. The gate bottom protection region is formed only with respect to the second trench. A method for manufacturing a semiconductor device according to claim 10 or 11.

15. The gate bottom protection region is formed over both the first trench and the second trench. The width of the gate bottom protection area formed in relation to the first trench is smaller than the width of the first trench. A method for manufacturing a semiconductor device according to claim 10 or 11.

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