Power converter and method for setting the upper limit of carrier frequency

Abstract

The present invention provides a power converter that can suppress unstable operation caused by transitions in the number of synchronous PWM pulses depending on the output frequency range used. [Solution] The power conversion device comprises a circuit that converts DC power to AC power using a pulse width modulation method, and a control device that controls the circuit. The control device controls the circuit to operate in an asynchronous mode in which the carrier and the modulated wave are generated asynchronously, and a synchronous mode in which the number of carrier pulses per period of the modulated wave is set in multiples of 3 from the high frequency side to the low frequency side, from the first to the nth order, and the kth order (k

Description

[[TECHNICAL FIELD]]

[0001] The present invention relates to a power conversion device and a carrier frequency upper limit setting method. [[BACKGROUND ART]]

[0002] A power conversion device that converts DC power into AC power by a Pulse Width Modulation (PWM) method is known. Patent Document 1 describes a power conversion device that converts a DC voltage into an AC voltage having a desired amplitude and frequency by performing on-off control on a plurality of switching elements via PWM.

[0003] The above power conversion device operates in variable voltage variable frequency control that increases the modulation rate in proportion to the frequency, i.e., asynchronous mode, in a region where the frequency of the AC voltage fundamental wave is low. Further, after the amplitude of the AC voltage reaches the maximum, the above power conversion device operates in constant voltage variable frequency control that increases only the frequency of the AC voltage, i.e., synchronous mode. [[PRIOR ART DOCUMENTS]] [[PATENT DOCUMENTS]]

[0004] [[Patent Document 1]] Japanese Patent Laid-Open No. 2014-204560 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] For the PWM carrier frequency in a power converter, an upper limit frequency is set for various reasons such as increased electromagnetic noise and increased leakage current. Therefore, in the synchronous mode of the power converter, when increasing the output frequency, once the carrier frequency reaches the upper limit frequency, control is performed to reduce the number of carrier pulses per one cycle of the modulated wave (hereinafter also referred to as the number of synchronous PWM pulses) to lower the carrier frequency band. That is, when using the power converter, if the output frequency is changed in the synchronous mode, the number of synchronous PWM pulses transitions at a position where the carrier frequency is close to the upper limit frequency.

[0006] On the other hand, when the number of synchronous PWM pulses transitions, the operation of the power converter, that is, load driving, tends to become unstable. For this reason, there is a demand from users that transitions of the number of synchronous PWM pulses should not occur frequently in an output frequency range that is frequently used.

[0007] An object of the present invention is to provide a power converter capable of suppressing unstable operation caused by transitions of the number of synchronous PWM pulses according to the output frequency range to be used. [Means for Solving the Problem]

[0008] A power converter according to one embodiment comprises: a circuit that converts DC power to AC power by a pulse width modulation method; and a control device that controls the circuit. The control device executes: processing for controlling the circuit to operate in an asynchronous mode in which a carrier and a modulated wave are generated asynchronously, and a synchronous mode that is used in an output frequency range higher than that in the asynchronous mode, where the number of carrier pulses per one cycle of the modulated wave is set from the first order to the n-th order in multiples of 3 from the high frequency side to the low frequency side; processing for setting the upper limit frequency of the k-th order (k < n) carrier frequency range to a higher frequency side than a common upper limit frequency initially set for each order of the synchronous mode; and processing for setting the upper limit frequency of the (k+1)-th order carrier frequency range to a lower frequency side than the common upper limit frequency.

[0009] A carrier frequency upper limit setting method according to one embodiment is a method for setting an upper limit of a carrier frequency in a power conversion device that operates in an asynchronous mode that converts DC power into AC power by a pulse width modulation method and generates a carrier and a modulated wave asynchronously, and a synchronous mode that is used in an output frequency range higher than the output frequency range in the asynchronous mode, and in which the number of carrier pulses per cycle of the modulated wave is set from a high frequency side to a low frequency side from the first order to the n-th order in multiples of 3, wherein a control device included in the power conversion device performs: processing for setting, for each order of the synchronous mode, an upper limit frequency of a k-th order (k < n) carrier frequency range to a higher frequency side than a commonly used common upper limit frequency that is initially set; and processing for setting an upper limit frequency of a (k+1)-th order carrier frequency range to a lower frequency side than the common upper limit frequency. Effects of the Invention

[0010] According to one embodiment, it is possible to provide a power conversion device capable of suppressing unstable operation caused by transition of the number of synchronous PWM pulses according to the output frequency range to be used. Brief Description of Drawings

[0011] [Figure 1A] It is a diagram showing an example of the hardware configuration of an inverter device according to the present embodiment. [Figure 1B] It is a diagram showing an example of the functional block configuration of an inverter device according to the present embodiment. [Figure 2] It is a diagram showing the relationship between carrier frequency and output frequency for each number of synchronous PWM pulses according to a reference example. [Figure 3] It is a diagram showing the relationship between carrier frequency and output frequency for each number of synchronous PWM pulses according to a study example. [Figure 4] It is a diagram showing the relationship between carrier frequency and output frequency for each number of synchronous PWM pulses according to the example of the present embodiment. [Figure 5] It is a flow chart showing an example of processing related to setting of a carrier frequency in an inverter device according to the present embodiment. [Figure 6]This figure shows examples of various waveforms in PWM control for inverter devices. [Figure 7] This figure shows an example of an operating pattern in an inverter device. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described below. In the embodiments, the same or corresponding components are denoted by the same reference numerals, and repeated descriptions are omitted except where necessary.

[0013] (The inventor's review process) Figure 6 shows examples of waveforms in PWM control in an inverter device. An inverter device is an example of a power conversion device. Figure 6 shows a modulated wave, which is obtained by normalizing the command value of the AC voltage with the DC voltage of the inverter device, a triangular wave-shaped carrier, and a PWM pulse, which is an on / off command to the switching elements of the inverter device. Note that Figure 6 shows the waveforms for one phase of the three-phase AC. As shown in Figure 6, the PWM pulse is based on the relative magnitudes of the modulated wave and the carrier; if the modulated wave is larger than the carrier, it becomes an on command, and if the modulated wave is smaller than the carrier, it becomes an off command.

[0014] Figure 7 shows an example of an operating pattern in an inverter device. In an inverter device, in the region where the frequency of the output AC voltage, i.e., the output frequency, is low, the AC voltage is output using the asynchronous mode shown in Figure 7. The asynchronous mode is a method of generating PWM pulses using a carrier with a sufficiently high frequency relative to the frequency of the modulated wave, without fixing the phase relationship between the modulated wave and the carrier. In other words, the asynchronous mode is a mode in which the carrier and the modulated wave are generated asynchronously.

[0015] In the asynchronous mode region, in the region where the frequency of the modulated wave is low, as shown in FIG. 7, the carrier frequency is sufficiently high relative to the modulated wave frequency, so distortion of the AC voltage is small. However, as the frequency of the modulated wave increases, the distortion of the AC voltage increases. Therefore, when the frequency of the modulated wave reaches or exceeds a certain value, the operation mode shifts from the asynchronous mode to the synchronous mode.

[0016] In the synchronous mode, as the frequency of the modulated wave increases, the number of carrier pulses per one cycle of the modulated wave, that is, the number of synchronous PWM pulses, decreases stepwise while taking values of multiples of 3, based on the symmetry of three-phase AC.

[0017] The operation pattern shown in FIG. 7 is an example where a motor is connected as a driving load of an inverter device. In this example, asynchronous PWM control is performed in the low-speed operation section, which is the operation section from startup to a steady operation speed (steady rotation speed) (the operation range corresponding to section (701) in the figure). Then, in the high-speed operation section that is the operation section from the steady operation speed to speeds equal to or higher than the steady operation speed, control is performed such that the number of synchronous PWM pulses is switched in the order of 9 pulses, 6 pulses, and 3 pulses as the motor rotation speed (rotational speed) increases.

[0018] As shown in FIG. 7, at startup when the motor rotation speed is low and in the low-speed operation range (section (701) in the figure), PWM control in the asynchronous mode with a fixed carrier frequency is performed. At that time, control is performed to increase the motor rotation speed to the steady operation speed and then maintain the steady operation speed. Since the carrier frequency is fixed in section (701), as shown in FIG. 7, generated noise and leakage current can be suppressed to equal to or lower than the allowable values.

[0019] Furthermore, in the range of PWM control in synchronous mode, that is, in the sections (702) to (704) in the figure, asynchronous PWM control is switched to synchronous PWM control, and the number of pulses is switched while increasing or decreasing the carrier frequency such that generated noise and leakage current are equal to or less than allowable values. In the above section (702), control is performed with the number of synchronous PWM pulses set to 9 pulses, but as the rotational speed increases, the generated noise and leakage current increase to near the allowable values. Therefore, an upper limit frequency is set for the carrier frequency, and control is performed such that the carrier frequency does not exceed the upper limit frequency. Note that the upper limit frequency of the carrier frequency is determined based on, for example, the processing load of the control device, generated noise, leakage current, characteristics of the switching element, and the like.

[0020] By the way, some users frequently change the output frequency for use in an output frequency range of 400 to 1000 Hz, for example. In this case, there are transitions of synchronous PWM pulses, and a phenomenon occurs in which the behavior of the load driven by the power conversion device is unstable in the output frequency region near the switching point of the number of synchronous PWM pulses. Therefore, for such users, there is a need to reduce transitions in the number of synchronous PWM pulses at frequently used output frequencies.

[0021] In order to address the above need, the inventor set the number of synchronous PWM pulses to 3, 9, 15, 21, 27, and 33, which are odd multiples of 3, starting from the high frequency side of the output frequency. Furthermore, the inventor set the upper limit of the carrier frequency to 10 kHz. Note that setting the number of synchronous PWM pulses to "odd multiples" of 3 rather than just multiples of 3 is based on the inventor's study results and experience that an inverter device can be operated relatively stably. In this case, the output frequency ranges (Hz) used for each number of synchronous PWM pulses are as follows. 33 pulses: approx. 60 Hz to approx. 300 Hz, 27 pulses: approx. 300 Hz to approx. 370 Hz, 21 pulses: approx. 370 Hz to approx. 476 Hz, 15 pulses: approx. 476 Hz to approx. 666 Hz, 9 pulses: approx. 666 Hz to approx. 1111 Hz, 3 pulses: approx. 1111 Hz and above.

[0022] However, another user most frequently uses the 500-700Hz output frequency range. In this case, if the upper and lower limits of the carrier frequency range per synchronous PWM pulse count remain at their default settings, transitions in the synchronous PWM pulse count frequently occur between 15 pulses and 9 pulses. As a result, it was found that the output current jumps during transitions in the synchronous PWM pulse count, causing the inverter device to become unstable, and furthermore, frequent changes in the carrier tone occur.

[0023] Therefore, in order to broaden the output frequency band of the 15 pulses, the inventor removed the upper limit on the carrier frequency from 10 kHz to 11 kHz.

[0024] However, this resulted in the lower limit of the output frequency at 15 pulses being too high, causing frequent transitions between 15 and 21 pulses in the synchronous PWM pulse count.

[0025] In other words, even when attempting to broaden the output frequency range corresponding to a specific number of synchronous PWM pulses in an inverter device, it is not possible to broaden it sufficiently, which can lead to frequent transitions in the number of synchronous PWM pulses.

[0026] Due to the circumstances described above, there is a need for an inverter device that can suppress unstable operation caused by transitions in the number of synchronous PWM pulses in the output frequency domain during synchronous mode, depending on the output frequency domain used.

[0027] (Embodiment) In this embodiment, we describe an example of a method for suppressing unstable operation associated with switching the number of synchronous PWM pulses in synchronous mode.

[0028] Specifically, the inverter device according to the present embodiment includes a circuit that converts DC power into AC power by a PWM (Pulse Width Modulation) method, and a control device that controls the circuit. The control device controls the circuit to operate in an asynchronous mode and a synchronous mode. The asynchronous mode is a mode in which a carrier and a modulation wave are generated asynchronously. The synchronous mode is used in an output frequency range higher than that in the asynchronous mode, and is a mode in which the number of carrier pulses per cycle of the modulation wave is set from the first order to the n-th order in multiples of 3 from the high frequency side to the low frequency side. The control device executes a process of setting the upper limit frequency of the k-th (k < n) carrier frequency range to a higher frequency side than the common upper limit frequency initially set for each order of the synchronous mode. The control device also executes a process of setting the upper limit frequency of the (k+1)-th carrier frequency range to a lower frequency side than the common upper limit frequency.

[0029] That is, the inverter device according to the present embodiment is configured such that the upper limit frequency of the carrier frequency range corresponding to a desired number of synchronous PWM pulses (the k-th order) can be set higher than the initially set common upper limit frequency. Further, the inverter device is configured such that the lower limit frequency of the carrier frequency range corresponding to the desired number of synchronous PWM pulses can be set lower than the lower limit frequency determined by the initial setting. In other words, in the PWM control in the synchronous mode, the inverter device according to the present embodiment is configured such that the pulse number switching point on the high frequency side of the output frequency range corresponding to the desired number of synchronous PWM pulses can be moved to a higher frequency side than the frequency determined by the initial setting. Further, the inverter device is configured such that the pulse number switching point on the low frequency side of the output frequency range corresponding to the desired number of synchronous PWM pulses can be moved to a lower frequency side than the frequency determined by the initial setting.

[0030] Figure 1A shows an example of the hardware configuration of an inverter device according to this embodiment. The inverter device 100 according to this embodiment includes a DC conversion circuit 102, a DC smoothing circuit 103, an AC conversion circuit 104, a control device 120, an operating device 127, and a display device 128. The control device 120 is composed of, for example, a computer, a microcontroller, an IC chip, an FPGA, an electronic circuit board, etc.

[0031] The control device 120 includes, for example, a processor 121, memory 122, interface 124, storage 123, and bus 125. The processor 121, memory 122, interface 124, and storage 123 are each connected to the bus 125. The processor 121 is, for example, a CPU, MPU, GPU, etc. The memory 122 is, for example, RAM, ROM, etc. The interface 124 is a module that handles signal input and output. The storage 123 is, for example, an SSD, HDD, flash memory, etc.

[0032] A predetermined program 126 is stored in memory 122 or storage 123. The processor 121 reads and executes this program 126, thereby functioning as various functional blocks.

[0033] The operating device 127 is composed of, for example, key buttons, a joystick, a touch sensor, a keyboard, a mouse, etc. The display device 128 is, for example, a liquid crystal monitor, an organic EL monitor, etc. The operating device 127 and the display device 128 may be integrally formed touch panels, control panels, etc. Furthermore, the operating device 127 and the display device 128 may be implemented using a GUI (Graphical User Interface). The operating device 127 and the display device 128 may also be external devices such as a personal computer or tablet terminal that are connected externally.

[0034] A three-phase AC power supply 101 is connected to the DC conversion circuit 102. The three-phase AC power supply 101 is, for example, a power supply provided by a power company that outputs a three-phase AC voltage, or a power supply provided by a generator that outputs an AC voltage. The three-phase AC power supply 101 outputs a three-phase AC voltage to the DC conversion circuit 102. An AC motor 105 is connected to the AC conversion circuit 104. The AC motor 105 is, for example, an AC motor, an induction motor, etc.

[0035] Figure 1B shows an example of the functional block configuration of the inverter device according to this embodiment.

[0036] The DC conversion circuit 102 is constructed using, for example, a diode, or an IGBT and a flywheel diode. The DC conversion circuit 102 converts the AC voltage input from the three-phase AC power supply 101 into a DC voltage and outputs it to the DC smoothing circuit 103.

[0037] The DC smoothing circuit 103 is composed of, for example, a smoothing capacitor. The DC smoothing circuit 103 smooths the DC voltage input from the DC conversion circuit 102 and outputs it to the AC conversion circuit 104. For example, if the output of the generator is a DC voltage, the DC smoothing circuit 103 may receive the DC voltage directly from the generator without going through the DC conversion circuit 102.

[0038] The AC conversion circuit 104 is constructed, for example, using an IGBT and a flywheel diode. The AC conversion circuit 104 takes the DC voltage output from the DC smoothing circuit 103 and the PWM command from the PWM generation device 106 as input, converts the DC voltage to an AC voltage, and outputs it to the AC motor 105.

[0039] The control device 120 shown in Figure 1A functions as a PWM generator 106, a speed command generator 107, a carrier frequency limiter 108, an asynchronous carrier frequency setting device 109, and a synchronous carrier frequency setting device 110.

[0040] The PWM generator 106 takes the frequency command output by the speed command generator 107 and the carrier frequency command output by the carrier frequency limiter 108 as input, generates a PWM, and outputs it to the AC conversion circuit 104.

[0041] The speed command generation device 107 determines the output frequency of the AC voltage to be output by the inverter based on, for example, a voltage command obtained from an external source or communication data from an external source, and outputs a frequency command to the PWM generation device 106.

[0042] The carrier frequency limiter 108 takes the carrier frequency settings output by the asynchronous carrier frequency setting device 109 and the synchronous carrier frequency setting device 110 as input and outputs a carrier frequency command to the PWM generator 106.

[0043] The asynchronous carrier frequency setting device 109 is composed of, for example, a memory element. The asynchronous carrier frequency setting device 109 stores a pre-set carrier frequency setting value for asynchronous mode. If the user later inputs a carrier frequency setting value, the device stores the input carrier frequency setting value. In this case, the carrier frequency in asynchronous mode is restricted to be set within a predetermined range.

[0044] The synchronous carrier frequency setting device 110 is composed of, for example, a memory element. The synchronous carrier frequency setting device 110 stores a pre-set carrier frequency setting value for synchronous mode. If the user later inputs a carrier frequency setting value, the device stores the input carrier frequency setting value. The carrier frequency setting value for synchronous mode includes the upper limit frequency of the carrier frequency for each synchronous PWM pulse count (order). In this case, the upper limit frequency of the carrier frequency in synchronous mode is restricted to be set within a predetermined range.

[0045] The control device, operating device 127, and display device 128 shown in Figure 1A function as an input receiving device 111 that receives various operations from the user, performs processing according to those operations, and displays various information to the user.

[0046] Next, we will explain the operation in the inverter device 100, where it switches from asynchronous PWM control to synchronous PWM control, and the number of synchronous PWM pulses transitions according to the output frequency. This operation will be explained in the following order: a standard example, a study example, and an example of this embodiment.

[0047] <Example of criteria> Figure 2 shows the relationship between carrier frequency and output frequency for each number of synchronous PWM pulses, based on a reference example.

[0048] The carrier frequency setting value output by the synchronous carrier frequency setting device 110 determines the switching point for the number of synchronous PWM pulses corresponding to the output frequency. In the reference example shown in Figure 2, the carrier frequency setting value output by the synchronous carrier frequency setting device 110 is a fixed default value, which is the common carrier upper limit frequency (209) common to all synchronous PWM pulse counts. The synchronous PWM pulse counts used are 33 pulses (203; 6th order), 27 pulses (204; 5th order), 21 pulses (205; 4th order), 15 pulses (206; 3rd order), 9 pulses (207; 2nd order), and 3 pulses (208; 1st order).

[0049] Once the common carrier upper frequency (209) and the number of synchronous PWM pulses used are determined, the carrier lower frequency for each number of synchronous PWM pulses is also determined. In other words, if the common carrier upper frequency is a fixed default value, then the carrier lower frequency for each number of synchronous PWM pulses can similarly be considered a fixed default value.

[0050] Here, the upper carrier frequency limit when the number of synchronous PWM pulses is N will be referred to as the N-pulse carrier upper frequency limit. Similarly, the lower carrier frequency limit when the number of synchronous PWM pulses is N will be referred to as the N-pulse carrier lower frequency limit.

[0051] The carrier lower limit frequencies for each number of synchronous PWM pulses specifically include the carrier lower limit frequencies at 27 pulses (210), 21 pulses (211), 15 pulses (212), 9 pulses (213), and 3 pulses (214).

[0052] The carrier upper or lower frequency limits for each number of synchronous PWM pulses determine the switching point for each number of synchronous PWM pulses corresponding to the output frequency.

[0053] In asynchronous mode, the inverter device 100 operates at the carrier frequency (201) for asynchronous mode. In synchronous mode, the inverter device 100 operates at the carrier frequency for synchronous mode, which can be determined from the following equation (1).

[0054] In synchronous mode, carrier frequency = output frequency × number of synchronous PWM pulses …(1)

[0055] Figure 2 shows an example where the number of synchronous PWM pulses transitions to 33 pulses (203) when switching from asynchronous mode to synchronous mode. However, when switching from asynchronous mode to synchronous mode, the number of synchronous PWM pulses may also transition to 27 pulses (204), 21 pulses (205), 15 pulses (206), 9 pulses (207), or 3 pulses (208).

[0056] Figure 2 shows an example where the carrier frequency (201) in asynchronous mode is set to 2.0 kHz using the asynchronous carrier frequency setting device 109. Figure 2 also shows an example where the common upper limit carrier frequency (209) in synchronous mode is set to 10.0 kHz using the synchronous carrier frequency setting device 110.

[0057] When using the above example settings, the carrier lower limit frequencies for each number of synchronous PWM pulses are as follows: The lower limit frequency at 33 pulses is the same as the asynchronous carrier frequency (201), which is 2.0 kHz. The carrier lower limit frequency at 27 pulses (210) is approximately 8.1 kHz. The carrier lower limit frequency at 21 pulses (211) is approximately 7.8 kHz. The carrier lower limit frequency at 15 pulses (212) is approximately 7.1 kHz. The carrier lower limit frequency at 9 pulses (213) is approximately 6.0 kHz. The carrier lower limit frequency at 3 pulses (214) is approximately 3.3 kHz.

[0058] Furthermore, under the above example settings, the output frequency range for each number of synchronous PWM pulses is as follows: At 33 pulses, the output frequency range is approximately 60Hz to 300Hz. At 27 pulses, the output frequency range is approximately 300Hz to 370Hz. At 21 pulses, the output frequency range is approximately 370Hz to 476Hz. At 15 pulses, the output frequency range is approximately 476Hz to 666Hz. At 9 pulses, the output frequency range is approximately 666Hz to 1111Hz. At 3 pulses, the output frequency range is approximately 1111Hz to the design maximum output frequency. The mode switching frequency (202) is approximately 60Hz.

[0059] In the case of the settings according to the above example, let's assume that the output frequency range frequently used by the user is 500Hz to 700Hz. In this case, the number of synchronous PWM pulses repeatedly transitions between 15 pulses (206) and 9 pulses (207), with the output frequency being approximately 666Hz. Therefore, it is not possible to suppress unstable operation due to the transition in the number of synchronous PWM pulses depending on the output frequency range used.

[0060] <Example of consideration> Figure 3 shows the relationship between carrier frequency and output frequency for each number of synchronous PWM pulses in the example study. The example study is one in which the upper limit of the carrier frequency is removed and increased compared to the standard example above.

[0061] In the above example, as shown in Figure 3, the carrier frequency setting value output by the synchronous carrier frequency setting device 110 is the common carrier upper limit frequency (315) common to each synchronous PWM pulse count. As for the synchronous PWM pulse count, 33 pulses (303; 6th order), 27 pulses (304; 5th order), 21 pulses (305; 4th order), 15 pulses (306; 3rd order), 9 pulses (307; 2nd order), and 3 pulses (308; 1st order) are used, as in the above reference example.

[0062] Once the common carrier upper frequency limit (315) and the number of synchronous PWM pulses used are determined, the carrier lower frequency limit for each number of synchronous PWM pulses is also determined.

[0063] The carrier lower limit frequencies for each number of synchronous PWM pulses specifically include the carrier lower limit frequencies at 27 pulses (310), 21 pulses (311), 15 pulses (312), 9 pulses (313), and 3 pulses (314).

[0064] These common carrier upper frequency limits or carrier lower frequency limits for each number of synchronous PWM pulses determine the switching point for each number of synchronous PWM pulses corresponding to the output frequency.

[0065] In the above example, as shown in Figure 3, we show an example where, similar to the above standard example, the number of synchronous PWM pulses transitions to 33 pulses (303) when switching from asynchronous mode to synchronous mode.

[0066] In the above example, as shown in Figure 3, an example is shown where the carrier frequency (301) in asynchronous mode is set to 2.0 kHz in the asynchronous carrier frequency setting device 109. In addition, the above example is shown where the common carrier upper limit frequency (315) in synchronous mode is set to 11.0 kHz in the synchronous carrier frequency setting device 110. The common carrier upper limit frequency (315) exceeds the common carrier upper limit frequency (309) of 10.0 kHz in the above reference example.

[0067] The reason why the upper limit of the carrier frequency can be raised from the original upper limit is that the original common carrier upper limit is set with a certain margin during the design phase. Furthermore, when raising the common carrier upper limit, a certain degree of increase in generated noise, leakage current, etc., must be tolerated. Therefore, it is important to note that a significant increase in the common carrier upper limit is difficult, and there are limits to how much it can be increased.

[0068] In the settings described in the above example, the carrier lower limit frequency for each number of synchronous PWM pulses is as follows: At 33 pulses, the carrier lower limit frequency is the same as the carrier frequency in asynchronous mode (301), which is 2.0 kHz. At 27 pulses, the carrier lower limit frequency (310) is approximately 9.0 kHz. At 21 pulses, the carrier lower limit frequency (311) is approximately 8.5 kHz. At 15 pulses, the carrier lower limit frequency (312) is approximately 7.9 kHz. At 9 pulses, the carrier lower limit frequency (313) is approximately 6.6 kHz. At 3 pulses, the carrier lower limit frequency (314) is approximately 3.7 kHz.

[0069] Furthermore, in the case of the settings described in the above example, the output frequency range for each number of synchronous PWM pulses is as follows: The output frequency range for 33 pulses is approximately 60Hz to 333Hz. The output frequency range for 27 pulses is approximately 333Hz to 407Hz. The output frequency range for 21 pulses is approximately 407Hz to 524Hz. The output frequency range for 15 pulses is approximately 524Hz to 733Hz. The output frequency range for 9 pulses is approximately 733Hz to 1222Hz. The output frequency range for 3 pulses is approximately 1222Hz to the design maximum output frequency. The mode switching frequency (302) is approximately 60Hz.

[0070] In the above example, let's assume that the output frequency range frequently used by the user is 500Hz to 700Hz. In this case, the number of synchronous PWM pulses repeatedly transitions between 21 pulses (305) and 15 pulses (306), with the output frequency being approximately 524Hz. Therefore, even if the upper limit of the carrier frequency is opened and increased, as in the above example, the usable output frequency range within the same synchronous PWM pulse cannot be sufficiently widened. In other words, it is difficult to suppress unstable operation due to the transition in the number of synchronous PWM pulses depending on the output frequency range used.

[0071] <Example of this embodiment> Figure 4 shows the relationship between the carrier frequency and the output frequency according to an example of this embodiment. In this example, the carrier upper frequency limit can be set to a higher frequency than the initially set common carrier upper frequency limit for a desired number of synchronous PWM pulses, and the carrier lower frequency limit can be set to a lower frequency than the frequency determined by the initial setting.

[0072] In this embodiment, as shown in Figure 4, the number of synchronous PWM pulses used is the same as in the above reference example and the above study example: 33 pulses (403; 6th order), 27 pulses (404; 5th order), 21 pulses (405; 4th order), 15 pulses (406; 3rd order), 9 pulses (407; 2nd order), and 3 pulses (408; 1st order).

[0073] In the synchronous carrier frequency setting device 110, a common carrier upper limit frequency (409) is set as an initial setting for each synchronous PWM pulse count.

[0074] However, in this embodiment, after the initial setup, the carrier upper frequency limit (415) for 15 pulses (third order) is set to a higher frequency than the common carrier upper frequency limit (409). Also, the carrier upper frequency limit (416) for 21 pulses (fourth order) is set to a lower frequency than the common carrier upper frequency limit (409). Note that setting the carrier frequency upper limit (416) for 21 pulses (fourth order) is substantially the same as setting the carrier frequency lower limit (413) for 15 pulses (third order).

[0075] The carrier frequency lower limits for each number of synchronous PWM pulses include the carrier frequency lower limit for 27 pulses (5th order) (410), the carrier frequency lower limit for 21 pulses (4th order) (411), the carrier frequency lower limit for 15 pulses (3rd order) (413), the carrier frequency lower limit for 9 pulses (2nd order) (412), and the carrier frequency lower limit for 3 pulses (1st order) (414).

[0076] The carrier upper or lower frequency limits for each number of synchronous PWM pulses determine the switching point for each number of synchronous PWM pulses corresponding to the output frequency.

[0077] In this embodiment, as shown in Figure 4, we show an example where, similar to the above-described standard example and study example, the number of synchronous PWM pulses transitions to 33 pulses (403) when switching from asynchronous mode to synchronous mode.

[0078] In this embodiment, as shown in Figure 4, an example is shown where the carrier frequency (401) in asynchronous mode is set to 2.0 kHz in the asynchronous carrier frequency setting device 109. Furthermore, the common carrier upper limit frequency (409) is set to 10.0 kHz in the synchronous carrier frequency setting device 110. The highest frequency that can be set as an individual carrier upper limit frequency is, for example, 11.0 kHz. Additionally, the carrier upper limit frequency (415) at 15 pulses (third order) is set to 11.0 kHz, and the carrier upper limit frequency (416) at 21 pulses (fourth order) is set to 9.0 kHz.

[0079] In the configuration according to this embodiment, the carrier lower limit frequency for each number of synchronous PWM pulses is as follows: The carrier lower limit frequency at 33 pulses is the same as the carrier frequency in asynchronous mode (401), which is 2.0 kHz. The carrier lower limit frequency at 27 pulses (410) is approximately 8.1 kHz. The carrier lower limit frequency at 21 pulses (411) is approximately 7.8 kHz. The carrier lower limit frequency at 15 pulses (413) is approximately 6.4 kHz. The carrier lower limit frequency at 9 pulses (412) is approximately 6.6 kHz. The carrier lower limit frequency at 3 pulses (414) is approximately 3.3 kHz.

[0080] Furthermore, in the case of the settings according to this embodiment, the output frequency range for each number of synchronous PWM pulses is as follows: The output frequency range for 33 pulses is approximately 60Hz to approximately 300Hz. The output frequency range for 27 pulses is approximately 300Hz to approximately 370Hz. The output frequency range for 21 pulses is approximately 370Hz to approximately 429Hz. The output frequency range for 15 pulses is approximately 429Hz to approximately 733Hz. The output frequency range for 9 pulses is approximately 733Hz to approximately 1111Hz. The output frequency range for 3 pulses is approximately 1111Hz to the maximum design output frequency. The mode switching frequency (402) is approximately 60Hz.

[0081] As explained in the above example, simply removing the upper limit of the carrier frequency was insufficient to prevent switching of the number of synchronous PWM pulses in the output frequency range of approximately 500Hz to 700Hz.

[0082] However, in the example of this embodiment, in synchronous PWM control, the upper limit frequency of the carrier frequency domain corresponding to the desired number of synchronous PWM pulses can be set higher than the initially set common upper limit frequency. Furthermore, the lower limit frequency of the carrier frequency domain corresponding to the desired number of synchronous PWM pulses can be set lower than the frequency determined by the initial setting. In other words, the switching point on the low-frequency side of the desired synchronous PWM pulse is set to a lower frequency, and the switching point on the high-frequency side is set to a higher frequency. Alternatively, the switching point on the low-frequency side of the desired synchronous PWM pulse is made earlier, and the switching point on the high-frequency side is made later.

[0083] This makes it possible to prevent the switching of the number of synchronous PWM pulses from occurring in the output frequency range where switching of the number of synchronous PWM pulses occurs frequently in the above standard example or the above study example settings. For example, as shown in Figure 4, it is possible to prevent the occurrence of switching points for the number of synchronous PWM pulses in the output frequency range of approximately 500Hz to 700Hz. As a result, unstable operation due to the transition (switching) of synchronous PWM pulses can be suppressed in the inverter device.

[0084] Furthermore, users can change the upper limit frequency of the carrier frequency domain for the k-th and k+1-th order synchronous PWM pulse counts, corresponding to frequently used output frequency ranges, from the default settings. Specifically, the upper limit frequency of the carrier frequency domain for the k-th order synchronous PWM pulse count can be increased from the default setting. Conversely, the upper limit frequency of the carrier frequency domain for the k+1-th order synchronous PWM pulse count can be decreased from the default setting. This allows users to avoid switching the number of synchronous PWM pulses in frequently used output frequency ranges, thereby suppressing unstable operation caused by synchronous PWM pulse transitions (switches).

[0085] Furthermore, the above configuration of the inverter device according to this embodiment can also be expected to provide the following effects, for example.

[0086] According to this embodiment, if there is a resonance point near the synchronous PWM pulse switching frequency, it becomes possible to shift the frequency at which the number of synchronous PWM pulses transitions back and forth, increasing the number of patterns that can avoid the resonance point.

[0087] Furthermore, this embodiment allows for more flexible setting of the transition timing of the number of synchronous PWM pulses that switch the carrier frequency. As a result, when using the carrier frequency in a frequency range where the timbre of the carrier frequency is perceived as unpleasant, there are more patterns in which the unpleasant timbre of the carrier frequency can be avoided.

[0088] Furthermore, according to this embodiment, the upper limit of the carrier frequency can be lowered from the initially set frequency, resulting in a lower carrier frequency in the same output frequency range compared to not lowering it. Therefore, the amount of heat generated by the inverter device can be reduced, giving customers the advantage of being able to select a smaller inverter device.

[0089] Furthermore, according to this embodiment, the upper limit of the carrier frequency can be lowered from the initially set frequency, resulting in a larger synchronous PWM pulse width compared to when it is not lowered. This leads to an increase in the output voltage, and as a result, a larger output torque can be generated when compared at the same output frequency.

[0090] Figure 5 is a flowchart showing an example of the process for setting the carrier frequency in the inverter device 100 according to this embodiment. The process for setting the carrier frequency is performed, for example, according to the flowchart shown in Figure 5. In the flowchart shown in Figure 5, terminals marked with symbol A, terminals marked with symbol B, terminals marked with symbol C, and terminals marked with symbol D are connected to each other. The configuration, processing content, and order of each step in the flowchart shown in Figure 5 are merely examples and are not limited thereto.

[0091] In step S501, the carrier frequency is initially set (default setting). Specifically, the asynchronous carrier frequency setting device 109 performs a process to set a predetermined default value as the asynchronous carrier frequency. In addition, the synchronous carrier frequency setting device 110 performs a process to set predetermined default values ​​for the common upper limit frequency of the carrier for each number of synchronous PWM pulses (1st to nth order) as the synchronous carrier frequency setting value. The default value for the asynchronous carrier frequency is, for example, 2.0 kHz. The default value for the common upper limit frequency of the carrier is, for example, 10.0 kHz. Note that the process in step S501 is performed, for example, before shipment of the inverter device 100, during restart, etc.

[0092] In step S502, a determination is made as to whether or not information has been entered. Specifically, the input receiving device 111 performs a process to determine whether or not information has been entered through direct operation by the user, through a terminal by the user, or from an external device. If it is determined that information has been entered (S502:Yes), the process proceeds to step S503. On the other hand, if it is determined that no information has been entered (S502:No), the process returns to step S502.

[0093] In step S503, it is determined whether or not a carrier frequency setting request has been made. Specifically, the input receiving device 111 performs a process to determine whether or not a carrier frequency setting request has been made to set the carrier frequency, based on the input information. If it is determined that a carrier frequency setting request has been made (S503:Yes), the process proceeds to step S504. On the other hand, if it is determined that a carrier frequency setting request has not been made (S503:No), the process proceeds to step S510.

[0094] In step S510, processing is performed according to the input information. Specifically, the input receiving device 111 executes processing according to the input information. Once this processing is completed, the processing steps return to step S502.

[0095] In step S504, it is determined whether the target to be configured is in asynchronous mode or synchronous mode. Specifically, the input receiving device 111 performs a process to determine whether the target to be configured is in asynchronous mode or synchronous mode based on the input information. If it is determined that the target to be configured is in asynchronous mode (S504: asynchronous), the process steps proceed to step S505. On the other hand, if it is determined that the target to be configured is in synchronous mode (S504: synchronous), the process steps proceed to step S507.

[0096] In step S505, the asynchronous carrier frequency is set. Specifically, the asynchronous carrier frequency setting device 109 performs the process of setting the asynchronous carrier frequency based on the information input via the input receiving device 111. After that, the process steps proceed to step S506.

[0097] In step S506, a determination is made as to whether or not to terminate the process. Specifically, the input receiving device 111 performs a process to determine whether or not to terminate the process based on whether or not there are factors that would cause the process to terminate, such as the issuance of an error signal or the input of a forced termination operation. If it is determined that the process should be terminated (S506:Yes), the process is terminated. On the other hand, if it is determined that the process should not be terminated (S506:No), the process steps return to step S502.

[0098] In step S507, the carrier upper limit frequency for the k-th synchronous PWM pulse count is determined and set. Specifically, the synchronous carrier frequency setting device 110 performs a process to determine the frequency to be set as the carrier upper limit frequency for the k-th synchronous PWM pulse count based on the information input via the input receiving device 111. Then, the synchronous carrier frequency setting device 110 performs a process to set the determined frequency as the carrier upper limit frequency for the k-th synchronous PWM pulse count. After that, the process steps proceed to step S508.

[0099] In this embodiment, the number of k-th order synchronous PWM pulses to be set is selected from 27 pulses (5th order), 21 pulses (4th order), 15 pulses (3rd order), 9 pulses (2nd order), and 3 pulses (1st order). The input information above may be user input information. This allows the user to set the "carrier upper limit frequency corresponding to the desired number of synchronous PWM pulses" to a desired frequency. For the k-th order carrier upper limit frequency, a frequency higher than the initial common carrier upper limit frequency can be set. However, the maximum configurable frequency is, for example, 11.0 kHz. Here, for example, the 3rd order carrier upper limit frequency, i.e., the carrier upper limit frequency when the number of synchronous PWM pulses is 15 pulses, is set to 11.0 kHz.

[0100] In step S508, the carrier upper limit frequency for the k+1th order synchronous PWM pulse count is determined and set. Specifically, the synchronous carrier frequency setting device 110 performs a process to determine the frequency to be set as the carrier upper limit frequency for the k+1th order synchronous PWM pulse count based on the information input via the input receiving device 111. Then, the synchronous carrier frequency setting device 110 performs a process to set the determined frequency as the carrier upper limit frequency for the k+1th order synchronous PWM pulse count. After that, the process steps proceed to step S509.

[0101] In this embodiment, the number of synchronous PWM pulses of the (k+1)th order to be set is selected from among 33 pulses (6th order), 27 pulses (5th order), 21 pulses (4th order), 15 pulses (3rd order), and 9 pulses (2nd order). The input information above may be user input information. This allows the user to set the "carrier lower limit frequency corresponding to the desired number of synchronous PWM pulses" to a desired frequency. For the (k+1)th order carrier upper limit frequency, a frequency lower than the initial common carrier upper limit frequency can be set. Here, for example, the 4th order carrier upper limit frequency, i.e., the carrier upper limit frequency when the number of synchronous PWM pulses is 21, is set to 9.0 kHz.

[0102] The processing in steps S507 and S508 allows the user to change the upper limit frequency of the carrier frequency domain for the k-th and k+1-th order synchronous PWM pulse counts, corresponding to frequently used output frequency ranges, from the initial setting to a different frequency. Specifically, the upper limit frequency of the carrier frequency domain for the k-th order synchronous PWM pulse count can be raised from the initial setting. Conversely, the upper limit frequency of the carrier frequency domain for the k+1-th order synchronous PWM pulse count can be lowered from the initial setting. This allows the user to avoid switching the number of synchronous PWM pulses in frequently used output frequency ranges, for example, in this example, approximately 500Hz to approximately 700Hz, thereby suppressing unstable operation caused by transitions (switching) of synchronous PWM pulses.

[0103] In this example, step 508 is performed after step S507, but the order of processing is not limited to this; step 507 may be performed after step S508.

[0104] In step S509, a determination is made as to whether or not to terminate the setting in synchronous mode. Specifically, the input receiving device 111 performs a process to determine whether or not to terminate the setting of the carrier upper limit frequency in synchronous mode based on the information input by the user. If it is determined that the setting in synchronous mode should be terminated (S509: Yes), the process steps proceed to step S506. On the other hand, if it is determined that the setting in synchronous mode should not be terminated, i.e., to be continued (S509: No), the process steps proceed to step S507.

[0105] Thus, the carrier frequency upper limit setting method, which is performed based on the flow shown in Figure 5, is also one embodiment.

[0106] In the embodiment described above, the inverter device converts a DC voltage into a three-phase AC voltage. Such inverter devices are often used to drive motors that require relatively large torque and high rotational speeds, such as automobile wheels and railway vehicle wheels. Therefore, the inverter device according to the embodiment described above is particularly effective for motors that require high torque and high rotational speeds.

[0107] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are explained in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described.

[0108] For example, the inverter device according to the above embodiment converts DC voltage to AC voltage, but it may also convert DC current to AC current. Furthermore, the inverter device according to the above embodiment converts DC power to three-phase AC power, but it may also convert DC power to single-phase AC power.

[0109] Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

[0110] Furthermore, it is possible to add, delete, or replace some of the configurations in each embodiment with other configurations.

[0111] Furthermore, each of the above-mentioned configurations, functions, processing units, processing means, etc., may be implemented in hardware, in whole or in part, for example, by designing them as integrated circuits.

[0112] Furthermore, each of the above configurations and functions may be implemented in software by the processor interpreting and executing programs that realize each function. Information such as programs, tables, and files that realize each function can be stored in memory, storage devices such as hard disks and SSDs (Solid State Drives), or recording media such as IC cards, SD cards, and DVDs.

[0113] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and not all control lines and information lines are necessarily shown in the actual product. In reality, it is safe to assume that almost all components are interconnected. [Explanation of symbols]

[0114] 100...Inverter device, 101...Three-phase AC power supply, 102...DC conversion circuit, 103...DC smoothing circuit, 104...AC conversion circuit, 105...AC motor, 106...PWM generation device, 107...Speed ​​command generation device, 108...Carrier frequency limiting device, 109...Asynchronous carrier frequency setting device, 110...Synchronous carrier frequency setting device, 111...Input receiving device, 120...Control device, 121...Processor, 122...Memory, 123...Storage, 124...Interface, 125...Bus, 126...Program, 127...Operating device, 128...Display device, 201,301,401...Carrier frequency in asynchronous mode, 202,302,402...Mode switching output frequency, 203,303,403...33 pulses, 204,304,404...27 pulses Russ, 205, 305, 405... 21 pulses, 206, 306, 406... 15 pulses, 207, 307, 407... 9 pulses, 208, 308, 408... 3 pulses, 209, 309, 409... Carrier common upper frequency, 210, 310, 410... Carrier lower frequency at 27 pulses (5th order), 211, 311, 411... Carrier lower frequency at 21 pulses (4th order) 212, 312, 413…Carrier lower frequency limit at 15 pulses (3rd order), 213, 313, 412…Carrier lower frequency limit at 9 pulses (2nd order), 214, 314, 414…Carrier lower frequency limit at 3 pulses (1st order), 315…Carrier common upper frequency limit, 415…Carrier upper frequency limit at 15 pulses (3rd order), 416…Carrier upper frequency limit at 21 pulses (4th order).

Claims

1. A circuit that converts DC power to AC power using pulse width modulation, The system includes a control device that controls the aforementioned circuit, The control device is The circuit is controlled to operate in an asynchronous mode in which the carrier and the modulated wave are generated asynchronously, and in a synchronous mode in which the number of carrier pulses per modulated wave period is set in multiples of 3 from the high frequency side to the low frequency side, from the first to the nth order, in an output frequency range higher than the output frequency range of the asynchronous mode. A process to set the upper limit frequency of the k-th (k < n) carrier frequency domain to a higher frequency than the common upper limit frequency that is initially set for each order of the synchronization mode, The process of setting the upper limit frequency of the k+1th order carrier frequency domain to a lower frequency than the common upper limit frequency is performed. Power converter.

2. The control device performs a process to determine, based on user input information, the frequency to be set as the upper limit frequency of the k-th order carrier frequency domain and the frequency to be set as the upper limit frequency of the k+1-th order carrier frequency domain. The power conversion device according to claim 1.

3. The aforementioned multiples of 3 are odd multiples of 3. The power conversion device according to claim 1.

4. Converts DC voltage to three-phase AC voltage. The power conversion device according to claim 1.

5. A method for setting the upper limit of the carrier frequency of a power converter that operates in an asynchronous mode, which converts DC power to AC power using a pulse width modulation scheme and generates the carrier and modulated wave asynchronously, and a synchronous mode, which is used in an output frequency range higher than the output frequency range of the asynchronous mode, and in which the number of carrier pulses per period of the modulated wave is set from the first to the nth order in multiples of 3 from the high frequency side to the low frequency side, wherein The control device provided in the power converter is A process to set the upper limit frequency of the k-th (k < n) carrier frequency domain to a higher frequency than the common upper limit frequency that is initially set for each order of the synchronization mode, The process of setting the upper limit frequency of the k+1th order carrier frequency domain to a lower frequency than the common upper limit frequency is performed. How to set the carrier frequency limit.

6. The control device performs a process to determine, based on user input information, the frequency to be set as the upper limit frequency of the k-th order carrier frequency domain and the frequency to be set as the upper limit frequency of the k+1-th order carrier frequency domain. The method for setting the upper limit of the carrier frequency according to claim 5.

7. The aforementioned multiples of 3 are odd multiples of 3. The method for setting the upper limit of the carrier frequency according to claim 5.

8. The aforementioned power conversion device converts a DC voltage to a three-phase AC voltage. The method for setting the upper limit of the carrier frequency according to claim 5.

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