Semiconductor equipment

Abstract

To improve the performance of semiconductor devices. [Solution] A plurality of conductor patterns 2CP1 formed on the wiring layer WL1 of the wiring substrate SUB1 of the semiconductor device PKG1 are located outside the chip mounting area RCP and include a plurality of bonding fingers BF1 arranged in the Y direction, and a plurality of wirings 2W1 connected to each of the bonding fingers BF1. The plurality of conductor patterns 2CP1 include a fixed potential pattern FP located between each of two adjacent wirings 2W1 within the area R1 and connected to a fixed potential transmission path. The fixed potential pattern FP located between each of the plurality of wirings 2W1 and the two wirings 2W1 each extend in the X direction, which intersects the Y direction, so as to straddle the outer edge of the chip mounting area RCP.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background Art]

[0002] There is a known technique in which a semiconductor chip mounted on a wiring board is electrically connected to the wiring board via a plurality of wires (see, for example, Patent Document 1). Patent Document 1 describes that a dummy conductor pattern is arranged in a region where no wiring conductor pattern is arranged on the main surface of a wiring board. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2002-190488 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] When a semiconductor chip is mounted on a wiring board, an adhesive is interposed between the wiring board and the semiconductor chip. However, when the flatness of the chip mounting region on the upper surface of the wiring board is low, voids (gaps) may occur between the adhesive and the wiring board. Voids cause separation between the adhesive and the wiring board. Therefore, from the viewpoint of improving the reliability of the semiconductor device, a technique for suppressing the generation of voids is required.

[0005] Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problem]

[0006] A semiconductor device according to one embodiment includes a semiconductor chip, a wiring substrate on which the semiconductor chip is mounted, and a film-like adhesive disposed between the semiconductor chip and the wiring substrate and bonded to the semiconductor chip and the wiring substrate, respectively. The wiring substrate includes a first wiring layer on which a plurality of first conductor patterns are formed, and a first insulating layer covering the first wiring layer and having a third surface. The plurality of first conductor patterns include a plurality of bonding fingers, each disposed outside the chip mounting area. The plurality of first conductor patterns include a plurality of first wirings, each disposed within a first region including a portion of the outer edge of the chip mounting area, and connected to each of the plurality of first bonding fingers. The plurality of first conductor patterns include a fixed potential pattern, which is disposed between each of two adjacent first wirings within the first region and connected to a fixed potential transmission path. The plurality of first bonding fingers are arranged in a first direction. The fixed potential pattern and the plurality of first wirings, which are positioned between each of the two first wirings, extend in a second direction that intersects the first direction, straddling the outer edge of the chip mounting area.

[0007] A semiconductor device according to another embodiment includes a semiconductor chip, a wiring substrate on which the semiconductor chip is mounted, and a film-like adhesive disposed between the semiconductor chip and the wiring substrate and bonded to the semiconductor chip and the wiring substrate, respectively. The wiring substrate includes a first wiring layer on which a plurality of first conductor patterns are formed, and a first insulating layer covering the first wiring layer and having a third surface. The plurality of first conductor patterns include a plurality of bonding fingers, each disposed outside the chip mounting area. The plurality of first conductor patterns are disposed within a first area including a portion of the outer edge of the chip mounting area, and include a plurality of first wirings, each connected to a plurality of the first bonding fingers. The plurality of first bonding fingers are arranged in a first direction. The width of the plurality of first wirings is wider than the spacing between the plurality of first wirings. Each of the plurality of first wirings extends across the outer edge of the chip mounting area in a second direction intersecting the first direction. [Effects of the Invention]

[0008] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view of a semiconductor device according to one embodiment. [Figure 2] Figure 1 is a bottom view of the semiconductor device shown. [Figure 3] This is a plan view showing the state after the sealing material shown in Figure 1 has been removed. [Figure 4] This is a cross-sectional view along line AA in Figure 1. [Figure 5] This is an enlarged plan view of section B of the wiring board shown in Figure 3. [Figure 6] Figure 5 is an enlarged cross-sectional view along the CC line. [Figure 7] This is an enlarged plan view showing the layout of the topmost wiring layer of a wiring board, which is an example of a study for Figure 5. [Figure 8] Figure 7 is an enlarged cross-sectional view along the DD line. [Figure 9] This is an enlarged plan view of a wiring board, which is a modified version of Figure 5. [Figure 10] Figure 9 is an enlarged cross-sectional view along the EE line. [Figure 11] Figure 1 is an explanatory diagram showing an example of the manufacturing process for a semiconductor device. [Figure 12] Figure 11 is a cross-sectional view of the semiconductor chip prepared in the semiconductor chip preparation process. [Figure 13] Figure 11 is a plan view showing an example of a wiring board prepared in the wiring board preparation process. [Modes for carrying out the invention]

[0010] (Explanation of format, basic terminology, and usage in this application) In this application, the descriptions of the embodiments are divided into multiple sections for convenience. These are not independent of each other, but rather one is a detail of the other, or one is a variation of the other. In principle, similar parts will be omitted from repeated explanations. Furthermore, each component in the embodiments is not essential unless it is explicitly indicated as an essential component, its number is theoretically limited, or it is clearly essential from the context.

[0011] Similarly, in the description of embodiments and the like, even if a statement such as "X consisting of A" is used regarding materials, compositions, etc., this does not exclude those containing elements other than A, except when it is clearly limited, or when it is clearly limited by context. For example, as for components, it means "X containing A as a main component". For example, even the term "silicon member" is not limited to pure silicon, and also includes members containing SiGe (silicon-germanium) alloys, other multi-component alloys with silicon as the main component, other additives, and the like. In addition, even when terms such as gold plating, Cu layer, and nickel plating are used, unless explicitly stated otherwise, they shall include not only pure substances but also members having gold, Cu, nickel, etc. as the main components, respectively.

[0012] Furthermore, when reference is made to a specific numerical value or quantity, the specific numerical value is described as an example, unless it is clearly limited, or when it is clearly limited by context.

[0013] In addition, in each drawing of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and descriptions thereof will not be repeated in principle.

[0014] In addition, in the accompanying drawings, hatching or the like may be omitted even for a cross-section if it would make the drawing unnecessarily complicated or if the distinction from a void is clear. In connection with this, if it is clear from the description and the like, the outline of the background may be omitted even for a closed hole in plan view. Furthermore, even for non-cross-sectional portions, hatching or a dot pattern may be added to clearly indicate that the portion is not a void or to clearly indicate the boundary of a region.

[0015] <Semiconductor Device> First, the semiconductor device according to the present embodiment will be described. FIG. 1 is a perspective view of a semiconductor device according to an embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. In addition, FIG. 3 is a plan view showing a state where the sealing body shown in FIG. 1 is removed. In addition, FIG. 4 is a cross-sectional view taken along line A-A of FIG. 1.

[0016] Figures 1 through 4 show either the X direction (see Figures 1 through 4), the Y direction (see Figures 1, 2, and 3), or the Z direction (see Figures 1 and 4). The Y direction intersects the X direction, and in the following explanation, the X and Y directions are orthogonal to each other. The Z direction is orthogonal to both the X and Y directions. In other words, the Z direction is the normal direction (or perpendicular direction) to the XY plane, which includes the X and Y directions. In the following explanation, "thickness" generally refers to the length in the Z direction. Also, in the following explanation, "plan view" generally refers to a plan view of the XY plane.

[0017] The semiconductor device PKG1 of this embodiment includes a wiring board SUB1 and a semiconductor chip CHP1 mounted on the wiring board SUB1 (see Figure 3).

[0018] Furthermore, as shown in Figure 4, the semiconductor device PKG1 has a semiconductor chip CHP1 and a film-like adhesive DAF1 bonded to the wiring substrate SUB1. The adhesive DAF1 is positioned between the lower surface 3b of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1.

[0019] Furthermore, the semiconductor device PKG1 has multiple wires BW connected to the semiconductor chip CHP1 and the wiring board SUB1, respectively.

[0020] Furthermore, the semiconductor device PKG1 includes a encapsulant MR that encapsulates the semiconductor chip CHP1 and a plurality of wires BW. The encapsulant MR is formed to cover the upper surface 2t of the wiring substrate SUB1.

[0021] As shown in Figure 4, the semiconductor chip CHP1 mounted on the wiring board SUB1 has an upper surface (main surface, front surface) 3t and a lower surface (main surface, back surface) 3b opposite to the upper surface 3t.

[0022] Furthermore, as shown in Figure 3, the semiconductor chip CHP1 has a rectangular shape in plan view. As shown in Figure 3, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 such that each side of the upper surface 3t of the semiconductor chip CHP1 aligns with each side that constitutes the outer edge of the upper surface 2t of the wiring substrate SUB1.

[0023] Multiple pads (electrode pads) PD are arranged on the upper surface 3t of the semiconductor chip CHP1. These multiple pads PD are input / output terminals of the semiconductor chip CHP1 and are exposed from the protective film (passivation film) formed in openings on the upper surface 3t of the semiconductor chip CHP1.

[0024] In the example shown in Figure 3, multiple pads PD are arranged along two of the four sides of the semiconductor chip CHP1 that extend in the Y direction. However, there are various other variations of the pad layout besides the one shown in Figure 3. For example, pads PD may be arranged along each of the four sides of the semiconductor chip CHP1. Also, each of the multiple pads PD may be made primarily of aluminum (Al), for example.

[0025] As shown in Figures 3 and 4, the semiconductor chip CHP1 is mounted on the upper surface 2t of the wiring board SUB1. In the example shown in Figure 3, the semiconductor chip CHP1 is mounted in the center of the upper surface 2t of the wiring board SUB1. In the following description, the area of ​​the upper surface 2t of the wiring board SUB1 on which the semiconductor chip CHP1 is mounted, or the area on which the semiconductor chip CHP1 is planned to be mounted, will be referred to as the chip mounting area.

[0026] As shown in Figure 4, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 via adhesive DAF1, with its lower surface 3b facing the upper surface 2t of the wiring substrate SUB1. In other words, the semiconductor chip CHP1 is mounted using a so-called face-up mounting method, where the opposite side (lower surface 3b) of the upper surface 3t, where multiple pads PD are formed, faces the chip mounting surface (upper surface 2t).

[0027] The adhesive DAF1 is used to bond and fix the semiconductor chip CHP1 to the wiring board SUB1, and is, for example, a resin film called DAF (Die Attach Film). As will be described in detail later, the adhesive DAF1 is used in a state where it is pre-attached to the lower surface 3b of the semiconductor chip CHP1 during the die bonding process. Generally, a paste-like adhesive applied to the wiring board is sometimes used as a die bonding material for mounting a semiconductor chip onto the wiring board. The adhesive DAF1 is distinct from the paste-like adhesive described above.

[0028] As shown in Figure 4, the wiring board SUB1 has an upper surface (main surface, chip mounting surface) 2t on which the semiconductor chip CHP1 is mounted, and a lower surface (main surface, mounting surface) 2b opposite to the upper surface 2t. In addition, each of the upper surface 2t and lower surface 2b of the wiring board SUB1 has multiple edges 2s (see Figures 2 and 3). In this embodiment, the upper surface 2t (see Figure 3) and lower surface 2b (see Figure 2) of the wiring board SUB1 are both rectangular. As shown in Figure 4, the upper surface 2t of the wiring board SUB1 is the chip mounting surface that faces the lower surface 3b of the semiconductor chip CHP1.

[0029] The wiring board SUB1 includes a wiring layer WL1 on which multiple conductor patterns 2CP1 are formed, and an insulating layer SR1 that covers the wiring layer WL1 and has an upper surface 2t. The wiring board SUB1 also includes a wiring layer WL2 on which multiple conductor patterns 2CP2 are formed, and an insulating layer SR2 that covers the wiring layer WL2 and has a lower surface 2b.

[0030] Wiring layer WL1 is the wiring layer located closest to the top surface 2t among the multiple wiring layers of the wiring board SUB1. Wiring layer WL2 is the wiring layer located closest to the bottom surface 2b among the multiple wiring layers of the wiring board SUB1. In the example shown in Figure 4, the wiring board SUB1 is a two-layer wiring board consisting of wiring layer WL1 and wiring layer WL2.

[0031] Each of the wiring layers WL1 and WL2 is formed on the core insulating layer (insulating layer) 2CR. The core insulating layer 2CR is made of, for example, a prepreg made of glass fibers impregnated with resin. Multiple through-hole wirings (via wirings) 2THW, which are interlayer conductive paths, are formed on the core insulating layer 2CR. The through-hole wirings 2THW are conductor patterns that penetrate the core insulating layer 2CR in the thickness direction. Wiring layers WL1 and WL2 are electrically connected via the through-hole wirings 2THW.

[0032] In this embodiment, the interlayer conductive path penetrating the core insulating layer 2CR will be described as through-hole wiring 2THW. However, in the following description, the interlayer conductive path described as through-hole wiring 2THW can be read as via wiring. Similarly, in the following description, the conductor pattern described as through-hole land 2THL (see Figure 5, described later) can be read as via land.

[0033] Multiple conductor patterns 2CP1 of the top wiring layer WL1 of the wiring board SUB1 include bonding fingers (terminals, terminals on the chip mounting side) BF, wiring 2W1, and fixed potential patterns (conductor planes, large area patterns) FP.

[0034] Most of the multiple conductor patterns 2CP1 are covered by the insulating layer SR1. However, as shown in Figures 3 and 4, each of the multiple bonding fingers BF is exposed from the insulating layer SR1 through openings formed in the insulating layer SR1. One end of a wire BW is bonded to the exposed surface of the bonding finger BF. The other end of the wire BW is bonded to a pad PD arranged on the upper surface 3t of the semiconductor chip CHP1.

[0035] The wiring layer WL1 is entirely covered by the insulating layer SR1 where it overlaps with the chip mounting area RCP. Furthermore, each of the multiple bonding fingers BF is exposed from the insulating layer SR1 where at least multiple wires BW are bonded.

[0036] Multiple conductor patterns 2CP2 of the bottommost wiring layer WL2 of the wiring board SUB1 include lands (terminals, mounting side terminals) 2LD. Each of the multiple conductor patterns 2CP1 and multiple conductor patterns 2CP2 is made of, for example, copper (Cu).

[0037] The wiring layer WL2 is covered by the insulating layer SR2. Both the insulating layer SR1 and the insulating layer SR2 are solder resist films. Multiple openings are formed in the insulating layer SR2, and lands 2LD are exposed from the insulating layer SR2 at these openings. Solder balls SB, which are ball-shaped solder material, are connected to the exposed surfaces of lands 2LD.

[0038] Multiple pads PD on the semiconductor chip CHP1 and multiple bonding fingers BF on the wiring board SUB1 are electrically connected via multiple wires BW. The multiple wires BW are made of a metal, such as gold (Au) or copper (Cu), as the main component.

[0039] Furthermore, the number of external terminals (solder balls SB) on the wiring board SUB1, or their layout, can be modified in various ways in addition to the configuration shown in Figure 2. Also, while Figure 4 shows an example of a two-layer wiring board SUB1 with wiring layers formed on the upper and lower surfaces of the core insulating layer 2CR, the number of wiring layers is not limited to two, and it may have three or more wiring layers.

[0040] As shown in Figure 4, the semiconductor chip CHP1 and multiple wires BW are sealed by a encapsulant MR. The encapsulant MR has an upper surface MRt and a lower surface MRb located opposite the upper surface MRt. As shown in Figure 1, the encapsulant MR forms a rectangle in plan view.

[0041] In this embodiment, the entire upper surface 2t of the wiring board SUB1 shown in Figure 3 is covered by the sealing body MR shown in Figure 1. Therefore, the planar area of ​​the sealing body MR (the area when viewed from above from the upper surface MRt side) is the same as the planar area of ​​the upper surface 2t of the wiring board SUB1 (see Figure 3). In addition, the side surface of the sealing body MR is continuous with the side surface of the wiring board SUB1.

[0042] <Details of the area surrounding the chip mounting area> Next, we will describe the detailed structure of the area surrounding the chip mounting region RCP on the upper surface 2t of the wiring board SUB1 shown in Figure 3, where the semiconductor chip CHP1 is mounted. Figure 5 is an enlarged plan view of section B of the wiring board shown in Figure 3. In Figure 5, the plan view of the wiring layer WL1, one of the layers of the wiring board SUB1 shown in Figure 4, is shown. In other words, Figure 5 is a transparent plan view of section B of Figure 3. Also in Figure 5, the boundary line between the chip mounting region RCP and the surrounding area of ​​the chip mounting region RCP (in other words, the outer edge of the chip mounting region RCP) shown in Figure 3 is shown by a dashed line. Figure 6 is an enlarged cross-sectional view along line CC in Figure 5.

[0043] In the following explanation, the region of part B in Figure 3, i.e., the region shown in Figure 5, within the wiring layer WL1 of the wiring board SUB1, will be defined as region R1. As shown in Figure 5, in a transparent plan view, region R1 includes a part of the chip mounting region RCP and a part of the region outside the chip mounting region RCP (region RNCP shown in Figure 5). Region RNCP is the region adjacent to the chip mounting region RCP.

[0044] As shown in Figure 5, the multiple conductor patterns 2CP1 include multiple bonding fingers BF, multiple wirings 2W1, and fixed potential patterns FP. The multiple bonding fingers BF are located outside the chip mounting area RCP (area RNCP shown in Figure 5).

[0045] In the example shown in Figure 5, the multiple conductor patterns 2CP1 include wiring 2W2. One end of wiring 2W2 is connected to the bonding finger BF and extends in the opposite direction from the chip mounting area RCP. Wiring 2W2 is used as a power supply line when forming the bonding finger BF and wiring 2W1 by electroplating. However, in a modified example, wiring 2W1 shown in Figure 5 may not be formed.

[0046] Wiring 2W1 is located within region R1 in a transmitted plan view. One end of wiring 2W1 is electrically connected to multiple bonding fingers BF1 located in region R1, among multiple bonding fingers BF. The other end of wiring 2W1 is connected to a through-hole land (via land) 2THL, ​​which is connected to through-hole wiring 2THW shown in Figure 4.

[0047] The fixed-potential pattern FP is positioned between each of the multiple wirings 2W1 within region R1 in a transmitted planar view. In particular, at the boundary between the chip mounting region RCP and the region RNCP outside the chip mounting region RCP, the multiple wirings 2W1 and the fixed-potential pattern FP are arranged alternately in the Y direction.

[0048] A fixed-potential pattern FP is connected to a transmission path for the fixed potential. In the example shown in Figure 5, the fixed-potential pattern FP is connected to the ground path GP, which is the transmission path for the earth potential (reference potential). In other words, the earth potential is supplied to the fixed-potential pattern FP. Although not shown in the figure, the fixed-potential pattern FP may also be connected to the power path, which is the transmission path for the power supply potential. Furthermore, some of the multiple fixed-potential pattern FPs may be connected to the transmission path for the reference potential, while others may be connected to the power supply path for the power supply potential.

[0049] From the viewpoint of reducing potential fluctuations (in other words, noise), the paths supplying fixed potentials, such as reference potentials and power supply potentials, are preferably large-area conductor patterns. In this embodiment, the multiple fixed potential patterns FP are separated via wiring 2W1 at the boundary between the chip mounting area RCP and the area RNCP outside the chip mounting area RCP. However, the multiple fixed potential patterns FP are connected to each other inside the chip mounting area RCP.

[0050] As shown in Figure 5, the multiple bonding fingers BF1 are arranged in the Y direction. In a transparent plan view, the fixed potential pattern FP, which is placed between each of the multiple wirings 2W1, and the multiple wirings 2W1 each extend in the X direction, which intersects the Y direction, so as to straddle the outer edge of the chip mounting area RCP.

[0051] Here, a semiconductor device, which is an example of a design for this embodiment, will be described. Figure 7 is an enlarged plan view showing the layout of the topmost wiring layer of a wiring board, which is an example of a design for Figure 5. Figure 8 is an enlarged cross-sectional view along the DD line in Figure 7.

[0052] The wiring board SUB2 of the semiconductor device PKG2 shown in Figures 7 and 8 differs from the wiring board SUB1 of the semiconductor device PKG1 shown in Figures 5 and 6 in the layout of the wiring layer WL1. Specifically, in the case of wiring board SUB2, as shown in Figure 7, multiple wirings 2W1 are adjacent to each other at the boundary between the chip mounting area RCP and area RNCP. In other words, in the wiring layer WL1 of wiring board SUB2, fixed potential patterns FP are not placed between multiple wirings 2W1 at the boundary between the chip mounting area RCP and area RNCP.

[0053] As shown in Figure 8, the insulating layer SR1 covering the wiring layer WL1 is formed to cover the wiring layer WL1. Therefore, the upper surface of the insulating layer SR1 has a shape that conforms to the irregularities of the underlying wiring layer WL1. In other words, the flatness of the upper surface of the insulating layer SR1 depends on the flatness of the underlying wiring layer WL1.

[0054] Therefore, as shown in Figure 8, in areas where multiple wirings 2W1 are densely arranged, many irregularities (depressions or grooves) are easily formed at a narrow pitch on the upper surface of the insulating layer SR1 covering the wirings 2W1. The semiconductor device PKG2, like the semiconductor device PKG1 according to this embodiment, uses a film-like adhesive DAF1 as a die bond material for bonding and fixing the semiconductor chip CHP1 onto the wiring substrate SUB2.

[0055] Unlike paste-type adhesives, adhesive DAF1 has poor filling performance for irregularities on the bonded surface. Therefore, as shown in Figure 8, if many irregularities are formed at a narrow pitch on the upper surface of the insulating layer SR1, voids (gaps) VD may occur between adhesive DAF1 and the upper surface of the insulating layer SR1 (i.e., upper surface 2t) in some of the numerous irregularities.

[0056] Void VD expands or contracts in response to changes in the ambient temperature of the semiconductor device PKG2. Each time void VD expands or contracts, stress is applied to the adhesive interface between the adhesive DAF1 and the insulating layer SR1. As a result, the adhesive DAF1 and the insulating layer SR1 may delaminate.

[0057] Furthermore, if voids (VD) occur, the bonding area decreases compared to when the entire surface of the adhesive DAF1 is bonded to the insulating layer SR1. The strength with which the semiconductor chip CHP1 is fixed to the wiring substrate SUB2 is proportional to the bonding area between the adhesive DAF1 and the insulating layer SR1. Therefore, from the viewpoint of improving the reliability of semiconductor devices, it is necessary to suppress the occurrence of voids (VD).

[0058] As explained using Figure 5, the fixed potential pattern FP, which is placed between each of the multiple wirings 2W1, and the multiple wirings 2W1 each extend so as to straddle the outer edge of the chip mounting area RCP in the X direction. Therefore, at the boundary between the chip mounting area RCP and the area RNCP, the fixed potential pattern FP is placed between two adjacent wirings 2W1.

[0059] The distance between two adjacent wirings 2W1 and the wiring width of wiring 2W1 are determined according to the design specifications. Therefore, from the viewpoint of improving design flexibility, it is preferable that the values ​​of the distance between two adjacent wirings 2W1 and the wiring width of wiring 2W1 can be set arbitrarily.

[0060] In this embodiment, in the chip mounting area RCP, a fixed potential pattern FP is placed between adjacent wirings 2W1. Therefore, by adjusting the width of the fixed potential pattern FP in the Y direction, the distance between the wiring 2W1 and the fixed potential pattern FP can be controlled.

[0061] As shown in Figure 6, even when using a film-like adhesive DAF1, if the difference in height of the irregularities on the upper surface 2t is small, it is possible to adhere the entire lower surface of the adhesive DAF1 to the insulating layer SR1. In the case of the wiring board SUB1 shown in Figure 6, the area occupied by the conductor pattern 2CP1 formed on the wiring layer WL1 in the chip mounting area RCP is higher than that of the wiring board SUB2 shown in Figure 8. The reason why the area occupied can be higher is that the fixed potential pattern FP is placed between adjacent wirings 2W1.

[0062] Thus, according to this embodiment, even when the adhesive DAF1 is used as the die bond material for bonding and fixing the semiconductor chip CHP1 to the wiring substrate SUB1, the generation of voids VD as shown in Figure 8 can be suppressed. As a result, delamination between the adhesive DAF1 and the insulating layer SR1 can be suppressed, thereby improving the reliability of the semiconductor device PKG1.

[0063] Next, we will explain the preferred relationships between the multiple conductor patterns 2CP1 formed on the wiring layer WL1, such as the spacing distance and the arrangement pitch. In the following explanation, "arrangement pitch" refers to the distance between the centers of the two conductor patterns in question. "Spacing distance" refers to the distance between the two conductor patterns in question, specifically the shortest distance. "Width" refers to the length in the direction perpendicular to the longitudinal direction.

[0064] First, in the example shown in Figure 5, the arrangement pitch PW1 of each of the multiple wirings 2W1 at a position overlapping with the outer edge of the chip mounting area RCP is greater than the arrangement pitch PF1 of each of the multiple bonding fingers BF1 in the Y direction. In other words, each of the multiple wirings 2W1 is arranged within the chip mounting area RCP with an arrangement pitch PW1 that is wider than the arrangement pitch PF1 of the bonding fingers BF1.

[0065] As described above, the semiconductor device PKG1 has a structure in which a fixed-potential pattern FP is placed between adjacent wirings 2W1 within the chip mounting area RCP. For this reason, it is preferable that the array pitch PW1 of adjacent wirings 2W1 is wide. If the array pitch PW1 of wirings 2W1 is narrow, it may not be possible to secure a sufficient width for the fixed-potential pattern FP in the Y direction in Figure 5. If the array pitch PW1 of adjacent wirings 2W1 is sufficiently wide, it is possible to widen the width of the fixed-potential pattern FP. In this case, patterning of the fixed-potential pattern FP is easier. Alternatively, the processing accuracy of the separation distance GFW between the fixed-potential pattern FP and the wiring 2W1 can be improved.

[0066] On the other hand, multiple bonding fingers BF1 are located outside the chip mounting area RCP. The adhesive DAF1 shown in Figure 6 is not located outside the chip mounting area RCP. Therefore, even if depressions or grooves are formed on the upper surface 2t of the insulating layer SR1 in area RNCP (see Figure 5), the above-mentioned problems do not occur. Thus, the arrangement pitch PF1 of the bonding fingers BF1 is not particularly limited. Considering the arrangement efficiency of the bonding fingers BF1, a smaller arrangement pitch PF1 is preferable.

[0067] Furthermore, as explained using Figure 5, the fixed potential pattern FP placed between each of the multiple wirings 2W1 and the multiple wirings 2W1 extend in the X direction so as to straddle the outer edge of the chip mounting area RCP. This suppresses the formation of voids VD (see Figure 8) between the adhesive DAF1 and the insulating layer SR1 shown in Figure 6 in the peripheral region of the chip mounting area RCP.

[0068] Considering the above, it is preferable that the arrangement pitch PW1 of each of the multiple wirings 2W1 at a position overlapping with the outer edge of the chip mounting area RCP is greater than the arrangement pitch PF1 of each of the multiple bonding fingers BF1 in the Y direction.

[0069] Next, in the example shown in Figure 5, at a position overlapping with the outer edge of the chip mounting area RCP, the distance GFW between each of the multiple wirings 2W1 and the fixed potential pattern FP is smaller than the width WFP of the fixed potential pattern FP in the Y direction.

[0070] As shown in Figure 6, reducing the value of the separation distance GFW can reduce the depth of the depression formed on the upper surface 2t of the insulating layer SR1. However, if the value of the separation distance GFW is made extremely small, there is a concern that the wiring 2W1 and the fixed potential pattern FP may short-circuit due to processing accuracy. Therefore, it is preferable that the value of the separation distance GFW be as small as possible within an acceptable range from the viewpoint of processing accuracy.

[0071] On the other hand, as described above, a reference potential (e.g., ground potential) or power supply potential is supplied to the fixed potential pattern FP. Therefore, from the viewpoint of stabilizing the potential of the fixed potential pattern FP, it is preferable that the width WFP of the fixed potential pattern FP in the Y direction be large.

[0072] For the reasons stated above, it is preferable that the distance GFW between each of the multiple wirings 2W1 and the fixed potential pattern FP at a position overlapping with the outer edge of the chip mounting area RCP is smaller than the width WFP of the fixed potential pattern FP in the Y direction.

[0073] Next, in the example shown in Figure 5, at the position overlapping with the outer edge of the chip mounting area RCP, the separation distance GFW between each of the multiple wirings 2W1 and the fixed potential pattern FP is smaller than the width WW1 of the multiple wirings 2W1. Note that if the width WW1 of the wirings 2W1 is small, the separation distance GFW may be the same value as the width WW1 of the wirings 2W1.

[0074] Each of the multiple wirings 2W1 is, for example, part of a transmission path for different electrical signals. In other words, each of the multiple wirings 2W1 constitutes a signal transmission path SGP. The signal transmission path SGP is designed so that there are no impedance discontinuities (in other words, so that it has a characteristic impedance) in order to suppress losses due to signal reflection. For this reason, the wirings 2W1 that make up the signal transmission path SGP are formed to extend with a constant wiring width. Furthermore, the wirings 2W1 are connected to bonding fingers BF1 to which wire BW (see Figure 3) is connected, or to through-hole lands 2THL to which through-hole wiring 2THW is connected.

[0075] From the perspective of matching the impedance of the conductor pattern 2CP1, such as bonding finger BF1 or through-hole land 2THL, ​​with that of the wiring 2W1, the width WW1 of the wiring 2W1 tends to be small. For example, in the example shown in Figure 5, the width WW1 of multiple wirings 2W1 is smaller than the width WBF of bonding finger BF1 in the Y direction.

[0076] In the example shown in Figure 5, the separation distance GFW is smaller than the width WW1 of the wiring 2W1 that constitutes the signal transmission path. As previously mentioned, reducing the value of the separation distance GFW can reduce the depth of the depression formed on the upper surface 2t of the insulating layer SR1 shown in Figure 6.

[0077] Furthermore, in the example shown in Figure 5, multiple conductor patterns 2CP1 include wiring 2W2, which is a power supply line. The width WW2 of wiring 2W2 is the same as, for example, the width WW1 of wiring 2W1. Therefore, in this embodiment, the separation distance GFW is smaller than the width WW2 of wiring 2W2, which is a power supply line.

[0078] <Modification of the area around the chip mounting area> Next, we will describe modifications of the semiconductor device PKG1 and wiring board SUB1 described using Figures 5 and 6. In the case of the semiconductor device PKG1 shown in Figures 5 and 6, an embodiment was described in which the gap between conductor patterns 2CP1 is reduced by placing a fixed potential pattern FP between adjacent wirings 2W1 in the chip mounting area RCP. In the modifications described below, an embodiment is described in which the gap between conductor patterns 2CP1 is reduced by increasing the wiring width. In the following, we will mainly describe the differences from the semiconductor device PKG1 and wiring board SUB1 already described, and in principle, we will omit the explanation of common parts.

[0079] Figure 9 is an enlarged plan view of a wiring board, which is a modified version of Figure 5. Figure 10 is an enlarged cross-sectional view along line EE of Figure 9. The wiring board SUB3 of the semiconductor device PKG3 shown in Figures 9 and 10 differs from the wiring board SUB1 described using Figures 5 and 6 in the following respects.

[0080] In the case of the wiring board SUB3, no fixed-potential pattern FP is placed between adjacent wirings 2W1 at the location overlapping with the outer edge of the chip mounting area RCP. In other words, multiple wirings 2W1 are adjacent to each other. This is the same as the wiring board SUB2 shown in Figure 7.

[0081] In the case of wiring board SUB3, the width WW1 of multiple wires 2W1 is wider than the spacing GWW between multiple wires 2W1. This differs from wiring board SUB1 shown in Figure 5 and wiring board SUB2 shown in Figure 7, respectively.

[0082] In the case of the wiring board SUB3 of the semiconductor device PKG3, the width WW1 of multiple wirings 2W1 is increased to reduce the distance GWW between adjacent wirings 2W1. In this modified example, by reducing the distance GWW between wirings 2W1, the depth of the depression formed on the upper surface 2t of the insulating layer SR1 shown in Figure 10 can be reduced.

[0083] In the example shown in Figure 9, no fixed-potential pattern FP is placed between multiple wirings 2W1 at the boundary between the chip mounting area RCP and the area RNCP outside the chip mounting area RCP. However, in a modified example, a fixed-potential pattern FP may be placed in part of the arrangement of multiple wirings 2W1. In this case, it is preferable that the relationship between the fixed-potential pattern FP and the wiring 2W1 adjacent to the fixed-potential pattern FP is as described using Figures 5 and 6. As explained using Figure 6, the depth of the depression formed on the upper surface 2t of the insulating layer SR1 can be reduced.

[0084] Furthermore, in the example shown in Figure 9, the width WW1 of the multiple wires 2W1 is greater than the width WBF of the bonding finger BF1. The bonding finger BF1 is the part that joins the wire BW, as shown in Figure 3. Therefore, considering the error in the positional accuracy of wire bonding, it is preferable that the width WBF be of a certain size. Note that if the arrangement pitch PF1 of the bonding finger BF1 is small, the width WW1 of the wire 2W1 may be the same as the width WBF of the bonding finger BF1.

[0085] On the other hand, wire BW is not connected to wiring 2W1. Furthermore, considering the characteristic impedance in the signal transmission path, impedance matching is easier if the width WW1 of wiring 2W1 is designed to be smaller than the width WBF of bonding finger BF1.

[0086] However, in this modified example, as shown in Figure 10, priority is given to reducing the value of the spacing GWW between the wirings 2W1. As a result, as described above, the width WW1 of the multiple wirings 2W1 is greater than the width WBF of the bonding finger BF1.

[0087] However, if the width WW1 of multiple wires 2W1 becomes extremely large, the flexibility of the wiring layout decreases. Also, if the width WW1 of multiple wires 2W1 becomes extremely large, it becomes difficult to match the impedance value of the signal transmission path to the characteristic impedance.

[0088] Therefore, it is preferable that the width WW1 of multiple wires 2W1 is not extremely large. In this modified example, as shown in Figure 9, each of the multiple wires 2W1 is connected to a through-hole land (via land) 2THL, ​​which has one end connected to a through-hole wire (via wire) 2THW. The width WTHL of the through-hole land 2THL is greater than the width WW1 of the wire 2W1. In other words, the width WW1 of the wire 2W1 (length of the wire 2W1 in the Y direction) is smaller than the width WTHL of the through-hole land 2THL (diameter of the through-hole land 2THL).

[0089] The semiconductor device PKG3 shown in Figures 9 and 10 differs from the semiconductor device PKG1 shown in Figures 5 and 6 in the following respects: In semiconductor device PKG3, the arrangement pitch PW1 of each of the multiple wirings 2W1 at a position overlapping with the outer edge of the chip mounting area RCP is equal to the arrangement pitch PF1 of each of the multiple bonding fingers BF1 in the Y direction. In other words, each of the multiple wirings 2W1 is arranged within the chip mounting area RCP with the same arrangement pitch PW1 as the arrangement pitch PF1 of the bonding fingers BF1.

[0090] Although not shown in the diagram, a further modification of the semiconductor device PKG3 is that the array pitch PW1 may be greater than the array pitch PF1 of each of the multiple bonding fingers BF1. However, in this modification, the width WW1 of the wiring 2W1 becomes even larger than in the example shown in Figure 9. Therefore, from the viewpoint of suppressing the increase in width WW1, it is preferable that the array pitch PW1 is less than or equal to the array pitch PF1 when no fixed-potential pattern FP is placed between adjacent wirings 2W1.

[0091] The semiconductor device PKG3 shown in Figures 9 and 10 is similar to the semiconductor device PKG1 shown in Figures 5 and 6, except for the differences described above. For example, each of the multiple wirings 2W1 shown in Figure 9 is part of a transmission path for different electrical signals. Also, for example, in a transparent plan view, the portion of the wiring layer WL1 shown in Figure 9 that overlaps with the chip mounting area RCP is entirely covered by the insulating layer SR1 (see Figure 10). Furthermore, as explained using Figure 3, each of the multiple bonding fingers BF has at least a portion where multiple wires BW are bonded exposed from the insulating layer SR1.

[0092] <Manufacturing method for semiconductor devices> Next, a method for manufacturing a semiconductor device will be described. Figure 11 is an explanatory diagram showing an example of the manufacturing process for the semiconductor device shown in Figure 1. The method for manufacturing a semiconductor device according to this embodiment includes the steps illustrated in Figure 11.

[0093] <Semiconductor chip preparation process> The semiconductor device manufacturing method according to this embodiment includes a semiconductor chip preparation step. In the semiconductor chip preparation step, the semiconductor chip CHP1 shown in Figure 12 is prepared. Figure 12 is a cross-sectional view of the semiconductor chip prepared in the semiconductor chip preparation step of Figure 11. The semiconductor chip CHP1 has an upper surface 3t and a lower surface 3b (see Figure 4) opposite to the upper surface 3t. Multiple pads (electrode pads) PD are arranged on the upper surface 3t of the semiconductor chip CHP1.

[0094] As shown in Figure 12, the adhesive DAF1 is pre-bonded to the lower surface 3b of the semiconductor chip CHP1 prepared in the semiconductor chip preparation process. The adhesive DAF1 has an adhesive layer ADL and a release layer RL attached to the lower surface ADLb of the adhesive layer ADL. The release layer RL is a non-adhesive resin layer. In addition to a single-layer structure of adhesive layer ADL, adhesive DAF1 also has a three-layer structure in which adhesive layer ADL is provided on both the upper and lower surfaces of the non-adhesive substrate. In either case, the adhesive layer ADL is attached to the lower surface 3b of the semiconductor chip CHP1. Furthermore, it is preferable that the release layer RL is attached to the adhesive layer ADL so that the lower surface ADLb of the adhesive layer ADL is not exposed until the semiconductor chip mounting process shown in Figure 11.

[0095] <Wiring board preparation process> The semiconductor device manufacturing method according to this embodiment includes a wiring board preparation step. In the wiring board preparation step, the wiring board SUB1 shown in Figure 13 is prepared. Figure 13 is a plan view showing an example of a wiring board prepared in the wiring board preparation step shown in Figure 11.

[0096] In the following description, we will focus on an embodiment in which a wiring board SUB1 corresponding to one semiconductor device is prepared. However, there are various variations in the wiring board prepared in this process.

[0097] For example, in this process, a so-called multi-cavity substrate may be prepared, which has multiple device areas (areas corresponding to the wiring board SUB1 in Figure 13). In this case, as will be explained below, manufacturing efficiency can be improved compared to assembling semiconductor device PKG1 one by one.

[0098] However, when manufacturing using a multi-piece substrate, a piece-making process is required, as shown in parentheses in Figure 11.

[0099] The wiring board SUB1 prepared in this process has an upper surface 2t that includes the chip mounting area RCP, which is the area where the semiconductor chip CHP1 is to be mounted. Of the wiring layer WL1 explained using Figures 5 and 6, the portion that overlaps with the chip mounting area RCP is entirely covered by the insulating layer SR1, as shown in Figure 13. In addition, for each of the multiple bonding fingers BF, the area where the wire BW (see Figure 3) is to be joined is exposed from the insulating layer SR1.

[0100] <Semiconductor chip mounting process> The semiconductor device manufacturing method according to this embodiment includes a semiconductor chip mounting process. In the semiconductor chip mounting process, as shown in Figures 3 and 4, a semiconductor chip CHP1 is mounted on the upper surface 2t of the wiring substrate SUB1.

[0101] As shown in Figure 12, which has already been explained, adhesive DAF1 is pre-bonded to the lower surface 3b of the semiconductor chip CHP1. In the semiconductor chip mounting process, after peeling off the release layer RL attached to the lower surface ADLb of the adhesive layer ADL of the adhesive DAF1, the lower surface ADLb is bonded to the upper surface 2t of the wiring board SUB1.

[0102] As described above, in the chip mounting area RCP of the wiring board SUB1 shown in Figure 13, the entire wiring layer WL1 (see Figure 5) is covered by the insulating layer SR1. Therefore, as explained using Figure 8, if many irregularities (depressions or grooves) are formed at a narrow pitch on the upper surface of the insulating layer SR1, voids (gaps) VD may occur between the adhesive DAF1 and the upper surface of the insulating layer SR1 (i.e., the upper surface 2t).

[0103] In this embodiment, as explained with reference to Figure 6, the depth of the depression formed on the upper surface of the insulating layer SR1 can be reduced. As a result, the entire insulating layer SR1 can be brought into close contact with the lower surface of the adhesive material DAF1, i.e., the lower surface ADLb of the adhesive layer ADL shown in Figure 12, in the chip mounting area RCP.

[0104] In this embodiment, the semiconductor chip CHP1 is mounted such that its lower surface 3b, which is the opposite side of the upper surface 3t on which multiple pads PD are arranged, faces the upper surface 2t of the wiring board SUB1. This mounting method is called the face-up mounting method.

[0105] <Wire bonding process> The semiconductor device manufacturing method according to this embodiment includes a wire bonding step. In the wire bonding step, as shown in Figures 3 and 4, a plurality of pads PD on the semiconductor chip CHP1 and a plurality of bonding fingers BF on the wiring board SUB1 are electrically connected via a plurality of wires BW.

[0106] <Sealing process> The semiconductor device manufacturing method according to this embodiment includes a sealing step. In the sealing step, as shown in Figure 4, each of the semiconductor chip CHP1 and the plurality of wires BW is sealed with a sealing body MR. The sealing body MR is formed on the upper surface 2t of the wiring substrate SUB1.

[0107] The method for forming the encapsulant MR is not particularly limited, and various methods can be applied. For example, one example is a method in which a fluid resin is molded in a mold and then the resin is cured, so-called transfer molding, to form the encapsulant MR.

[0108] <Ball mounting process> The semiconductor device manufacturing method according to this embodiment includes a ball mounting step. In the ball mounting step, multiple lands 2LD on the wiring board SUB1 shown in Figure 4 are joined to multiple solder balls SB. After placing the solder balls SB on each of the multiple lands 2LD exposed on the lower surface 2b of the wiring board SUB1, a reflow process is performed. The solder balls SB are joined to the lands 2LD by heating them above their melting point and then cooling them.

[0109] Through the above steps, the semiconductor device PKG1 shown in Figures 1 to 4 is obtained. As mentioned above, when using a multi-cavity substrate in the wiring substrate preparation step, a dicing step is performed in which each of the multiple device regions is separated into individual pieces by cutting along the dicing region.

[0110] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0111] For example, the various modifications described above may be combined with each other. [Explanation of Symbols]

[0112] 2b Bottom surface (surface, main surface, mounting surface) 2CP1, 2CP2 Conductor Pattern 2CR core insulating layer (insulating layer) 2LD Land (Terminal, Mounting Side Terminal) 2t Top surface (surface, main surface, chip mounting surface) 2THL Through Hole Land (Beer Land) 2THW Through-hole wiring (via wiring) 2W1, 2W2 wiring 3b Bottom surface (main surface, back surface) 3t Top surface (principal surface, surface) ADL adhesive layer ADLb bottom side BF, BF1 Bonding Fingers (Terminals, terminals on the chip mounting side) BW Wire CHP1 semiconductor chip DAF1 Adhesive FP fixed potential pattern (conductor plane, large area pattern) GFW separation distance GP Ground Route GWW separation distance MR sealed body MRb bottom side MRt top surface PD pads (electrode pads) PF1 array pitch PKG1, PKG2, PKG3 Semiconductor Device PW1 Array Pitch R1,RNCP area RCP chip mounting area RL Delamination Layer SB Handa Ball SGP signal transmission path SR1, SR2 insulating layer SUB1, SUB2, SUB3 Wiring Board VD (Void) WBF, WFP, WTHL, WW1, WW2 width WL1, WL2 wiring layers

Claims

1. A semiconductor chip having a first surface on which multiple electrode pads are arranged, and a second surface opposite to the first surface, A wiring board having a third surface including a chip mounting area on which the aforementioned semiconductor chip is mounted, A film-like adhesive is disposed between the second surface of the semiconductor chip and the third surface of the wiring substrate, and is bonded to the semiconductor chip and the wiring substrate, respectively. A plurality of wires connected to the semiconductor chip and the wiring board, It has, The aforementioned wiring board is A first wiring layer on which multiple first conductor patterns are formed, A first insulating layer that covers the first wiring layer and has the third surface, Includes, The plurality of first conductor patterns, in a transparent plan view, A plurality of bonding fingers are arranged outside the chip mounting area, to which the plurality of wires are joined, and which are arranged in a first direction. A plurality of first wirings are arranged within a first region including a portion of the outer edge of the chip mounting region and are connected to a plurality of first bonding fingers among the plurality of bonding fingers, A fixed potential pattern is arranged within the first region between two adjacent first wirings among the plurality of first wirings and connected to a fixed potential transmission path, Includes, A semiconductor device in which, in a transmitted plan view, the fixed potential pattern positioned between the two first wirings and the plurality of first wirings each extend in a second direction intersecting the first direction, straddling the outer edge of the chip mounting area.

2. In the semiconductor device described in claim 1, A semiconductor device wherein the arrangement pitch of each of the plurality of first wirings at a position overlapping with the portion of the outer edge of the chip mounting area is greater than the arrangement pitch of each of the plurality of first bonding fingers in the first direction.

3. In the semiconductor device described in claim 2, A semiconductor device wherein, at a position overlapping with the portion of the outer edge of the chip mounting area, the distance between each of the two first wirings and the fixed potential pattern is smaller than the width of the fixed potential pattern.

4. In the semiconductor device described in claim 1, A semiconductor device in which each of the plurality of first wirings is part of a transmission path for different electrical signals.

5. In the semiconductor device according to claim 4, A semiconductor device wherein, at a position overlapping with the portion of the outer edge of the chip mounting area, the distance between each of the two first wirings and the fixed potential pattern is smaller than the width of each of the two first wirings.

6. In the semiconductor device described in claim 5, A semiconductor device in which the width of each of the plurality of first wirings is smaller than the width of each of the plurality of first bonding fingers.

7. In the semiconductor device according to claim 4, A semiconductor device to which the ground potential is supplied to the aforementioned fixed potential pattern.

8. In the semiconductor device described in claim 1, The first wiring layer is, The portion overlapping with the chip mounting area is entirely covered by the first insulating layer. A semiconductor device wherein each of the plurality of bonding fingers has at least the portion to which the plurality of wires are joined exposed from the first insulating layer.

9. A semiconductor chip having a first surface on which multiple electrode pads are arranged, and a second surface opposite to the first surface, A wiring board having a third surface including a chip mounting area on which the aforementioned semiconductor chip is mounted, A film-like adhesive is disposed between the second surface of the semiconductor chip and the third surface of the wiring substrate, and is bonded to the semiconductor chip and the wiring substrate, respectively. A plurality of wires connected to the semiconductor chip and the wiring board, It has, The aforementioned wiring board is A first wiring layer on which multiple first conductor patterns are formed, A first insulating layer that covers the first wiring layer and has the third surface, Includes, The plurality of first conductor patterns, in a transparent plan view, A plurality of bonding fingers are arranged outside the chip mounting area, to which the plurality of wires are joined, and which are arranged in a first direction. A plurality of first wirings are arranged within a first region including a portion of the outer edge of the chip mounting region and are connected to a plurality of first bonding fingers among the plurality of bonding fingers, Includes, The plurality of first bonding fingers are arranged in a first direction, The width of the plurality of first wirings is wider than the distance between the plurality of first wirings. A semiconductor device in which, in a transparent planar view, each of the plurality of first wirings extends across the outer edge of the chip mounting area in a second direction intersecting the first direction.

10. In the semiconductor device described in claim 9, A semiconductor device in which the width of each of the plurality of first wirings is greater than the width of each of the plurality of first bonding fingers.

11. In the semiconductor device according to claim 10, Each of the aforementioned plurality of first wirings is connected to a via land, with one end connected to a via wiring. A semiconductor device wherein the width of the via land in the first direction is greater than the width of the first wiring.

12. In the semiconductor device described in claim 9, A semiconductor device in which each of the plurality of first wirings is part of a transmission path for different electrical signals.

13. In the semiconductor device described in claim 9, The first wiring layer is, In a transparent planar view, the portion overlapping with the chip mounting area is entirely covered by the first insulating layer. A semiconductor device wherein each of the plurality of bonding fingers has at least the portion to which the plurality of wires are joined exposed from the first insulating layer.

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