Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, using a bonding technology that facilitates the reuse of substrates. [Solution] The method involves forming an opening in a laminate having a first substrate 18 through which laser light can pass, a first layer provided on its first surface 18a, a second layer having a higher laser light absorption rate and thermal conductivity than the first layer, a third layer having a lower laser light absorption rate and thermal conductivity than the second layer, and a fifth layer provided between the first layer and the first substrate and having electrical conductivity, and forming an opening that penetrates the third layer, the second layer and the first layer and reaches the fifth layer, and forming an electrically conductive columnar portion in the opening, forming a fourth layer SL on the third layer that is electrically connected to the columnar portion and has electrical conductivity, forming a sixth layer 91 on the fourth layer that has a device electrically connected to the fourth layer, bonding a seventh layer 92 having an electrical circuit and provided on the third surface of a second substrate 17 having a third surface 17a and a fourth surface 17b, irradiating the second surface with laser light, and peeling off the first substrate.

Description

[[Technical Field]]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. [[Background Art]]

[0002] Semiconductor devices using a bonding technique for bonding substrates to each other and methods for manufacturing the same have been developed. [[Prior Art Documents]] [[Patent Documents]]

[0003] [[Patent Document 1]] US Patent Application Publication No. 2011 / 0132549 Specification [[Patent Document 2]] US Patent Application Publication No. 2007 / 0128827 Specification [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0004] An object of the embodiments is to provide a method for manufacturing a semiconductor device and a semiconductor device using a bonding technique for bonding substrates to each other, in which the substrate can be easily reused. [[Means for Solving the Problem]]

[0005] The manufacturing method of the semiconductor device of the embodiment involves forming an opening in a laminate that penetrates the third layer, the second layer and the first layer and reaches the fifth layer, forming an electrically conductive columnar portion in the opening, forming an electrically conductive fourth layer on the third layer which is electrically connected to the columnar portion, forming a sixth layer on the fourth layer which has a device electrically connected to the fourth layer, forming a seventh layer which has an electrical circuit and is provided on the third surface of the second substrate which has a third surface and the fourth surface, irradiating the second surface with laser light, and peeling off the first substrate. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view of the memory pillar CL of the semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a schematic cross-sectional view showing a method for manufacturing the main part of a semiconductor device according to the first embodiment. [Figure 7] This is a schematic cross-sectional view showing a method for manufacturing the main part of a semiconductor device according to the first embodiment. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing the main part of a semiconductor device according to the first embodiment. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing the main part of a semiconductor device according to the first embodiment. [Figure 10]It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the first embodiment. [Figure 11] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 12] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 13] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 14] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 15] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the second embodiment. [Figure 16] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the third embodiment. [Figure 17] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the third embodiment. [Figure 18] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the third embodiment. [Figure 19] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment. [Figure 20] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment. [Figure 21] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment. [Figure 22] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment. [Figure 23] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment. [Figure 24] It is a schematic cross-sectional view illustrating a method for manufacturing a main part of the semiconductor device according to the fourth embodiment.

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same or similar portions are denoted by the same or similar reference numerals.

[0008] In the present specification, to indicate the positional relationship of components and the like, the upward direction of the drawings is described as "upper" and the downward direction of the drawings as "lower". In the present specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity.

[0009] (First Embodiment) The method for manufacturing a semiconductor device of the present embodiment includes: forming, for a laminate including a first substrate that is permeable to laser light and has a first surface and a second surface, a first layer provided on the first surface, a second layer provided on the first layer, having a higher laser light absorptivity than the first layer and a higher thermal conductivity than the first layer, a third layer provided on the second layer, having a lower laser light absorptivity than the second layer and a lower thermal conductivity than the second layer, and a fifth layer provided between the first layer and the first substrate and having electrical conductivity, an opening that penetrates the third layer, the second layer and the first layer and reaches the fifth layer; forming a columnar portion having electrical conductivity in the opening, and a fourth layer that is electrically connected to the columnar portion and has electrical conductivity on the third layer; forming a sixth layer having a device electrically connected to the fourth layer on the fourth layer; bonding a seventh layer, which is provided on a third surface of a second substrate having the third surface and a fourth surface and has an electric circuit, to the sixth layer; irradiating the second surface with laser light; and peeling off the first substrate.

[0010] FIG. 1 is a schematic cross-sectional view of the semiconductor device of the present embodiment. The semiconductor device in FIG. 1 is a three-dimensional memory in which an array chip 1 and a circuit chip 2 are bonded together.

[0011] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, a third layer 56 on the memory cell array 11, an interlayer insulating film 13 under the memory cell array 11, and an insulating film 14 under the interlayer insulating film 13. The insulating film 14 is, for example, a silicon oxide film or a silicon nitride film. The third layer 56 will be described later.

[0012] The circuit chip 2 is located beneath the array chip 1. The symbol S indicates the bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 comprises an insulating film 15, an interlayer insulating film 16 beneath the insulating film 15, and a substrate 17 (an example of a second substrate) beneath the interlayer insulating film 16. The insulating film 15 is, for example, a silicon oxide film or a silicon nitride film. The substrate 17 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 17 has a surface 17a (an example of a third surface) and a surface 17b (an example of a fourth surface) opposite to surface 17a.

[0013] Figure 1 shows the X direction parallel to the surface (surfaces 17a and 17b) of the substrate 17, the Y direction parallel to the surface of the substrate 17 and intersecting the X direction, and the Z direction perpendicular to the surface of the substrate 17 and intersecting the X and Y directions.

[0014] For example, the memory cell array 11 is located above the substrate 17, and the substrate 17 is located below the memory cell array 11. The -Z direction may or may not coincide with the direction of gravity. The X and Y directions are also parallel to the surface (planes 18a and 18b) of the substrate 18, which will be described later, and the Z direction is also perpendicular to the surface of the substrate 18.

[0015] The array chip 1 comprises multiple word lines WL, a source-side selection gate SGS, a drain-side selection gate SGD, and a source line SL (an example of a fourth layer) as electrode layers within the memory cell array 11. Figure 1 shows the stepped structure 21 of the memory cell array 11.

[0016] As shown in Figure 1, each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22, and the source-side selection gate SGS is electrically connected to the source-side selection gate wiring layer 25 via a contact plug 24. Furthermore, the drain-side selection gate SGD is electrically connected to the drain-side selection gate wiring layer 27 via a contact plug 26, and the source line SL is electrically connected to the source wiring layer 30 via a contact plug 29. The memory pillar CL, which passes through the word lines WL, the source-side selection gate SGS, and the drain-side selection gate SGD, is electrically connected to the bit line BL via a plug 28 and is also electrically connected to the source line SL.

[0017] The circuit chip 2 comprises a plurality of transistors 31. Each transistor 31 comprises a gate electrode 32 provided on the substrate 17 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 17. The circuit chip 2 further comprises a plurality of plugs 33 provided on the source diffusion layer or drain diffusion layer of these transistors 31, a wiring layer 34 provided on these plugs 33 and containing a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and containing a plurality of wires. The circuit chip 2 further comprises a plurality of via plugs 36 provided on the wiring layer 35, and a plurality of metal pads 37 provided on these via plugs 36 within the insulating film 15. The metal pads 37 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip 2 functions as a control circuit (logic circuit) that controls the array chip 1. This control circuit includes transistors 31, etc., and is electrically connected to the metal pads 37.

[0018] The array chip 1 comprises a plurality of metal pads 41 provided on a metal pad 37 within an insulating film 14, a plurality of via plugs 42 provided on the metal pads 41, and a wiring layer 43 provided on these via plugs 42 and containing a plurality of wirings. Each word line WL and each bit line BL are electrically connected to the corresponding wiring in the wiring layer 43. The metal pads 41 are, for example, Cu layers or Al layers. The array chip 1 further comprises via plugs 44 provided within the interlayer insulating film 13 or the third layer 56 and on the wiring layer 43, and metal pads 45 provided on the insulating film 13 or on the via plugs 44. The metal pads 45 are, for example, Cu layers or Al layers and function as external connection pads (bonding pads) of the semiconductor device in Figure 1, and can be connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc.

[0019] Figure 2 is a schematic cross-sectional view of the memory pillar CL of the semiconductor device according to this embodiment.

[0020] As shown in Figure 2, the memory cell array 11 comprises a plurality of word lines WL and a plurality of insulating layers 81 alternately arranged on an interlayer insulating film 13 (Figure 1). These word lines WL are stacked spaced apart from each other in the Z direction. The word lines WL are, for example, W (tungsten) layers or Mo (molybdenum) layers. The insulating layer 81 is, for example, a silicon oxide film.

[0021] The memory pillar CL comprises, in order, a block insulating film 82, a charge storage layer 83, a tunnel insulating film 84, a channel semiconductor layer 85, and a core insulating film 86. The charge storage layer 83 is, for example, a silicon nitride film and is formed on the side surfaces of the word line WL and the insulating layer 81 via the block insulating film 82. The channel semiconductor layer 85 is, for example, a polysilicon layer and is formed on the side surfaces of the charge storage layer 83 via the tunnel insulating film 84. The block insulating film 82, the tunnel insulating film 84, and the core insulating film 86 are, for example, silicon oxide films or metal oxide films.

[0022] In Figure 1, an insulating film 14 is formed on the lower surface of the interlayer insulating film 13, but the insulating film 14 may be included in and integrated with the interlayer insulating film 13. Similarly, in Figure 1, an insulating film 15 is formed on the upper surface of the interlayer insulating film 16, but the insulating film 15 may be included in and integrated with the interlayer insulating film 16.

[0023] The portion of the array chip 1 from the insulating film 14 and metal pad 41 to the interlayer insulating film 13 below the source line SL and below the third layer 56 is the device layer 91. The device layer 91 is an example of a sixth layer having memory cells (an example of a device). Here, the memory pillar CL included in the memory cell array 11 is electrically connected to the source line SL. Therefore, the device layer 91 having memory cells is electrically connected to the source line SL. Note that the device included in the device layer 91 may be other devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), PRAM (Phase-change Random Access Memory), or JFET (Junction Field Effect Transistor).

[0024] The portion of the circuit chip 2 from the insulating film 15 and metal pad 37 to the interlayer insulating film 16, transistor 31, gate electrode 32, and plug 33 on the substrate 17 is the circuit layer 92. The circuit layer 92 is an example of a seventh layer having an electrical circuit. The circuit layer 92 is provided on surface 17a of the substrate 17.

[0025] Figures 3 to 5 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor device according to this embodiment.

[0026] Figure 3 shows the array chip 1 and the circuit chip 2. A substrate 18 (an example of a first substrate) is provided on the third layer 56. The substrate 18 is a semiconductor substrate such as a silicon substrate. The substrate 18 has a surface 18a (an example of a first surface) and a surface 18b (an example of a second surface).

[0027] A circuit chip 2 is fabricated by forming a transistor 31, a gate electrode 32, a plug 33, a wiring layer 34, a wiring layer 35, a via plug 36, an interlayer insulating film 16, an insulating film 15, a metal pad 37, etc., on a substrate 17.

[0028] Furthermore, a memory cell array 11 and an interlayer insulating film 13 are formed on the surface 18a of the substrate 18 via a third layer 56, and via plugs 44, wiring layers 43, via plugs 42, insulating film 14, metal pads 41, etc. are formed in the third layer 56 and the interlayer insulating film 13 to fabricate an array chip 1.

[0029] Next, the array chip 1 is bonded to the circuit chip 2 (Figure 4). In other words, the device layer 91 and the circuit layer 92 are bonded together. Specifically, first, the array chip 1 and the circuit chip 2 are bonded together by mechanical pressure. Next, the array chip 1 and the circuit chip 2 are annealed at a temperature of, for example, 250°C to 400°C. This causes the metal pad 41 to be bonded to the metal pad 37 and electrically bonded to the metal pad 37.

[0030] Next, the substrate 18 is removed from the array chip 1 (Figure 5). As a result, the via plugs 44 are exposed. The substrate 18 is removed, for example, by irradiating the surface 18b of the substrate 18 toward the device layer 91 with laser light, as described later. The substrate 18 may also be removed by CMP (Chemical Mechanical Polishing) or wet etching.

[0031] Next, a metal pad 45 (Figure 1) is formed on the third layer 56 and the via plug 44, for example, by CVD (Chemical Vapor Deposition) and RIE (Reactive Ion Etching), to obtain the semiconductor device of this embodiment.

[0032] For illustrative purposes, Figures 3 to 5 show one array chip 1 and one circuit chip 2. However, it is preferable to use a process in which a substrate 18 having multiple array chips 1 and a substrate 17 having multiple circuit chips 2 are bonded together, and then cut by dicing or the like.

[0033] Figures 6 to 10 are schematic cross-sectional views showing the manufacturing method of the main part (an example of a laminate) of the semiconductor device of this embodiment. Figures 6 to 10 are schematic cross-sectional views showing the periphery of the surface 18a of the substrate 18 of the semiconductor device. In Figures 6 to 8, the +Z direction is shown downwards in the drawing. In Figures 9 and 10, the +Z direction is shown upwards in the drawing.

[0034] First, a fifth layer 58 is formed on the surface 18a of the substrate 18. Next, a first layer 52 is formed on the fifth layer 58. Next, a second layer 54 is formed on the first layer 52. Next, a third layer 56 is formed on the second layer 54 (Figure 6). For example, CVD is used to form the fifth layer 58, the first layer 52, the second layer 54, and the third layer 56.

[0035] Next, an opening H1 is formed that penetrates the third layer 56, the second layer 54, and the first layer 52, reaching the fifth layer 58. For example, a RIE is used to form the opening H1.

[0036] Next, a source wire SL is formed on the third layer 56. A first columnar portion 60 (an example of a columnar portion) is also formed within the opening H1, electrically connected to the source wire SL and having electrical conductivity (Figure 7). For example, CVD is used to form the source wire SL and the first columnar portion 60.

[0037] As a result, the first layer 52 is provided on surface 18a. The second layer 54 is provided on top of the first layer 52. The third layer 56 is provided on top of the second layer 54. The fifth layer 58 is provided between surface 18a and the first layer 52.

[0038] The substrate 18 is transparent to laser light. For example, if the substrate 18 is a silicon substrate, a CO2 laser is preferably used as the laser. The wavelength of the CO2 laser is, for example, 9.2 μm to 10.8 μm. However, the combination of substrate 18 and laser is not limited to the above.

[0039] The second layer 54 has a higher laser light absorption rate and a higher thermal conductivity than the first layer 52 and the third layer 56. The first layer 52 and the third layer 56 have a lower laser light absorption rate and a lower thermal conductivity than the second layer 54. Preferably, the thermal conductivity of the first layer 52 is 1 / 10 or less of the thermal conductivity of the second layer 54.

[0040] For example, the first layer 52 and the third layer 56 may be layers containing silicon oxide. The first layer 52 and the third layer 56 may also contain other insulating materials, such as silicon nitride.

[0041] For example, consider the case where there is no second layer 54, and a first layer 52 or a third layer 56 is provided between the source line SL and the surface 18a. In this case, when the substrate 18 is peeled off by irradiating the surface 18b with laser light, the first layer 52 or the third layer 56 absorbs the laser light through the substrate 18, causing the substrate 18 to deform thermally and be peeled off. At this time, damage such as lattice defects may occur on the surface 18a of the substrate 18. Here, it is preferable that the peeled substrate 18 be reused to form the device layer 91 again. However, if damage occurs to the surface 18a, there is a problem that such reuse becomes difficult.

[0042] To suppress this, a second layer 54 is provided, which has a higher laser light absorption rate and a higher thermal conductivity than the first layer 52 and the third layer 56. In this case, the second layer 54 expands due to the absorption of laser light by the second layer 54. As a result, cracks are generated at the interface between the second layer 54 and the first layer 52, thereby suppressing damage to the substrate 18 and enabling the substrate 18 to be peeled off.

[0043] The second layer 54 preferably contains, for example, polysilicon. Compared to silicon oxide and silicon nitride, polysilicon has a higher thermal conductivity and a larger average coefficient of thermal expansion. Therefore, heat generated by the laser light is easily transferred uniformly throughout the second layer 54, making it easier for cracks to form between the first layer 52 and the second layer 54.

[0044] The film thickness of the first layer 52 is preferably 20 nm to 100 nm. The film thickness of the second layer 54 is preferably 100 nm to 500 nm.

[0045] The first columnar portion 60 is electrically conductive and electrically connects the source wire SL and the substrate 18. During the manufacturing process of semiconductor devices, "arking" can occur, in which a large current is instantaneously discharged through an insulator or air. To suppress the destruction of devices such as memory cells due to this "arking," the first columnar portion 60 is provided. As a result, the large current generated by the discharge from the device flows from the device through the first columnar portion 60 to the substrate 18 via the fifth layer 58, which will be described later. Therefore, device destruction is suppressed.

[0046] The first columnar portion 60 preferably contains polysilicon, for example. Alternatively, the source wire SL and the first columnar portion 60 may be formed simultaneously using polysilicon, for example by CVD.

[0047] In Figure 7, the shape of the first columnar portion 60 is such that its diameter decreases from the third layer 56 side towards the substrate 18 side. However, the shape of the first columnar portion 60 may also be such that its diameter increases from the third layer 56 side towards the substrate 18 side. Thus, the shape of the first columnar portion 60 is not limited to that shown in Figure 7.

[0048] The fifth layer 58 is electrically conductive and transmits laser light (is a layer through which laser light can pass). Preferably, the fifth layer 58 contains, for example, silicon and germanium. Preferably, the fifth layer 58 contains 40 atomic% to 60 atomic% of silicon and 10 atomic% to 60 atomic% of germanium. The fifth layer 58 may also be electrically conductive by containing an organic conductive film such as polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or PEDOT-PSS (poly(3,4-ethylence-dioxythiopherene-poly)).

[0049] When the device is heated to form the device within the device layer 91, for example, germanium in the fifth layer 58 diffuses into the polysilicon of the first columnar portion 60 and the polysilicon of the second layer 54 (Figure 8). The portion 55 in which germanium has diffused into the second layer 54 is also shown in Figure 8.

[0050] Next, the device layer 91 and the circuit layer 92 are bonded together, and the substrate 18 is peeled off by irradiating the surface 18b with laser light (Figure 9).

[0051] Next, a portion of the second layer 54 and a portion of the first columnar portion 60 on the third layer 56 are removed, for example, by CMP (Figure 10).

[0052] Next, the method for manufacturing the semiconductor device according to this embodiment and the effects of the semiconductor device will be described.

[0053] As described above, even if the second layer 54 is provided, if the fifth layer 58 is not provided and the surface 18a of the substrate 18 is in direct contact with the first columnar portion 60, there is a problem that the surface 18a will be damaged at the point where it contacts the surface 18a and the first columnar portion 60.

[0054] The provision of the fifth layer 58 prevents the first columnar portion 60 from directly contacting the surface 18a, or from a part of the first columnar portion 60 from being located within the substrate 18. Furthermore, because the fifth layer 58 is electrically conductive, the conduction of current from the first columnar portion 60 to the substrate 18 is not hindered. Moreover, because the fifth layer 58 transmits laser light, the heating of the second layer 54 by the laser light is not hindered. As a result, damage to the substrate 18 is suppressed, making it easier to reuse the substrate 18.

[0055] The fifth layer preferably contains 40 to 90 atomic percent of silicon and 10 to 60 atomic percent of germanium. This is because if the germanium ratio is less than 10 atomic percent, the frequency characteristics deteriorate, and if the germanium ratio is more than 60 atomic percent, controllability deteriorates due to lattice mismatch and other factors.

[0056] Preferably, the thermal conductivity of the first layer 52 is 1 / 10 or less of the thermal conductivity of the second layer 54. This allows the second layer 54 to conduct heat better than the first layer 52, making it easier for the second layer 54 to expand due to heat, and thus making it easier for cracks to occur at the interface between the second layer 54 and the first layer 52, thus facilitating the peeling of the substrate 18.

[0057] The thickness of the first layer 52 is preferably 20 nm or more and 100 nm or less. If the thickness of the first layer 52 is less than 20 nm, the first layer 52 is too thin, and cracks in the first layer 52 may cause damage to the surface 18a. On the other hand, if the thickness of the first layer 52 is thicker than 100 nm, the first layer 52 is too thick, and the laser light may not be properly transmitted to the second layer 54.

[0058] The thickness of the second layer 54 is preferably 100 nm or more and 500 nm or less. If the thickness of the second layer 54 is less than 100 nm, the second layer 54 is too thin, and the laser light may penetrate too far into the third layer 56, potentially resulting in insufficient heating of the second layer 54. On the other hand, if the thickness of the second layer 54 is thicker than 500 nm, the second layer 54 is too thick, and the laser light may not heat the entire second layer 54 uniformly, potentially resulting in the substrate 18 not being properly peeled off.

[0059] According to this embodiment, it becomes possible to provide a semiconductor device manufacturing method and a semiconductor device using a bonding technology that bonds substrates together, which facilitates the reuse of substrates.

[0060] (Second Embodiment) The semiconductor device manufacturing method of this embodiment involves forming an opening through the third layer, the second layer and the first layer in a laminate having a first substrate that is transparent to laser light and has a first surface and a second surface, a first layer provided on the first surface, a second layer provided on the first layer having a higher laser light absorption rate and a higher thermal conductivity than the first layer, and a third layer provided on the second layer having a lower laser light absorption rate and a lower thermal conductivity than the second layer, and within the opening, the side of the first layer and the side of the second layer A first film containing a material different from the first, second, and third layers is formed on the surface and the side surface of the third layer, an electrically conductive columnar portion is formed in the opening, a fourth layer electrically connected to the columnar portion and electrically conductive is formed on the third layer, a sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer, a seventh layer having an electrical circuit is provided on the third surface of the second substrate having the third surface and the fourth surface, and the sixth layer is bonded together, the second surface is irradiated with laser light and the first substrate is peeled off.

[0061] The semiconductor device of this embodiment comprises a second substrate having a third surface and a fourth surface; a seventh layer provided on the third surface and having an electrical circuit; a sixth layer provided on the seventh layer and having a device; a fourth layer provided on the sixth layer and electrically connected to the device and being electrically conductive; a third layer provided on the fourth layer; a columnar portion penetrating the third layer and electrically connected to the fourth layer and being electrically conductive; and a first film provided between the columnar portion and the third layer and containing a material different from that of the third layer.

[0062] Here, we will omit descriptions that overlap with those of the first embodiment.

[0063] Figures 11 to 15 are schematic cross-sectional views showing a manufacturing method for the main part (an example of a laminate) of the semiconductor device of this embodiment. In Figures 11 to 13, the +Z direction is shown downwards. In Figures 14 and 15, the +Z direction is shown upwards.

[0064] A first layer 52 is formed on the surface 18a of the substrate 18. Next, a second layer 54 is formed on the first layer 52. Next, a third layer 56 is formed on the second layer 54. In this embodiment, a fifth layer 58 is not provided. Next, an opening H1 is formed that penetrates the third layer 56, the second layer 54, and the first layer 52 and reaches the substrate 18 (Figure 11).

[0065] Next, a first film 62 is formed on the side surface 52a of the first layer, the side surface 54a of the second layer, and the side surface 56a of the third layer, for example, by CVD and etch-back. The first film 62 contains a different material from the first layer 52, the second layer 54, and the third layer 56 (Figure 12).

[0066] The first film 62 preferably contains, for example, silicon, carbon, and nitrogen. The first film 62 preferably contains, for example, silicon carbonitride. The first film 62 preferably is, for example, a SiCN film.

[0067] Alternatively, the first film 62 preferably contains, for example, silicon and nitrogen. The first film 62 preferably contains, for example, silicon nitride. The first film 62 preferably is, for example, a SiN film.

[0068] Next, an electrically conductive source wire SL is formed on the third layer 56. Furthermore, a first electrically conductive columnar portion 60 is formed within the opening H1, electrically connected to the source wire SL (Figure 13).

[0069] Next, the device layer 91 and the circuit layer 92 are bonded together, and the substrate 18 is peeled off by irradiating the surface 18b with laser light (Figure 14).

[0070] Next, a portion of the second layer 54 on the third layer 56, a portion of the first columnar portion 60, and a portion of the first film 62 between the third layer 56 and the first columnar portion 60 are removed, for example, by CMP. As a result, the first columnar portion 60 provided within the third layer 56 and the first film 62 provided between the third layer 56 and the first columnar portion 60 remain (Figure 15).

[0071] The other steps are the same as in the first embodiment.

[0072] The first film 62 is easily separated from the substrate 18 and the first layer 52 when stress is applied due to delamination of the substrate 18. This is because the first film 62 contains different materials from the first layer 52, the second layer 54, and the third layer 56. Therefore, damage to the substrate 18 from the first columnar portion 60 is less likely. In particular, if the first layer 52 contains silicon oxide, it is preferable that the first film 62 contains silicon, carbon, and nitrogen. Alternatively, it is preferable that the first film 62 contains silicon and nitrogen.

[0073] This embodiment also makes it possible to provide a semiconductor device manufacturing method and a semiconductor device that use a bonding technology to bond substrates together, which facilitates the reuse of substrates.

[0074] (Third embodiment) The semiconductor device manufacturing method of this embodiment involves forming an opening through the third layer, the second layer and the first layer on a second substrate, forming an electrically conductive columnar portion within the opening, forming an electrically conductive fourth layer on the third layer and the columnar portion, forming a sixth layer on the fourth layer having a device electrically connected to the fourth layer, bonding the seventh layer of the fourth substrate, which has a third surface and a fourth surface, and the seventh layer of the fourth substrate, which has an electrical circuit, and irradiating the second surface with laser light to peel off the first substrate.

[0075] Here, descriptions that overlap with the first and second embodiments are omitted.

[0076] Figures 16 to 18 are schematic cross-sectional views showing a manufacturing method for the main part (an example of a laminate) of the semiconductor device of this embodiment. In Figure 16, the +Z direction is shown downwards. In Figures 17 and 18, the +Z direction is shown upwards.

[0077] In this embodiment, after forming an opening H1 that penetrates the third layer 56, the second layer 54, and the first layer 52 and reaches the substrate 18, a second columnar portion 64 (an example of a columnar portion) containing single-crystal silicon is formed, for example, by epitaxial growth of silicon. Next, a source wire SL is formed on the third layer 56 and the second columnar portion 64. The source wire SL and the substrate 18 are electrically connected by the second columnar portion 64 (Figure 16).

[0078] Next, the device layer 91 and the circuit layer 92 are bonded together, and the substrate 18 is peeled off by irradiating the surface 18b with laser light (Figure 17).

[0079] Next, a portion of the second layer 54 above the third layer 56, and a portion of the second columnar portion 64 are removed, for example, by CMP. As a result, a portion of the second columnar portion 64 remains within the third layer 56 (Figure 18).

[0080] In Figure 17, the shape of the second columnar portion 64 is such that its diameter decreases from the side of the third layer 56 towards the side of the substrate 18. However, the shape of the second columnar portion 64 is not limited to that shown in Figure 17.

[0081] Other steps are the same as in the first and second embodiments.

[0082] In the first and second embodiments, the contact point between polysilicon and silicon was the interface between the first columnar portion 60 and the substrate 18. Therefore, the polysilicon contained in the first columnar portion 60 generates heat due to the laser. In contrast, in this embodiment, the contact point between polysilicon and silicon is the interface between the second columnar portion 64 and the source wire SL. This makes it possible to increase the distance between the polysilicon, which absorbs the laser and generates heat, and the substrate 18. As a result, stress is less likely to be directly applied to the substrate 18 during delamination. Therefore, damage to the substrate 18 can be suppressed.

[0083] This embodiment also makes it possible to provide a semiconductor device manufacturing method and a semiconductor device that use a bonding technology to bond substrates together, which facilitates the reuse of substrates.

[0084] (Fourth embodiment) The semiconductor device manufacturing method of this embodiment involves forming an opening in the laminate that penetrates the third layer, the second layer and the first layer and reaches the protrusion, forming an electrically conductive columnar portion in the opening, forming a fourth layer on the third layer which is electrically connected to the columnar portion and is electrically conductive, forming a sixth layer on the fourth layer which has a device electrically connected to the fourth layer, forming a seventh layer which has an electrical circuit and is provided on the third surface of the second substrate which has the third surface and the fourth surface, irradiating the second surface with laser light, and peeling off the first substrate.

[0085] Here, descriptions that overlap with the first to third embodiments are omitted.

[0086] Figures 19 to 24 are schematic cross-sectional views showing a manufacturing method for a key part (an example of a laminate) of the semiconductor device of this embodiment. In Figures 19 to 22, the +Z direction is shown downwards. In Figures 23 and 24, the +Z direction is shown upwards.

[0087] A protrusion 19 is formed on the substrate 18, for example, by photolithography. For example, a portion of the substrate 18 including surface 18a is removed, thereby forming the protrusion 19 on surface 18c (an example of the first surface) (Figure 19).

[0088] Next, a first layer 52 is formed on the surface 18c and the protrusion 19. Next, a second layer 54 is formed on the first layer 52. Next, a third layer 56 is formed on the second layer 54 (Figure 20).

[0089] Next, an opening H2 is formed that penetrates the third layer 56, the second layer 54, and the first layer 52, reaching the protrusion 19 (Figure 21).

[0090] Next, a source wire SL is formed on the third layer 56. A first columnar portion 60, electrically connected to the source wire SL and having electrical conductivity, is also formed within the opening H2 (Figure 22).

[0091] Next, the device layer 91 and the circuit layer 92 are bonded together, and the substrate 18 is peeled off by irradiating the surface 18b with laser light (Figure 23).

[0092] Next, any remaining parts of the second layer 54, the first layer 52, or the protrusions 19 on the third layer 56 are removed, for example, by CMP (Figure 24). Some of the first columnar portion 60, parts of the protrusions 19, parts of the first layer 52, or parts of the second layer 54 may remain within the third layer 56.

[0093] Other steps are the same as in the first to third embodiments.

[0094] In the first and second embodiments, the contact point between polysilicon and silicon was the interface between the first columnar portion 60 and the substrate 18. Therefore, the polysilicon contained in the first columnar portion 60 generates heat when exposed to the laser. In contrast, in this embodiment, the presence of the protrusion 19 increases the distance between the surface 18c and the first columnar portion 60 containing polysilicon that generates heat when exposed to the laser. This makes it less likely for stress to be directly applied to the substrate 18 during delamination. As a result, damage to the substrate 18 can be suppressed.

[0095] This embodiment also makes it possible to provide a semiconductor device manufacturing method and a semiconductor device that use a bonding technology to bond substrates together, which facilitates the reuse of substrates.

[0096] While several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0097] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 1) A first substrate having a first surface and a second surface, through which laser light can pass; A first layer provided on the first surface, A second layer is provided on the first layer, and has a higher absorption rate of the laser light and a higher thermal conductivity than the first layer. A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, A fifth layer, which is electrically conductive, is provided between the first layer and the first substrate. An opening is formed in the laminate having the third layer, the second layer and the first layer, and reaching the fifth layer. An electrically conductive columnar portion is formed within the opening, and a fourth layer, which is electrically connected to the columnar portion and is electrically conductive, is formed on the third layer. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A second substrate having a third surface and a fourth surface is provided on the third surface, and a seventh layer having an electrical circuit and the sixth layer are bonded together. The laser light is irradiated onto the second surface, Remove the first substrate. A method for manufacturing a semiconductor device. (Technical proposal 2) The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The aforementioned second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. The fifth layer contains silicon and germanium. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 3) When forming the sixth layer, the germanium in the fifth layer diffuses to the columnar portion and the second layer. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 4) The fifth layer contains 40 to 90 atomic percent of silicon and 10 to 60 atomic percent of germanium. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 5) The thickness of the first layer is 20 nm or more and 100 nm or less. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 6) The thickness of the second layer is between 100 nm and 500 nm. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 7) The thermal conductivity of the first layer is 1 / 10 or less of the thermal conductivity of the second layer. A method for manufacturing a semiconductor device as described in Technical Proposal 1. (Technical proposal 8) The aforementioned laser light is irradiated using a CO2 laser. A method for manufacturing a semiconductor device as described in Technical Proposal 1.

[0098] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 9) A first substrate having a first surface and a second surface, through which laser light can pass; A first layer provided on the first surface, A second layer is provided on the first layer, and has a higher absorption rate of the laser light and a higher thermal conductivity than the first layer. A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, To a laminate having the above, an opening is formed that penetrates the third layer, the second layer and the first layer. A first film containing a material different from the first, second, and third layers is formed on the side surfaces of the first layer, the second layer, and the third layer within the opening. An electrically conductive columnar portion is formed within the opening, and a fourth layer, which is electrically connected to the columnar portion and is electrically conductive, is formed on the third layer. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A second substrate having a third surface and a fourth surface is provided on the third surface, and a seventh layer having an electrical circuit and the sixth layer are bonded together. The laser light is irradiated onto the second surface, Remove the first substrate. A method for manufacturing a semiconductor device. (Technical proposal 10) The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The aforementioned second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. The first film contains nitrogen and silicon. A method for manufacturing a semiconductor device as described in Technical Proposal 9. (Technical proposal 11) The aforementioned first film further contains carbon, A method for manufacturing a semiconductor device as described in Technical Proposal 10. (Technical proposal 12) The thickness of the first layer is 20 nm or more and 100 nm or less. A method for manufacturing a semiconductor device as described in Technical Proposal 9. (Technical proposal 13) The thickness of the second layer is between 100 nm and 500 nm. A method for manufacturing a semiconductor device as described in Technical Proposal 9. (Technical proposal 14) The thermal conductivity of the first layer is 1 / 10 or less of the thermal conductivity of the second layer. A method for manufacturing a semiconductor device as described in Technical Proposal 9. (Technical proposal 15) The aforementioned laser light is irradiated using CO2 laser light. A method for manufacturing a semiconductor device as described in Technical Proposal 9.

[0099] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 16) A second substrate having a third surface and a fourth surface, A seventh layer is provided on the third surface and has an electrical circuit, A sixth layer having a device is provided on the seventh layer, A fourth electrically conductive layer is provided on the sixth layer and electrically connected to the device, A third layer is provided on top of the aforementioned fourth layer, A columnar portion that penetrates the third layer, is electrically connected to the fourth layer, and has electrical conductivity, A first film is provided between the columnar portion and the third layer, and the first film contains a material different from that of the third layer. A semiconductor device equipped with a semiconductor device. (Technical proposal 17) The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. The first film contains nitrogen and silicon. A semiconductor device as described in Technical Proposal 16.

[0100] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 18) A first substrate having a first surface and a second surface, through which laser light can pass; A first layer provided on the first surface, A second layer is provided on the first layer, and has a higher absorption rate of the laser light and a higher thermal conductivity than the first layer. A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, An opening is formed in the second substrate having the third layer, the second layer and the first layer, An electrically conductive columnar portion is formed within the opening. A fourth layer is formed on the third layer and the columnar portion, which is electrically conductive and contains a material different from that of the columnar portion. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A third substrate having a third surface and a fourth surface, A seventh layer is provided on the third surface and has an electrical circuit, The seventh layer of the fourth substrate having the sixth layer is bonded to the sixth layer. The laser light is irradiated onto the second surface, Remove the first substrate. A method for manufacturing a semiconductor device. (Technical proposal 19) The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The aforementioned second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer contains polysilicon, The columnar portion contains single-crystal silicon. A method for manufacturing a semiconductor device as described in Technical Proposal 18.

[0101] Furthermore, the above embodiments can be summarized in the following technical proposal. (Technical proposal 20) A first substrate that is transparent to laser light and has a first surface, a second surface, and a protrusion provided on the first surface, A first layer provided on the first surface and the protrusion, A second layer is provided on the first layer, and has a higher absorption rate of the laser light and a higher thermal conductivity than the first layer. A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, An opening is formed in the laminate having the third layer, the second layer and the first layer, and reaching the protrusion. An electrically conductive columnar portion is formed within the opening, and a fourth layer, which is electrically connected to the columnar portion and is electrically conductive, is formed on the third layer. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A second substrate having a third surface and a fourth surface is provided on the third surface, and a seventh layer having an electrical circuit is bonded to the sixth layer. The laser light is irradiated onto the second surface, Remove the first substrate. A method for manufacturing a semiconductor device. (Technical proposal 21) The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The aforementioned second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. A method for manufacturing a semiconductor device as described in Technical Proposal 20. [Explanation of symbols]

[0102] 1: Array chip 2: Circuit chip 11: Memory cell array 13: Interlayer insulating film 14: Insulating film 15: Insulating film 16: Interlayer insulating film 17: Circuit board (second circuit board) 17a: Side (3rd side) 17b: Surface (4th surface) 18: Circuit board (first circuit board) 18a: Side (first side) 18b: Side (2nd side) 18c: Surface (first side) 19: Convex part 21: Stair structure 22: Contact Plug 23: Word Wiring Layer 24: Contact plug 25: Source-side selected gate wiring layer 26: Contact plug 27: Drain-side selected gate wiring layer 28: Plug 29: Contact plug 30: Source wiring layer 31: Transistor 32: Grid gate 33: Plug 34: Wiring layer 35: Wiring layer 36: Beer Plug 37: Metal pad 41: Metal pad 42: Beer Plug 43: Wiring layer 44: Beer Plug 45: Metal pad 52: 1st layer 52a: Side view 54: 2nd layer 54a: Side view 56: 3rd layer 56a: Side 58: 5th layer 60: 1st columnar part (columnar part) 62: 1st membrane 64:Second columnar part (columnar part) 72:Circuit layer 81: Insulating layer 82: Block insulating film 83: Charge storage layer 84: Tunnel Insulating Film 85: Channel semiconductor layer 86: Core insulating film 91: Device layer (the 6th layer containing the device) 92: Circuit layer (the 7th layer containing electrical circuits) BL: Bit line CL: Memory Pillar H1: Opening H2: Opening SGD: Drain-side selection gate SGS: Source-side selection gate SL: Source line (Layer 4) WL: Word line

Claims

1. A first substrate having a first surface and a second surface, through which laser light can pass; A first layer provided on the first surface, A second layer is provided on the first layer, having a higher absorption rate of the laser light and a higher thermal conductivity than the first layer, A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, A fifth layer, which is electrically conductive, is provided between the first layer and the first substrate. An opening is formed in the laminate having the third layer, the second layer and the first layer, and reaching the fifth layer. An electrically conductive columnar portion is formed within the opening, and a fourth layer, which is electrically connected to the columnar portion and is electrically conductive, is formed on the third layer. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A second substrate having a third surface and a fourth surface is provided on the third surface, and a seventh layer having an electrical circuit and the sixth layer are bonded together. The laser light is irradiated onto the second surface, The first substrate is peeled off. A method for manufacturing a semiconductor device.

2. The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. The fifth layer contains silicon and germanium. A method for manufacturing a semiconductor device according to claim 1.

3. When the sixth layer is formed, the germanium in the fifth layer diffuses to the columnar portion and the second layer. A method for manufacturing a semiconductor device according to claim 1.

4. The fifth layer contains 40 atomic percent or more and 90 atomic percent or less of silicon, and 10 atomic percent or more and 60 atomic percent or less of germanium. A method for manufacturing a semiconductor device according to claim 1.

5. The thickness of the first layer is 20 nm or more and 100 nm or less. A method for manufacturing a semiconductor device according to claim 1.

6. The thickness of the second layer is 100 nm or more and 500 nm or less. A method for manufacturing a semiconductor device according to claim 1.

7. The thermal conductivity of the first layer is 1 / 10 or less of the thermal conductivity of the second layer. A method for manufacturing a semiconductor device according to claim 1.

8. The aforementioned laser light is CO ２ Irradiated using a laser, A method for manufacturing a semiconductor device according to claim 1.

9. A second substrate having a third surface and a fourth surface, A seventh layer is provided on the third surface and has an electrical circuit, A sixth layer having a device is provided on the seventh layer, A fourth electrically conductive layer is provided on the sixth layer and electrically connected to the device, A third layer is provided on top of the aforementioned fourth layer, A columnar portion that penetrates the third layer, is electrically connected to the fourth layer, and is electrically conductive, A first film is provided between the columnar portion and the third layer, and the first film contains a material different from that of the third layer. A semiconductor device equipped with a semiconductor device.

10. The third layer contains silicon and oxygen, The fourth layer and the columnar portion contain polysilicon. The first film contains nitrogen and silicon. The semiconductor device according to claim 9.

11. A first substrate having a first surface and a second surface, through which laser light can pass; A first layer provided on the first surface, A second layer is provided on the first layer, having a higher absorption rate of the laser light and a higher thermal conductivity than the first layer, A third layer is provided on the second layer, having a lower absorption rate of the laser light and a lower thermal conductivity than the second layer, An opening is formed in the second substrate having the third layer, the second layer, and the first layer, An electrically conductive columnar portion is formed within the opening. A fourth layer is formed on the third layer and the columnar portion, which is electrically conductive and contains a material different from that of the columnar portion. A sixth layer having a device electrically connected to the fourth layer is formed on the fourth layer. A third substrate having a third surface and a fourth surface, A seventh layer is provided on the third surface and has an electrical circuit, The seventh layer of the fourth substrate having the sixth layer is bonded to the sixth layer. The laser light is irradiated onto the second surface, The first substrate is peeled off. A method for manufacturing a semiconductor device.

12. The first substrate is a silicon substrate, The first layer contains silicon and oxygen, The second layer contains polysilicon, The third layer contains silicon and oxygen, The fourth layer contains polysilicon, The columnar portion contains single-crystal silicon. A method for manufacturing a semiconductor device according to claim 11.

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