Chip resistor

Abstract

To provide chip resistors with fewer plating defects. [Solution] The device comprises an insulating substrate 2, a first electrode 3 disposed on a first main surface 21 located on one side of the insulating substrate 2 in the thickness direction, a resistor 4 formed on the first main surface 21 and electrically connected to the first electrode 3, a second electrode 5 disposed on a second main surface 22 located on the other side of the insulating substrate 2 in the thickness direction, an end electrode 6 formed on an end surface 23 along the thickness direction of the insulating substrate 2 and electrically connecting the first electrode 3 and the second electrode 5, and a plating layer 7 formed over the surfaces of the first electrode 3, the second electrode 5 and the end electrode 6. The second electrode 5 is formed in an electrode formation region 50 on the second main surface 22, and the electrode formation region 50 has a plating reduction portion 500 to which the plating layer 7 is less likely to adhere than to the second electrode 5.

Description

[Technical Field]

[0001] The present disclosure relates to a chip resistor. More specifically, the present disclosure relates to a chip resistor including an insulating substrate and a resistor body. [Background Art]

[0002] Patent Document 1 discloses a chip resistor including: an insulating substrate formed into a rectangle in a plan view; a resistive film formed on an upper surface of the insulating substrate; a pair of upper surface electrodes formed on the upper surface of the insulating substrate; and a pair of terminal electrodes formed on both left and right long side surfaces of the insulating substrate extending in the longitudinal direction of the rectangle, the terminal electrodes being electrically connected to the upper surface electrodes.

[0003] Each of the upper surface electrodes is formed in a portion of the upper surface of the insulating substrate adjacent to the long side surface of the insulating substrate, and extends in a strip shape along the long side surface. Meanwhile, one end of the resistive film is integrally provided with a connection portion connected to one of the two upper surface electrodes, and the other end of the resistive film is integrally provided with a connection portion connected to the other upper surface electrode. These two connection portions are connected to respective corresponding upper surface electrodes at positions spaced an appropriate distance from each other along the longitudinal direction of the rectangle of the insulating substrate. [Prior Art Document] [Patent Document]

[0004] [Patent Document 1] Japanese Unexamined Patent Publication No. 2007-142165 [Summary of the Invention] [Problem to be Solved by the Invention]

[0005] In the chip resistor described above, terminal electrodes that electrically connect the upper and lower electrodes are formed by a plating layer. This plating layer is formed by barrel plating in a barrel with many work-in-progress pieces before the terminal electrodes are formed. However, if the plating layer is formed with the lower surfaces of the work-in-progress pieces facing each other, the lower electrodes will bond together, and a defect (poor adhesion) is likely to occur where the plating layer is not formed properly.

[0006] While the above-mentioned defects can be reduced by decreasing the amount of work-in-progress loaded into the barrel, this also risks decreasing the production quantity per batch and worsening mass productivity.

[0007] The objective of this disclosure is to provide a chip resistor with fewer plating defects. [Means for solving the problem]

[0008] A chip resistor according to one aspect of the present disclosure comprises an insulating substrate, a first electrode disposed on a first main surface located on one side of the insulating substrate in the thickness direction, a resistor formed on the first main surface and electrically connected to the first electrode, a second electrode disposed on a second main surface located on the other side of the insulating substrate in the thickness direction, an end face electrode formed on an end face of the insulating substrate along the thickness direction and electrically connecting the first electrode and the second electrode, and a plating layer formed over the surfaces of the first electrode, the second electrode and the end face electrode, wherein the second electrode is formed in an electrode formation region on the second main surface, and the electrode formation region has a plating reduction portion to which the plating layer is less likely to adhere than to the second electrode. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide chip resistors with fewer plating defects. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a cross-sectional view showing a first embodiment of the chip resistor according to this disclosure. [Figure 2] Figure 2 is a bottom view showing a portion of the same. [Figure 3] Figure 3 is a cross-sectional view of line III-III in Figure 2. [Figure 4] Figure 4 is a bottom view showing a part of a second embodiment of the chip resistor according to this disclosure. [Figure 5] Figure 5 is a cross-sectional view of VV in Figure 4. [Figure 6] Figure 6 is a bottom view showing a part of the third embodiment of the chip resistor according to this disclosure. [Figure 7] Figure 7 is a cross-sectional view of XX in Figure 6. [Figure 8] Figure 8 is a bottom view showing a part of the fourth embodiment of the chip resistor according to this disclosure. [Figure 9] Figure 9 is a cross-sectional view taken along line XII-XII in Figure 8. It is a cross-sectional view of a chip resistor according to this embodiment. [Figure 10] Figure 10 is a bottom view showing a part of the fifth embodiment of the chip resistor according to this disclosure. [Figure 11] Figure 11 is a rear view taken from the direction of arrow D31 in Figure 10. [Figure 12] Figure 12 is a front view taken from the direction of arrow D32 in Figure 10. [Modes for carrying out the invention]

[0011] 1. Overview Embodiments of this disclosure will be described with reference to the figures. Note that the embodiments described below are only a selection of the various embodiments of this disclosure. Furthermore, the embodiments described below can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved. The figures referenced below are schematic diagrams, and the dimensional ratios of the components shown in the figures do not necessarily reflect the actual dimensional ratios. The arrows indicating direction in the drawings are not intended to specify the direction in which the chip resistor 1 is used, but are merely there to facilitate understanding of the explanation and do not represent actual dimensions.

[0012] In the present disclosure, the first direction D1 indicates the thickness direction (vertical direction) of the chip resistor 1, the second direction D2 indicates the left-right direction of the chip resistor 1, and the third direction D3 indicates the front-rear direction of the chip resistor 1.

[0013] As shown in FIG. 1, the chip resistor 1 according to the present embodiment includes an insulating substrate 2, a first electrode 3, a resistor 4, a second electrode 5, an end face electrode 6, and a plating layer 7.

[0014] The first electrode 3 is disposed on a first main surface 21 located on one side in the thickness direction of the insulating substrate 2. The resistor 4 is formed on the first main surface 21 and electrically connected to the first electrode 3. The second electrode 5 is disposed on a second main surface 22 located on the other side in the thickness direction of the insulating substrate 2. The end face electrode 6 is formed on an end face 23 along the thickness direction of the insulating substrate 2, and electrically connects the first electrode 3 and the second electrode 5. The plating layer 7 is formed over the surfaces of the first electrode 3, the second electrode 5, and the end face electrode 6. The second electrode 5 is formed in an electrode formation region 50 on the second main surface 22, and the electrode formation region 50 is provided with a plating reduction portion 500 to which the plating layer 7 is less likely to adhere than to the second electrode 5.

[0015] In the chip resistor 1 of the present embodiment, the electrode formation region 50 where the second electrode 5 is formed has the plating reduction portion 500 to which the plating layer 7 is less likely to adhere than to the second electrode 5, so that the plating layer 7 is less likely to be formed on the plating reduction portion 500. That is, conventionally, the solid (flat) second electrode 5 is formed over the entire electrode formation region 50, and no portion to which the plating layer 7 is less likely to adhere, such as the plating reduction portion 500, is provided. Therefore, in the present embodiment, the amount (size and area) of the plating layer 7 formed in the electrode formation region 50 can be reduced compared to the case where the second electrode 5 is formed over the entire electrode formation region 50. Accordingly, when forming the plating layer 7, even if the second electrodes 5 are arranged to face each other, bonding of the second electrodes 5 to each other by the plating layer 7 is reduced, and plating defects (such as chipping and peeling) of the plating layer 7 can be reduced.

[0016] In the chip resistor 1 of the present embodiment, since the plating reducing portion 500 exists in the electrode forming region 50, a portion where the plating layer 7 is not formed may exist as a void in the electrode forming region 50. Therefore, even when the chip resistor 1 of the present embodiment is heated during mounting on another member such as a circuit board by solder bonding, the expansion and contraction of the second electrode 5 and the expansion and contraction of the circuit board caused by the heating are absorbed by the voids, so that strain generated in the solder can be alleviated. Accordingly, damage to the second electrode 5, the solder and the circuit board is less likely to occur, and falling off of the chip resistor 1 from the circuit board can be reduced.

[0017] 2. Details (First Embodiment) (1) Description of chip resistor FIG. 1 shows the chip resistor 1 of the present embodiment. The chip resistor 1 is mounted on the surface (upper surface) of a circuit board 100. The circuit board 100 is formed of a printed wiring board or the like, and a wiring portion 102 is provided on the surface of an insulating layer 101. The chip resistor 1 is disposed on the wiring portion 102 and bonded to the wiring portion 102 by solder 103. The solder 103 bonds the surface of the wiring portion 102 to the outer surface of the plating layer 7 on the lower surface and side surfaces (right surface and left surface) of the chip resistor 1.

[0018] The chip resistor 1 includes an insulating substrate 2, a pair of first electrodes 3, a resistor 4, a pair of second electrodes 5, a pair of end face electrodes 6, and a plating layer 7.

[0019] <Insulating Substrate> The insulating substrate 2 is, for example, a ceramic substrate. The material of the ceramic substrate is, for example, an alumina sintered body having an alumina content of 96% or more. The insulating substrate 2 is formed in a rectangular shape in a plan view from the first direction D1. In the first embodiment, the insulating substrate 2 is formed in a rectangular shape having a long side extending in a second direction D2 orthogonal to the first direction D1, and a short side extending in a third direction D3 orthogonal to the first direction D1 and the second direction D2. The insulating substrate 2 has a first main surface (upper surface) 21, a second main surface (lower surface) 22, and an end face (outer peripheral surface) 23.

[0020] The first main surface 21 and the second main surface 22 face each other in the first direction D1. Each of the first main surface 21 and the second main surface 22 is a plane along the second direction D2. The end face (outer peripheral surface) 23 includes four sides along the first direction D1. The first direction D1 is the direction parallel to the thickness direction of the insulating substrate 2 (up and down direction in Figure 1). The second direction D2 is the direction parallel to the longitudinal direction or width direction (short direction) of the insulating substrate 2 (left and right direction in Figure 1). In the first embodiment, as an example, the second direction D2 is the direction parallel to the longitudinal direction of the insulating substrate 2.

[0021] <resistor> The resistor 4 is provided on the insulating substrate 2. More specifically, the resistor 4 is, for example, a thick film and is formed on the first main surface 21 of the insulating substrate 2. In a plan view from the first direction D1, the resistor 4 is, for example, rectangular, but any shape is possible depending on the resistance value of the resistor 4. The resistor 4 is not formed on the first main surface 21 over the entire length of the second direction D2 and the third direction D3, and is not formed at both ends of the second direction D2 and the third direction D3.

[0022] The resistor 4 electrically connects a pair of first electrodes (top electrodes) 3. The resistor 4 is a cured product formed by printing a thick film material (paste) containing, for example, copper-nickel, silver-palladium, or ruthenium oxide onto the first main surface 21 of the insulating substrate 2, and then firing it.

[0023] <First electrode> The chip resistor 1 of this embodiment has a pair of first electrodes (top electrodes) 3. The pair of first electrodes 3 are provided on an insulating substrate 2. More specifically, the pair of first electrodes 3 are formed on a first main surface 21 located on one side in the thickness direction (first direction D1) of the insulating substrate 2. The pair of first electrodes 3 are provided at both ends of the insulating substrate 2 in the left-right direction (second direction D2). Each of the pair of first electrodes 3 contains at least one of Cu and Ag. In the first embodiment, each of the pair of first electrodes 3 is formed by printing and firing a thick film material having a metal such as silver. Each of the pair of first electrodes 3 is, for example, rectangular in a plan view from the first direction D1. The pair of first electrodes 3 are formed on the first main surface 21 over the entire length in the third direction D3.

[0024] <Second electrode> The chip resistor 1 of this embodiment has a pair of second electrodes (bottom electrodes) 5. Each of the pair of second electrodes 5 is made of, for example, an epoxy resin containing Ag (silver) as a conductor. The pair of second electrodes 5 are formed on the second main surface 22 located on the other side in the thickness direction (first direction D1) of the insulating substrate 2. As shown in Figure 1, the pair of second electrodes 5 are located at both ends in the left-right direction (second direction D2) of the second main surface 22 of the insulating substrate 2. The pair of second electrodes 5 are formed, for example, by screen printing to apply silver-containing epoxy resin to both ends in the left-right direction of the second main surface 22 of the insulating substrate 2, and then curing the silver-containing epoxy resin by irradiation with ultraviolet light.

[0025] The pair of second electrodes 5 correspond one-to-one with the pair of first electrodes 3. That is, one first electrode 3 and the second electrode 5 in the second direction D2 (for example, the right side) correspond to each other, and the other first electrode 3 and the second electrode 5 in the second direction D2 (for example, the left side) correspond to each other. The corresponding first electrodes 3 and second electrodes 5 are electrically connected by the end face electrodes 6.

[0026] When viewed from a direction perpendicular to the second main surface 22, the ratio of the area of ​​the pair of second electrodes 5 to the area of ​​the second main surface 22 is preferably 30% or more and 75% or less. This makes it possible to reduce the overlapping area of ​​the second electrodes 5 formed on two different insulating substrates 2 while ensuring electrical connection with the end electrode 6, and makes it difficult for the second electrodes 5 to bond to each other when the plating layer 7 is formed.

[0027] <End face electrode> The chip resistor 1 of this embodiment has a pair of end electrodes 6. The pair of end electrodes 6 are formed on the end face (outer peripheral surface) 23 of the insulating substrate 2 along the thickness direction (first direction D1). Each of the pair of end electrodes 6 is made of an alloy such as CuNi or NiCr. The pair of end electrodes 6 are located at both ends of the insulating substrate 2 in the second direction D2. The pair of end electrodes 6 are formed at both ends of the insulating substrate 2 in the left-right direction, for example, using a thin-film process such as sputtering. The pair of end electrodes 6 each electrically connect the corresponding first electrode 3 and second electrode 5. That is, one end electrode 6 (for example, the right side) electrically connects one corresponding first electrode 3 and second electrode 5 in the thickness direction, and the other end electrode 6 (for example, the left side) electrically connects the other corresponding first electrode 3 and second electrode 5 in the thickness direction.

[0028] The end face electrode 6 has an end face portion 60, a first electrode portion 61, and a second electrode portion 62. The end face portion 60 is formed on the end face (outer peripheral surface) 23 of the insulating substrate 2. The first electrode portion 61 is provided at one end (upper end) of the end face portion 60 in a first direction D1. The first electrode portion 61 is provided in contact with the surface of the first electrode 3 and covers a portion of the surface of the first electrode 3 in a second direction D2. The second electrode portion 62 is provided at the other end (lower end) of the end face portion 60 in a first direction D1. The second electrode portion 62 is provided in contact with the surface of the second electrode 5 and covers a portion of the surface of the second electrode 5 in a second direction D2.

[0029] <Plating layer> The chip resistor 1 of this embodiment has a pair of plating layers 7. The pair of plating layers 7 are formed over the surfaces of the first electrode (upper electrode) 3, the second electrode (lower electrode) 5, and the end electrode 6, respectively. That is, one (for example, the right side) plating layer 7 is formed over one first electrode 3 and second electrode 5 and the end electrode 6 that electrically connects them in the thickness direction, while the other (for example, the left side) plating layer 7 is formed over the other first electrode 3 and second electrode 5 and the end electrode 6 that electrically connects them in the thickness direction.

[0030] Each pair of plating layers 7 covers a portion of the corresponding first electrode 3 of the pair of first electrodes 3 (the portion not covered by the second protective film 82) and is in contact with the second protective film 82. Each pair of plating layers 7 covers the entirety of the corresponding end electrode 6 of the pair of end electrodes 6. Each pair of plating layers 7 covers the entirety of the corresponding second electrode 5 of the pair of second electrodes 5.

[0031] Each pair of plating layers 7 is composed of two layers: a Ni plating layer and a Sn plating layer. The Ni plating layer is in contact with the surfaces of the first electrode 3, the second electrode 5, and the end electrode 6. The Sn plating layer is formed to cover the outer surface of the Ni plating layer. Therefore, the outer surface of the pair of plating layers 7 is formed of the Sn plating layer.

[0032] <Protective film> The protective film 8 is a film that covers and protects the resistor 4. As shown in Figure 1, the protective film 8 also covers a portion of the pair of first electrodes 3. The protective film 8 has a first protective film 81 and a second protective film 82.

[0033] The first protective film 81 is an inorganic protective film, made of, for example, lead oxide glass. The first protective film 81 is formed, for example, by screen printing and firing. Note that the first protective film 81 is not limited to lead oxide glass, but may be made of, for example, silicate glass.

[0034] The second protective film 82 is a resin protective film, and for example, it contains a resin such as epoxy resin. The second protective film 82 covers the entire first protective film 81 and a portion of the pair of first electrodes 3. That is, in a plan view from the first direction D1, the second protective film 82 covers the boundary between the first protective film 81 and the pair of first electrodes 3, and continuously covers at least a portion of the pair of first electrodes 3 from the first protective film 81.

[0035] The second protective film 82 is formed, for example, by applying a resin such as epoxy resin by screen printing, and then curing it by heat curing or ultraviolet irradiation. Of the pair of first electrodes 3, the portion located between the first protective film 81 in the second direction D2 (the portion covering the pair of first electrodes 3) and the plating layer 7 is directly covered by the second protective film 82.

[0036] (2) Method for manufacturing chip resistors Next, a method for manufacturing the chip resistor 1 according to the first embodiment will be described. The method for manufacturing the chip resistor 1 involves performing the following steps in this order: substrate preparation step, main surface electrode formation step, resistor formation step, protective film formation step, end surface electrode formation step, and plating layer formation step.

[0037] The substrate preparation process is the process of preparing the insulating substrate 2. More specifically, in the substrate preparation process, for example, the insulating substrate 2 is positioned such that the first main surface 21 is on the upper side and the second main surface 22 is on the lower side.

[0038] The main surface electrode formation process involves forming a pair of first electrodes 3 on the first main surface 21 of the insulating substrate 2 and forming a pair of second electrodes 5 on the second main surface 22 of the insulating substrate 2. More specifically, in the main surface electrode formation process, for example, a pair of first electrodes 3 are formed on both sides of the first main surface 21 of the insulating substrate 2 in the second direction D2 by screen printing using a paste material. Also, for example, a pair of second electrodes 5 are formed on both sides of the second main surface 22 of the insulating substrate 2 in the second direction D2 by screen printing using a paste material.

[0039] The paste material described above can be an epoxy resin containing a conductive material (such as silver). By applying the paste material to both ends of the first main surface 21 and the second main surface 22 of the insulating substrate 2 in the second direction D2 using screen printing, and then curing the epoxy resin by irradiating it with ultraviolet light, a pair of first electrodes 3 and a pair of second electrodes 5 can be formed.

[0040] The resistor formation process involves forming a resistor 4 on an insulating substrate 2. More specifically, in the resistor formation process, a thick film material (paste) containing, for example, copper-nickel, silver-palladium, or ruthenium oxide is printed onto the main surface 21 of the insulating substrate 2, and then fired. In addition, trimming is performed in the resistor formation process as needed.

[0041] The protective film formation step is a step of forming a protective film 8 (first protective film 81 and second protective film 82) so as to cover at least one of the pair of first electrodes 3 and resistors 4. More specifically, in the protective film formation step, for example, the first protective film 81 is formed on the entire upper surface of the resistor 4 and a portion of the surface of the pair of first electrodes 3 by applying glass. Then, for example, epoxy resin is applied by screen printing, and the epoxy resin is cured by irradiation with ultraviolet light to form the second protective film 82.

[0042] In the end electrode formation process, for example, a pair of end electrodes 6 are formed at both ends of the insulating substrate 2 in the second direction D2 using a thin-film process such as sputtering.

[0043] The plating layer formation process involves forming a pair of plating layers 7 on an insulating substrate 2, which has a pair of first electrodes 3, a resistor 4, a pair of second electrodes 5, a pair of end-face electrodes 6, and a protective film 8, by barrel plating. In barrel plating, the plating layers 7 are formed on the surfaces of the pair of first electrodes 3, the pair of bottom electrodes 5, and the pair of end-face electrodes 6, but not on the surfaces of the insulating substrate 2 and the protective film 8.

[0044] (3) Shape of the second electrode Figures 2 and 3 show the shape of the second electrode 5 in this embodiment. In Figures 2 to 12, the insulating substrate 2, the first electrode 3, the second electrode 5, and the end electrode 6 are shown in order to clarify the shape of the second electrode 5, while the resistor 4, plating layer 7, and protective film 8 are omitted from the illustration.

[0045] The second electrode 5 is formed on the electrode formation region 50 of the second main surface 22. The second main surface 22 is provided with two electrode formation regions 501 and 502. The two electrode formation regions 501 and 502 are provided at both ends of the second direction D2 of the second main surface 22. The pair of second electrodes 5 are formed in one electrode formation region 501 and the other electrode formation region 502, respectively.

[0046] The electrode formation region 50 is formed in a rectangular shape when viewed from the bottom of the insulating substrate 2 (viewed from a direction perpendicular to the second main surface 22). The dimension of the electrode formation region 50 in the third direction D3 is the same as the dimension of the insulating substrate 2 in the third direction D3. The electrode formation region 50 is formed with predetermined dimensions from the edge of the insulating substrate 2 in the second direction D2 toward the center of the insulating substrate 2 in the second direction D2. The dimension of the electrode formation region 50 in the second direction D2 can be formed to the maximum dimension of the second electrode 5 in the second direction D2.

[0047] In this embodiment, the second electrode 5 is formed of a plurality of disc portions 51. In a bottom view of the insulating substrate 2, each of the plurality of disc portions 51 is formed in a circular shape. In a bottom view of the insulating substrate 2, the plurality of disc portions 51 are arranged in a third direction D3. Also, in a bottom view of the insulating substrate 2, the plurality of disc portions 51 are arranged in two rows in a second direction D2. The surface (bottom surface) of the plurality of disc portions 51 is formed as a flat surface.

[0048] In this embodiment, the dimension of the electrode formation region 50 in the second direction D2 is formed to be equal to twice the diameter of the disc portion 51. The second electrode portion 62 of the end face electrode 6 is formed in contact with one row of disc portions 51 that are aligned along the edge of the insulating substrate 2 in the second direction D2, out of the multiple disc portions 51 arranged in two rows. In this case, the dimension of the second electrode portion 62 in the second direction D2 is slightly smaller than the radius of the disc portion 51.

[0049] In this embodiment, the outer surfaces of multiple adjacent disc portions 51 are in contact in the second direction D2 and the third direction D3. Therefore, within the electrode formation region 50, gaps are created between adjacent disc portions 51 where the second electrode 5 is not formed. In this embodiment, the gaps formed between adjacent disc portions 51 are formed as plating reduction portions 500.

[0050] The plating reduction section 500 is a section where the plating layer 7 is less likely to form. In other words, the plating layer 7 is formed by adhering to the second electrode 5, but the second electrode 5 is not present in the plating reduction section 500. Therefore, the plating layer 7 does not adhere to the plating reduction section 500, and the plating layer 7 is less likely to form there than on the second electrode 5.

[0051] In this embodiment, the electrode formation region 50 has a plating reduction portion 500 to which the plating layer 7 is less likely to adhere than to the second electrode 5. Therefore, there is a tendency for areas in the electrode formation region 50 where the plating layer 7 is not formed (the portion of the plating reduction portion 500). Consequently, compared to the case where a solid surface (flat surface) second electrode 5 is formed over the entire electrode formation region 50, the amount (size and area) of the plating layer 7 formed in the electrode formation region 50 can be reduced. Therefore, even if the second electrodes 5 are arranged facing each other during the formation of the plating layer 7, the second electrodes 5 are less likely to be joined together by the plating layer 7, and plating defects (such as defects and peeling) of the plating layer 7 can be reduced.

[0052] Furthermore, in this embodiment, since plating defects in the plating layer 7 are reduced, the yield is improved and productivity is also increased.

[0053] Furthermore, in this embodiment, since the chip resistor 1 has voids in the electrode formation region 50 where the plating layer 7 is not formed, even when it is heated when joining it to the wiring portion 102 of the circuit board 100 with solder 103, the expansion and contraction of the second electrode 5 and the circuit board 100 due to the heating are absorbed by the voids where the plating layer 7 is not formed, thereby mitigating the strain generated in the solder 103.

[0054] Furthermore, during the mounting of the chip resistor 1, the amount of load placed on the solder 103 connecting the chip resistor 1 and the circuit board 100 due to the difference in thermal expansion coefficients between the alumina insulating substrate 2 and the circuit board 100 was confirmed by simulation. As a result, it was found that in this embodiment, the stress on the solder 103 is reduced by approximately 18% compared to conventional chip resistors.

[0055] (Second Embodiment) The chip resistor 1 according to the second embodiment differs from that of the first embodiment in the shape of the second electrode 5.

[0056] Hereinafter, components similar to those in the first embodiment will be denoted by common reference numerals and their descriptions will be omitted as appropriate. The components described in the second embodiment can be applied in appropriate combination with the components described in the first embodiment.

[0057] As shown in Figures 4 and 5, in this embodiment, the second electrode 5 is formed with a base portion 52 and a plurality of protrusions 53. The base portion 52 is rectangular in shape when viewed from below. The base portion 52 extends over the entire electrode formation region 50. Therefore, the dimension of the base portion 52 in the second direction D2 is the same as the dimension of the electrode formation region 50 in the second direction D2, and the dimension of the base portion 52 in the third direction D3 is the same as the dimension of the electrode formation region 50 in the third direction D3. The surface (bottom surface) of the base portion 52 is formed as a flat surface.

[0058] Multiple protrusions 53 are formed on the surface of the base portion 52. In a bottom view of the insulating substrate 2, each of the multiple protrusions 53 is formed in a circular shape. In a bottom view of the insulating substrate 2, the multiple protrusions 53 are arranged in a third direction D3. Also, in a bottom view of the insulating substrate 2, the multiple protrusions 53 are arranged in two rows in a second direction D2.

[0059] The second electrode portion 62 of the end face electrode 6 is formed to contact the end of the base portion 52 in the second direction D2 (the portion along the end of the insulating substrate 2). The second electrode portion 62 is formed along the entire length of the base portion 52 in the third direction D3.

[0060] In this embodiment, the outer surfaces of the multiple adjacent protrusions 53 in the second direction D2 and the third direction D3 are not in contact. Therefore, within the electrode formation region 50, a gap is created between (around) the adjacent protrusions 53 where the second electrode 5 is not formed. In this embodiment, the gap formed between (around) the adjacent protrusions 53 is formed as a plating reduction portion 500.

[0061] Similar to the first embodiment, in this embodiment as well, the plating reduction portion 500 is a portion where the plating layer 7 is less likely to form. That is, the plating layer 7 is formed by adhering to the second electrode 5, but the second electrode 5 is not present in the plating reduction portion 500. Therefore, the plating layer 7 does not adhere to the plating reduction portion 500, and the plating layer 7 is less likely to form there than on the second electrode 5. Thus, it has the same effects as the first embodiment.

[0062] (Third embodiment) The chip resistor 1 according to the third embodiment differs from that of the first and second embodiments in the shape of the second electrode 5.

[0063] Hereinafter, components similar to those in the first and second embodiments will be denoted by common reference numerals and their descriptions will be omitted as appropriate. The components described in the third embodiment can be applied in appropriate combination with the components described in the first and second embodiments.

[0064] As shown in Figures 6 and 7, in this embodiment, the second electrode 5 is formed by a plurality of rectangular plate portions 54. Each of the plurality of rectangular plate portions 54 is formed as a rectangle when viewed from the bottom. The plurality of rectangular plate portions 54 are formed as rectangles in which the dimension in the second direction D2 is longer than the dimension in the third direction D3.

[0065] The dimensions of the multiple rectangular plate portions 54 are the same (constant) in the second direction D2 and the third direction D3. The dimensions of the multiple rectangular plate portions 54 in the second direction D2 are the same as the dimensions of the electrode formation region 50 in the second direction D2. The dimensions of the electrode formation region 50 in the third direction D3 are the same as the dimensions of the insulating substrate 2 in the third direction D3. The surface (bottom surface) of the multiple rectangular plate portions 54 is formed as a flat surface.

[0066] Multiple rectangular plate portions 54 are formed on the surface (bottom surface) of the insulating substrate 2. When viewed from the bottom of the insulating substrate 2, the multiple rectangular plate portions 54 are arranged in a third direction D3 with predetermined intervals between them. Therefore, the multiple rectangular plate portions 54 are arranged in a border-like (stripe-like) pattern within the electrode formation region 50.

[0067] The second electrode portion 62 of the end face electrode 6 is formed to contact the ends of the multiple rectangular plate portions 54 in the second direction D2 (the portions along the ends of the insulating substrate 2). The second electrode portion 62 is formed along the entire length of the insulating substrate 2 in the third direction D3.

[0068] In this embodiment, the outer surfaces of two adjacent rectangular plate portions 54 are not in contact in the third direction D3. Therefore, within the electrode formation region 50, a gap is created between adjacent rectangular plate portions 54 where the second electrode 5 is not formed. In this embodiment, the gap formed between adjacent rectangular plate portions 54 is formed as a plating reduction portion 500.

[0069] Similar to the first and second embodiments, in this embodiment as well, the plating reduction portion 500 is a portion where the plating layer 7 is less likely to form. That is, the plating layer 7 is formed by adhering to the second electrode 5, but the second electrode 5 is not present in the plating reduction portion 500. Therefore, the plating layer 7 does not adhere to the plating reduction portion 500, and the plating layer 7 is less likely to form there than on the second electrode 5. Thus, it has the same effects as the first and second embodiments.

[0070] (Fourth embodiment) The chip resistor 1 according to the fourth embodiment differs from that of the first to third embodiments in the shape of the second electrode 5.

[0071] In the following, components similar to those in the first to third embodiments will be denoted by common reference numerals and their descriptions will be omitted as appropriate. The configuration described in the fourth embodiment can be applied in appropriate combination with the configurations described in the first to third embodiments.

[0072] As shown in Figures 8 and 9, in this embodiment, the two second electrodes 5 are each formed by a frame-shaped body 55. The two frame-shaped bodies 55 are each formed in the shape of a rectangular frame when viewed from below. The frame-shaped body 55 is formed as a rectangle in which the dimension in the third direction D3 is longer than the dimension in the second direction D2.

[0073] The dimensions (outer dimensions) of the frame-like body 55 in the second direction D2 are the same as the dimensions of the electrode formation region 50 in the second direction D2. The dimensions (outer dimensions) of the electrode formation region 50 in the third direction D3 are the same as the dimensions of the insulating substrate 2 in the third direction D3. The surface (bottom surface) of the frame-like body 55 is formed as a flat surface.

[0074] The second electrode portion 62 of the end face electrode 6 is formed to contact the ends of the multiple rectangular plate portions 54 in the second direction D2 (the portions along the ends of the insulating substrate 2). The second electrode portion 62 is formed along the entire length of the insulating substrate 2 in the third direction D3.

[0075] The frame-shaped body 55 is formed on the surface (bottom surface) of the insulating substrate 2. The frame-shaped body 55 is formed in a rectangular frame shape when viewed from the bottom of the insulating substrate 2. Therefore, within the electrode formation region 50, there is a void inside the second electrode 5 where the second electrode 5 is not formed. In this embodiment, a rectangular void extending in the third direction D3 is formed when viewed from the bottom, and this void is formed as the plating reduction portion 500.

[0076] Similar to the first to third embodiments, in this embodiment as well, the plating reduction portion 500 is a portion where the plating layer 7 is less likely to form. That is, the plating layer 7 is formed by adhering to the second electrode 5, but the second electrode 5 is not present in the plating reduction portion 500. Therefore, the plating layer 7 does not adhere to the plating reduction portion 500, and the plating layer 7 is less likely to form there than on the second electrode 5. Thus, it has the same effects as the first to third embodiments.

[0077] (Fifth embodiment) The chip resistor 1 according to the fifth embodiment differs from that of the first to fourth embodiments in the shape of the second electrode 5.

[0078] In the following, components similar to those in the first to fourth embodiments will be denoted by common reference numerals and their descriptions will be omitted as appropriate. The configuration described in the fifth embodiment can be applied in appropriate combination with the configurations described in the first to fourth embodiments.

[0079] As shown in Figures 10, 11, and 12, in this embodiment, the two electrode formation regions 50 are formed in a rectangular shape when viewed from below (from a direction perpendicular to the second main surface 22). The second electrodes 5 formed in each of the two electrode formation regions 50 are formed as triangular bodies 56 that fit within the electrode formation region 50 when viewed from below. In this embodiment, the plating reduction portion 500 is the portion within the electrode formation region 50 where the second electrodes 5 are not formed. Figure 11 shows a rear view along arrow D31 shown in Figure 10. Figure 12 shows a front view along arrow D32 in Figure 10.

[0080] The two triangular bodies 56 are each formed in a triangular shape when viewed from the base. Although the two triangular bodies 56 are identical in shape when viewed from the base, they are non-linearly symmetric and non-point-symmetric. That is, the two triangular bodies 56 do not overlap even when an axis of symmetry parallel to either the second direction D2 or the third direction D3 is assumed. Furthermore, the two triangular bodies 56 do not overlap even when rotated around the center of the second main surface 22 of the insulating substrate 2 when viewed from the base.

[0081] Each of the two triangular bodies 56 has a long side 561, a short side 562, and a hypotenuse 563. The dimension of the long side 561 is the same as the dimension of the insulating substrate 2 in the third direction D3. The long side 561 and the short side 562 intersect at a right angle. That is, the two triangular bodies 56 are right-angled triangles. The dimension of the short side 562 in the second direction is the same as the dimension of the electrode formation region 50 in the second direction D2. The hypotenuses 563 of the two triangular bodies 56 are formed parallel to each other.

[0082] The hypotenuses 563 of the two triangular bodies 56 are each formed on the diagonals of the rectangular electrode formation region 50. Therefore, the two electrode formation regions 50 are each divided in half by the hypotenuses 563, with one half formed by the second electrode 5 and the other half formed as the plating reduction region 500.

[0083] The second electrode portion 62 of the end face electrode 6 is formed along the entire length of the insulating substrate 2 in the third direction D3. On one second electrode 551, the second electrode portion 62 is formed along the long side 561 of the triangular body 56, and the second electrode portion 62 is in contact with the entire length of the second electrode 551 in the third direction D3. On the other second electrode 552, the second electrode portion 62 is formed so as to be in contact with the corner portion formed by the short side 562 and the hypotenuse 563 of the triangular body 56.

[0084] In this embodiment, one second electrode 551 is formed by a triangular body 56 provided within one electrode formation region 501. The other second electrode 552 is formed by a triangular body 56 provided within the other electrode formation region 502. In the two electrode formation regions 501 and 502, there is a void where the two second electrodes 551 and 552 of the triangular body 56 are not formed. In this embodiment, a void approximately the same shape as the triangular body 56 is formed in each of the two electrode formation regions 501 and 502 when viewed from below, and this void is formed as a plating reduction portion 500.

[0085] Similar to the first to fourth embodiments, in this embodiment as well, the plating reduction portion 500 is a portion where the plating layer 7 is less likely to form. That is, the plating layer 7 is formed by adhering to the second electrode 5, but the second electrode 5 is not present in the plating reduction portion 500. Therefore, the plating layer 7 is not adhered to the plating reduction portion 500, and the plating layer 7 is less likely to form there than on the second electrode 5. Thus, it has the same effects as the first to fourth embodiments. In particular, in this embodiment, since the two second electrodes 551 and 552 have non-linearly symmetric and non-point-symmetric shapes, the second electrode 551 and the second electrode are even less likely to come into contact over their entire surface, and the second electrodes 5 are less likely to be joined together by the plating layer 7.

[0086] (Aspect) As is clear from the embodiments described above, this disclosure includes the following embodiments. Hereafter, reference numerals are enclosed in parentheses solely to indicate their correspondence with the embodiments.

[0087] A chip resistor (1) according to a first aspect of the present disclosure comprises an insulating substrate (2), a first electrode (3) disposed on a first main surface (21) located on one side of the insulating substrate (2) in the thickness direction, a resistor (4) formed on the first main surface (21) and electrically connected to the first electrode (3), a second electrode (5) disposed on a second main surface (22) located on the other side of the insulating substrate (2) in the thickness direction, an end electrode (6) formed on an end surface (23) of the insulating substrate (2) along the thickness direction and electrically connecting the first electrode (3) and the second electrode (5), and a plating layer (7) formed over the surfaces of the first electrode (3), the second electrode (5), and the end electrode (6), wherein the second electrode (5) is formed in an electrode formation region (50) on the second main surface (22), and the electrode formation region (50) is provided with a plating reduction portion (500) to which the plating layer (7) is less likely to adhere than to the second electrode (5).

[0088] According to this embodiment, compared to the case in which the second electrode (5) is formed over the entire electrode formation region (50), the plating layer (7) is less likely to form in the plating reduction region (500), the second electrodes (5) are less likely to be joined together by the plating layer (7), and it is easier to obtain a chip resistor (1) with fewer plating defects.

[0089] A second aspect of the present disclosure is a chip resistor (1) according to the first aspect, wherein the second electrode (5) is formed by a plurality of disc portions (51), and the plating reduction portion (500) is formed by a gap formed between two adjacent disc portions (51) among the plurality of disc portions (51).

[0090] According to this embodiment, even if the circumferential surfaces of multiple disc portions (51) come into contact, a plating reduction portion (500) can be formed, making it easier to form the plating reduction portion (500).

[0091] A third aspect of the present disclosure is a chip resistor (1) according to the first aspect, wherein the second electrode (5) is formed by a base portion (52) and a plurality of protrusions (53) formed on the surface of the base portion (52), and the plating reduction portion (500) is formed by a gap formed between two adjacent protrusions (53) among the plurality of protrusions (53).

[0092] According to this embodiment, even if plating reduction portions (500) are formed between a plurality of protrusions (53), the plating layer (7) can be attached to the base portion (52).

[0093] A fourth aspect of the present disclosure is a chip resistor (1) according to the first aspect, wherein the second electrode (5) is formed by a plurality of rectangular plate portions (54), and the plating reduction portion (500) is formed by a gap formed between two adjacent rectangular plate portions (54) among the plurality of rectangular plate portions (54).

[0094] According to this embodiment, a plating reduction section (500) can be formed by arranging multiple rectangular plate sections (54), making it easier to form the plating reduction section (500).

[0095] A fifth aspect of the present disclosure is a chip resistor (1) according to the first aspect, wherein the second electrode (5) is formed by a frame-shaped body (55), and the plating reduction portion (500) is formed by an internal void of the frame-shaped body (55).

[0096] According to this embodiment, a plating reduction portion (500) can be formed on the inside of the second electrode (5), and the plating reduction portion (500) is easy to form.

[0097] A sixth aspect of the present disclosure is a chip resistor (1) according to the first aspect, wherein the electrode formation region (50) is formed in a rectangular shape when viewed from an orthogonal direction perpendicular to the second main surface (22), the second electrode (5) is formed as a triangular body (56) that fits within the electrode formation region (50) when viewed from the orthogonal direction, and the plating reduction portion (500) is the portion within the electrode formation region (50) where the second electrode (5) is not formed.

[0098] According to this embodiment, the second electrodes (5) are less likely to come into contact with each other over their entire surface, and the second electrodes (5) are less likely to be joined together by the plating layer (7).

[0099] A seventh aspect of the present disclosure is a chip resistor (1) according to the sixth aspect, wherein the second main surface (22) has two electrode forming regions (501, 502), and a second electrode (551, 552) is formed in each of the two electrode forming regions (501, 502), and the second electrode (551) formed in one electrode forming region (501) and the second electrode (552) formed in the other electrode forming region (502) are non-linearly symmetric and non-point-symmetric when viewed from the orthogonal direction.

[0100] According to this embodiment, the second electrodes (5) are less likely to come into contact with each other over their entire surface, and the second electrodes (5) are less likely to be joined together by the plating layer (7). [Explanation of Symbols]

[0101] 1. Chip resistor 2. Insulating substrate 21 First principal surface 22 Second principal surface 23 End face 3 First electrode 4 Resistors 5, 551, 552 Second electrode 6 End electrode 7 Plating layer 50, 501, 502 Electrode formation area 51 Disc section 52 Base section 53 Protrusion 54 Rectangular plate section 55 Frame-shaped body 500 Plating reduction section

Claims

1. Insulating substrate and A first electrode is disposed on the first main surface located on one side in the thickness direction of the insulating substrate, A resistor formed on the first main surface and electrically connected to the first electrode, A second electrode is disposed on the second main surface located on the other side of the insulating substrate in the thickness direction, An end face electrode is formed on the end face of the insulating substrate along the thickness direction and electrically connects the first electrode and the second electrode, The system comprises a plating layer formed over the surfaces of the first electrode, the second electrode, and the end electrode, The second electrode is formed in the electrode formation region on the second main surface, The electrode formation region is provided with a plating reduction portion in which the plating layer is less likely to adhere than that of the second electrode. Chip resistor.

2. The second electrode is formed by a plurality of disc portions, The plating reduction portion is formed by a gap formed between two adjacent disc portions among the plurality of disc portions. A chip resistor according to claim 1.

3. The second electrode is, The base part, Formed by a plurality of protrusions formed on the surface of the base portion, The plating reduction portion is formed by a gap formed between two adjacent protrusions among the plurality of protrusions. A chip resistor according to claim 1.

4. The second electrode is formed by a plurality of rectangular plate portions, The plating reduction portion is formed by a gap formed between two adjacent rectangular plate portions among the plurality of rectangular plate portions. A chip resistor according to claim 1.

5. The second electrode is formed by a frame-shaped body, The plating reduction portion is formed by the void inside the frame-shaped body. A chip resistor according to claim 1.

6. The electrode formation region is formed in a rectangular shape when viewed from a direction perpendicular to the second main surface, The second electrode is formed in a triangular shape that fits within the electrode formation region when viewed from the orthogonal direction. The aforementioned plating reduction portion is the portion within the electrode formation region where the second electrode is not formed. A chip resistor according to claim 1.

7. The second main surface has two electrode-forming regions, The second electrode is formed in each of the two electrode formation regions. The second electrode formed in one of the two electrode formation regions and the second electrode formed in the other of the two electrode formation regions are, when viewed from the orthogonal direction, non-linearly symmetric and non-point-symmetric. The chip resistor according to claim 6.

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