Stacked semiconductor package

Abstract

To reduce the size of stacked semiconductor packages. [Solution] The present invention includes a substrate 120 on which a first substrate pad array 121 and a second substrate pad array 122 are formed, and a plurality of semiconductor dies 130, 140, 150, and 160 on which a first die pad array 131 and a second die pad array 132 are formed, respectively, and which are stacked on the substrate 120. Of the plurality of semiconductor dies, the lowest semiconductor die 130 is stacked such that the first die pad array 131 and the second die pad array 132 face the first substrate pad array 121 and the second substrate pad array 122, and the remaining semiconductor dies 140, 150, and 160, excluding the lowest semiconductor die 130, are stacked in the opposite direction to the lowest semiconductor die 130.

Description

Technical Field

[0001] The present invention relates to semiconductor circuits, and in particular to a stacked type semiconductor package using a wire bonding structure.

Background Art

[0002] Semiconductor package assembly technology is intended to protect a semiconductor die on which an integrated circuit is formed from the external environment, enable easy mounting of the semiconductor die on a substrate, and ensure the operational reliability of the semiconductor die. In package assembly technology, as one method for connecting a semiconductor die and a substrate, a wire bonding method is used, in which the semiconductor die and the substrate are connected via a conductive wire.

[0003] The wire bonding method is a general-purpose connection method and is suitable for use in laminated structures. However, when the number of stacked semiconductor dies increases, the length of the wires increases and the signal transmission path becomes longer, which causes problems such as degraded electrical characteristics and an increase in package size.

[0004] Accordingly, along with the application of the wire bonding method, there is a demand for technological development that can reduce package size.

Summary of the Invention

Problem to be Solved by the Invention

[0005] Embodiments of the present invention aim to provide a semiconductor package capable of reducing package size.

Means for Solving the Problem

[0006] Embodiments of the present invention include a substrate on which a first substrate pad array and a second substrate pad array are formed, and a plurality of semiconductor dies on which a first die pad array and a second die pad array are formed, respectively, and which are stacked on the substrate, wherein the lowest semiconductor die is stacked such that the first die pad array and the second die pad array face the first substrate pad array and the second substrate pad array, and the remaining semiconductor dies, excluding the lowest semiconductor die, are stacked in the opposite direction to the lowest semiconductor die.

[0007] Embodiments of the present invention include a substrate including a first substrate pad array and a second substrate pad array; a first semiconductor die having a first die pad array and a second die pad array formed on its front surface, the first die pad array being electrically connected to the first substrate pad array via a first bump array, and the second die pad array being electrically connected to the second substrate pad array via a second bump array; a second semiconductor die having a first die pad array and a second die pad array formed on its front surface, and stacked on the first semiconductor die such that its back surface faces the back surface of the first semiconductor die; a third semiconductor die having a first die pad array and a second die pad array formed on its front surface, and stacked on the second semiconductor die such that its back surface faces the front surface of the second semiconductor die; and a plurality of conductive wires electrically connecting the second die pad array of the second semiconductor die, the second die pad array of the third semiconductor die, and the second substrate pad array.

[0008] Embodiments of the present invention may include a substrate on which a substrate pad array is formed, a plurality of semiconductor dies stacked on the substrate on which a first die pad array, a second die pad array, and at least one third die pad array are formed, and a plurality of conductive wires electrically connecting the substrate pad array, at least one third die pad array of the uppermost semiconductor die among the plurality of semiconductor dies, and the first die pad array of the uppermost semiconductor die. [Effects of the Invention]

[0009] This technology can reduce the size of semiconductor packages and improve signal transfer quality by reducing the loading required to transmit signals from outside the package to the semiconductor die. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic cross-sectional view showing a semiconductor package according to one embodiment of the present invention. [Figure 2] Figure 1 is a perspective view showing a portion of a semiconductor package. [Figure 3] This is a schematic cross-sectional view showing a semiconductor package according to one embodiment of the present invention. [Figure 4] Figure 3 is a perspective view showing a portion of a semiconductor package. [Figure 5] Figure 3 is a perspective view showing some of the pads in a semiconductor package. [Figure 6] This figure shows the pad connection state as shown in Figure 3. [Figure 7] This figure shows an internal circuit according to one embodiment of the present invention. [Figure 8] This diagram shows the configuration of the first switching circuit in Figure 7. [Figure 9] Figure 7 shows the operation of the switching circuit. [Figure 10] This is a schematic cross-sectional view showing a semiconductor package according to another embodiment of the present invention. [Figure 11] This is a schematic cross-sectional view showing a semiconductor package according to another embodiment of the present invention. [Modes for carrying out the invention]

[0011] Hereinafter, embodiments of the present invention will be described in more detail based on the attached drawings.

[0012] Figure 1 is a schematic cross-sectional view showing a semiconductor package 10 according to one embodiment of the present invention.

[0013] Referring to Figure 1, the semiconductor package 10 can include a substrate 20, a plurality of semiconductor dies 30, 40, 50, 60, and a plurality of conductive wire arrays 71-74. Figure 1 shows an example in which four semiconductor dies are stacked on the substrate 20, but the number of stacked semiconductor dies can vary depending on the total storage capacity of the package and the storage capacity of each semiconductor die.

[0014] The substrate 20 may include a first substrate pad array 21 and a second substrate pad array 22. The first substrate pad array 21 can be electrically connected to the outside of the package via a bump array 80.

[0015] Multiple semiconductor dies 30, 40, 50, 60 can be stacked on a substrate 20. Multiple semiconductor dies 30, 40, 50, 60 can be configured similarly to one another. Multiple semiconductor dies 30, 40, 50, 60 can each include a first die pad array 31 / 41 / 51 / 61 and a second die pad array 32 / 42 / 52 / 62 formed on a first surface (e.g., the front surface). The first semiconductor die 30 includes the first die pad array 31 and the second die pad array 32. The second semiconductor die 40 includes the first die pad array 41 and the second die pad array 42. The third semiconductor die 50 includes the first die pad array 51 and the second die pad array 52. ​​The fourth semiconductor die 60 includes the first die pad array 61 and the second die pad array 62.

[0016] Multiple semiconductor dies 30, 40, 50, and 60 can be stacked with steps between them so that even after stacking, the first die pad array and the second die pad array of each die pad array remain exposed to the outside.

[0017] The first conductive wire array 71 can electrically connect the second substrate pad array 22 to the first die pad array 31 of the first semiconductor die 30. The second conductive wire array 72 can electrically connect the second die pad array 32 of the first semiconductor die 30 to the second die pad array 42 of the second semiconductor die 40. The third conductive wire array 73 can electrically connect the second die pad array 42 of the second semiconductor die 40 to the second die pad array 52 of the third semiconductor die 50. The fourth conductive wire array 74 can electrically connect the second die pad array 52 of the third semiconductor die 50 to the second die pad array 62 of the fourth semiconductor die 60.

[0018] FIG. 2 is a perspective view showing a part of the semiconductor package 10 according to FIG. 1. FIG. 2 shows a part of the pad groups respectively included in the second substrate pad array 22, the first die pad arrays 31 / 41, and the second die pad arrays 32 / 42 of FIG. 1.

[0019] Referring to FIG. 2, the pad group of the second substrate pad array 22 can be connected to the pad group of the first die pad array 31 of the first semiconductor die 30 in a 1:1 ratio via the conductive wire group of the first conductive wire array 71. The pad group of the second die pad array 32 of the first semiconductor die 30 can be connected to the pad group of the second die pad array 42 of the second semiconductor die 40 in a 1:1 ratio via the conductive wire group of the second conductive wire array 72.

[0020] Referring to FIG. 1 and FIG. 2, among the plurality of semiconductor dies 30, 40, 50, 60, the lowermost semiconductor die stacked on the substrate 20, that is, the first semiconductor die 30, can operate as a master, and the remaining semiconductor dies 40, 50, 60 can operate as slaves. The first semiconductor die 30 operating as a master can receive a signal group from outside the semiconductor package 10 from the substrate 20, and transmit the signal group to the second to fourth semiconductor dies 40, 50, 60 operating as slaves.

[0021] More specifically, a group of signals transferred from an external device to the semiconductor package 10 can be transmitted to the first die pad array 31 of the first semiconductor die 30 via the bump array 80, the first substrate pad array 21, the second substrate pad array 22, and the first conductive wire array 71. The group of signals transmitted to the first semiconductor die 30 can be transmitted to the second to fourth semiconductor dies 40, 50, and 60 via the second die pad array 32, the second to fourth conductive wire arrays 72 to 74, and the second die pad arrays 42, 52, and 62.

[0022] The signal group within the semiconductor package 10 can be transmitted to an external device via the bump array 80 through a path opposite to the method described above.

[0023] Figure 3 is a schematic cross-sectional view showing a semiconductor package 100 according to one embodiment of the present invention.

[0024] Referring to Figure 3, the semiconductor package 100 may include a substrate 120, a plurality of semiconductor dies 130, 140, 150, 160, and a plurality of conductive wire arrays 171-173.

[0025] A first substrate pad array 121 and a second substrate pad array 122 can be formed on the substrate 120 on a first surface (e.g., the front surface). The first substrate pad array 121 can be formed at a first distance from the center of the substrate 120 in the first outer edge direction (right outer edge direction based on Figure 3). The second substrate pad array 122 can be formed at a second distance from the first substrate pad array 121 in the first outer edge direction. The first substrate pad array 121 can be electrically connected to an external device of the semiconductor package 100 via an external bump array 183 to transmit / receive signals.

[0026] Multiple semiconductor dies 130, 140, 150, and 160 can be stacked on a substrate 120, with a first die pad array 131 / 141 / 151 / 161 and a second die pad array 132 / 142 / 152 / 162 formed on their respective first surfaces (e.g., front surfaces). The multiple semiconductor dies 130, 140, 150, and 160 can be configured similarly to one another.

[0027] Of the multiple semiconductor dies 130, 140, 150, and 160, the lowest semiconductor die 130 can be stacked such that the first die pad array 131 and the second die pad array 132 face the first substrate pad array 121 and the second substrate pad array 122. The remaining semiconductor dies 140, 150, and 160, excluding the lowest semiconductor die 130, can be stacked in the opposite direction to the lowest semiconductor die 130. The lowest semiconductor die 130 can be stacked so that its front surface faces the front surface of the substrate 120, and the remaining semiconductor dies 140, 150, and 160, excluding the lowest semiconductor die 130, can be stacked so that their respective back surfaces face the front surface of the substrate 120.

[0028] The multiple semiconductor dies 130, 140, 150, and 160 include a first semiconductor die 130, a second semiconductor die 140, a third semiconductor die 150, and a fourth semiconductor die 160, which are arranged in the order in which they are stacked on the substrate 120.

[0029] The first die pad array 131 of the first semiconductor die 130 can be electrically connected to the first substrate pad array 121 via the first bump array 181. The second die pad array 132 of the first semiconductor die 130 can be electrically connected to the second substrate pad array 122 via the second bump array 182.

[0030] The second semiconductor die 140 has the first die pad array 141 and the second die pad array 142 formed on its front surface, and can be stacked on the first semiconductor die 130 such that its back surface faces the back surface of the first semiconductor die 130.

[0031] The third semiconductor die 150 has a first die pad array 151 and a second die pad array 152 formed on its front surface, and can be stacked on the second semiconductor die 140 such that its back surface faces the front surface of the second semiconductor die 140.

[0032] The fourth semiconductor die 160 has a first die pad array 161 and a second die pad array 162 formed on its front surface, and can be stacked on the third semiconductor die 150 such that its back surface faces the front surface of the third semiconductor die 150.

[0033] The multiple conductive wire arrays 171 to 173 may include a first conductive wire array 171, a second conductive wire array 172, and a third conductive wire array 173. The first conductive wire array 171 can electrically connect the second substrate pad array 122 to the second die pad array 142 of the second semiconductor die 140. The second conductive wire array 172 can electrically connect the second die pad array 142 of the second semiconductor die 140 to the second die pad array 152 of the third semiconductor die 150. The third conductive wire array 173 can electrically connect the second die pad array 152 of the third semiconductor die 150 to the second die pad array 162 of the fourth semiconductor die 160.

[0034] Figure 4 is a perspective view showing a portion of the semiconductor package 100 according to Figure 3. Figure 4 shows a portion of the pad groups included in the second substrate pad array 122 and the second die pad arrays 142 / 152, respectively, of Figure 3.

[0035] Referring to Figure 4, the first semiconductor die 130 is not visible in Figure 4 because the first die pad array 131 and the second die pad array 132 are stacked so that they face the first substrate pad array 121 and the second substrate pad array 122.

[0036] The pads of the second substrate pad array 122 can be connected in a 1:1 ratio to the pads of the second die pad array 142 of the second semiconductor die 140 via the conductive wires of the first conductive wire array 171. The pads of the second die pad array 142 of the second semiconductor die 140 can be connected in a 1:1 ratio to the pads of the second die pad array 152 of the third semiconductor die 150 via the conductive wires of the second conductive wire array 172.

[0037] The semiconductor package 100 in Figure 4 electrically connects the first semiconductor die 130 to the substrate 120 without conductive wires, and electrically connects the outermost pad arrays of the second semiconductor die 140, third semiconductor die 150, and fourth semiconductor die 160, i.e., the second die pad array 142 / 152 / 162, to the substrate 120 via the pads of the second substrate pad array 122 and a plurality of conductive wire arrays 171-173. Since multiple semiconductor dies 130, 140, 150, and 160 can be stacked on the substrate 120 without exposing the first die pad array 131 / 141 / 151 / 161 to the outside, the package size can be reduced.

[0038] Figure 5 is a perspective view showing some of the pads of the semiconductor package 100 according to Figure 3, and Figure 6 is a diagram showing the pad connection state according to Figure 3. Figure 6 shows some of the pad groups included in the first substrate pad array 121, the second substrate pad array 122, the first die pad array 131, and the second die pad arrays 132 / 142, respectively.

[0039] Referring to Figure 5, among the multiple semiconductor dies, the first semiconductor die 130, which is located at the bottom, has a front surface where the first die pad array 131 and the second die pad array 132 are formed, facing the substrate 120. However, the second to fourth semiconductor dies 140, 150, and 160, excluding the first semiconductor die 130, have a back surface where the first die pad array 141 / 151 / 161 and the second die pad array 142 / 152 / 162 are not formed, facing the substrate 120.

[0040] Since the multiple semiconductor dies 130, 140, 150, and 160 are configured similarly to each other, the signals transferred are determined by the order of the pads. However, because the first semiconductor die 130 is stacked in opposite directions to the second to fourth semiconductor dies 140, 150, and 160, the order of the corresponding pads will be different for each other.

[0041] The pads of the first die pad array 131 and the second die pad array 132 of the first semiconductor die 130 can transfer signals in the same order, and the pads of the first die pad array 141 and the second die pad array 142 of the second semiconductor die 140 can also transfer signals in the same order. However, since pads "1", "2", "3", and "4" of the second die pad array 132 of the first semiconductor die 130 are connected to pads "4", "3", "2", and "1" of the second die pad array 142 of the second semiconductor die 140, respectively, they can transfer signals in an order different from the intended one.

[0042] Referring to Figure 6, the group of signals transferred via pads 121a, 121b, 121c, and 121d numbered "1" to "4" of the first substrate pad array 121 can be transferred via the first bump array 181 to pads 131d, 131c, 131b, and 131a numbered "4" to "1" of the first die pad array 131 of the first semiconductor die 130, which acts as the master. The signals can be transferred to pads 131d, 131c, 131b, and 131a numbered "4" to "1" of the first die pad array 131 in an order different from the original intention.

[0043] The group of signals transferred via pads 131d, 131c, 131b, and 131a numbered "4" to "1" of the first die pad array 131 of the first semiconductor die 130 can be transferred to pads 132d, 132c, 132b, and 132a numbered "4" to "1" of the second die pad array 132 via an internal signal processing circuit (not shown) and through a predetermined signal processing process.

[0044] The group of signals transferred via pads 132d, 132c, 132b, and 132a numbered "4" to "1" of the second die pad array 132 can be transferred via the second bump array 182 to pads 122a, 122b, 122c, and 122d numbered "1" to "4" of the second substrate pad array 122 of the substrate 120.

[0045] The group of signals transferred to pads 122a, 122b, 122c, and 122d numbered "1" through "4" of the second substrate pad array 122 can be transferred via the first conductive wire array 171 to pads 142a, 142b, 142c, and 142d numbered "1" through "4" of the second die pad array 142 of the second semiconductor die 140, which operates as a slave.

[0046] As explained with reference to Figures 5 and 6, signals transferred from outside the semiconductor package 100 can be transmitted to the lowest semiconductor die acting as the master, with their order changed. Therefore, each of the multiple semiconductor dies contained in the semiconductor package 100 can include a switching circuit configured to change the order of the signal groups transferred between the pad groups of the first die pad array and the pad groups of the second die pad array, based on the master sorting signal.

[0047] Figure 7 shows an internal circuit 190 according to one embodiment of the present invention.

[0048] Referring to Figure 7, the internal circuit 190 can be connected between the first die pad array and the second die pad array. The internal circuit 190 is a circuit for performing signal processing and control related to the input and output of signals on the semiconductor die. The internal circuit 190 may include a control circuit 191 and a switching circuit 192.

[0049] The control circuit 191 can set the master sorting signal (MST) to the corresponding logic level based on the stacking position information. The control circuit 191 can generate multiple control signals (CTRL1, CTRL2) based on the master sorting signal (MST) and the read / write operation state. The control circuit 191 can receive signals transferred via the first die pad array, perform predetermined signal control operations, and provide them to the switching circuit 192. The control circuit 191 can receive signals transferred via the second die pad array and the switching circuit 192, and perform predetermined signal control operations.

[0050] Among the multiple semiconductor dies 130, 140, 150, and 160, the semiconductor die operating as a master and the semiconductor die operating as a slave have their Master Segmentation Signal (MST) set to different logic levels. The logic level of the Master Segmentation Signal (MST) is determined based on stacking position information that is internally generated by the stacking of semiconductor dies. Figure 3 shows an embodiment of the present invention in which the lowest semiconductor die operates as a master. The lowest semiconductor die operating as a master is stacked on the substrate 120, so its Master Segmentation Signal (MST) is set to a first logic level, for example, logic high level, and the group of semiconductor dies stacked on the lowest semiconductor die and operating as slaves have their Master Segmentation Signal (MST) set to a second logic level, for example, logic low level.

[0051] The control circuit 191 can generate multiple control signals (CTRL1, CTRL2) as "0" and "1" (logic high level) respectively during write operation (WT), even though the master identification signal (MST) is "0" (logic low level). The control circuit 191 can generate multiple control signals (CTRL1, CTRL2) as "1" and "0" respectively during read operation (RD), even though the master identification signal (MST) is "0". The control circuit 191 can generate multiple control signals (CTRL1, CTRL2) as "1" and "0" respectively during write operation (WT), even though the master identification signal (MST) is "1". The control circuit 191 can generate multiple control signals (CTRL1, CTRL2) as "0" and "1" respectively during read operation (RD), even though the master identification signal (MST) is "1".

[0052] The switching circuit 192 may include a first switching circuit 192A and a second switching circuit 192B.

[0053] The first switching circuit 192A can transfer an output signal group generated by multiplexing the input signal group, i.e., the signal group transferred from the control circuit 191 via the first die pad array, based on the first control signal (CTRL1) and the master / distinguishing signal (MST), to the second die pad array. The master / distinguishing signal (MST) is set to a logic high level for semiconductor dies operating as masters and to a logic low level for semiconductor dies operating as slaves. When the master / distinguishing signal (MST) is at a logic high level, the first switching circuit 192A can generate the output signal group by changing the order of the input signal group. When the master / distinguishing signal (MST) is at a logic low level, the first switching circuit 192A can generate the output signal group without changing the order of the input signal group. The first switching circuit 192A can operate in response to the activation of the first control signal (CTRL1) and can cease operation in response to the deactivation of the first control signal (CTRL1).

[0054] The second switching circuit 192B can transfer to the control circuit 191 an output signal group generated by multiplexing the input signal group, i.e., the signal group transferred via the second die pad array, based on the master partition signal (MST). When the master partition signal (MST) is at a high logic level, the second switching circuit 192B can generate the output signal group by changing the order of the signal group transferred via the pad group of the second die pad array. When the master partition signal (MST) is at a low logic level, the second switching circuit 192B can generate the output signal group without changing the order of the signal group transferred via the pad group of the second die pad array. The second switching circuit 192B can operate in response to the activation of the second control signal (CTRL2) and can cease operation in response to the deactivation of the second control signal (CTRL2).

[0055] Figure 8 shows the configuration of the first switching circuit 192A in Figure 7.

[0056] Referring to Figure 8, the first switching circuit 192A can include multiple multiplexers 193 to 196. The multiple multiplexers 193 to 196 can operate in response to the activation of the first control signal (CTRL1) and can cease operation in response to the deactivation of the first control signal (CTRL1). The first multiplexer 193 can select the first input signal (IN1) and generate the first output signal (OUT1) when the master partition signal (MST) is at a low logic level, and can select the fourth input signal (IN4) and generate the first output signal (OUT1) when the master partition signal (MST) is at a high logic level. The second multiplexer 194 can select the second input signal (IN2) and generate the second output signal (OUT2) when the master partition signal (MST) is at a low logic level, and can select the third input signal (IN3) and generate the second output signal (OUT2) when the master partition signal (MST) is at a high logic level. The third multiplexer 195 can generate a third output signal (OUT3) by selecting a third input signal (IN3) when the master partition signal (MST) is at a low logic level, and can generate a third output signal (OUT3) by selecting a second input signal (IN2) when the master partition signal (MST) is at a high logic level. The fourth multiplexer 196 can generate a fourth output signal (OUT4) by selecting a fourth input signal (IN4) when the master partition signal (MST) is at a low logic level, and can generate a fourth output signal (OUT4) by selecting a first input signal (IN1) when the master partition signal (MST) is at a high logic level. The first to fourth input signals (IN1 to IN4) are provided by the control circuit 191.

[0057] The second switching circuit 192B is configured similarly to the first switching circuit 192A, except that the first to fourth input signals (IN1 to IN4) are signals transferred via each of the pad groups of the second die pad array, and it operates / stops operation in response to the activation / deactivation of the second control signal (CTRL2).

[0058] Figure 9 shows the operation of the switching circuit 192 in Figure 7.

[0059] The operation of the switching circuit 192 will be explained based on Figures 7 to 9.

[0060] First, we will explain the operation of the switching circuit 192 based on the group of semiconductor dies that operate as slaves.

[0061] A group of semiconductor dies operating as slaves has its Master Segmentation Signal (MST) set to "0" (logic low level).

[0062] When a signal is input from outside the semiconductor package 100, for example during a write operation (WT), the control circuit 191 outputs a first control signal (CTRL1) as "0" (logic low level) and a second control signal (CTRL2) as "1" (logic high level).

[0063] Since the second control signal (CTRL2) is "1", the second switching circuit 192B is activated, and since the first control signal (CTRL1) is "0", the first switching circuit 192A ceases operation.

[0064] The second switching circuit 192B receives the first to fourth input signals (IN1 to IN4) via the second die pad array. The second switching circuit 192B is included in a semiconductor die operating as a slave, and since its master selection signal (MST) is "0", it generates the first to fourth output signals (OUT1 to OUT4) without changing the order of the first to fourth input signals (IN1 to IN4). The first to fourth output signals (OUT1 to OUT4) are then transferred to the control circuit 191.

[0065] On the other hand, during operations in which a signal is output from inside the semiconductor package 100, such as a read operation (RD), the control circuit 191 outputs a first control signal (CTRL1) as "1" and a second control signal (CTRL2) as "0".

[0066] Since the first control signal (CTRL1) is "1", the first switching circuit 192A is activated, and since the second control signal (CTRL2) is "0", the second switching circuit 192B is deactivated.

[0067] The first switching circuit 192A receives the first to fourth input signals (IN1 to IN4) from the control circuit 191. Since the master segmentation signal (MST) of the first switching circuit 192A is "0", it generates the first to fourth output signals (OUT1 to OUT4) without changing the order of the first to fourth input signals (IN1 to IN4). The first to fourth output signals (OUT1 to OUT4) are then transferred to the second die pad array.

[0068] Next, the operation of the switching circuit 192 will be described based on the semiconductor die acting as the master.

[0069] A semiconductor die acting as a master has its Master Segmentation Signal (MST) set to "1".

[0070] During light operation (WT), the control circuit 191 outputs a first control signal (CTRL1) as "1" and a second control signal (CTRL2) as "0".

[0071] Since the first control signal (CTRL1) is "1", the first switching circuit 192A is activated, and since the second control signal (CTRL2) is "0", the second switching circuit 192B is deactivated.

[0072] The first switching circuit 192A receives the first to fourth input signals (IN1 to IN4) from the control circuit 191 via the first die pad array. Since the master segmentation signal (MST) of the first switching circuit 192A is "1", it changes the order of the first to fourth input signals (IN1 to IN4) to IN4, IN3, IN2, IN1, and generates the first to fourth output signals (OUT1 to OUT4). The first to fourth output signals (OUT1 to OUT4) are then transferred to the second die pad array.

[0073] On the other hand, during a read operation (RD), the control circuit 191 outputs a first control signal (CTRL1) as "0" and a second control signal (CTRL2) as "1".

[0074] Since the second control signal (CTRL2) is "1", the second switching circuit 192B is activated, and since the first control signal (CTRL1) is "0", the first switching circuit 192A ceases operation.

[0075] The second switching circuit 192B receives the first to fourth input signals (IN1 to IN4) via the second die pad array. Since the master segmentation signal (MST) is "0", the second switching circuit 192B changes the order of the first to fourth input signals (IN1 to IN4) to IN4, IN3, IN2, IN1, and generates the first to fourth output signals (OUT1 to OUT4). The first to fourth output signals (OUT1 to OUT4) are transferred to the first die pad array via the control circuit 191.

[0076] Figures 10 and 11 are schematic cross-sectional views showing semiconductor packages 200A and 200B according to other embodiments of the present invention.

[0077] Referring to Figure 10, the semiconductor package 200A may include a substrate 220, a plurality of semiconductor dies 230, 240, 250, 260, and a plurality of conductive wire arrays 271, 272, 273, 281, 282.

[0078] A substrate pad array 221 can be formed on the substrate 220.

[0079] Multiple semiconductor dies 230, 240, 250, and 260 can be stacked on a substrate 220.

[0080] Multiple semiconductor dies 230, 240, 250, and 260 can each form a first die pad array 231 / 241 / 251 / 261, a second die pad array 232 / 242 / 252 / 262, and at least one third die pad array 233A, 233B / 243A, 243B / 253A, 253B / 263A, and 263B on their respective first surfaces, for example, the front surface.

[0081] One of the multiple semiconductor dies 230, 240, 250, and 260 can operate as a master, while the remaining semiconductor dies can operate as slaves. Other embodiments of the present invention shown in Figures 10 and 11 illustrate an example in which the topmost semiconductor die operates as the master.

[0082] The multiple semiconductor dies 230, 240, 250, and 260 include a first semiconductor die 230, a second semiconductor die 240, a third semiconductor die 250, and a fourth semiconductor die 260, which are ordered in the order in which they are stacked on the substrate 220. The first semiconductor die 230, the second semiconductor die 240, the third semiconductor die 250, and the fourth semiconductor die 260 can be configured similarly to each other.

[0083] A first die pad array 231, a second die pad array 232, and a third die pad array 233A, 233B can be formed on the front surface of the first semiconductor die 230. A first die pad array 241, a second die pad array 242, and a third die pad array 243A, 243B can be formed on the front surface of the second semiconductor die 240. A first die pad array 251, a second die pad array 252, and a third die pad array 253A, 253B can be formed on the front surface of the third semiconductor die 250. A first die pad array 261, a second die pad array 262, and a third die pad array 263A, 263B can be formed on the front surface of the fourth semiconductor die 260.

[0084] The first conductive wire array 271 can electrically connect the second die pad array 232 of the first semiconductor die 230 to the second die pad array 242 of the second semiconductor die 240. The second conductive wire array 272 can electrically connect the second die pad array 242 of the second semiconductor die 240 to the second die pad array 252 of the third semiconductor die 250. The third conductive wire array 273 can electrically connect the second die pad array 252 of the third semiconductor die 250 to the second die pad array 262 of the fourth semiconductor die 260. The fourth conductive wire array 281 can electrically connect the substrate pad array 221 to the topmost semiconductor die that acts as a master, i.e., the outermost third die pad array 263A of the third die pad arrays 263A and 263B of the fourth semiconductor die 260. The fifth conductive wire array 282 can electrically connect the third die pad array 263A of the fourth semiconductor die 260 with the first die pad array 261.

[0085] The semiconductor package 200A shown in Figure 10 above connects the outermost pad arrays of the first semiconductor die 230, second semiconductor die 240, third semiconductor die 250, and fourth semiconductor die 260, i.e., the second die pad array group, and electrically connects the first die pad array 261 of the uppermost fourth semiconductor die 260 to the substrate 220 via the third die pad array 263A. Since multiple semiconductor dies 230, 240, 250, and 260 can be stacked on the substrate 220 without exposing the first die pad array group to the outside, the package size can be reduced.

[0086] Referring to Figure 11, the semiconductor package 200B may include a substrate 220, a plurality of semiconductor dies 230, 240, 250, 260, and a plurality of conductive wire arrays 271, 272, 273, 291, 292, 293.

[0087] The semiconductor package 200A described with reference to Figure 10 is an example in which the substrate pad array 221 and the top semiconductor die, i.e., the first die pad array 261 of the fourth semiconductor die 260, are connected via the fourth conductive wire array 281 and the fifth conductive wire array 282. Although the desired signal transfer quality can also be obtained by directly connecting the third die pad array 263A of the fourth semiconductor die 260 and the first die pad array 261 via the fifth conductive wire array 282, there is a risk of degrading the signal quality due to various environmental factors such as the characteristics of the conductive wires, the characteristics of the semiconductor die, and the characteristics of the package design.

[0088] Therefore, in the case where the desired signal transfer quality cannot be secured by the method shown in Figure 10, the semiconductor package 200B according to another embodiment of the present invention is configured such that the substrate pad array 221 is connected to the first die pad array 261 via a plurality of third die pad arrays 263A, 263B through a fourth conductive wire array 291, a fifth conductive wire array 292, and a sixth conductive wire array 293.

[0089] The semiconductor package 200B shown in Figure 11 allows multiple semiconductor dies 230, 240, 250, and 260 to be stacked on the substrate 220 without exposing the first die pad array to the outside. This reduces the package size while simultaneously preventing a degradation in signal quality.

[0090] Thus, a person of ordinary skill in the art to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, it must be understood that the examples described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims described below rather than by the detailed description, and it must be understood that all modified or altered forms derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the present invention. [Explanation of Symbols]

[0091] 10 Semiconductor Packages 20 circuit boards 21 First substrate pad array 22 Second substrate pad array 30 First semiconductor die 31 First die pad array 32 Second die pad array 40 Second semiconductor die 41 First die pad array 42 Second die pad array 50 Third semiconductor die 51 First die pad array 52 Second die pad array 60. The fourth semiconductor die 61 First die pad array 62 Second die pad array 71-74 Conductive wire array 80 Bump Array 100 semiconductor packages 120 circuit boards 121 First substrate pad array 122 Second substrate pad array 130 First semiconductor die 131 First die pad array 132 Second die pad array 140 Second semiconductor die 141 First die pad array 142 Second die pad array 150 Third semiconductor die 151 First die pad array 152 Second die pad array 160 The fourth semiconductor die 161 First die pad array 162 Second die pad array 171 First conductive wire array 172 Second conductive wire array 173 Third conductive wire array 181 First Bump Array 182. Second Bump Array 183 External Bump Array 190 Internal circuit 191 Control Circuit 192 Switching Circuits 192A First switching circuit 192B Second switching circuit 193 First Multiplexer 194 Second Multiplexer 195 The third multiplexer 196 The fourth multiplexer 200A semiconductor package 200B Semiconductor Package 220 circuit boards 221 PCB pad array 230 First semiconductor die 231 First die pad array 232 Second die pad array 233A Third die pad array 233B Third die pad array 240 Second semiconductor die 241 First die pad array 242 Second die pad array 243A Third die pad array 243B Third die pad array 250 Third semiconductor die 251 First die pad array 252 Second die pad array 253A Third die pad array 253B Third die pad array 260 The fourth semiconductor die 261 First die pad array 262 Second die pad array 263A Third die pad array 263B Third die pad array 271 First conductive wire array 272 Second conductive wire array 273 Third conductive wire array 281 Fourth conductive wire array 282 The fifth conductive wire array 291 Fourth conductive wire array 292 Fifth conductive wire array 293 The sixth conductive wire array CTRL1 First control signal CTRL2 Second control signal IN1~IN4 Input Signals MST Master Segmentation Signal OUT1~OUT4 Output Signals

Claims

1. A substrate on which a first substrate pad array and a second substrate pad array are formed, The invention includes a plurality of semiconductor dies, each having a first die pad array and a second die pad array formed on it, which are stacked on the substrate. A semiconductor package in which, among the plurality of semiconductor dies, the lowest semiconductor die is stacked such that the first die pad array and the second die pad array face the first substrate pad array and the second substrate pad array, and the remaining semiconductor dies, excluding the lowest semiconductor die, are stacked in the opposite direction to the lowest semiconductor die.

2. The semiconductor package according to claim 1, wherein the first substrate pad array is electrically connected to the first die pad array of the lowest semiconductor die via a first bump array.

3. The semiconductor package according to claim 2, wherein the second substrate pad array is electrically connected to the second die pad array of the lowest semiconductor die via a second bump array.

4. The semiconductor package according to claim 1, wherein each of the first die pad arrays is formed at a first distance in the outer direction from the center of the corresponding semiconductor die, and the second die pad array is formed at a second distance from the first die pad array in the outer direction.

5. The semiconductor package according to claim 1, wherein the second die pad array of the remaining semiconductor dies among the plurality of semiconductor dies, excluding the lowest semiconductor die, is electrically connected to the second substrate pad array of the substrate via a group of conductive wires.

6. The semiconductor package according to claim 1, wherein, among the plurality of semiconductor dies, the lowest semiconductor die is configured to operate as a master, and the remaining semiconductor dies, excluding the lowest semiconductor die, are configured to operate as slaves.

7. The semiconductor package according to claim 1, wherein the plurality of semiconductor dies are configured to operate as masters or slaves depending on their position, and the master-distinguishing signals of the semiconductor dies operating as masters and the semiconductor dies operating as slaves are set to different logic levels.

8. The semiconductor package according to claim 1, wherein each of the plurality of semiconductor dies includes a switching circuit configured to change the order of a group of signals transferred between the first die pad array and the second die pad array based on a master sorting signal.

9. The aforementioned switching circuit is A first switching circuit configured to multiplex and output the group of signals transferred via the first die pad array based on the master sorting signal, The semiconductor package according to claim 8, further comprising: a second switching circuit configured to multiplex and output a group of signals transferred via the second die pad array based on the master sorting signal.

10. The first switching circuit is, When the master classification signal is a logic level representing a master, the order of the signal group transferred via the pad group of the first die pad array is changed and output. The semiconductor package according to claim 9, wherein, when the master classification signal is at a logic level representing a slave, the package is configured to output the signal group without changing the order of the signal group transferred via the pad group of the first die pad array.

11. Each of the aforementioned plurality of semiconductor dies is, A switching circuit configured to change the order of a group of signals transferred between the first die pad array and the second die pad array based on a plurality of control signals and a master classification signal, The semiconductor package according to claim 1, comprising a control circuit configured to set the master division signal based on stacking position information and to generate the plurality of control signals based on the master division signal.

12. A substrate including a first substrate pad array and a second substrate pad array, A first die pad array and a second die pad array are formed on the front surface of a first semiconductor die, the first die pad array is electrically connected to the first substrate pad array via a first bump array, and the second die pad array is electrically connected to the second substrate pad array via a second bump array. A second semiconductor die is stacked on the first semiconductor die such that a first die pad array and a second die pad array are formed on the front surface, and the back surface faces the back surface of the first semiconductor die. A third semiconductor die is stacked on the second semiconductor die such that a first die pad array and a second die pad array are formed on its front surface, and its back surface faces the front surface of the second semiconductor die. A semiconductor package comprising a second die pad array of the second semiconductor die, a second die pad array of the third semiconductor die, and a plurality of conductive wires electrically connecting the second substrate pad array.

13. The semiconductor package according to claim 12, wherein each of the first die pad arrays is formed at a first distance in the outer direction from the center of the corresponding semiconductor die, and the second die pad array is formed at a second distance from the first die pad array in the outer direction.

14. The semiconductor package according to claim 12, wherein the first semiconductor die operates as a master and the master classification signal is set to a first logic level, and the second and third semiconductor dies operate as slaves and the master classification signal is set to a second logic level.

15. The semiconductor package according to claim 12, wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die each include a switching circuit configured to change the order of a group of signals transferred between a corresponding first die pad array and a corresponding second die pad array based on a master sorting signal.

16. The aforementioned switching circuit is A first switching circuit configured to multiplex and output a group of signals transferred via the corresponding first die pad array based on the master sorting signal, The semiconductor package according to claim 15, further comprising: a second switching circuit configured to multiplex and output a group of signals transferred via the corresponding second die pad array based on the master sorting signal.

17. The first semiconductor die, the second semiconductor die, and the third semiconductor die are each, A switching circuit configured to change the order of the signal group transferred between the corresponding first die pad array and the corresponding second die pad array based on a plurality of control signals and a master classification signal, The semiconductor package according to claim 12, comprising a control circuit configured to set the master division signal based on stacking position information and to generate the plurality of control signals based on the master division signal.

18. A substrate on which a substrate pad array is formed, A plurality of semiconductor dies are stacked on the substrate, each having a first die pad array, a second die pad array, and at least one third die pad array. A semiconductor package comprising the substrate pad array, at least one third die pad array of the uppermost semiconductor die among the plurality of semiconductor dies, and a plurality of conductive wires electrically connecting the first die pad array of the uppermost semiconductor die.

19. The semiconductor package according to claim 18, further comprising a plurality of conductive wires for electrically connecting a second die pad array group of the plurality of semiconductor dies.

20. The semiconductor package according to claim 18, wherein the substrate pad array is formed on the outer periphery of the substrate in a first direction.

21. The semiconductor package according to claim 18, wherein the first die pad array is formed on the outer casing in a second direction, the second die pad array is formed at a first distance from the first die pad array in the second direction, and the at least one third die pad array is formed at a second distance from the first die pad array in the first direction.

22. The semiconductor package according to claim 18, wherein, among the plurality of semiconductor dies, the topmost semiconductor die is configured to operate as a master, and the remaining semiconductor dies, excluding the topmost semiconductor die, are configured to operate as slaves.

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