Multilayer electronic components

Abstract

The present invention provides a multilayer electronic component that offers excellent reliability, suppresses electrostrictive phenomena, and ensures high capacitance. [Solution] The stacked electronic component includes a body containing a dielectric layer 111 and internal electrodes 121, 122 arranged alternately with the dielectric layer, and external electrodes arranged on the body. The dielectric layer includes a central part CP separated from the internal electrodes and containing a first dielectric crystal grain G1, and interface parts IP1, IP2 arranged between the internal electrodes and the central part and containing a second dielectric crystal grain G2. When the average size of the first dielectric crystal grain is Gs1, the average size of the second dielectric crystal grain is Gs2, the number of moles of Gd per 100 moles of Ti in the central part is Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface part is Mgd2, the following conditions are satisfied: Gs2 / Gs1 < 1, Mgd1 / Mgd2 < 1, and 4.0 ≤ Mgd2 ≤ 25.0.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] A multilayer ceramic capacitor (MLCC), a type of multilayer electronic component, is a chip-type capacitor that is mounted on the printed circuit boards of various electronic products such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and plays the role of charging or discharging electricity.

[0003] Multilayer ceramic capacitors offer the advantages of being small yet guaranteeing high capacitance and being easy to mount, making them suitable for use as components in various electronic devices. As computers, mobile devices, and other electronic equipment become smaller and more powerful, the demand for smaller and / or higher-capacitance multilayer ceramic capacitors is increasing.

[0004] Furthermore, as the operating environments for multilayer ceramic capacitors become more diverse, reliability at high voltages is also required.

[0005] MLCCs used in high-voltage environments are called high-voltage MLCCs, and their rated voltage is 250V or higher. Because high-voltage MLCCs have a significantly higher rated voltage than general MLCCs, there is a risk of crack formation due to electrostriction when an electric field is applied, reduced moisture resistance, and a decrease in breakdown voltage. [Overview of the project] [Problems that the invention aims to solve]

[0006] One of the various objectives of the present invention is to provide a highly reliable stacked electronic component.

[0007] One of the various objectives of the present invention is to provide a multilayer electronic component that can suppress electrostrictive phenomena.

[0008] One of the various objectives of the present invention is to provide a stacked electronic component that can ensure high capacity.

[0009] However, the objectives of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Means for solving the problem]

[0010] A stacked electronic component according to one embodiment of the present invention includes a body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and external electrodes arranged on the body, wherein the dielectric layer includes a central portion separated from the internal electrodes and containing first dielectric crystal grains, and an interface portion arranged between the internal electrodes and the central portion and containing second dielectric crystal grains, and when the average size of the first dielectric crystal grains is Gs1, the average size of the second dielectric crystal grains is Gs2, the number of moles of Gd per 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface portion is Mgd2, then the following conditions can be satisfied: Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≦Mgd2≦25.0. [Effects of the Invention]

[0011] One of the various effects of the present invention is that the reliability of multilayer electronic components can be improved by controlling the average size of dielectric crystal grains and the Gd content in the interface and central part of the dielectric layer.

[0012] However, the diverse yet significant advantages and effects of the present invention are not limited to those described above and can be more easily understood in the process of describing specific embodiments of the present invention. [Brief explanation of the drawing]

[0013] [Figure 1]This is a schematic perspective view of a multilayer electronic component according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view taken along line I-I' of FIG. 1. [Figure 3] This is a schematic cross-sectional view taken along line II-II' of FIG. 1. [Figure 4] This is an exploded view of the main body of FIG. 1. [Figure 5] This is an enlarged view of the region K1 in FIG. 2. [Figure 6] This is a view corresponding to FIG. 5 according to another embodiment of the present invention. [Figure 7] This is a view corresponding to FIG. 5 according to still another embodiment of the present invention. MODE FOR CARRYING OUT THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shapes and dimensions of elements in the drawings may be scaled up or down (or emphasized or simplified) for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0015] In addition, in order to clearly describe the present invention in the drawings, portions unrelated to the description are omitted. The sizes and thicknesses of the illustrated components are arbitrarily shown for convenience of description, and thus the present invention is not necessarily limited by the illustrations. Further, components having the same function within the scope of the same concept will be described with the same reference numerals. Furthermore, throughout the specification, the expression that a certain portion "comprises" a certain component means that, unless otherwise stated to the contrary, other components can be further included rather than excluding other components.

[0016] In drawings, the X direction can be defined as the first direction, the lamination direction, or the thickness (T) direction; the Y direction as the second direction or the length (L) direction; and the Z direction as the third direction or the width (W) direction.

[0017] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is a schematic cross-sectional view along the line I-I' in Figure 1; Figure 3 is a schematic cross-sectional view along the line II-II' in Figure 1; Figure 4 is an exploded view of the main body of Figure 1; and Figure 5 is an enlarged view of the K1 region in Figure 2.

[0018] The following describes in detail a multilayer electronic component 100 according to one embodiment of the present invention with reference to Figures 1 to 5. While a multilayer ceramic capacitor (MLCC) will be described as an example of a multilayer electronic component, the present invention is not limited to this and can be applied to various multilayer electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0019] A stacked electronic component 100 according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer, and external electrodes 131 and 132 arranged on the body, wherein the dielectric layer 111 includes a central portion CP separated from the internal electrodes and containing a first dielectric crystal grain G1, and interface portions IP1 and IP2 arranged between the internal electrodes and the central portion and containing a second dielectric crystal grain G2, and when the average size of the first dielectric crystal grain is Gs1, the average size of the second dielectric crystal grain is Gs2, the number of moles of Gd per 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface portion is Mgd2, then the following conditions can be satisfied: Gs2 / Gs1 < 1, Mgd1 / Mgd2 < 1, and 4.0 ≤ Mgd2 ≤ 25.0.

[0020] Adding Gd to the dielectric layer can lower the dielectric constant and suppress electrostriction, but this may reduce the capacitance of the multilayer ceramic capacitor.

[0021] According to one embodiment of the present invention, by increasing the Gd content of the interface IP1 and IP2 relative to the central CP and reducing the average size of the dielectric crystal grains, it is possible to suppress electrostriction phenomena while suppressing capacitance reduction due to Gd addition, thereby improving the reliability of the stacked electronic component 100.

[0022] The following describes the various components included in the stacked electronic component 100 according to one embodiment of the present invention.

[0023] The main body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked alternately.

[0024] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be hexahedral or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, the main body 110 is not a perfectly straight hexahedron, but can be substantially hexahedral.

[0025] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2 and connected to the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0026] As margin regions where internal electrodes 121 and 122 are not placed overlap the dielectric layer 111, steps are created due to the thickness of the internal electrodes 121 and 122, and the corners connecting the first surface with the third, fourth, and fifth surfaces and / or the corners connecting the second surface with the third, fourth, and fifth surfaces may have a form that is contracted toward the center of the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, due to the contraction behavior during the sintering process of the main body, the corners connecting the first surface 1 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, fourth surface 4, fifth surface 5, and sixth surface 6 may have a form that is contracted toward the center of the first direction of the main body 110 when viewed with reference to the first or second surface. Alternatively, in order to prevent chipping defects, etc., the corners connecting each surface of the main body 110 can be rounded by performing a separate process, thereby allowing the corners connecting the first surface with the third, fourth, fifth, and sixth surfaces and / or the corners connecting the second surface with the third, fourth, fifth, and sixth surfaces to have a rounded shape.

[0027] On the other hand, in order to suppress the step difference caused by the internal electrodes 121 and 122, if the internal electrodes after lamination are cut so that they are exposed on the fifth surface 5 and sixth surface 6 of the main body, and then a single dielectric layer or two or more dielectric layers are laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form side margin portions 114 and 115, the portions connecting the first surface and the fifth and sixth surfaces, and the portions connecting the second surface and the fifth and sixth surfaces, may not have a contracted form.

[0028] The multiple dielectric layers 111 forming the main body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). There is no particular limit to the number of dielectric layers stacked, and it can be determined considering the size of the multilayer electronic component. For example, the main body can be formed by stacking 400 or more dielectric layers.

[0029] Referring to Figure 5, the dielectric layer 111 is separated from the internal electrodes 121 and 122 and may include a central portion CP containing a first dielectric crystal grain G1, and interfaces IP1 and IP2 containing a second dielectric crystal grain G2, which are positioned between the internal electrodes 121 and 122 and the central portion CP.

[0030] Furthermore, when Gs1 is the average size of the first dielectric crystal grain G1, Gs2 is the average size of the second dielectric crystal grain G2, Mgd1 is the number of moles of Gd per 100 moles of Ti in the central region CP, and Mgd2 is the number of moles of Gd per 100 moles of Ti in the interface regions IP1 and IP2, the following conditions can be satisfied: Gs2 / Gs1 < 1, Mgd1 / Mgd2 < 1, and 4.0 ≤ Mgd2 ≤ 25.0. This makes it possible to suppress electrostriction while suppressing the decrease in capacitance due to Gd addition.

[0031] If the average size Gs1 of the first dielectric crystal grain is smaller than the average size Gs2 of the second dielectric crystal grain, it may be difficult to suppress the electrostrictive phenomenon.

[0032] If Mgd1 is equal to or greater than Mgd2, the capacity may decrease. For example, Mgd1 may be 2.0 or less. On the other hand, the central CP does not necessarily have to contain Gd, and the central CP does not have to contain Gd, in which case Mgd1 may be 0.

[0033] If Mgd2 is less than 4.0, the effect of suppressing electrostrictive expansion of the central CP may be insufficient, and if Mgd2 exceeds 25.0, the capacity may decrease. Therefore, it is preferable to satisfy 4.0 ≤ Mgd2 ≤ 25.0, and more preferably to satisfy 5.0 ≤ Mgd2 ≤ 10.0.

[0034] In one embodiment, Gs1 and Gs2 can satisfy the condition Gs2 / Gs1 ≥ 0.5. This is because if the difference in grain size is too large, other side effects may occur.

[0035] On the other hand, there is no need to specifically limit the scope of Gs1 and Gs2.

[0036] For example, in one embodiment, Gs1 may be between 300 nm and 700 nm, and Gs2 may be between 150 nm and 600 nm. This can further improve the capacity reduction suppression and electrostrictive development suppression effects of the present invention.

[0037] In one embodiment, Gs1 and Gs2 can satisfy the condition Gs1-Gs2≦100nm. This is because if the difference in grain size is too large, other side effects may occur.

[0038] On the other hand, the average size Gs1 of the first dielectric crystal grains, the average size Gs2 of the second dielectric crystal grains, the number of moles of Gd per 100 moles of Ti in the central part Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface part Mgd2 may be measured from image images obtained by observing the cross-sections of the main body 110 in the first and second directions using SEM-EDS (Scanning Electron Microscope-Energy Dispersive X-ray Spectrometer), TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), or FE-SEM-EDS (Field Emission-scanning Electron Microscope-Energy Dispersive X-ray Spectrometer).

[0039] More specifically, the multilayer electronic component 100 is polished up to the 1 / 2 point in the third direction to expose the cross-sections of the multilayer electronic component 100 in the first and second directions. After this, the average size of the dielectric crystal grains can be measured at the interface and the central part of the dielectric layer located in the central part of the first direction of the capacitance forming part Ac using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x). Because the size of the dielectric crystal grains changes abruptly at the boundary between the interface and the central part, the interface and the central part can be easily distinguished from the image scanned by the SEM. The size of the dielectric crystal grains may also be measured by measuring the equivalent diameter of a circle using image analysis software (ImageJ), and the sizes of 30 or more dielectric crystal grains at the interface and the central part can be averaged to obtain Gs1 and Gs2.

[0040] Furthermore, the content (mol%) of Gd and Ti is measured in both the interface and the central region. This allows us to calculate the number of moles of Gd per 100 moles of Ti in the interface and the central region, respectively, and thereby determine Mgd1 and Mgd2.

[0041] On the other hand, by selecting 10 dielectric layers located in the upper, central, and lower parts of the capacitance-forming section Ac in the first direction, and calculating Gs1, Gs2, Mgd1, and Mgd2 for a total of 30 dielectric layers, the average value of these values ​​can be calculated to further generalize Gs1, Gs2, Mgd1, and Mgd2.

[0042] In one embodiment, the internal electrodes 121 and 122 include a first internal electrode 121 and a second internal electrode 122 that are alternately arranged with a dielectric layer 111 in between, and the interface portions IP1 and IP2 may include a first interface portion IP1 arranged between the central portion CP and the first internal electrode 121, and a second interface portion IP2 arranged between the central portion CP and the second internal electrode 122.

[0043] In one embodiment, when the average thickness of the first interface IP1 is tdi1, the average thickness of the second interface IP2 is tdi2, and the average thickness of the central CP is tdc, the conditions tdi1 / tdc ≤ 0.2 and tdi2 / tdc ≤ 0.2 can be satisfied. If tdi1 / tdc exceeds 0.2 or tdi2 / tdc exceeds 0.2, the capacity degradation suppression effect according to the present invention may be insufficient.

[0044] On the other hand, there is no need to specifically limit the scope of tdi1, tdi2, and tdc.

[0045] For example, in one embodiment, tdi1 and tdi2 may each be between 200 nm and 500 nm.

[0046] In one embodiment, the above TDC may be 1000 nm or greater.

[0047] In one embodiment, the sum of tdi1, tdi2, and tdc may be between 1.4 μm and 10.0 μm. Here, the sum of tdi1, tdi2, and tdc can represent the average thickness td of the dielectric layer.

[0048] Here, tdi1, tdi2, and tdc can represent the thickness in the first direction. tdi1, tdi2, and tdc can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. The thicknesses of the first interface IP1, the second interface IP2, and the central CP can be measured at 30 equally spaced points in the second direction, and their average values ​​can be calculated. These 30 equally spaced points can be specified by the capacitance forming section Ac, which will be described later. Furthermore, by extending this average value measurement to 10 dielectric layers 111 and measuring the average values, tdi1, tdi2, and tdc can be further generalized.

[0049] In one embodiment, the dielectric constant of the interface IP1 and IP2 may be 1500 or less, while the dielectric constant of the central portion CP may be 2000 or more. This can further improve the capacitance reduction suppression and electrostrictive development suppression effects of the present invention.

[0050] On the other hand, referring to Figure 6, the second dielectric crystal grain G2' contained in the interface IP1 and IP2 of the dielectric layer 111' can have a core-shell structure including a core G2c and a shell G2s surrounding at least a part of the core G2c. In this case, the atomic percentage of the Gd content contained in the shell G2s can be higher than the atomic percentage of the Gd content contained in the core G2c. In this case, the first dielectric crystal grain G1 contained in the central part CP does not have to have a core-shell structure.

[0051] However, the design is not limited to this, and as shown in Figure 7, all first dielectric crystal grains G1' and second dielectric crystal grains G2' contained in the dielectric layer 111'' may have a core-shell structure. Referring to Figure 7, the first dielectric crystal grains G1' contained in the central part CP of the dielectric layer 111' may also have a core-shell structure including a core G1c and a shell G1s surrounding at least a part of the core G1c. In this case, the atomic percentage of the Gd content contained in the shell G1s may be higher than the atomic percentage of the Gd content contained in the shell G1s.

[0052] The method for forming the dielectric layer 111 is not particularly limited.

[0053] For example, a ceramic green sheet can be prepared by coating a carrier film with a ceramic slurry containing an organic solvent and a binder, such that the Gd content is higher at the interface than in the center. A dielectric layer can then be formed by sintering the ceramic green sheet.

[0054] The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained. For example, barium titanate (BaTiO₃)-based powder can be used as the ceramic powder. To give a more specific example, the ceramic powder is BaTiO₃, (Ba 1-x Ca x )TiO₃ (0<x<1), Ba(Ti 1-y Ca y )O₃ (0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O₃ (0<x<1, 0<y<1) and Ba(Ti 1-y Zr y )O₃ (0<y<1) may be one or more of the above.

[0055] Therefore, in one embodiment, the dielectric layer 111 comprises BaTiO₃, (Ba 1-x Ca x )TiO₃ (0<x<1), Ba(Ti 1-y Ca y )O₃ (0<y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O₃ (0<x<1, 0<y<1) and Ba(Ti 1-y Zr y )O₃ (0<y<1) may contain one or more of the above as a main component. Here, the term "main component" can mean that the number of moles of the remaining components excluding the main component is 30 moles or less per 100 moles of the main component.

[0056] The main body 110 includes a capacitance forming portion Ac that is disposed inside the main body 110 and forms a capacitance including a first internal electrode 121 and a second internal electrode 122 disposed to face each other with the dielectric layer 111 interposed therebetween, and cover portions 112 and 113 formed on upper and lower sides of the capacitance forming portion Ac in the first direction.

[0057] Furthermore, the capacitance-forming portion Ac can be formed by repeatedly stacking multiple first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 in between, as a portion that contributes to the capacitance formation of the capacitor.

[0058] The cover portions 112 and 113 may include an upper cover portion 112 positioned above the volume-forming portion Ac in the first direction and a lower cover portion 113 positioned below the volume-forming portion Ac in the first direction.

[0059] The upper cover portion 112 and the lower cover portion 113 described above can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion Ac, respectively, and can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0060] The upper cover portion 112 and the lower cover portion 113 described above do not include internal electrodes and may contain the same material as the dielectric layer 111.

[0061] In other words, the upper cover portion 112 and the lower cover portion 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0062] On the other hand, the thickness of the cover portions 112 and 113 is not particularly limited. For example, the thickness tc of the cover portions 112 and 113 may be 100 μm or less.

[0063] The average thickness tc of the cover portions 112 and 113 can represent the size in the first direction, and may be the average value of the sizes of the cover portions 112 and 113 in the first direction measured at five equally spaced points on the upper or lower part of the volume forming portion Ac.

[0064] Furthermore, margin portions 114 and 115 can be arranged on the side surface of the volume-forming portion Ac.

[0065] The margin portions 114 and 115 may include a first margin portion 114 located on the fifth surface 5 of the main body 110 and a second margin portion 115 located on the sixth surface 6. That is, the margin portions 114 and 115 can be located on both end surfaces in the width direction of the ceramic main body 110.

[0066] As shown in Figure 5, the margin portions 114 and 115 can refer to the regions between the interface between both ends of the first internal electrode 121 and the second internal electrode 122 and the body 110 in a cross-section obtained by cutting the body 110 in the width-thickness (WT) direction.

[0067] The margins 114 and 115 can essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0068] The margin portions 114 and 115 may be formed by applying conductive paste to the ceramic green sheet, except where the margin portions are formed, to form internal electrodes.

[0069] Furthermore, in order to suppress the step caused by the internal electrodes 121 and 122, after cutting the laminated internal electrodes so that they are exposed on the fifth and sixth surfaces 5 and 6 of the main body, a single dielectric layer or two or more dielectric layers can be laminated on both sides of the capacitance forming portion Ac in the third direction (width direction) to form margin portions 114 and 115.

[0070] On the other hand, the width of the margin portions 114 and 115 does not need to be particularly limited. For example, the average width of the margin portions 114 and 115 may be 100 μm or less.

[0071] The average width of the margin portions 114 and 115 can represent the average size MW1 in the third direction of the region where the internal electrodes are separated from the fifth surface and the average size MW2 in the third direction of the region where the internal electrodes are separated from the sixth surface, and can be the average value of the sizes of the margin portions 114 and 115 in the third direction measured at five equally spaced points on the side surface of the capacitance forming portion Ac.

[0072] Therefore, in one embodiment, the average size MW1 and MW2 in the third direction of the region where the internal electrodes 121 and 122 are separated from the fifth and sixth surfaces may be 100 μm or less, respectively.

[0073] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrode 121 and the second internal electrode 122 are arranged alternately so as to face each other across the dielectric layer 111 that constitutes the main body 110, and can be exposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively.

[0074] The first internal electrode 121 is separated from the fourth surface 4 and exposed via the third surface 3, and the second internal electrode 122 can be separated from the third surface 3 and exposed via the fourth surface 4. The first external electrode 131 is positioned on the third surface 3 of the main body and connected to the first internal electrode 121, and the second external electrode 132 is positioned on the fourth surface 4 of the main body and can be connected to the second internal electrode 122.

[0075] In other words, the first internal electrode 121 is not connected to the second external electrode 132, but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131, but is connected to the second external electrode 132. Therefore, the first internal electrode 121 can be formed at a certain distance apart on the fourth surface 4, and the second internal electrode 122 can be formed at a certain distance apart on the third surface 3. Furthermore, the first internal electrode 121 and the second internal electrode 122 may be arranged at a distance from the fifth and sixth surfaces of the main body 110.

[0076] The conductive metals contained in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, W, Ti, and alloys thereof, but the present invention is not limited thereto.

[0077] The average thickness te of the internal electrodes does not need to be particularly limited. In this case, the thickness of the internal electrodes 121 and 122 can represent the size of the internal electrodes 121 and 122 in the first direction.

[0078] However, in order to more easily achieve miniaturization and high capacitance of the multilayer electronic component, the average thickness of the internal electrodes 121 and 122 may be 0.4 μm or less.

[0079] Here, the average thickness te of the internal electrodes can be measured by scanning the cross-sections of the main body 110 in the first and second directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the thickness of one internal electrode 121, 122 can be measured at multiple points, for example, 30 points equally spaced in the second direction, and the average value can be measured. The 30 equally spaced points can be specified in the capacitance forming section Ac. Furthermore, by extending this average value measurement to 10 internal electrodes 121, 122 and measuring the average value, the average thickness of the internal electrodes 121, 122 can be further generalized.

[0080] External electrodes 131 and 132 may be arranged on the third surface 3 and fourth surface 4 of the main body 110.

[0081] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132, which are arranged on the third surface 3 and fourth surface 4 of the main body 110, respectively, and connected to a first internal electrode 121 and a second internal electrode 122, respectively.

[0082] Referring to Figure 1, the external electrodes 131 and 132 can be positioned to cover both end faces of the side margin portions 114 and 115 in the second direction.

[0083] In this embodiment, a structure in which the stacked electronic component 100 has two external electrodes 131 and 132 is described, but the number and shape of the external electrodes 131 and 132 can be changed according to the form of the internal electrodes 121 and 122 or other purposes.

[0084] On the other hand, the external electrodes 131 and 132 can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. Furthermore, they can have a multilayer structure.

[0085] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a placed on the main body 110, and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0086] To give a more specific example for the electrode layers 131a and 132a, the electrode layers 131a and 132a may be firing electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0087] Furthermore, the electrode layers 131a and 132a may be formed in a manner in which a fired electrode and a resin-based electrode are sequentially formed on the main body. Also, the electrode layers 131a and 132a may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0088] The conductive metal contained in the electrode layers 131a and 132a can be any material with excellent electrical conductivity, but is not particularly limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0089] The plating layers 131b and 132b play a role in improving mounting characteristics. The types of plating layers 131b and 132b are not particularly limited and may be plating layers containing one or more of Ni, Sn, Pd, and their alloys, and may be formed in multiple layers.

[0090] To give a more specific example for the plating layers 131b and 132b, the plating layers 131b and 132b may be Ni plating layers or Sn plating layers, and may be in a form in which Ni plating layers and Sn plating layers are formed sequentially on the electrode layers 131a and 132a, or may be in a form in which Sn plating layers, Ni plating layers and Sn plating are formed sequentially. Furthermore, the plating layers 131b and 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0091] The size of the multilayer electronic component 100 is not particularly limited. For example, the size of the multilayer electronic component 100 may be 0201 (length x width, 0.2 mm x 0.1 mm), 0603 (length x width, 0.6 mm x 0.3 mm), 1005 (length x width, 1.0 mm x 0.5 mm), 2012 (length x width, 2.0 mm x 1.2 mm), 3216 (length x width, 3.2 mm x 1.6 mm), 3225 (length x width, 3.2 mm x 2.5 mm), etc.

[0092] Manufacturing method for multilayer electronic components The following describes an example of a method for manufacturing a stacked electronic component 100 according to one embodiment of the present invention. However, the method for manufacturing the stacked electronic component 100 of the present invention is not limited thereto.

[0093] First, a ceramic slurry containing ceramic powder, an organic solvent, and a binder is applied to a carrier film to create a ceramic green sheet. The ceramic green sheet can be manufactured by ensuring that the Gd content is higher at the interface of the ceramic sheet than in the center.

[0094] Subsequently, a conductive paste for internal electrodes containing metal powder, binder, organic solvent, etc., is printed onto the ceramic green sheet to a predetermined thickness using screen printing or gravure printing to form an internal electrode pattern, thereby producing a ceramic green sheet for the capacitance forming section.

[0095] A laminate can be obtained by stacking ceramic green sheets for the volume-forming section in the X direction. At this time, ceramic green sheets without internal electrode patterns can be stacked on the upper and lower parts of the laminate to form the cover sections 112 and 113 after sintering.

[0096] Next, the laminate is cut to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both sides of the cut chip facing the third direction.

[0097] Next, the margin-forming sheet can be attached to both sides of the cut chip in the third direction, and then fired to form the main body 110 and the side margin portions 114 and 115. The firing temperature may be, for example, 1000°C or more and 1400°C or less, but the present invention is not limited thereto.

[0098] The sheet used for forming the margin area is not particularly limited, and the general ceramic green sheet described above can be used.

[0099] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0100] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0101] Furthermore, electroplating and / or electroless plating may be performed to form plating layers 131b and 132b on the underlying electrode layers 131a and 132a.

[0102] (Example of experiment) Using the manufacturing method described above, sample chips of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) were prepared.

[0103] Sample chips were fabricated such that the average size Gs1 of the first dielectric crystal grains, the average size Gs2 of the second dielectric crystal grains, the number of moles of Gd per 100 moles of Ti in the central region Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface region Mgd2 satisfy Table 1 below.

[0104] The average size Gs1 of the first dielectric crystal grain, the average size Gs2 of the second dielectric crystal grain, the number of moles of Gd per 100 moles of Ti in the central region Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface region Mgd2 were measured by analyzing the cross-sections in the first and second directions of the sample chip, which had been polished to the halfway point in the third direction, via FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x).

[0105] The capacitance of the sample chips was measured using an LCR meter under 1 kHz conditions, and the relative values ​​are listed in Table 1 below.

[0106] Furthermore, humidity resistance reliability was assessed by applying a high voltage (1kV) for 1000 hours at a temperature of 85°C and relative humidity of 85% after mounting the sample chip to a substrate. If the insulation resistance value fell to 1 / 100 or less of the initial value, it was indicated as "×", and if the insulation resistance value remained above 1 / 100 of the initial value, it was indicated as "○". In the case of "×", it can be judged that cracks occurred due to electrostriction and the electrostriction suppression effect was insufficient. In the case of "○", it can be considered that the electrostriction phenomenon was suppressed and no cracks occurred, and it can be judged that the electrostriction suppression effect was excellent.

[0107] [Table 1]

[0108] Referring to Table 1, test number 1, where Mgd1 and Mgd2 are 0, shows the best capacity, but its moisture resistance reliability is confirmed to be degraded. Test numbers 2 and 3, which have small amounts of Gd added, also show degraded moisture resistance reliability. In the case of test numbers 6 and 7, the amount of Gd added is large, and it is confirmed that the capacity is reduced.

[0109] On the other hand, in the case of test numbers 4 and 5, which satisfy all of the following conditions: Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≦Mgd2≦25.0, it can be confirmed that the moisture resistance reliability is excellent while suppressing capacity degradation.

[0110] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the embodiments described above and the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the technical idea of ​​the present invention as described in the claims, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, and these also fall within the scope of the present invention.

[0111] Furthermore, the expression "one embodiment" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and describe the unique and distinct features of each embodiment. However, the present embodiments are not excluded from being realized in combination with features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is inconsistent with that matter.

[0112] The terms used in this disclosure are used solely to describe one embodiment and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0113] 100 Stacked Electronic Components 110 Main Unit 111 Dielectric layer IP1, IP2 interface part CP center 112, 113 Cover section 114, 115 Margin section 121, 122 Internal electrode 131, 132 External electrode 131a, 132a electrode layer 131b, 132b Plating layer

Claims

1. A body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, The body includes an external electrode disposed on the main body, The dielectric layer includes a central portion separated from the internal electrode and containing first dielectric crystal grains, and an interface portion disposed between the internal electrode and the central portion and containing second dielectric crystal grains. When the average size of the first dielectric crystal grains is Gs1, the average size of the second dielectric crystal grains is Gs2, the number of moles of Gd per 100 moles of Ti in the central part is Mgd1, and the number of moles of Gd per 100 moles of Ti in the interface part is Mgd2, A multilayer electronic component satisfying Gs2 / Gs1 < 1, Mgd1 / Mgd2 < 1, and 4.0 ≤ Mgd2 ≤ 25.

0.

2. The stacked electronic component according to claim 1, wherein Gs1 and Gs2 satisfy Gs2 / Gs1 ≥ 0.

5.

3. The aforementioned Gs1 is between 300 nm and 700 nm. The multilayer electronic component according to claim 1, wherein the Gs2 is 150 nm or more and 600 nm or less.

4. The stacked electronic component according to claim 1, wherein Gs1 and Gs2 satisfy Gs1 - Gs2 ≤ 100 nm.

5. The stacked electronic component according to claim 1, wherein Mgd2 satisfies 5.0 ≤ Mgd2 ≤ 10.

0.

6. The stacked electronic component according to claim 1, wherein Mgd1 is 0.

7. The internal electrodes include first internal electrodes and second internal electrodes that are alternately arranged with the dielectric layer in between. The multilayer electronic component according to any one of claims 1 to 6, wherein the interface portion includes a first interface portion disposed between the central portion and the first internal electrode and a second interface portion disposed between the central portion and the second internal electrode.

8. When the average thickness of the first interface is tdi1, the average thickness of the second interface is tdi2, and the average thickness of the central part is tdc, The stacked electronic component according to claim 7, satisfying tdi1 / tdc ≤ 0.2 and tdi2 / tdc ≤ 0.

2.

9. The stacked electronic component according to claim 8, wherein tdi1 and tdi2 are each 200 nm or more and 500 nm or less.

10. The stacked electronic component according to claim 8, wherein the TDC is 1000 nm or more.

11. The stacked electronic component according to claim 8, wherein the sum of tdi1, tdi2, and tdc is 1.4 μm or more and 10.0 μm or less.

12. The dielectric layer contains BaTiO ３ , (Ba １－ｘ Ca ｘ )TiO ３ (0 < x < 1), Ba(Ti １－ｙ Ca ｙ )O ３ (0 < y < 1), (Ba １－ｘ Ca ｘ )(Ti １－ｙ Zr ｙ )O ３ (0 < x < 1, 0 < y < 1) and Ba(Ti １－ｙ Zr ｙ )O ３ The multilayer electronic component according to any one of claims 1 to 6, wherein the dielectric layer comprises one or more of (0 < y < 1) as a main component.

13. The laminated electronic component according to any one of claims 1 to 6, wherein the dielectric constant of the interface portion is 1500 or less, and the dielectric constant of the central portion is 2000 or more.

14. The stacked electronic component according to any one of claims 1 to 6, wherein the second dielectric crystal grain has a core-shell structure.

15. The stacked electronic component according to claim 14, wherein the first dielectric crystal grain has a core-shell structure.

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