Display device and electronic device including the same

Abstract

The objective is to provide a display device and an electronic device including the same that can efficiently arrange the components of each pixel and the wiring connected to the pixels within a limited space. [Solution] The display device according to the present invention includes a pixel which is a light-emitting element, a first transistor which operates in response to the potential of a first node and is connected between a first power line and a second node, a second transistor which is connected between a data line and a first node and receives a write scan signal, a third transistor which is connected between a first node and a reference voltage line and receives a reference scan signal, a first light-emitting control transistor which is connected between a second node and a first electrode of the light-emitting element and receives a first light-emitting control signal, and a fourth transistor which is connected between a first electrode of the light-emitting element and an initialization voltage line and receives a black scan signal. The first light-emitting control line is superimposed on the black scan line on a plane.

Description

Technical Field

[0001] The present invention relates to a display device and an electronic device including the same, and more particularly to a high-resolution display device and an electronic device including the same. Background Art

[0002] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablets, include a display panel for displaying images. Various types of display panels have been developed, including liquid crystal display panels, organic light emitting display panels, electro wetting display panels, and electrophoretic display panels.

[0003] A display panel includes a plurality of pixels for generating images. Each pixel includes a light emitting element, and a plurality of transistors and a capacitor connected to the light emitting element. As the resolution of display devices increases, there is a demand for a technology that can efficiently arrange components of each pixel and wirings connected to the pixels in a limited space. Prior Art Documents Patent Documents

[0004] Patent Document 1 Korean Patent Laid-Open No. 2024-0028270 Summary of the Invention Problem to be Solved by the Invention

[0005] An object of the present invention is to provide a display device that can efficiently arrange components of each pixel and wirings connected to the pixels in a limited space, and an electronic device including the same. Means for Solving the Problem

[0006] A display device according to one embodiment of the present invention includes a display panel that includes pixels.

[0007] The pixel includes a light-emitting element with first and second electrodes, a first transistor that operates in response to the potential of a first node and is connected between a first power line and a second node, a second transistor connected between a data line and the first node and receiving a write scan signal, a third transistor connected between the first node and a reference voltage line and receiving a reference scan signal, a first light-emitting control transistor connected between the second node and the first electrode of the light-emitting element and receiving a first light-emitting control signal through a first light-emitting control line, and a fourth transistor connected between the first electrode of the light-emitting element and an initialization voltage line and receiving a black scan signal through a black scan line.

[0008] The inactive interval of the first light emission control signal is included within the active interval of the black scan signal, and the first light emission control line superimposed on the black scan line on a plane.

[0009] A display device according to one embodiment of the present invention includes a display panel that includes pixels.

[0010] The pixel includes a light-emitting element with first and second electrodes, a first transistor that operates in response to the potential of a first node and is connected between a first power line and a second node, a second transistor connected between a data line and the first node and receiving a write scan signal, a third transistor connected between the first node and a reference voltage line and receiving a reference scan signal, a first light-emitting control transistor connected between the second node and the first electrode of the light-emitting element and receiving a shared control signal, and a fourth transistor connected between the first electrode of the light-emitting element and an initialization voltage line and receiving the shared control signal.

[0011] Each of the first and fourth transistors is an N-type transistor, and the first light-emitting control transistor is a P-type transistor.

[0012] An electronic device according to one embodiment of the present invention includes a display panel including pixels, a panel driver for driving the display panel, a drive controller for controlling the driving of the panel driver, and a processor for providing image signals to the drive controller.

[0013] The pixel includes a light-emitting element with first and second electrodes, a first transistor that operates in response to the potential of a first node and is connected between a first power line and a second node, a second transistor connected between a data line and the first node and receiving a write scan signal, a third transistor connected between the first node and a reference voltage line and receiving a reference scan signal, a first light-emitting control transistor connected between the second node and the first electrode of the light-emitting element and receiving a first light-emitting control signal through a first light-emitting control line, and a fourth transistor connected between the first electrode of the light-emitting element and an initialization voltage line and receiving a black scan signal through a black scan line.

[0014] The inactive interval of the first light emission control signal is included within the active interval of the black scan signal, and the first light emission control line superimposed on the black scan line on a plane. [Effects of the Invention]

[0015] According to the present invention, the fourth transistor and the first light-emitting control transistor are composed of different types of transistors, and the first light-emitting control line that applies a light-emitting control signal to the first light-emitting control transistor can be superimposed on a plane with the black scan line that applies a black scan signal to the fourth transistor. As a result, even if the resolution of the display device is increased, the components of each pixel and the signal lines can be efficiently arranged in a limited space. [Brief explanation of the drawing]

[0016] [Figure 1] It is a block diagram of an electronic device according to one embodiment. [Figure 2] It is a schematic diagram illustrating embodiments of various electronic devices. [Figure 3] It is a perspective view of an electronic device according to one embodiment of the present invention. [Figure 4] It is a drawing exemplarily illustrating a cross-section of the electronic device illustrated in FIG. 3. [Figure 5] It is a drawing exemplarily illustrating a cross-section of the display panel illustrated in FIG. 4. [Figure 6] It is a block diagram of a display device according to one embodiment of the present invention. [Figure 7A] It is a circuit diagram of one pixel among the pixels illustrated in FIG. 6. [Figure 7B] It is a circuit diagram of a pixel according to one embodiment of the present invention. [Figure 8] It is a waveform diagram illustrating signals applied to the pixel illustrated in FIG. 7A. [Figure 9] It is a cross-sectional view of a display panel according to one embodiment of the present invention. [Figure 10A] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10B] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10C] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10D] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10E] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10F] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10G] It is a plan view illustrating a manufacturing process of a display panel according to one embodiment of the present invention. [Figure 11] It is a cross-sectional view taken along cutting line I-I' illustrated in FIG. 10E. [Figure 12A] This is a plan view showing the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 12B] This is a plan view showing the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view taken along the cutting line II-II' shown in Figure 12B. [Figure 14A] This is a circuit diagram of a pixel according to one embodiment of the present invention. [Figure 14B] Figure 14A is a waveform diagram showing the signal applied to the pixel illustrated. [Figure 15A] This is a circuit diagram of a pixel according to one embodiment of the present invention. [Figure 15B] Figure 15A is a waveform diagram showing the signal applied to the pixel illustrated. [Figure 16A] This is a plan view showing the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 16B] This is a plan view showing the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 17] This is a cross-sectional view taken along the cutting line III-III' shown in Figure 16B. [Modes for carrying out the invention]

[0017] In this specification, when a given component (or region, layer, part, etc.) is described as being “on top of,” “connected to,” or “joined with” another component, it means that it can be directly placed on / connected to / joined with the other component, or that a third component can be placed between them.

[0018] Identical drawing reference numerals indicate identical components. Furthermore, the thickness, proportions, and dimensions of components in drawings are exaggerated for the sake of efficient technical explanation. "and / or" includes all possible combinations of related components.

[0019] The terms "first," "second," etc., may be used to describe a variety of components, but such components should not be limited by such terms. The terms are used solely for the purpose of distinguishing one component, part, region, layer, or portion from other components, parts, regions, layers, or portions. For example, without departing from the scope of the present invention, a first component, first part, first region, first layer, or first portion may be referred to as a second component, second part, second region, second layer, or second portion, and similarly, a second component, second part, second region, second layer, or second portion may also be referred to as a first component, first part, first region, first layer, or first portion. A singular expression may include plural expressions unless clearly distinguished in context.

[0020] Furthermore, terms such as “down,” “on the lower side,” “up,” and “on the upper side” are used to describe the relationships between components shown in the drawing. These terms are relative concepts and are described in relation to the direction shown in the drawing.

[0021] Terms such as “includes” or “possesses” are intended to specify the existence of features, numbers, stages, operations, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the existence or possibility of adding one or more other features, numbers, stages, operations, components, parts, or combinations thereof.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted to have the meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an overly idealistic or overly formal sense unless expressly defined herein.

[0023] Embodiments of the present invention will be described in detail below with reference to the drawings.

[0024] Figure 1 is a block diagram of an electronic device according to one embodiment.

[0025] Referring to Figure 1, an electronic device EA according to one embodiment may include a display electronic module (or display device DM), a processor PR, a memory MR, and a power supply electronic module PM.

[0026] A processor PR may include at least one of the following: a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), or a controller.

[0027] Memory MR can store data information necessary for the operation of the processor PR and the display electronic module DM. When the processor PR executes the application stored in memory MR, image data signals and / or input control signals are transmitted to the display electronic module DM, which processes the received signals and outputs image information through the display screen. The display electronic module DM may include a display panel for displaying images.

[0028] The power supply electronic module PM shall include a power conversion electronic module. The power conversion electronic module can convert the power supplied by a power supply electronic module such as a power adapter or battery device to generate the power required for the operation of the electronic device EA.

[0029] At least one of the components of the electronic device EA described above can be included in a display electronic module according to one embodiment described later, and in a display device according to one embodiment including the same. Furthermore, some of the individual modules functionally included in one module may be included in the display device, while other parts may be provided separately from the display device. For example, the display device may include a display electronic module DM, and the processor PR, memory MR, and power supply electronic module PM may be provided in the form of different devices within the electronic device EA that are not the display device.

[0030] Figure 2 is a schematic diagram showing various embodiments of electronic devices.

[0031] Referring to Figure 2, a variety of electronic devices including a display module (or display device) according to one embodiment can include not only image display electronic devices such as smartphones EA_1a, tablet PCs EA_1b, laptops EA_1c, TVs EA_1d, and desk monitors EA_1e, but also wearable electronic devices such as smart glasses EA_2a, head-mounted displays EA_2b, and smartwatches EA_2c, as well as automotive electronic devices EA_3 such as CIDs (Center Information Displays) located on car instrument panels, center fascias, and dashboards, and rearview mirror displays.

[0032] Figure 3 is a perspective view of an electronic device according to one embodiment of the present invention.

[0033] Referring to Figure 3, the electronic device EA may include a long side extending parallel to the first direction DR1 and a short side extending parallel to the second direction DR2 which intersects the first direction DR1. However, this is illustrated as an example, and the electronic device EA may include sides of the same length with respect to both the first direction DR1 and the second direction DR2, and is not limited to any one embodiment.

[0034] Hereinafter, the direction that intersects substantially perpendicularly with the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Alternatively, in this specification, the meaning of "as seen on the plane" (or "on the plane") is defined as the state as seen from the third direction DR3.

[0035] The front surface of the electronic device EA can be defined as a display surface DS, which may have planes defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device EA can be provided to the user through the display surface DS.

[0036] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA is the area where an image is displayed, and the non-display area NDA may be the area where no image is displayed. The non-display area NDA may be adjacent to at least one side of the display area DA. In this embodiment, the non-display area NDA may have a frame shape surrounding the display area DA. However, this is illustrated as an example, and in one embodiment of the present invention, the non-display area NDA may be omitted, in which case the display surface DS may consist only of the display area DA.

[0037] The electronic device EA may sense inputs applied externally to the electronic device EA. For example, the electronic device EA can sense a first input via touch TC and a second input via a stylus pen PEN. The first input via touch TC can include various forms of external input using a part of the user's body, light, heat, or pressure. The stylus pen PEN can be an active pen or an electromagnetic pen, and is not limited to any one embodiment. The stylus pen PEN can be defined as an input device, and the display area DA can provide the user with a sensing area that can sense input in addition to displaying an image.

[0038] In one embodiment, the electronic device EA may be a large electronic device such as a television, monitor, or external light advertising board. Alternatively, the electronic device EA may be a small electronic device such as a personal computer, laptop computer, personal digital terminal, car navigation unit, game console, smartphone, tablet, or camera. However, this is illustrative, and different electronic devices EA may be used as long as they do not deviate from the concept of the present invention. Figure 3 illustrates the electronic device EA as a tablet device.

[0039] Figure 4 is an illustrative diagram showing a cross-section of the electronic device shown in Figure 3. Figure 5 is an illustrative diagram showing a cross-section of the display panel shown in Figure 4.

[0040] Referring to Figure 4, the electronic device EA may include a display panel DP, an input sensor ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and first and second adhesive layers AL1 and AL2.

[0041] A display panel DP according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may contain organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may contain quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an example of an organic light-emitting display panel.

[0042] Referring to Figure 5, the display panel DP may include a substrate BS, a circuit element layer DP-CL, a display element layer DP-ED, and a thin-film encapsulation layer TFE. The circuit element layer DP-CL, the display element layer DP-ED, and the thin-film encapsulation layer TFE can be arranged sequentially on the substrate BS.

[0043] The substrate BS may contain glass or a flexible plastic material such as polyimide (PI).

[0044] Multiple pixels can be arranged in the circuit element layer DP-CL and the display element layer DP-ED. Each pixel may include a transistor located in the circuit element layer DP-CL and a light-emitting element located in the display element layer DP-ED and connected to the transistor.

[0045] The thin-film encapsulation layer TFE can be positioned on the circuit element layer DP-CL so as to cover the display element layer DP-ED. The thin-film encapsulation layer TFE can protect the pixels from moisture, oxygen, and external foreign matter. In this embodiment, the thin-film encapsulation layer TFE is shown to cover the entire area of ​​the substrate BS, but in one embodiment of the present invention, the substrate BS may include a portion of the area exposed from the thin-film encapsulation layer TFE. Alternatively, the area exposed from the thin-film encapsulation layer TFE may be formed along the edge of the substrate BS, and the invention is not limited to any one embodiment.

[0046] Referring to Figure 4, the input sensor ISP can be positioned on the display panel DP. The input sensor ISP may include multiple sensing units (not shown) for sensing external inputs in a capacitive manner. The input sensor ISP can be formed directly on the display panel DP during the manufacturing of the electronic device EA. Specifically, the conductive patterns and insulating layers constituting the input sensor ISP can be directly deposited or patterned onto the display panel DP. However, this is not the only embodiment, and the input sensor ISP may be manufactured on a separate panel from the display panel DP and attached to the display panel DP via an adhesive layer.

[0047] Referring to Figure 4, the anti-reflective layer RPL can be placed on the input sensor ISP. The anti-reflective layer RPL can reduce the ambient light reflectance of the electronic device EA, thereby improving the visibility of the image displayed on the electronic device EA. The anti-reflective layer RPL may include a phase delay element, polarizer, black matrix, color filter, etc., and is not limited to any one embodiment. The anti-reflective layer RPL may be formed directly on the input sensor ISP through a coating or vapor deposition process, or it may be provided in film form and attached to the input sensor ISP via an adhesive layer, and is not limited to any one embodiment.

[0048] WindowWIN can be placed on top of the anti-reflective layer RPL. WindowWIN can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external scratches and impacts.

[0049] A panel protection film (PPF) can be placed beneath the display panel (DP). The panel protection film (PPF) can support the display panel (DP) and protect the lower part of the display panel (DP). The panel protection film (PPF) can be insulating. For example, the panel protection film (PPF) may contain, but is not limited to, resins such as polyethylene terephthalate (PET), polyimide, or polypropylene (PP).

[0050] The first adhesive layer AL1 is placed between the display panel DP and the panel protective film PPF, and the first adhesive layer AL1 allows the display panel DP and the panel protective film PPF to be bonded together. The second adhesive layer AL2 is placed between the window WIN and the anti-reflective layer RPL, and the second adhesive layer AL2 allows the window WIN and the anti-reflective layer RPL to be bonded together.

[0051] Figure 6 is a block diagram of a display device according to one embodiment of the present invention.

[0052] Referring to Figure 6, the display device DD includes a display panel DP, a panel driver, and a drive controller 100. In one example of the present invention, the panel driver includes a data driver 200, a scan driver 300, a light-emitting driver 350, and a voltage generator 400.

[0053] The drive controller 100 receives the image signal RGB and the control signal CTRL from the processor PR (see Figure 1). The drive controller 100 generates image data I_DAT by converting the data format of the image signal RGB to match the interface specifications with the data driver 200. Based on the control signal CTRL, the drive controller 100 generates a first control signal SCS, a second control signal ECS, and a third control signal DCS.

[0054] The data driver 200 receives the third control signal DCS and image data I_DAT from the drive controller 100. The data driver 200 converts the image data I_DAT into a data signal (or data voltage) and outputs the data signal to several data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data I_DAT.

[0055] The scan driver 300 receives a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 can output a scan signal to the scan line.

[0056] The voltage generator 400 generates the voltages used to operate the display panel DP. In this embodiment, the voltage generator 400 generates a first power supply voltage ELVDD, a second power supply voltage ELVSS, a reference voltage VREF, and an initialization voltage VINT.

[0057] The display panel DP may include a display area DP-DA corresponding to the display area DA (illustrated in Figure 1) and a non-display area DP-NDA corresponding to the non-display area NDA (illustrated in Figure 1).

[0058] The display panel DP may include multiple pixels PX arranged in the display area DP-DA. The display panel DP further includes write scan lines GWL1~GWLn, reference scan lines GRL1~GRLn, black scan lines GBL1~GBLn, first light emission control lines EMBL1~EMBLn, second light emission control lines EML1~EMLn, and data lines DL1~DLm. The write scan lines GWL1~GWLn, reference scan lines GRL1~GRLn, black scan lines GBL1~GBLn, first light emission control lines EMBL1~EMBLn, and second light emission control lines EML1~EMLn extend in the first direction DR1. The write scan lines GWL1~GWLn, reference scan lines GRL1~GRLn, black scan lines GBL1~GBLn, first light emission control lines EMBL1~EMBLn, and second light emission control lines EML1~EMLn are arranged spaced apart from each other in the second direction DR2. Data lines DL1 to DLm are extended in the second direction DR2 and arranged in the first direction DR1, spaced apart from each other. Here, n and m are natural numbers greater than or equal to 1.

[0059] Multiple pixel PXs are electrically connected to write scan lines GWL1-GWLn, reference scan lines GRL1-GRLn, black scan lines GBL1-GBLn, first light emission control lines EMBL1-EMBLn, second light emission control lines EML1-EMLn, and data lines DL1-DLm, respectively. For example, each of the multiple pixel PXs can be electrically connected to 3 scan lines and 2 light emission control lines. However, the number of scan lines and light emission control lines connected to each pixel PX is not limited to this and can be changed.

[0060] The scan driver 300 can be located in the non-display area DP-NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 can output write scan signals to the write scan lines GWL1 to GWLn, reference scan signals to the reference scan lines GRL1 to GRLn, and black scan signals to the black scan lines GBL1 to GBLn.

[0061] The light-emitting driver 350 can be located in the non-display area DP-NDA of the display panel DP. The light-emitting driver 350 receives a second control signal ECS from the drive controller 100. In response to the second control signal ECS, the light-emitting driver 350 can output a first light-emitting control signal to the first light-emitting control lines EMBL1 to EMBLn and a second light-emitting control signal to the second light-emitting control lines EML1 to EMLn.

[0062] Figure 7A is a circuit diagram of one pixel among the pixels shown in Figure 6. Figure 7B is a circuit diagram of a pixel according to one embodiment of the present invention. Figures 7A and 7B exemplify the equivalent circuit diagram of one pixel PXij among the multiple pixels PX shown in Figure 6. Since each of the multiple pixels PX has the same circuit structure, the explanation is for the circuit structure of pixel PXij, and specific explanations for the remaining pixels are omitted.

[0063] Referring to Figures 7A and 7B, a pixel PXij can include a light-emitting element ED and a pixel circuit PC. The light-emitting element ED is a light-emitting diode, and as an example, the light-emitting element ED may be an organic light-emitting diode including an organic light-emitting layer. The pixel circuit PC is connected to the light-emitting element ED and can control the amount of current flowing to the light-emitting element ED, and the light-emitting element ED can generate light having a predetermined brightness according to the amount of current received.

[0064] Pixel PXij can be connected to the j-th data line DLj (hereinafter referred to as the data line), the i-th write scan line GWLi (hereinafter referred to as the write scan line), the i-th reference scan line GRLi (hereinafter referred to as the reference scan line), the i-th black scan line GBLi (hereinafter referred to as the black scan line), the i-th first light emission control line EMBLi (hereinafter referred to as the first light emission control line), and the i-th second light emission control line EMLi (hereinafter referred to as the second light emission control line). The pixel circuit PC may include six transistors T1, T2, T3, T4, ET1, ET2 and three capacitors C1, C2, C3. The six transistors T1, T2, T3, T4, ET1, ET2 may include first to fourth transistors T1 to T4 and first and second light emission control transistors ET1 and ET2. The three capacitors C1, C2, and C3 may include the first to third capacitors C1, C2, and C3.

[0065] Each of the first to fourth transistors T1, T2, T3, and T4 may be an N-type transistor with an oxide semiconductor as its semiconductor layer. Each of the first and second light emission control transistors ET1 and ET2 may be a P-type transistor with amorphous silicon, LTPS (low-temperature polycrystalline silicon), and crystalline silicon as its semiconductor layer. However, this is illustrative, and in one embodiment of the present invention, the first to fourth transistors T1, T2, T3, T4 and the second light emission control transistor ET2 may be N-type, and only the first light emission control transistor ET1 may be P-type, and the present invention is not limited to any one embodiment.

[0066] The write scan signal GWi can be applied to the write scan line GWLi, the reference scan signal GRi can be applied to the reference scan line GRLi, and the black scan signal GBi can be applied to the black scan line GBLi. The first light emission control line EMBLi can be applied to the first light emission control signal EMBi, and the second light emission control line EMLi can be applied to the second light emission control signal EMi. The data signal Vd can be applied to the data line DLj.

[0067] The first power supply voltage ELVDD is applied to the first power supply line PL1, and the second power supply voltage ELVSS is applied to the second power supply line PL2. The second power supply voltage ELVSS may have a lower voltage level than the first power supply voltage ELVDD. The reference voltage VREF is applied to the reference voltage line VL1, and the initialization voltage VINT is applied to the initialization voltage line VL2.

[0068] The light-emitting element ED is connected to a pixel circuit PC and can emit light in response to a drive current provided through the pixel circuit PC. The light-emitting element ED may include a first electrode (i.e., referred to as the anode) connected to the pixel circuit PC and a second electrode (i.e., referred to as the cathode) connected to a second power supply line PL2.

[0069] Each of the six transistors T1, T2, T3, T4, ET1, and ET2 can include a source, a drain, and a gate electrode. Hereinafter, in Figures 7A and 7B, for convenience, one of the source and drain may be referred to as the first electrode, and the other as the second electrode. Alternatively, the gate electrode may be referred to as the control electrode.

[0070] The first transistor T1 operates in response to the potential of the first node N1 and is connected between the first power line PL1 and the second node N2. The first transistor T1 may include a source electrically connected to the first power line PL1, a drain connected to the second node N2, and a gate electrode connected to the first node N1. The first transistor T1 may be referred to as the driver transistor. In this embodiment, the first transistor T1 may further include a back gate electrode BGE1 connected to the second node N2. The back gate electrode BGE1 can source-sink the first transistor T1 through the second node N2, and the first transistor T1 can have a low resistance value through a source-follower compensation scheme. The first transistor T1 may be an N-type transistor. For example, the first transistor T1 may have an NMOS structure. Here, source-sinking means stabilizing (sinking / drawing in) the source potential. In other words, by connecting the back gate electrode BGE1 to the second node N2, fluctuations in the source potential of the first transistor T1 are suppressed, and the operation of the first transistor T1 is made more stable.

[0071] The second transistor T2 is connected between the data line DLj and the first node N1 and receives the write scan signal GWi. The second transistor T2 may include a source connected to the data line DLj, a drain connected to the first node N1, and a gate electrode that receives the write scan signal GWi. The gate electrode of the second transistor T2 may be connected to the write scan line GWLi. The second transistor T2 may be referred to as a switching transistor. The second transistor T2 may be an N-type transistor. For example, the second transistor T2 may have an NMOS structure.

[0072] The third transistor T3 is connected between the first node N1 and the reference voltage line VL1 and receives the reference scan signal GRi. The third transistor T3 may include a source connected to the reference voltage line VL1, a drain connected to the first node N1, and a gate electrode that receives the reference scan signal GRi. The gate electrode of the third transistor T3 may be connected to the reference scan line GRLi. The third transistor T3 may be an N-type transistor. For example, the third transistor T3 may have an NMOS structure.

[0073] The fourth transistor T4 is connected between the first electrode of the light-emitting element ED and the initialization voltage line VL2, and receives the black scan signal GBi. The fourth transistor T4 may include a source connected to the initialization voltage line VL2, a drain connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the black scan signal GBi. The gate electrode of the fourth transistor T4 may be connected to the black scan line GBLi. The fourth transistor T4 may be an N-type transistor. For example, the fourth transistor T4 may have an NMOS structure.

[0074] The first light emission control transistor ET1 is connected between the second node N2 and the first electrode of the light-emitting element ED and receives the first light emission control signal EMBi. The first light emission control transistor ET1 may include a drain connected to the second node N2, a source connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the first light emission control signal EMBi. The gate electrode of the first light emission control transistor ET1 may be connected to the first light emission control line EMBLi. The first light emission control transistor ET1 may be a P-type transistor. For example, the first light emission control transistor ET1 may have a PMOS structure.

[0075] In this embodiment, the fourth transistor T4 may further include a back gate electrode BGE4 connected to the first light emission control line EMBLi. However, the present invention is not limited thereto. As shown in Figure 7B, the back gate electrode BGE4a of the fourth transistor T4 may be connected to the gate electrode (or black scan line GBLi) of the fourth transistor T4.

[0076] The second light emission control transistor ET2 is connected between the first power supply line PL1 and the first transistor T1 and receives the second light emission control signal EMi. The second light emission control transistor ET2 may include a drain connected to the first power supply line PL1, a source connected to the source of the first transistor T1, and a gate electrode that receives the second light emission control signal EMi. The gate electrode of the second light emission control transistor ET2 may be connected to the second light emission control line EMLi. The second light emission control transistor ET2 may be a P-type transistor. For example, the second light emission control transistor ET2 may have a PMOS structure.

[0077] A first capacitor C1 is connected between a first node N1 and a second node N2, and can charge a voltage corresponding to the potential difference between the first node N1 and the second node N2. The first capacitor C1 may be referred to as a storage capacitor. A first transistor T1 can adjust the amount of light emitted by the light-emitting element ED by controlling the amount of current supplied to the light-emitting element ED according to the voltage charged in the first capacitor C1. A second capacitor C2 is connected between a first power line PL1 and a second node N2, and can charge a voltage corresponding to the potential difference between the first power line PL1 and a second node N2. The second capacitor C2 may be referred to as a hold capacitor. A third capacitor C3 may be connected between the first electrode of the light-emitting element ED and the second electrode of the light-emitting element ED (or the second power line PL2). The third capacitor C3 can charge a voltage corresponding to the potential difference between the first and second electrodes of the light-emitting element ED. The third capacitor C3 may be a parasitic capacitor formed in the light-emitting element ED.

[0078] Figure 8 is a waveform diagram showing the signal applied to the pixel shown in Figure 7A.

[0079] Referring to Figures 7A and 8, each of the first to fourth transistors T1, T2, T3, and T4 may be an N-type transistor. Each of the first to fourth transistors T1, T2, T3, and T4 can be turned on when the signal received at the gate electrode is high level, and turned off when the signal received at the gate electrode is low level. Therefore, the active intervals of the write scan signal GWi, the reference scan signal GRi, and the black scan signal GBi can be defined as high-level intervals, and the inactive intervals can be defined as low-level intervals.

[0080] Each of the first and second light emission control transistors ET1 and ET2 may be a P-type transistor. Each of the first and second light emission control transistors ET1 and ET2 can be turned on when the signal received at its gate electrode is low level, and turned off when the signal received at its gate electrode is high level. Therefore, the active intervals of the first and second light emission control signals EMBi and EMi can be defined as low-level intervals, and the inactive intervals can be defined as high-level intervals.

[0081] During the active section AP1 (hereinafter referred to as the first active section) of the reference scan signal GRi, the third transistor T3 can be turned on, and the first node N1 can be initialized to the reference voltage VREF through the turned-on third transistor T3. During the active section AP2 (hereinafter referred to as the second active section) of the black scan signal GBi, the fourth transistor T4 can be turned on, and the first electrode of the light-emitting element ED can be initialized to the initialization voltage VINT through the turned-on fourth transistor T4. As an example of the present invention, the second active section AP2 and the first active section AP1 can be superimposed on each other. The first active section AP1 can be contained within the second active section AP2. Alternatively, the duration of the second active section AP2 can be greater than the duration of the first active section AP1.

[0082] During the active section AP3 (hereinafter referred to as the third active section) of the write scan signal GWi, the second transistor T2 is turned on, and the data signal Vd can be applied to the first node N1 through the turned-on second transistor T2. Therefore, the potential of the first node N1 can be changed from the reference voltage VREF to the data signal Vd. The change in the first node N1, VREF-Vd, can be reflected to the second node N2 by the first capacitor C1. The third active section AP3 can be unsupervised with the first active section AP1. Therefore, when the second transistor T2 is turned on, the third transistor T3 may be in the turned-off state.

[0083] Subsequently, even if the potential of the second node N2 changes, the amount of change in the second node N2 is reflected in the first node N1 by the first capacitor C1, so the gate-source voltage of the first transistor T1 can be kept constant.

[0084] The first light emission control transistor ET1 can be turned off during the inactive interval NAP1 (hereinafter referred to as the first inactive interval) of the first light emission control signal EMBi. The first inactive interval NAP1 overlaps with the second active interval AP2. In particular, the first inactive interval NAP1 can be contained within the second active interval AP2. As an example of the present invention, the duration of the second active interval AP2 can be greater than the duration of the first inactive interval NAP1.

[0085] The second light emission control transistor ET2 can be turned off during the inactive interval of the second light emission control signal EMi (hereinafter referred to as the second inactive interval). The second inactive interval may include a first sub-inactive interval NAP21 and a second sub-inactive interval NAP22. The first sub-inactive interval NAP21 may partially overlap with the first and second active intervals AP1 and AP2, and the second sub-inactive interval NAP22 may partially overlap with the second and third active intervals AP2 and AP3.

[0086] During the first and second inactive sections NAP1, NAP21, and NAP22, the first or second light emission control transistors ET1 and ET2 are turned off, so no drive current flows to the light-emitting element ED. When the first and second light emission control signals EMBi and EMi are all switched to the low state, the first and second light emission control transistors ET1 and ET2 are turned on, and a drive current can flow to the light-emitting element ED.

[0087] Figure 9 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0088] Referring to Figure 9, the display panel DP may include a substrate BS, a circuit element layer DP-CL, a display element layer DP-ED, and a thin film encapsulation layer TFE.

[0089] The display panel DP may include multiple insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. Insulating layers, semiconductor layers, and conductive layers are formed by methods such as coating and vapor deposition. Subsequently, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography and etching. Semiconductor patterns, conductive patterns, signal lines, etc., included in the circuit element layer DP-CL and the display element layer DP-ED can be formed using this method.

[0090] The substrate BS may include a glass substrate, a sapphire substrate, a plastic film, or a multilayer / inorganic film. The substrate BS may have a multilayer or monolayer structure. For example, the substrate BS may have a laminated structure of multiple plastic films bonded together with adhesive, or a laminated structure of a glass substrate and a plastic film bonded together with adhesive. The substrate BS may be flexible. For example, the substrate BS may contain polyimide. However, this is an illustrative description, and the substrate BS may be provided in a rigid state and is not limited to any one embodiment.

[0091] The circuit element layer DP-CL may include a pixel circuit, a buffer layer BFL, and a plurality of insulating layers GI1, GI2, ILD1, ILD2, VIA1, VIA2.

[0092] Referring to Figure 9, the circuit element layer DP-CL can be arranged on the substrate BS. For ease of explanation, Figure 9 illustrates two transistors TR1 and TR2, two capacitors, and multiple connecting electrodes in a pixel circuit, and shows multiple sequentially stacked insulating layers GI1, GI2, ILD1, ILD2, VIA1, and VIA2. Of the two transistors, the first transistor TR1 can correspond to the first light emission control transistor ET1 shown in Figure 7A and may include a first semiconductor pattern ACT and a first gate electrode GE1. The second transistor TR2 can correspond to the first transistor T1 shown in Figure 7A and may include a second semiconductor pattern OACT, a second gate electrode GE2, and a back gate electrode BGE1.

[0093] The buffer layer BFL can be placed on the substrate BS. The buffer layer BFL can improve the bonding strength between the substrate BS and the first semiconductor pattern ACT. The buffer layer BFL may include a silicon oxide layer and / or a silicon nitride layer. If the buffer layer BFL includes a silicon oxide layer and a silicon nitride layer, the two layers can be stacked alternately.

[0094] A buffer layer BFL can have a first semiconductor pattern ACT placed on it. In this embodiment, the first semiconductor pattern ACT can include a crystalline semiconductor material. For example, the first semiconductor pattern ACT can include a polycrystalline semiconductor material such as polycrystalline silicon. The first semiconductor pattern ACT can include a plurality of regions divided according to conductivity. The first semiconductor pattern ACT can include a source region, a channel region, and a drain region. The channel region may be a region having relatively lower electrical conductivity compared to the source region and the drain region. The source region and the drain region can be arranged separated from each other via the channel region.

[0095] The first insulating layer GI1 can be placed on the buffer layer BFL. The first insulating layer GI1 can be superimposed on multiple pixels PX (see Figure 6) in common and cover the first semiconductor pattern ACT. The first insulating layer GI1 is an inorganic layer and / or an organic layer and can have a single-layer or multilayer structure. The first insulating layer GI1 may contain silicon oxide.

[0096] A first gate electrode GE1 can be disposed on a first insulating layer GI1. A second insulating layer GI2 covering the first gate electrode GE1 can be disposed on the first insulating layer GI1. The second insulating layer GI2 is an inorganic layer and / or an organic layer, and can have a single-layer or multilayer structure. The second insulating layer GI2 may contain silicon nitride.

[0097] A back gate electrode BGE1 can be placed on the second insulating layer GI2. A third insulating layer ILD1 covering the back gate electrode BGE1 can be placed on the second insulating layer GI2. The third insulating layer ILD1 is an inorganic layer and / or an organic layer and can have a single-layer or multilayer structure. The third insulating layer ILD1 may contain the same material as the second insulating layer GI2. The third insulating layer ILD1 may contain silicon nitride.

[0098] A second semiconductor pattern OACT can be arranged on the third insulating layer ILD1. In this embodiment, the second semiconductor pattern OACT may include an oxide semiconductor. For example, the second semiconductor pattern OACT may include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or mixtures of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with their oxides.

[0099] The second semiconductor pattern OACT can be superimposed on the back gate electrode BGE1 on a planar surface. In a different example of the present invention, an additional metal electrode can be further placed between the second semiconductor pattern OACT and the back gate electrode BGE1.

[0100] An insulating pattern ILP covering the channel region of the second semiconductor pattern OACT can be placed on the third insulating layer ILD1. A second gate electrode GE2 can be placed on the insulating pattern ILP. However, the present invention is not limited to this embodiment. In a different example of the present invention, an insulating layer can be placed over the entire surface of the upper surface of the third insulating layer ILD1 and the second semiconductor pattern OACT, and the second gate electrode GE2 can be placed on the insulating layer. In this case, contact holes can be formed in the insulating layer to expose the source region and drain region of the second semiconductor pattern OACT.

[0101] A fourth insulating layer ILD2 can be disposed on the third insulating layer ILD1, covering the second semiconductor pattern OACT and the second gate electrode GE2. The fourth insulating layer ILD2 is an inorganic and / or organic layer and can have a single-layer or multilayer structure. The fourth insulating layer ILD2 may contain at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0102] First connecting electrodes CNE11, CNE12, CNE13, and CNE14 can be placed on the fourth insulating layer ILD2. The first connecting electrodes CNE11 and CNE12 can be connected to the first semiconductor pattern ACT through contact holes penetrating the first to fourth insulating layers GI1, GI2, ILD1, and ILD2. The first connecting electrodes CNE13 and CNE14 can be connected to the second semiconductor pattern OACT through contact holes penetrating the fourth insulating layer ILD2.

[0103] A fifth insulating layer VIA1 can be placed on the fourth insulating layer ILD2, covering the first connecting electrodes CNE11, CNE12, CNE13, and CNE14. The fifth insulating layer VIA1 is an inorganic and / or organic layer and can have a single-layer or multilayer structure. The fifth insulating layer VIA1 may contain at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0104] Second connecting electrodes CNE21 and CNE22 can be placed on the fifth insulating layer VIA1. The second connecting electrode CNE21 can be connected to the first connecting electrode CNE11 through a contact hole that penetrates the fifth insulating layer VIA1. The second connecting electrode CNE22 can face the first connecting electrode CNE14 via the fifth insulating layer VIA1.

[0105] A sixth insulating layer VIA2 covering the second connecting electrodes CNE21 and CNE22 can be disposed on the fifth insulating layer VIA1. The sixth insulating layer VIA2 is an inorganic and / or organic layer and can have a single-layer or multilayer structure. The sixth insulating layer VIA2 may contain at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0106] The display element layer DP-ED can be arranged on the circuit element layer DP-CL. The display element layer DP-ED may include a pixel definition film PDL and a light-emitting element ED.

[0107] The pixel definition film PDL can be placed on the sixth insulating layer VIA2 of the circuit element layer DP-CL. The pixel definition film PDL can define (or have) an emission aperture EOP. The emission aperture EOP can correspond to the first electrode AE ​​(i.e., anode) of the light-emitting element ED, and the pixel definition film PDL can expose at least a portion of the first electrode AE ​​of the light-emitting element ED through the emission aperture EOP.

[0108] The pixel definition film (PDL) can contain inorganic insulating materials. For example, the pixel definition film (PDL) can contain silicon nitride.

[0109] The light-emitting element ED may include a first electrode AE, a light-emitting layer EL, and a second electrode CE (i.e., a cathode).

[0110] The first electrode AE ​​can be placed on the sixth insulating layer VIA2 of the circuit element layer DP-CL. The first electrode AE ​​may be a transparent electrode, a semi-transparent electrode, or a reflective electrode. The first electrode AE ​​may be a single layer or a multilayer structure. The first electrode AE ​​may include multiple layers containing ITO and Ag. For example, the first electrode AE ​​may include a layer containing ITO (hereinafter referred to as the lower ITO layer), a layer containing Ag placed on the lower ITO layer (hereinafter referred to as the Ag layer), and a layer containing ITO placed on the Ag layer (hereinafter referred to as the upper ITO layer). However, it is not limited thereto, and the first electrode AE ​​may be provided as a single layer.

[0111] The light-emitting layer EL can be placed on the first electrode AE. The light-emitting layer EL may also be referred to as the 'organic layer' or 'intermediate layer'. The light-emitting layer EL can cover a portion of the upper surface of the pixel definition film PDL.

[0112] The second electrode CE can be placed on the light-emitting layer EL. The second electrode CE can cover the light-emitting layer EL. The second electrode CE can be commonly placed on pixels PX (see Figure 6). That is, the second electrode CE can be commonly placed on the light-emitting layer EL of pixels PX.

[0113] The thin-film encapsulation layer TFE can be placed on the light-emitting element ED. The thin-film encapsulation layer TFE may include sequentially stacked inorganic layers, organic layers, and inorganic layers. The inorganic layers contain inorganic materials and can protect the pixels from moisture / oxygen. The organic layers contain organic materials and can protect the pixels PX from foreign materials such as dust particles.

[0114] Figures 10A to 10G are plan views showing the manufacturing process of a display panel according to one embodiment of the present invention. Figure 11 is a cross-sectional view taken along the cutting line I-I' shown in Figure 10E.

[0115] Figures 10A to 10G illustrate two circuit regions (i.e., the first and second circuit regions PCA1 and PCA2) in which two pixel circuits (i.e., referred to as the first and second pixel circuits) are respectively arranged within the multiple pixel circuits PC (see Figure 7) provided in the display panel DP. The first and second circuit regions PCA1 and PCA2 are adjacent to each other in the first direction DR1.

[0116] Referring to Figure 10A, a first semiconductor pattern layer ACTL can be arranged on the buffer layer BFL shown in Figure 9. The first semiconductor pattern layer ACTL can include a plurality of 1-1 to 1-3 semiconductor patterns ACT1, ACT2, and ACT3 that are spaced apart from each other. In this embodiment, the 1-1 to 1-3 semiconductor patterns ACT1, ACT2, and ACT3 are spaced apart from each other in a first direction DR1. The 1-1 semiconductor pattern ACT1 is arranged in the first circuit region PCA1, and the 1-2 semiconductor pattern ACT2 is arranged in the second circuit region PCA2. The 1-3 semiconductor pattern ACT3 is superimposed on the first and second circuit regions PCA1 and PCA2, and can have a shape that is symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2. The 1-1 and 1-2 semiconductor patterns ACT1 and ACT2 can be symmetrical with respect to the said virtual axis.

[0117] Figure 10A illustrates the shapes of the first to third semiconductor patterns ACT1, ACT2, and ACT3 as an example. The shapes of the first to third semiconductor patterns ACT1, ACT2, and ACT3 can be varied in various ways according to the pixel circuit design and are not limited to any one embodiment.

[0118] In this embodiment, the first semiconductor pattern layer ACTL may include a crystalline semiconductor material. For example, the first semiconductor pattern layer ACTL may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0119] Referring to Figures 10A and 10B, the first semiconductor pattern layer ACTL is covered by the first insulating layer GI1 shown in Figure 9, and the first gate electrode layer GATL1 can be placed on the first insulating layer GI1. The first gate electrode layer GATL1 can include a plurality of patterns GAT1a, GAT1b, and GAT1c. The first-1 gate electrode pattern GAT1a and the first-2 gate electrode pattern GAT1b can be separated from each other in a first direction DR1. The first-1 gate electrode pattern GAT1a and the first-2 gate electrode pattern GAT1b can be symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2. The first-3 gate electrode pattern GAT1c can have a bar shape extended along the first direction DR1. The first-3 gate electrode pattern GAT1c can have a shape symmetrical with respect to the virtual axis.

[0120] The first-first gate electrode pattern GAT1a and the first-second gate electrode pattern GAT1b can be superimposed on the first-first semiconductor pattern ACT1 and the first-second semiconductor pattern ACT2, respectively, on a plane. The first-first gate electrode pattern GAT1a can form the first electrode of the first capacitor C1 (see Figure 7A) in the first circuit region PCA1, and the first-second gate electrode pattern GAT1b can form the first electrode of the first capacitor C1 in the second circuit region PCA2.

[0121] The first to third gate electrode patterns GAT1c are superimposed on the first semiconductor pattern ACT1 and the first to second semiconductor pattern ACT2 on a plane. The first to third gate electrode patterns GAT1c can form the first electrode of the second capacitor C2 (see Figure 7A) in the first circuit region PCA1 and the second circuit region PCA2, respectively.

[0122] The first gate electrode layer GATL1 may further include first and second light emission control lines EMBL and EML. The first and second light emission control lines EMBL and EML may extend in the first direction DR1 and be separated from each other in the second direction DR2. The first light emission control line EMBL is superimposed on the first-1 semiconductor pattern ACT1 and the first-2 semiconductor pattern ACT2 on a plane. The first light emission control line EMBL superimposed on the first-1 semiconductor pattern ACT1 in the first circuit region PCA1 can be used as the gate electrode of the first light emission control transistor ET1 (see Figure 7A) included in the first pixel circuit. The first light emission control line EMBL superimposed on the first-2 semiconductor pattern ACT2 in the second circuit region PCA2 can be used as the gate electrode of the first light emission control transistor ET1 included in the second pixel circuit.

[0123] The second light emission control line EML is superimposed on the first-third semiconductor pattern ACT3 on a plane. The second light emission control line EML superimposed on the first-third semiconductor pattern ACT3 in the first circuit region PCA1 can be used as the gate electrode of the second light emission control transistor ET2 (see Figure 7A) included in the first pixel circuit. The second light emission control line EML superimposed on the first-third semiconductor pattern ACT3 in the second circuit region PCA2 can be used as the gate electrode of the second light emission control transistor ET2 included in the second pixel circuit.

[0124] Referring to Figures 10B and 10C, the first gate electrode layer GATL1 is covered by the second insulating layer GI2 (see Figure 9), and the second gate electrode layer GATL2 can be placed on the second insulating layer GI2. The second gate electrode layer GATL2 can contain multiple patterns GAT2a, GAT2b. The second-first gate electrode pattern GAT2a and the second-second gate electrode pattern GAT2b can be separated from each other in the first direction DR1. The second-first gate electrode pattern GAT2a and the second-second gate electrode pattern GAT2b can be symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2.

[0125] The second-first gate electrode pattern GAT2a is superimposed on the first-first gate electrode pattern GAT1a and the first-third gate electrode pattern GAT1c in the first circuit region PCA1, and the second-second gate electrode pattern GAT2b is superimposed on the first-second gate electrode pattern GAT1b and the first-third gate electrode pattern GAT1c in the second circuit region PCA2. The second-first gate electrode pattern GAT2a forms the second electrode of the first capacitor C1 (see Figure 7A) included in the first pixel circuit in the first circuit region PCA1 (or the back gate electrode BGE1 of the first transistor). The second-second gate electrode pattern GAT2b forms the second electrode of the first capacitor C1 included in the second pixel circuit in the second circuit region PCA2 (or the back gate electrode BGE1 of the first transistor).

[0126] The second gate electrode layer GATL2 further includes a reference voltage line VL1 extended in the first direction DR1. The reference voltage line VL1 can be connected to the third transistor T3 (see Figure 7A) in the first and second circuit regions PCA1 and PCA2, respectively.

[0127] Referring to Figures 10C and 10D, the second gate electrode layer GATL2 is covered by a third insulating layer ILD1 (see Figure 9), and a second semiconductor pattern layer OACTL can be placed on the third insulating layer ILD1. In this embodiment, the second semiconductor pattern layer OACTL can include an oxide semiconductor. For example, the second semiconductor pattern layer OACTL can include metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or mixtures of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with their oxides.

[0128] The second semiconductor pattern layer OACTL may contain a plurality of 2-1 to 2-5 semiconductor patterns OACT1a, OACT1b, OACT2, OACT3a, and OACT3b that are spaced apart from each other. The 2-1 and 2-2 semiconductor patterns OACT1a and OACT1b are spaced apart from each other on the first direction DR1. The 2-1 semiconductor pattern OACT1a is located in the first circuit region PCA1, and the 2-2 semiconductor pattern OACT1b is located in the second circuit region PCA2. The 2-1 and 2-2 semiconductor patterns OACT1a and OACT1b are symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2.

[0129] The second-first semiconductor pattern OACT1a is superimposed on the second-first gate electrode pattern GAT2a in the first circuit region PCA1 on a planar surface, and the second-second semiconductor pattern OACT1b is superimposed on the second-second gate electrode pattern GAT2b in the second circuit region PCA2 on a planar surface.

[0130] The second-third semiconductor pattern OACT2 is superimposed on the first and second circuit regions PCA1 and PCA2 on a plane and has a shape that is symmetrical with respect to the virtual axis. The second-fourth and second-fifth semiconductor patterns OACT3a and OACT3b are separated from each other in the first direction DR1. The second-fourth and second-fifth semiconductor patterns OACT3a and OACT3b are arranged in the first and second circuit regions PCA1 and PCA2, respectively. The second-fourth and second-fifth semiconductor patterns OACT3a and OACT3b are symmetrical with respect to the virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2.

[0131] Referring to Figures 10D and 10E, the second semiconductor pattern layer OACTL is partially covered by an insulating pattern ILP (see Figure 9), and the third gate electrode layer GATL3 can be placed on the insulating pattern ILP.

[0132] The third gate electrode layer GATL3 can contain multiple patterns GAT3a, GAT3b, GAT3c, and GAT3d. The third-first gate electrode pattern GAT3a and the third-second gate electrode pattern GAT3b can be separated from each other in the first direction DR1. The third-first gate electrode pattern GAT3a and the third-second gate electrode pattern GAT3b can be symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2. The third-first gate electrode pattern GAT3a is superimposed on the second-first semiconductor pattern OACT1a in the first circuit region PCA1, and the third-second gate electrode pattern GAT3b is superimposed on the second-second semiconductor pattern OACT1b in the second circuit region PCA2. The third-first gate electrode pattern GAT3a forms the gate electrode of the first transistor T1 (see Figure 7A) included in the first pixel circuit, and the third-second gate electrode pattern GAT3b forms the gate electrode of the first transistor T1 included in the second pixel circuit.

[0133] The third-third gate electrode pattern GAT3c and the third-fourth gate electrode pattern GAT3d can be separated from each other in the first direction DR1. The third-third gate electrode pattern GAT3c and the third-fourth gate electrode pattern GAT3d can be symmetrical with respect to a virtual axis located at the boundary between the first and second circuit regions PCA1 and PCA2. The third-third gate electrode pattern GAT3c is superimposed on the second-third semiconductor pattern OACT2 in the first circuit region PCA1 on a plane, and the third-fourth gate electrode pattern GAT3d is superimposed on the second-third semiconductor pattern OACT2 in the second circuit region PCA2 on a plane. The third-third gate electrode pattern GAT3c forms the gate electrode of the second transistor T2 (see Figure 7A) included in the first pixel circuit, and the third-fourth gate electrode pattern GAT3d forms the gate electrode of the second transistor T2 included in the second pixel circuit.

[0134] The third gate electrode layer GATL3 may further include a reference scanline GRL and a black scanline GBL. The reference scanline GRL and black scanline GBL may extend in the first direction DR1 and be separated from patterns GAT3a, GAT3b, GAT3c, and GAT3d in the second direction DR2.

[0135] The reference scan line GRL superimposed on the second-third semiconductor pattern OACT2 in the first and second circuit regions PCA1 and PCA2, respectively. The reference scan line GRL forms the gate electrode of the third transistor T3 (see Figure 7A) included in the first pixel circuit in the first circuit region PCA1, and forms the gate electrode of the third transistor T3 included in the second pixel circuit in the second circuit region PCA2.

[0136] The black scanline GBL is superimposed on the second-fourth semiconductor pattern OACT3a in the first circuit region PCA1, and on the second-fifth semiconductor pattern OACT3b in the second circuit region PCA2. The black scanline GBL forms the gate electrode of the fourth transistor T4 (see Figure 7A) included in the first pixel circuit in the first circuit region PCA1, and forms the gate electrode of the fourth transistor T4 included in the second pixel circuit in the second circuit region PCA2.

[0137] Referring to Figures 10E and 11, the black scan line GBL can be superimposed on the first light emission control line EMBL on a plane. Therefore, the width of the first and second circuit regions PCA1 and PCA2 in the second direction DR2 can be reduced to about the width of the superposition of the black scan line GBL and the first light emission control line EMBL. In this way, when the black scan line GBL and the first light emission control line EMBL are superimposed, the space required to form the pixel circuit can be reduced.

[0138] The first light emission control line EMBL is placed on the first insulating layer GI1, and the black scan line GBL is placed on the insulating pattern ILP. Cross-sectionally, the second-fourth and second-fifth semiconductor patterns OACT3a and OACT3b can be placed between the black scan line GBL and the first light emission control line EMBL. In this case, the first light emission control line EMBL can perform the role of the back gate electrode BGE4 (see Figure 7A) of the fourth transistor T4 (see Figure 7A).

[0139] Referring to Figures 10E and 10F, the third gate electrode layer GATL3 is covered by the fourth insulating layer ILD2 (see Figure 9), and the first data electrode layer SDL1 can be placed on the fourth insulating layer ILD2.

[0140] The first data electrode layer SDL1 may include a plurality of connecting electrodes CNE11, CNE12, CNE13, and CNE14. The plurality of connecting electrodes CNE11, CNE12, CNE13, and CNE14 may be electrically connected to a pattern or line located below. Each of the plurality of connecting electrodes CNE11, CNE12, CNE13, and CNE14 may have an Irish shape.

[0141] The first data electrode layer SDL1 may further include a write scan line GWL and an initialization voltage line VL2. The write scan line GWL and the initialization voltage line VL2 extend in the first direction DR1 and may be spaced apart from a plurality of connecting electrodes CNE11, CNE12, CNE13, and CNE14. The write scan line GWL is connected to the third-third gate electrode pattern GAT3c in the first circuit region PCA1 and to the third-fourth gate electrode pattern GAT3d in the second circuit region PCA2. The initialization voltage line VL2 is connected to the second-fourth semiconductor pattern OACT3a in the first circuit region PCA1 and to the second-fifth semiconductor pattern OACT3b in the second circuit region PCA2.

[0142] The first data electrode layer SDL1 may further include a horizontal coupling line BRSH. The horizontal coupling line BRSH may be a line that connects to the vertical coupling line BRSV, as shown in Figure 10G. The horizontal coupling line BRSH may be a line that electrically connects the vertical coupling line BRSV to its corresponding data line.

[0143] Referring to Figures 10F and 10G, the first data electrode layer SDL1 is covered by the fifth insulating layer VIA1 (see Figure 9), and the second data electrode layer SDL2 can be placed on the fifth insulating layer VIA1.

[0144] The second data electrode layer SDL2 may include first and second data lines DL1 and DL2, a voltage coupling line VCL, and a vertical coupling line BRSV. The first and second data lines DL1 and DL2, the voltage coupling line VCL, and the vertical coupling line BRSV may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1.

[0145] The first data line DL1 is connected to the second transistor T2 (see Figure 7A) included in the first pixel circuit, and the second data line DL2 is connected to the second transistor T2 included in the second pixel circuit. The voltage coupling line VCL can be electrically connected to the reference voltage line VL1 or the initialization voltage line VL2. The vertical coupling line BRSV can be electrically connected to the horizontal coupling line BRSH.

[0146] Figures 12A and 12B are plan views showing the manufacturing process of a display panel according to one embodiment of the present invention. Figure 13 is a cross-sectional view taken along the cutting line II-II' shown in Figure 12B. For components shown in Figures 12A and 12B that are the same as those shown in Figures 10C and 10E, the same reference numerals are used, and specific descriptions thereof are omitted.

[0147] Referring to Figure 12A, the second gate electrode layer GATL2a further includes a shielding line SHDL extended in the first direction DR1. The shielding line SHDL can be superimposed on the first light emission control line EMBL on a plane.

[0148] Referring to Figure 12B, the third gate electrode layer GATL3a may further include a black scanline GBL extended in the first direction DR1. The black scanline GBL superimposed planarly with the second-fourth semiconductor pattern OACT3a in the first circuit region PCA1 and with the second-fifth semiconductor pattern OACT3b in the second circuit region PCA2. The black scanline GBL forms the gate electrode of the fourth transistor T4 (see Figure 7A) included in the first pixel circuit in the first circuit region PCA1, and forms the gate electrode of the fourth transistor T4 included in the second pixel circuit in the second circuit region PCA2.

[0149] The black scanline GBL can be superimposed on a plane with the first light emission control line EMBL and the shielding line SHDL.

[0150] As shown in Figure 13, a shielding line SHDL can be further placed between the first light emission control line EMBL and the black scan line GBL. The shielding line SHDL can be placed on the second insulating layer GI2. The shielding line SHDL can mitigate signal interference between the first light emission control line EMBL and the black scan line GBL.

[0151] In cross-section, the second-fourth and second-fifth semiconductor patterns OACT3a and OACT3b can be arranged between the black scan line GBL and the shielding line SHDL. In this case, the shielding line SHDL can perform the role of the back gate electrode BGE4a (see Figure 7B) of the fourth transistor T4 (see Figure 7B). As an example of the present invention, the shielding line SHDL can be electrically connected to the black scan line GBL. The black scan signal GBi can be applied to the back gate electrode BGE4a of the fourth transistor T4 in the same way as to the gate electrode of the fourth transistor T4.

[0152] Figures 12A to 13 illustrate embodiments in which the shielding line SHDL is included in the second gate electrode layer GATL2a, but the present invention is not limited to this embodiment. Alternatively, an additional metal layer can be further arranged between the second gate electrode layer GATL2a and the third gate electrode layer GATL3a to form the shielding line SHDL.

[0153] Figure 14A is a circuit diagram of a pixel according to one embodiment of the present invention, and Figure 14B is a waveform diagram showing the signal applied to the pixel shown in Figure 14A. Components shown in Figures 14A and 14B that are identical to those shown in Figures 7A and 8D are given the same reference numerals, and their specific descriptions are omitted.

[0154] Referring to Figure 14A, pixel PXij can be connected to the data line DLj, the write scan line GWLi, the reference scan line GRLi, the first light emission control line EMBLi, and the second light emission control line EMLi.

[0155] A pixel PXij may include a light-emitting element ED and a pixel circuit PC. The pixel circuit PC includes first to fourth transistors T1, T2, T3, T4a, and first and second light-emitting control transistors ET1, ET2. As an example of the present invention, the first to fourth transistors T1, T2, T3, T4a may be N-type, and the first and second light-emitting control transistors ET1, ET2 may be P-type.

[0156] The fourth transistor T4a is connected between the first electrode of the light-emitting element ED and the initialization voltage line VL2, and receives the first light emission control signal EMBi as a shared control signal. The fourth transistor T4a may include a source connected to the initialization voltage line VL2, a drain connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the first light emission control signal EMBi as a shared control signal. The gate electrode of the fourth transistor T4a may be connected to the first light emission control line EMBLi.

[0157] The first light emission control transistor ET1 is connected between the second node N2 and the first electrode of the light-emitting element ED, and receives the first light emission control signal EMBi as a shared control signal. The first light emission control transistor ET1 may include a drain connected to the second node N2, a source connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the first light emission control signal EMBi as a shared control signal. The gate electrode of the first light emission control transistor ET1 may be connected to the first light emission control line EMBLi.

[0158] The fourth transistor T4a is an N-type transistor, and the first light emission control transistor ET1 may be a P-type transistor. The gate electrode of the fourth transistor T4a and the gate electrode of the first light emission control transistor ET1 can be commonly connected to the first light emission control line EMBLi.

[0159] Referring to Figure 14B, the active section of the first light emission control signal EMBi can be defined as a low-level section, and the inactive section NAP1 can be defined as a high-level section. During the inactive section NAP1 of the first light emission control signal EMBi, the first light emission control transistor ET1 can be turned off and the fourth transistor T4a can be turned on. That is, the first light emission control transistor ET1 and the fourth transistor T4a are turned on alternately.

[0160] In this way, by having the fourth transistor T4 and the first light emission control transistor ET1 share one line at each pixel PXij, the number of lines required to supply a signal to each pixel PXij can be reduced.

[0161] Figure 15A is a circuit diagram of a pixel according to one embodiment of the present invention, and Figure 15B is a waveform diagram showing the signal applied to the pixel shown in Figure 15A.

[0162] Referring to Figure 15A, pixel PXij can be connected to the data line DLj, the write scan line GWLi, the reference scan line GRLi, the black scan line GBLj, and the second light emission control line EMLi.

[0163] A pixel PXij may include a light-emitting element ED and a pixel circuit PC. The pixel circuit PC includes first to fourth transistors T1, T2, T3, T4, and first and second light-emitting control transistors ET1a, ET2. As an example of the present invention, the first to fourth transistors T1, T2, T3, T4 may be N-type, and the first and second light-emitting control transistors ET1a, ET2 may be P-type.

[0164] The fourth transistor T4 is connected between the first electrode of the light-emitting element ED and the initialization voltage line VL2, and receives the black scan signal GBi as a shared control signal. The fourth transistor T4 may include a source connected to the initialization voltage line VL2, a drain connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the black scan signal GBi as a shared control signal. The gate electrode of the fourth transistor T4 may be connected to the black scan line GBLi.

[0165] The first light-emitting control transistor ET1a is connected between the second node N2 and the first electrode of the light-emitting element ED, and receives the black scan signal GBi as a shared control signal. The first light-emitting control transistor ET1a may include a drain connected to the second node N2, a source connected to the first electrode of the light-emitting element ED, and a gate electrode that receives the black scan signal GBi as a shared control signal. The gate electrode of the first light-emitting control transistor ET1a may be connected to the black scan line GBLi.

[0166] The fourth transistor T4 is an N-type transistor, and the first light-emitting control transistor ET1a may be a P-type transistor. The gate electrodes of the fourth transistor T4 and the first light-emitting control transistor ET1a can be commonly connected to the black scanline GBLi.

[0167] Referring to Figure 15B, the active section AP2 of the black scan signal GBi can be defined as a high-level section, and the inactive section can be defined as a low-level section. During the active section AP2 of the black scan signal GBi, the fourth transistor T4 can be turned on and the first light emission control transistor ET1a can be turned off. That is, the first light emission control transistor ET1a and the fourth transistor T4 are turned on alternately.

[0168] In this way, by having the fourth transistor T4 and the first light emission control transistor ET1a share one line at each pixel PXij, the number of lines required to supply a signal to each pixel PXij can be reduced.

[0169] Figures 16A and 16B are plan views showing the manufacturing process of a display panel according to one embodiment of the present invention. Figure 17 is a cross-sectional view taken along the cutting line III-III' shown in Figure 16B. For components shown in Figures 16A and 16B that are the same as those shown in Figures 10B and 10E, the same reference numerals are used, and specific explanations are omitted.

[0170] Referring to Figure 16A, the first gate electrode layer GATL1 can include multiple patterns GAT1a, GAT1b, GAT1c, and first and second light emission control lines EMBL and EML. The first and second light emission control lines EMBL and EML can be extended in the first direction DR1 and separated from each other in the second direction DR2. In the first circuit region PCA1, a portion of the first light emission control line EMBL can be used as the gate electrode of the first light emission control transistor ET1 (see Figure 7A) included in the first pixel circuit. In the second circuit region PCA2, a portion of the first light emission control line EMBL can be used as the gate electrode of the first light emission control transistor ET1 included in the second pixel circuit.

[0171] Referring to Figure 16B, the third gate electrode layer GATL3a may include multiple patterns GAT3a, GAT3b, GAT3c, GAT3d, a reference scan line GRL, and a connecting line CL. The reference scan line GRL and the connecting line CL can be extended in the first direction DR1 and separated from the patterns GAT3a, GAT3b, GAT3c, GAT3d in the second direction DR2. In the first circuit region PCA1, a portion of the connecting line CL is used as the gate electrode of the fourth transistor T4 (see Figure 7A) included in the first pixel circuit, and in the second circuit region PCA2, a portion of the connecting line CL is used as the gate electrode of the fourth transistor T4 included in the second pixel circuit.

[0172] Referring to Figures 16B and 17, the connecting line CL can be superimposed on the first light emission control line EMBL on a plane. The connecting line CL can be connected to the first light emission control line EMBL through the contact hole CNT1.

[0173] The first light emission control line EMBL is located on the first insulating layer GI1 and covered by the second insulating layer GI2. The connecting line CL is located on the third insulating layer ILD1 and is connected to the first light emission control line EMBL through a contact hole CNT1 formed through the second and third insulating layers GI2 and ILD1. Thus, the first light emission control line EMBL and the connecting line CL can be electrically connected. In this case, the first light emission control line EMBL can perform the role of the back gate electrode BGE4 (see Figure 7A) of the fourth transistor T4 (see Figure 7A).

[0174] Thus, when the fourth transistor T4 and the first light emission control transistor ET1a share one line in each pixel PXij, the space required to form the pixel circuit can be reduced compared to a structure in which the fourth transistor T4 and the first light emission control transistor ET1a are each connected to independent lines.

[0175] Although the invention has been described above with reference to preferred embodiments, a person skilled in the art or with ordinary knowledge of the art will understand that the invention can be modified and altered in various ways without departing from the spirit and scope of the invention as described in the claims below.

[0176] Therefore, the technical scope of the present invention is not limited to what is described in the detailed description of the specification, but must be determined by the claims. [Explanation of symbols]

[0177] ACTL First Semiconductor Pattern Layer DL1~DLm Dataline DP display panel ED light-emitting element EMBL Light Emission Control Line ET1, ET2 Light emission control transistors EMBL1~EMBLn First Light Emission Control Line EML1~EMLn Second Light Emission Control Line GBL1~GBLn Black Scanline GRL1~GRLn Reference Scanline GWL1~GWLn Write Scanline GATL1, 2, 3 gate electrode layers PCA1, PCA2 circuit area PX pixels OACTL Second Semiconductor Pattern Layer

Claims

1. Includes a display panel containing pixels, The aforementioned pixel is A light-emitting element including first and second electrodes, A first transistor operates in response to the potential of the first node and is connected between the first power line and the second node, A second transistor is connected between the data line and the first node and receives a write scan signal, A third transistor is connected between the first node and the reference voltage line and receives a reference scan signal, A first light-emitting control transistor is connected between the second node and the first electrode of the light-emitting element and receives a first light-emitting control signal, The light-emitting element includes a fourth transistor connected between the first electrode and the initialization voltage line, which receives a black scan signal, The inactive interval of the first light emission control signal is included within the active interval of the black scan signal. The first light emission control line to which the first light emission control signal is applied is a display device that superimposes on a plane the black scan line to which the black scan signal is applied.

2. The aforementioned fourth transistor is A source connected to the initialization voltage line, A drain connected to the first electrode of the light-emitting element, The display device according to claim 1, further comprising a gate electrode connected to the black scanline.

3. The aforementioned fourth transistor is The display device according to claim 2, further comprising a back gate electrode connected to the first light emission control line.

4. The aforementioned fourth transistor is The display device according to claim 2, further comprising a back gate electrode electrically connected to the gate electrode and arranged on a different layer from the gate electrode.

5. The aforementioned pixel is The display device according to claim 4, further comprising a shielding line that superimposes on the first light emission control line and the black scan line in a plane and is positioned between the first light emission control line and the black scan line in a cross-section.

6. The display device according to claim 5, wherein the back gate electrode of the fourth transistor is extended from the shielding line.

7. The display device according to claim 1, wherein the first to fourth transistors are N-type transistors, and the first light-emitting control transistor is a P-type transistor.

8. The black scan signal has a high level during the active interval. The display device according to claim 7, wherein the first light emission control signal has a high level during the inactive interval.

9. The aforementioned pixel is The system further includes a second light-emitting control transistor connected between the first power line and the first transistor, which receives a second light-emitting control signal. The display device according to claim 7, wherein the second light-emitting control transistor is a P-type transistor.

10. The aforementioned pixel is A first capacitor connected between the first node and the second node, The display device according to claim 9, further comprising a second capacitor connected between the second node and the first power line.

11. The first transistor is, A source connected to the second light-emitting control transistor, A drain connected to the aforementioned second node, A gate electrode connected to the first node, The display device according to claim 10, further comprising a back gate electrode connected to the second node.

12. The second electrode of the light-emitting element is connected to the second power supply line. The aforementioned pixel is The display device according to claim 10, further comprising a third capacitor connected between the first electrode and the second electrode of the light-emitting element.

13. Includes a display panel containing pixels, The aforementioned pixel is A light-emitting element including first and second electrodes, A first transistor operates in response to the potential of the first node and is connected between the first power line and the second node, A second transistor is connected between the data line and the first node and receives a write scan signal, A third transistor is connected between the first node and the reference voltage line and receives a reference scan signal, A first light-emitting control transistor is connected between the second node and the first electrode of the light-emitting element and receives a shared control signal, The light-emitting element includes a fourth transistor connected between the first electrode and the initialization voltage line, which receives the shared control signal, A display device wherein the first and fourth transistors are N-type transistors, and the first light-emitting control transistor is a P-type transistor.

14. The first light-emitting control transistor is The source connected to the aforementioned second node, A drain connected to the first electrode of the light-emitting element, A gate electrode connected to a first light emission control line that receives a first light emission control signal as the shared control signal, The aforementioned fourth transistor is A source connected to the initialization voltage line, A drain connected to the first electrode of the light-emitting element, The display device according to claim 13, further comprising a gate electrode connected to the first light emission control line.

15. The aforementioned pixel is The display device according to claim 14, further comprising a connecting line extending from the gate electrode of the fourth transistor and electrically connected to the first light emission control line.

16. The display device according to claim 15, wherein the connecting line extends parallel to the first light emission control line and overlaps with the first light emission control line on a plane.

17. The aforementioned fourth transistor is The display device according to claim 14, further comprising a back gate electrode electrically connected to the gate electrode of the fourth transistor and disposed on a different layer from the gate electrode of the fourth transistor.

18. The aforementioned fourth transistor is A source connected to the initialization voltage line, A drain connected to the first electrode of the light-emitting element, A gate electrode connected to a black scan line that receives a black scan signal as the shared control signal, is included, The first light-emitting control transistor is The source connected to the aforementioned second node, A drain connected to the first electrode of the light-emitting element, The display device according to claim 13, further comprising a gate electrode connected to the black scanline.

19. The aforementioned pixel is A second light-emitting control transistor is connected between the first power line and the first transistor and receives a second light-emitting control signal, A first capacitor connected between the first node and the second node, The system further includes a second capacitor connected between the second node and the first power line, The display device according to claim 13, wherein the second light-emitting control transistor is a P-type transistor.

20. A display panel including pixels, A panel driver that drives the aforementioned display panel, A drive controller that controls the operation of the panel driver, The system includes a processor that provides an image signal to the drive controller, The aforementioned pixel is A light-emitting element including first and second electrodes, A first transistor operates in response to the potential of the first node and is connected between the first power line and the second node, A second transistor is connected between the data line and the first node and receives a write scan signal, A third transistor is connected between the first node and the reference voltage line and receives a reference scan signal, A first light-emitting control transistor is connected between the second node and the first electrode of the light-emitting element and receives a first light-emitting control signal, The light-emitting element includes a fourth transistor connected between the first electrode and the initialization voltage line, which receives a black scan signal, The inactive interval of the first light emission control signal is included within the active interval of the black scan signal. The first light emission control line to which the first light emission control signal is applied is an electronic device superimposed on a plane with the black scan line to which the black scan signal is applied.

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