Shared column ADC for in-memory computing macros

Abstract

The present invention provides apparatus, systems, methods, architectures, mechanisms, and improvements thereof for scaling, aggregating, and converting analog signals representing weighted data, such as those supplied by multiple parallel outputs of an array of in-memory computing cells, into digital data. [Solution] The in-memory computing macro 200 scales and aggregates multiple weighted data representation analog signals supplied by a column of in-memory computing bit cells in an N×M array of bit cells, and the scaled results are supplied for further processing by analog accumulation or aggregation of the weighted data representation analog signals.

Description

[Technical Field]

[0001] Cross-Reference to Related Applications This application claims the benefit of U.S. Patent Application Serial No. 17 / 221,399, filed April 2, 2021 and is a continuation-in-part of U.S. Patent Application Serial No. 17 / 252,521. U.S. Patent Application Serial No. 17 / 252,521 claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 686,296, filed June 18, 2018, Serial No. 62 / 702,6 29, filed July 24, 2018, Serial No. 62 / 754,805, filed November 2, 2018, and Serial No. 62 / 7 56,951, filed November 7, 2018. All of these applications are hereby incorporated by reference in their entireties into this specification.

[0002] The present invention relates to the field of in-memory computing, and more specifically to in-memory weighted data supplied by multiple parallel outputs of an array of computing cells to the scaling, aggregation and conversion of analog signals representing data into digital data . [Background Art]

[0003] This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the invention described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of various aspects of the present invention. Accordingly, it should be understood that these descriptions are to be read in this light and should not be read as an admission of prior art.

[0004] In-memory computing (IMC) in the charge domain is a technology that enables in-memory computing. A robust and scalable method for performing this has recently emerged. Here, memory bits The calculation operations within the cell generally use voltage-to-charge conversion via a capacitor, and the charge is used as The result is provided. Therefore, the bit cell circuit has local within a given bit cell. With proper switching of the capacitor, the local capacitor is controlled by other bit cell capacitors. The results are properly combined with the combined bit cells, and the calculation results are aggregated across the entire combined bit cell. In-memory computing is well suited for performing matrix-vector multiplication. Matrix elements are stored in a memory array, and vector elements are broadcast in parallel on the memory array. It will be done.

[0005] Advantageously, the IMC computing architecture does not require individual memory like traditional memory. Instead of retrieving each bit one by one, a total of many bits stored in memory is calculated The calculation results are obtained. This reduces the number of data collection cycles required, thus improving the system. To improve the energy efficiency and speed of the system. The calculation results are derived within the memory sequence. In many cases, parallel input data is supplied to the row, and the memory where the data is stored is... The calculation (e.g., multiplication) is performed by the bit cell, and further calculations (e.g.,) are performed on the column bit line. The cumulative process is performed, resulting in a reduction to a single output. Reducing the output generally results in a single output. Compared to glubit access, the dynamic range (i.e., the number of signal levels) is increased. And this needs to be resolved. Furthermore, there are constraints on the memory circuit (bit cells, bit lines) To fit calculations within (etc.) and to enable a wider dynamic range, column calculations Analog calculations are often employed in arithmetic. This means that the analog output of the column is architectural. To convert each column into a digital representation suitable for further processing within the kucha, the analog- A digital-to-analog converter (ADC) is required. [Overview of the project]

[0006] Various shortcomings in conventional technology, in memory computing within an N×M array of bit cells Multiple weighted data representation analog signals supplied by a column of bit cells are scaled. By summarizing and aggregating, and representing weighted data, analog cumulative or aggregated analog signals The system and method ensure that the scaled results are supplied for further processing. This is addressed by laws, architectures, mechanisms, devices, and improvements thereof.

[0007] Each bit cell is measured or evaluated at its respective output element (e.g., output capacitor). The result of the calculation is provided within the bit cell, and each bit cell in the resulting bit cell column has the same weight. A weight based on the position of the bit cell within a row, so as to be associated with it (for example, The result associates the LSB (Less than Boundary) with the MSB (Most Squared Boundary) using binary or other weighting.

[0008] The analog signal (e.g., voltage or charge) associated with each column corresponds to the scaling stage. In addition, the aggregation or accumulation of scaled analog signals (e.g., voltage or charge) cumulative / aggregated analog signals, including analog domain representation of in-memory computing results. To provide, it is scaled according to the weight of each column, and then analog- It is used for digital conversion (ADC) and further processing.

[0009] The scaling stage is the remaining bit cells within each column (e.g., their output capacitors). When the charge levels of are accumulated to provide an aggregated analog signal, each column The charge contributed is proportional to the weight value of that column, and the corresponding weight value of that column is... Therefore, this may include detaching a portion of the bit cells within a column of bit cells.

[0010] The scaling stage involves signal dividers such as charge dividers or charge divider networks. It may include, so that the total charge provided by the bit cells in a row of bit cells is Provides charge levels or analog signals representing them according to the corresponding weighted values ​​in the column. It is divided for this purpose. This is because the accumulated / aggregated analog signal presented to the ADC is properly It may be performed before the ADC to scale, or the successive approximation of the ADC. Related to ADC sample-and-hold (S / H) operation, such as through selective switching of load splitting elements. It may be executed in this way.

[0011] Some embodiments scale and aggregate multiple weighted data representation analog signals. The device provides a mechanism for each analog signal to be processed by an in-memory compute bit cell. The voltage associated with each of the multiple combined bit cell outputs in the IMC array The device includes a plurality of charge-dividing circuits, each charge-dividing circuit having its respective weighted value The output signal is generated across each output capacitor with scaled capacitance values ​​according to the following method. To do this, the signal is configured to process each weighted data representation analog signal. The circuit includes a divider, and during the measurement phase of the calculation, the output capacitor of the charge divider circuit receives weighted data. Analog is configured to generate a digital output from which an analog signal is represented, which represents the sum of analog signals. Coupled to a sample-and-hold circuit associated with the input of a digital-to-digital converter (ADC). It will be done.

[0012] Further objects, advantages, and novel features of the present invention are partially described in the following description. This will be partially apparent to those skilled in the art through the following considerations, or through the implementation of the present invention. It will be possible to know. The object and advantages of the present invention are particularly indicated in the appended claims. It will be realized and achieved through the means and combinations that are selected.

[0013] The accompanying drawings incorporated herein and constituting part thereof illustrate embodiments of the present invention. This is based on the general description of the present invention described above and the detailed description of the embodiments shown below. Both are helpful in explaining the principles of the present invention. [Brief explanation of the drawing]

[0014] [Figure 1] This diagram illustrates a typical structure of an in-memory computing architecture. [Figure 2] This shows a block diagram of a fully row / column parallel (1152 rows x 256 columns) array of multiplication bit cells (M-BCs) for in-memory computing (IMC) macros that enable N-bit (5-bit) input processing. [Figure 3] Figure 2 shows a circuit architecture for a multiplication bit cell suitable for use in the M-BC array. [Figure 4A] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4B] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4C]This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4D] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 5] This is a diagram illustrating an example of an IMC column within an M-BC sequence. [Figure 6] This diagram illustrates an example of binary weighting scaling within a bit cell array in an in-memory computing architecture, which is useful for understanding the embodiments. [Figure 7] The schematics show various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 8] The schematics show various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 9] These are schematic diagrams of various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 10] Circuit diagrams of various embodiments of a binary weighted current division scaling circuit suitable for use in various embodiments are shown. [Modes for carrying out the invention]

[0015] The attached drawings are not necessarily to scale, and various features illustrating the basic principles of the present invention are shown to some extent. Please understand that this is a simplified representation. The series of operations disclosed herein Specific design features, such as the specific dimensions of various illustrated components, and directions. Features such as position and shape depend in part on the specific intended use and environment. This is determined. Certain features of the illustrated embodiments facilitate visualization and clear understanding. To achieve this, it is enlarged or distorted compared to other things, especially for clarity or explanation. In some cases, thin features are represented as thicker.

[0016] The following description and drawings are merely illustrative of the principles of the present invention. Therefore, this invention is not applicable to the present invention. If you are a person who embodies the principles of the present invention, even though it is not explicitly stated or indicated in this specification, It will be understood that various modifications falling within the scope of the present invention can be devised. All examples cited in this document are primarily intended to further illustrate the principles of the present invention and the relevant technical field to the reader. Education to help understand the concepts provided by the inventor(s) in order to advance It is intended solely for the purpose of being, and is not limited to such specifically cited examples and conditions. It should be interpreted that it does not mean that. Furthermore, the use of "or" in this specification Unless otherwise indicated, the term means non-exclusive "or" (for example, "or"). (, or in other cases) or in alternative cases. Also, some embodiments are one or more Because new embodiments can be formed by combining them with the other embodiments described above, this specification The various embodiments described herein are not necessarily mutually exclusive.

[0017] Many of the innovative teachings of this application will be described with particular reference to currently preferred exemplary embodiments. However, this type of embodiment has many advantages to the innovative teachings herein. Please understand that this only provides a few examples of applications. In general, the specification of this application is... The descriptions made are not necessarily limited to the various inventions claimed. Furthermore, The description applies to one inventive feature but not to another. There are. A person skilled in the art who has acquired knowledge through the teachings herein will know that the present invention is a very diverse invention. It will be understood that this is also applicable to other technical fields or embodiments.

[0018] Before describing the present invention in more detail, it should be noted that the present invention is not limited to the specific embodiments described. Therefore, it should be understood that it can, of course, be deformed. Furthermore, the scope of the present invention is limited to the attached special features. Because the terms used herein are limited only by the scope of the claims, they refer to a specific implementation. It is understood that the sole purpose is to describe the state, and not to limit it. sea ​​bream.

[0019] If a range of values ​​is provided, the intermediate values ​​between the upper and lower limits of that range, and their notation. It is understood that any other listed or intervening values ​​within the range described herein are incorporated into this invention. This intervening value is to one-tenth of the lower limit unless otherwise clearly indicated in the context. These smaller ranges have upper and lower limits that are independently included within the smaller range. They may be included, provided that they comply with any specific excluded restrictions within the stated scope. This is included within the present invention. If the described range includes one or both of the limit values, A range that excludes one or both of those included limits is also included in the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein are the same as those used in this document. This specification has the same meaning as it is generally understood by those skilled in the art in which the term "Mei" belongs. Any methods and materials similar to or equivalent to those described in this document are also part of the present invention. The methods and materials described herein are illustrative and may be used in practice or testing. Only a limited number will be described. (As used in this specification and the attached claims) The singular forms "a," "an," and "the" are used when the context is clear. Please note that unless otherwise explicitly indicated, it may contain multiple references.

[0021] Various embodiments include a large number of calculation results derived into a memory sequence, stored in memory. The context of the IMC computing architecture for obtaining calculation results bit by bit This will be considered within the context. In this case, parallel input data is supplied to the row, and the data is stored. The calculation (e.g., multiplication) is performed by the memory bit cells, and furthermore, by the column bit lines Then the calculation (for example, cumulative) is performed and associated with each column bit line. Each analog output signal representing the calculated result is supplied, and this signal is as follows: While it is described exemplarily as being provided as a charge level, in alternative embodiments... The analog output of the column may consist of either a current level or a voltage level.

[0022] In some of the various embodiments, separate analog-digital approaches are used for each column or bit line. The calculation results of multiple parallel sequences or bit lines in a way that does not require the use of an ADC. IMC computing architecture and equipment configured to acquire display output. This applies to methods and parts thereof, that is, associated with each bit line or column. Further processing of the generated analog output signal within the IMC computing architecture Rather than converting to a suitable digital representation for each of the various embodiments, bit lines Alternatively, some of this further processing can be performed using the analog output signals associated with the column. And while maintaining the accuracy of the analog output signal (i.e., ADC quantization error and other errors), (While reducing the impact of errors) the IMC computing architecture performs its functions. Reduce the number of ADCs required to achieve this.

[0023] Figure 1 shows a diagram illustrating a typical structure of an in-memory computing architecture. Specifically, the in-memory computing architecture 100 shown in Figure 1 This may be based on a memory array (standard bit cells or modified bit cells). ) and in-memory computing also includes two more "vertical" signal sets, namely (1) the input line and (2) the cumulative line are involved. Referring to Figure 1, the secondary of the bit cell It was found that the original array was shown, and there, multiple in-memory computing channels Channels 110-1 to 110-N (collectively referred to as in-memory computing channels 110) Each of the ) contains each column of bit cells, and each bit cell in the channel is common The cumulative lines and bit lines (columns) are associated with their respective input lines and word lines (rows). In this specification, the rows and columns of signals are described as being "perpendicular" to each other. However, this is because bit cells are like the two-dimensional array of bit cells shown in Figure 1. This is simply to indicate row / column relationships within the context of an array. The term "straight" is not intended to convey a specific geometric relationship.

[0024] The input / bit group and cumulative / bit group of signals are based on existing signals in memory (e.g., watt The do line and bit line can be physically combined or kept separate. To perform a Toll multiplication, first load the matrix elements into memory cells. Then, multiple inputs Apply all vector elements (presumably) at once via the input line. This allows each Local calculation operations, typically some form of multiplication, are performed in the Molybit cell. The result of the calculation operation is sent to a shared cumulative line. In this way, the cumulative line is the input vector. This represents the result of a calculation across multiple bit cells activated by a specific element. They are accessed one at a time via bit lines and activated by a single word line. This is in contrast to standard memory access.

[0025] In-memory computing, as described, has several important characteristics. First, calculations are usually analog. This is due to the limited structure of memory and bit cells. The construction is more complex compared to when it can be done with a simple digital switch-based abstraction. This is because it requires an arithmetic model. Secondly, local operations on bit cells are usually bit This involves calculations using 1-b representations stored in a cell. This is a standard memory array. This is because the cells do not join together in a binary weighting scheme. Such a join is This must be achieved by a method of accessing / reading bit cells from the periphery. The extension of in-memory computing proposed in this invention will be described below. ru.

[0026] In memory computing, in dealing with matrix-vector multiplication, is different from traditional digital computing. While acceleration may be insufficient, a typical computation pipeline is: This would include various other operations surrounding matrix-vector multiplication. Typically, such operations are Conventional digital acceleration will adequately address this. However, in memory con The parallelism associated with puteting and high throughput (and therefore high round-trip communication) A suitable architecture to address bandwidth requirements and common computation patterns. In this context, such acceleration hardware is used in in-memory computing. Placing components close to the hardware can sometimes offer significant advantages. (Peripheral computing) Since much of this is preferably done in the digital domain, analog-to-digital conversion via ADC is preferred. The transformation is included following each in-memory computing cumulative line, and this is in memory This is called a recomputing channel. The main challenge is to integrate the ADC hardware into each in-memory The integration is done through the pitch of the computing channel, but the appropriate ray adopted in this invention This becomes possible with an outside approach.

[0027] By introducing an ADC after each computing channel, efficient in-memory computing can be extended. This method makes it possible to multibit via bit-parallel / bit-serial (BPBS) computation. It supports bitwise matrices and vector elements. Bitwise parallel computing is performed on different matrix elements. This includes loading into different in-memory computing columns from different columns. The ADC output is then bit-shifted appropriately to represent the corresponding bit weighting. Digital summation is performed across a group of columns, and the result of multi-bit matrix element calculation is obtained. On the other hand, bitwise serial computation applies each bit of the input vector element one at a time. Each time, the ADC output is stored, and the stored output is appropriately bit-shifted before the subsequent input... This includes digitally accumulating the next output corresponding to the force vector bit. Analog calculation and digital Such a BPBS approach, which enables a hybrid with digital computing, Along with the high-efficiency, high-precision region (multi-bit), the high-efficiency, low-precision region (1-b) of analog is utilized. By using this method, it overcomes the access costs associated with conventional memory calculations, making it extremely efficient.

[0028] Figure 2 shows an in-memory processor that enables N-bit (5-bit) input processing according to one embodiment. Computing (IMC) macro multiplication bit cell (M-BC) full row / column parallel (1 A block diagram of a 152x256 array is shown.

[0029] An example of an IMC macro in Figure 2 is the compute-in-memory array (CIMA) discussed earlier. It may be used to implement structures such as structures, but an example of such an IMC macro is 28n Rendered via the manufacturing process, full row / column parallel matrix vector power We provide MVM (Metal Variable Manipulation) and high-precision analog computing based on metal fringe (wire) capacitors. Using this, the binary input vector elements are extended to 5-bit (5-b) input vector elements, Compared to the IMC and CIMA embodiments discussed above, the energy efficiency is approximately 16 times higher. It is configured to improve throughput by approximately five times.

[0030] The embodiments shown in Figures 2 and 3 represent computationally intensive and data-intensive AI workloads. The majority of MVM operations are performed in a way that drastically reduces computational energy and data transfer. So, we'll do it. This involves efficiently performing analog calculations in bit cells and then processing individual bits from memory. This is achieved by accessing the calculation result (for example, the inner product) rather than the input itself. This fundamentally creates an energy / throughput versus SNR trade-off, and analog By doing so, computational noise is generated, and by accessing the calculation results, the dynamic range The signal-to-noise ratio (SNR) of the given read architecture decreases.

[0031] Advantageously, IMC based on metal fringe capacitors overcomes the non-ideal nature of analog. The noise is very low, and therefore the dynamic range can be extremely high. At least some embodiments utilize this precise capacitor-based calculation mechanism. This ensures that improvements in dynamic range, as discussed in this specification, are possible.

[0032] Figure 2 shows a block diagram of the in-memory computing macro 200, The macro is 1152 (rows) x 256 (columns) of 10T SRAM multiplication bit cells (M-BC). ) Array 210 and peripherals for standard writing / reading to it (e.g., B 240 BL decoders and 256 BL drivers 242-1 to 242-25 6. Word Line (WL) Decoder 250 and WL Driver 252-1~25 2-1152, and control block 245 for controlling decoders 240 / 250) And peripherals to supply 5-bit input vector elements there (for example, 1152 Dynamic Range Doubling (DRD) DAC220-1~220-1152, and compatible A controller 225) and peripheral units for digitizing the calculation results from each column (for example) , 256 8-bit SAR ADC260-1~260-256, and column reset mechanism Nism 265-1~265-256 (For example, the output of column calculation line CL during the calculation reset phase) Reset voltage V RSTPull until the power of the column calculation line CL during the evaluation phase of the calculation. Includes a CMOS switch configured so that the pressure level reflects the respective calculation result. nothing.

[0033] The array 210 of the 10T SRAM multiplication bit cells (M-BC) in IMC macro 200 is: It works in the same way as described above for various figures. In particular, writing / reading is usually While it is executed row by row, MVM operations are typically performed on the input activation of a neural network. Applying the corresponding input vector elements to all rows or some rows at once Therefore, it is executed. That is, each DRD-DAC220 j Each of the 5-bit inputs Cthulhu element X j [4:0] In response to each differential output signal (IA j / IAb j )of Generates this differential output signal for each M-BC in the corresponding row of the M-BC. j And the stored heavy Mi (W ij / Wb ij ) is used for 1-bit multiplication with and the M-BC con on the calculation line (CL) The charge is accumulated across the entire denser through charge redistribution, and the inner product of each column is obtained, and then each of the columns This is digitized via ADC260. Each 10T SR forms array 210. The AM-M-BC calculation will be discussed in more detail below with reference to Figure 3.

[0034] Figure 3 shows the circuit architecture of a multiplying bit cell (M-BC) according to an embodiment. This is the 10T SRAM M-BC in Figure 2, and the same arrangement as above is required for various figures. It is suitable for use when performing prime calculations. Figure 3 shows the M-BC300 for weight storage and multiplication. includes a high-density structure to achieve the above, whereby a 10T SRAM multiply bit cell ( M-BC), implemented using M-BC such as the 1152 (row) × 256 (column) array 210 of M-BCs, minimizes a data broadcast distance and control signals within the context of an i-row j-column array .

[0035] An example of M-BC 300 includes a 6-transistor bit cell portion 320, a first switch SW 1, a second switch SW2, a capacitor C, a word line (WL) 210, a first bit line (BLj) 312, a second bit line (BLbj) 314, and a compute line (CL) 31 5.

[0036] The 6-transistor bit cell portion 320 is shown positioned in a central portion of M-BC 300 and includes six transistors 304a to 304f. The 6-transistor bit cell portion 320 can be used for data storage, reading and writing. In one example, the 6-transistor bit cell portion 320 stores filter weights. In some examples, data is written into M-BC 300 via word line (WL) 310, first bit line (BL) 312, and second bit line (BLb) 314 .

[0037] Multiply bit cell 300 includes a first CMOS switch SW1 and a second CMOS switch S W2. When the first switch SW1 is closed, SW1 is controlled by a first activation signal A (A ) to couple one of the received differential output signals provided by DRD-DAC 220, illustratively IA, to a first terminal of the capacitor C, and is shown as being ij controlled in this manner. When the second switch SW2 is closed, SW2 correspondingly ​The other of the differential output signals received by the DRD-DAC220, for example, IAB The second activation signal Ab(Ab) is coupled to the first terminal of capacitor C. ij ) by It is shown to be controlled in this way. The second terminal of capacitor C is the calculation line (CL) It is connected to switches SW1 and SW2. The supplied input signal is a fixed voltage (e.g., V dd ), ground, or other voltage levels It may include.

[0038] The M-BC300, which includes the first SW1 switch and the second SW2 switch, has 6 transistors. Calculations can be performed on the data stored in the tab cell section 320. The effect is driven as the charge of capacitor C. According to various implementations, capacitor C is bit It may be placed above the Tocell 300, and does not require the use of another area on the circuit. In the implementation of this, V dd Alternatively, either the logic value of ground is driven by capacitor C. In other embodiments, the voltage driven by capacitor C is the voltage of switches SW1 and SW2. Depending on the operation and the output voltage level generated by the corresponding DRD-DAC220 It may include a positive or negative voltage.

[0039] Therefore, the charge stored in capacitor C (as a function of the driving voltage) is, The value of C itself is very stable, and the drive voltage is very stable (for example, the power supply voltage is It is very stable because it is driven by (or driven to ground). Some examples So, capacitor C is a metal-oxide-metal (MOM) finger capacitor, and In some examples, capacitor C is a 1.2fF MOM capacitor. Because the sensors have excellent temperature characteristics and process characteristics matching, they exhibit high linearity and low cost. It is possible to perform fixed calculation operations. Note that the reset and evaluation stages of the M-BC calculation are also possible. In this case, the connection method of transistor 304 and / or switches SW1 and SW2 By changing the calling / operating method, you can use M-BC to perform other types of logical functions. It can be implemented.

[0040] In various implementations, the 6-transistor bit cell section 320 has a different number of transistors. This is implemented using and may have different architectures. In some examples, bit The cell portion 320 may be SRAM, DRAM, MRAM, or RRAM. Improved IMC cumulative and M-BC output scaling

[0041] As discussed above regarding Figure 2, N=5 (5-bit) input processing in memory computer The coating (IMC) macro 200 is similar to the M-BC300 described above in Figure 3. This assumes a fully parallel array of arithmetic bit cells (M-BC) with 1152 rows x 256 columns. Furthermore, IMC macro 200 is used for each of the connected M-BC columns in array 210. It is indicated that one 8-bit analog-to-digital converter (ADC) should be used. Please note that the analysis provided by each of the 256 example columns The log output signal, as discussed above, and in various related patent applications, further Before processing, each 8-bit ADC converts the data into its respective 8-bit digital representation individually. It will be converted.

[0042] In particular, multiplication with multibit data stored in bit cells is required, but bit precision When the degree cannot be adjusted within a single bit cell, the outputs of multiple parallel columns are combined. Within the context of the IMC architecture configured as described above, various embodiments are described below. In this case, bitwise parallel processing can be employed, and the most significant bit of the stored data is The bit cell in the column is, and the next most significant bit of the stored data is in the bit cell of the next column, and This process continues in the same manner down to the least significant bit of the stored data (usually, the stored data element (All bits are in the same row). In this case, each column is a specific bit weight of the calculated output. This represents the component corresponding to the multiplication operation. Due to the linear nature of the multiplication and accumulation operation, each column output is appropriately multiplied. Scaling is performed using weighted coefficients, and the output components of the columns are aggregated under different scaled conditions. By doing so, the overall calculation output can be derived. Generally, stored in different columns. The bit weighting of the generated data does not need to be binary. This corresponds to each column output. By applying a scaling factor (which does not necessarily have to be binary weighting), Supported by the I Ching.

[0043] Scaling and aggregation of the calculation result output of multiple parallel columns or bit lines are performed before the ADC. Alternatively, it can be done later. If done before ADC, scaling and aggregation calculations are performed. It must be applied to the corresponding analog signal, which is voltage, current, charge, etc. It is possible.

[0044] For example, a vector configured to multiply two vectors (or a vector and a scalar) Within the context of a net cell in-memory computing (IMC) array, V1 Each element is multiplied by each element of V2, and the sum is accumulated to obtain the result. It is stored in memory. Multiple bits of vector V1 are mapped to multiple columns, and the input bits of input vector V2 The bits are sequentially supplied to each column, and multiplication and bit shifts are repeated. Each column (in this example) is: Each of the weighted results (e.g., bit positions within multiple bitwords) associated with Including the total voltage or stored charge, exemplify the stored vector in a 4-bit input vector V2. A 4-bit binary word (MSB, MSB-1, Includes binary weighting results such as MSB-2 and LSB.

[0045] Resolve the multiplication result (for example, the result of multiplying all input vector elements by all stored vector elements). Instead of performing bit shifts in the digital domain after the A / D conversion of the column, various The embodiment involves weighting or scaling factors (e.g., bi) for the analog domain. Scaling of the total voltage or stored charge associated with each column according to the (set position), and each column It provides the cumulative scaling of voltage / charge and the analog representation of the multiplication result (e.g., The analog represents the result of multiplying a 4-bit input vector V2 by each element of the storage vector V1. It provides a cumulative voltage / charge level. This cumulative voltage / charge level is then used for A / D conversion. This provides a digital representation of the final multiplication result. For example, with a 4-bit input vector... Instead, 4 cycles of bit-parallel bit-series operations are performed, and 4 bits are analogous It is represented by a level, and only one cycle is required.

[0046] Figures 4A and 4B show the scale of the calculation result display output, which is useful for illustrating various embodiments. This diagram illustrates the ring and aggregation mechanism.

[0047] Specifically, each mechanism scales and aggregates the four calculation result output displays. As shown, each output is a column of connected bit cell output capacitors. Each of the four columns or bit lines represents the voltage level associated with the charge stored in This represents one of the values, and this voltage level is part of the cumulative result, such as the binary weighting portion of the cumulative result. This represents the respective weighted parts. As shown, the four columns are b, b+1, b+2, b+ 3 represents the binary weighted data of the cumulative 4-bit calculation result, with the most significant bit ( The MSB (Most Significant Bit) is represented by column b, and the least significant bit (LSB) is represented by column b+3.

[0048] As shown in Figures 4A and 4B, and as generally described herein, four IMC columns (I Each of MCb■IMCb+3) is a multiple bit cell output condition that forms a column. Each binary weighted portion of the cumulative result stored in the entire survey represents the respective It supplies a voltage signal or voltage level.

[0049] In various embodiments, instead of voltage signals / levels, four IMC columns (IMCb~ Each of IMCb+3) provides a current signal / level or other type of signal / level. Each IMC column can represent the respective binary weighted portion of the cumulative result. (For example, a signal such as a current or voltage signal provided by a buffer circuit, or I MC output capacitor and / or capacitor-based voltage or charge division cycle Voltage or charge division circuits based on resistors or transistors, rather than circuits. (The signal provided by). Furthermore, binary weighting and / or scaling are used. In other embodiments, rather than using, the application, components selected for IMC, and / Alternatively, depending on other factors, use other types of weighting and / or scaling. This is also fine. Thus, various embodiments can be used for weighted signals (or whatever kind of weighted signals are used). A mechanism that selectively attenuates or amplifies (whether of the type) according to its weighting coefficient. It provides a signal level (voltage level, current level, charge) that represents the cumulative result after aggregation. It provides levels, etc. The mechanism in Figure 4A provides the cumulative weight of the calculation results before ADC processing. Scaling and aggregation of the found portion are anticipated.

[0050] As shown in Figure 4A, and as generally described herein, the four IMC columns (IMCb~ Each of the IMCb+3) across the multiple bit cell output capacitors that form a column Each voltage signal represents the respective binary weighted portion of the stored cumulative result. Or it supplies voltage levels. These voltage signals / levels are mutually exclusive with each other. It is scaled to reflect the weighting. Specifically, in the LSB column (b+3) The scaling factor is 2 0 =1 is multiplied, and the next column (b+2) has a scaling factor of 2 1 = The scaling factor is multiplied by 2, and the next column (b+1) contains the scaling factor 2. 2 =4 is multiplied, and the last column ( b) contains a scaling factor of 2 3 =8 is multiplied. And the scaled voltage level The voltage is aggregated and represents the cumulative result, which is then digitized by the ADC converter. It will be converted to a barrel representation.

[0051] The mechanism in Figure 4B is the scaling of the cumulative weighting portion of the calculation results related to ADC processing. Scaling and aggregation are anticipated. Specifically, the scaling function described in Figure 4A. The aggregation function changes various parameters of the ADC calculation, as will be discussed in more detail below. This will be implemented by making changes.

[0052] Figures 4A and 4B show the cases where the four columns are combined before or within the ADC. As shown, in general, any number of columns can be combined in this way. Furthermore, ADC Such scaling and aggregation before / inside the ADC applies to any number of outputs after the ADC. This can be combined with scaling and aggregation in digital scaling. The application of a weighting coefficient (which reduces bitwise shifts for binary weighting) This includes aggregation in the digital domain. As will be discussed later, in addition to optimizing the practicality of implementation. This makes it possible to optimally manage the effects of quantization errors.

[0053] Figures 4C to 4D illustrate scaling of the calculation result display output, which is useful for describing various embodiments. This diagram illustrates the aggregation mechanism. The above considerations regarding Figures 4A and 4B are based on the following: This generally applies to Figures 4C to 4D. Note that in Figures 4C to 4D, the LSB column (b+3) is Kaling coefficient 1 / 2 0 Multiply by and add a scaling factor of 1 / 2 to the next column (b+2). 1 multiply Then, in the next column (b+1), the scaling factor is 1 / 2 2 Multiply by and add the scale to the last column (b). -ring coefficient 1 / 2 3 It assumes a scaling function that multiplies by . And scaling The collected voltage levels are aggregated to form a cumulative voltage level, which is then converted to an ADC voltage level. It is converted into a digital representation by a barter. Capacitor-based analog scaling and aggregation

[0054] Figure 5 illustrates an example of an IMC sequence within the M-BC sequence. As shown, each of the columns (1 to N) of the M-BC300 is an input (IA 1 / IAb1~IA N / I Ab N ) weighted value (W b,1 ~W b,N ) Multiply by and each result in The output voltage is provided as stored in a power capacitor, which is selectively output to the output column CL. b Combined This may also be done. In particular, Figure 5 shows the use of replacement capacitors, which allows for the use of specific columns. The column accumulation (subtraction) operation is performed through the redistribution of charge across the entire capacitor. Basically, Each bit cell capacitor forms a leg of a signal division circuit, such as a voltage / charge division circuit. The output voltage (i.e., the node connecting all capacitors) is the voltage / charge division input ( In other words, the goal is to bring it down to the average of the entire leg (the driving side). Such an average is the cumulative scale A scaled / normalized version is provided, where the scaling factor is the charge dispersion. It is set by the total capacitance (i.e., V = Q / C). As a result, the scale of the output voltage of the column Ringing and aggregation are performed by setting the capacities involved and short-circuiting the involved column capacities between columns. It can be achieved.

[0055] According to various embodiments, capacitor-based analog scaling and aggregation are performed below This may be achieved through several approaches, as described below. For example, (1 (2) setting and short-circuiting the column capacitance, and sampling the column voltage on the auxiliary capacitance, then Setting and short-circuiting the auxiliary capacitance (where the auxiliary capacitance is combined with the ADC sample-and-hold circuit) (It is acceptable if it is not.) Column capacity setting and short circuit

[0056] Capacitance-based IMC typically involves two stages: (1) Reset; Capacitor coupling By short-circuiting the circuit to a specific reference voltage, the charge on all capacitors is reset. 2) Evaluation. The capacitor coupling node is released from short-circuit to the reference voltage, and the voltage / charge division rate The input legs of signal division circuits such as roads are driven (via bit cells). After this, the ADC Therefore, the output voltage of each column can be sampled and then digitized.

[0057] Further steps are taken before the ADC to perform analog scaling and short-circuiting between columns. This can be added, which is referred to as scaling in this specification. After the column output voltage stabilizes, All couplings between column capacitors can be disconnected, and the remaining scaled amount of the entire shorted column is lost. A certain capacitance is obtained. Then, the short-circuit capacitance between the columns is sampled by an ADC and digitized. This approach can be used, for example, in the case of binary weighted scaling. This is shown in Figure 6.

[0058] Figure 6 shows an in-memory computing architecture that is useful for understanding this embodiment. This diagram illustrates an example of binary weighting scaling within a bit cell array in a CHAR array. Specifically, Figure 6 shows the four IMC columns (CL) of the multiplication bit cell. b ~CL b +3) An example of the arrangement of bit cell output capacitors for the eight IMC rows (R1~R8) is shown, IM Each in column C is a switch (S b ~S b+3 ) selectively to the ADC input via They are joined. The array is further combined between rows R7 and R8. b+3 , CL between lines R6 and R7 b +2 , CL between lines R4 and R5 b+1 Each of these includes an additional switch S. Additional switch S is introduced into the column at these locations, and disconnects some of the column capacitors at different positions in the column. To combine / combine.

[0059] During the calculation reset phase and the calculation evaluation phase, the additional switch S is closed. This allows for the joining of all capacities within the column. During the scaling phase of the operation, Additional switch S is released, and the remaining column capacity is allocated to column switch S b ~S b+3 Short-circuited by The resulting signal is then supplied to the ADC.

[0060] Furthermore, if the capacitance C of each output capacitor is substantially the same, by using the additional switch S, The charge contribution to the subsequent signal voltage of a column with more output capacitors becomes greater. For example, a column CL with 8 bit cell capacitors. b This uses four bit cell capacitors The column CL b+1 Effectively weighted twice as much as the weight of column CL b+1 is two bits Column CL with capacitor b+2 Effectively weighted twice as much as the weight of column CL b+2 teeth Column CL with one bit cell capacitor b+3 Effectively weighted twice as much as the weight of .

[0061] Considering the charge weighting due to the use of the additional switch S, the result applied to the ADC is The voltage signal represents the scaled cumulative power signal, and the digital representation of the cumulative power signal is It can be directly digitized by an ADC for delivery.

[0062] The inventors have created a switch (whether to disconnect the column capacitor coupling or to short-circuit between the column capacitors) (Whether to enable it or not) Introducing it adds parasitic capacity, and these parasitic capacities also affect the entire column. It needs to be appropriately weighted (binary or otherwise) for accurate scaling and aggregation. It should be noted that there is a parasitic offset swimmer. Thus, in various embodiments, S PO Alternatively, add other structures to the array to balance all switch-related parasitic capacities within the column. Take it.

[0063] Parasitic offset switch S PO Other structures may be functional or non-functional switches. It may include switches. For example, for each additional switch S that functions as described above in the column And, similarly, on the substrate used to form the bit cell array (for example, a VLSI substrate), This may include switches that are functional or non-functional (e.g., normally closed).

[0064] Therefore, in some embodiments in which binary weighting is used, as described herein In addition to an additional switch S that operates on the column to weight it in such a way, one of the other columns Above, a parasitic offset switch S with a similar structure PO Form in the corresponding location, capacity This ensures that the differences between columns are avoided. This technique is a weighting method other than binary weighting. It may also be used in embodiments in which Keem is implemented. Parasitic offset switch S POThe number and place The location may be changed depending on the manufacturing technology and other factors, and importantly, the relevant scale To avoid rigging errors as much as possible, the parasitic capacity added to the circuit by the additional switch S Parasitic offset switch S to balance or cancel out the quantities PO It is about forming That's it. Auxiliary capacitance sampling, setting, and short circuit

[0065] In other embodiments, the same capacitor is used for both column calculations and scaling operations across columns. Instead, the voltage across each group of column capacitors is determined by a signal divider such as a voltage / charge divider circuit. (i.e., an auxiliary capacitor network configured for charge sharing / sampling) The sample is first taken via a sampling capacitor, and the auxiliary sensor associated with the column is used. The pull-off capacitor is a value selected to produce a scaled output appropriate for that column. It has an additional capacitor formed for each column of the sampling capacitor, the ADC itself Sample-and-hold capacitors in the body (integrated within the ADC, or separate from the ADC) It may include one, or other capacitors.

[0066] In these embodiments, the signal associated with a particular column is the electrical signal associated with that column. The sample is taken through the auxiliary capacitor of the load splitting circuit, and this capacitor is also in its column. It may be selectively coupled to the divider circuit.

[0067] Various embodiments process the signals associated with each column via a weighted input ADC. This is the assumption. A weighted input ADC is, in other words, an ADC with multiple inputs. Each of those inputs is weighted, and the resulting weighted signal is AD It may be aggregated for C processing, thereby providing a digital output signal. It is an ADC.

[0068] Figures 7-9 show the vicinity of the output ADC of the in-memory computing architecture. Figure 7 shows circuit diagrams of various embodiments of internal binary weighting scaling. The embodiment shown in Figure 9 generally involves the entire bit cell output capacitor as described above. It is shown and described as processing the voltage signal provided by the load, but in practice The state also includes other types of signals (for example, voltage) as previously discussed in relation to Figures 4A and 4B. It may be used to process (electric current, etc.).

[0069] Figure 7 shows a circuit diagram useful for understanding various embodiments. Specifically, the circuit in Figure 7. 700 assumes multiple (for example, four) capacitive circuits, and each capacitive circuit is Each of the multiple bit cell output capacitors stores a portion of the charge in each sample Shared with a jack capacitor or auxiliary capacitor(s), and weighting of each cumulative result. It operates to provide a voltage output signal there for each part that has been cut off, and sample The voltage sampled across a capacitor or auxiliary capacitor(s) is... It is provided to the ADC for further processing.

[0070] Note that the sampling calculation for the auxiliary capacitor is achieved by charge sharing calculation. It is important to do so. Therefore, sampling is performed using the coefficient C of the sampled voltage. COL / (C COL +C AUXThis reduces to scaling by C, where COL The total number of entries quantity, C AUX This is the auxiliary sampling capacity. Therefore, C COL and C AUX and the entire column To ensure sufficient matching and reduce errors, C AUX Allow it to discharge completely at the start. This becomes important. After that, C AUX It is divided into binary weighted components, and appropriately binary The weighted components are short-circuited for accurate scaling and aggregation.

[0071] Specifically, the capacitance of a charge-dividing circuit (or more broadly, a signal-dividing circuit) is the mechanism for sharing capacitance. The rhythm stores the charge across multiple bit cell output capacitors in the corresponding capacitor. Scaling in the case of charge sharing events, such as sharing with a voltage / charge partitioning circuit. This is important when it is a mechanism (binary weighting or other). In this case, negative A charge-balancing capacitor is used (as shown in Figures 7-9), and each capacitor charge division cycle Ensure that the paths have essentially the same capacity.

[0072] In addition to charge sharing, scaling is performed by other means alone or in combination in various embodiments. This is achieved by, for example, in various embodiments, each weighted data representation analog The scaling of a signal depends on the nature of the analog signal being scaled, such as charge and voltage. , via current or impedance scaling techniques (e.g., weighting or ba (Using Inari weighted capacitor divider networks, resistor divider networks, etc.) This may be achieved. Various embodiments, as most frequently shown herein, are charge-based. Alternatively, to scale voltage-based weighted data representation analog signals, capacitive The present invention provides a charge-dividing circuit based on charge sharing or redistribution.

[0073] Generally speaking, multiple weighted data representations of analog signals (e.g., binary data per column) Each of the weights represents the total signal level of all the different weighted data representations of the analog signal. Or a specific weighted data representation of the cumulative signal level of an analog signal, The signal contributions (charge, voltage, current, etc.) are the weights of the analog signal representing that data (for example, The scale is proportional to the weight associated with the column position of the analog signal representing the data. It will be ringed.

[0074] For example, if the bit cell calculation output is resistive / conductive output impedance (not capacitive), If provided through [a specific method], the scaling circuit is either resistive scaling or signal division Minutes, transistor scaling or signal division components, or charge level or charge level Other scalings suitable for showing the weighting / scaling of each signal indicating a bell Alternatively, it may include signal division components (e.g., voltage / charge division circuits, charge sharing networks, etc.). That's fine too. In this case, a stable signal does not depend on capacitive loading, so load balancing There is no need to use a capacitor.

[0075] In this binary weighting example, column CL b The signal sampled from is from column CL. b+ Given twice the weight of signal 1, the column CL b+1 The signal is column CL b+2 Twice the weight of the signal Given, column CL b+2 The signal is column CL b+3It is given twice the weight. As can be seen in Figure 7, the capacitance of the voltage / charge divider circuit in each column is the same (i.e., C). Various switches are controlled to achieve this, but the sampling capacitor of each voltage / charge division circuit The capacitor or auxiliary capacitor is different. Specifically, column CL b The sampling capacitor Alternatively, the auxiliary capacitor is C(C / 2+C / 2), and column CL b+1 For C / 2, column CL b+2 For C / 4, column CL b+3 The sampling rate is C / 8. The signals present in each of the densors or auxiliary capacitors are the respective scaling of the cumulative result. This represents the selected portion, and each of the sampling capacitors or auxiliary capacitors in the column By connecting them together and supplying the signal to the ADC, a digital representation of the cumulative result is generated. This may be done. As shown, the capacitance of the voltage / charge divider circuit in each column is made the same, and the charge Errors due to shared events are equalized across the entire voltage / charge division circuit, and between the voltage / charge division circuits To prevent relative errors from occurring.

[0076] Figure 8 shows a circuit diagram useful for understanding various embodiments. Specifically, Figures 8 to 9 This shows the voltage / charge division circuit in Figure 7, where all sampling capacitors or auxiliary capacitors are present. The voltage sampled across the entire auxiliary capacitor is used during charge sharing events (e.g., during calculations). During the testing or evaluation phase, sample-and-hold (SH) operation of a successive approximation register (SAR) ADC. ) combined with SH, the feedback digital-to-analog converter (DAC) and It also works. This approach allows for a compact layout, and this is IMC reading Desirable for a disruptive ADC.

[0077] Figures 8 and 9 show the cumulative input power associated with only the four weighted input signals. This shows an 8-bit ADC receiving voltage. If eight weighted input signals are used, an 8-bit ADC will be used. If processed by C, each of its eight weighted input signals is first each This will be scaled by the divider circuit. When using a capacitor divider circuit, The capacitance of each of the four additional (e.g., LSB) voltage / charge divider circuits is also the same as the first four (e.g., It is the same as the voltage / charge division circuit (MSB), and each sampling capacitor or The auxiliary capacitors will also be scaled accordingly (for example, the next four columns are the cumulative results). Assuming that these represent four LSB values, C / 16, C / 32, C / 64, and C / 12 8).

[0078] In the context of the S / H SAR ADC shown in Figures 8-9, the S / H is integrated into the ADC. The SAR ADC includes a feedback circuit, in which digital-to-analog A digital-to-analog converter (DAC) receives different digital input signals supplied by SAR logic. The DAC output voltage, which is adjusted via the analog input voltage provided to the ADC, is finally determined to correspond to the analog input voltage. It generates digital words or bits that represent the analog input voltage to the ADC. Decide the number.

[0079] The analog input voltage is used by the sampling capacitor (i.e., C) of each voltage / charge division circuit. The lower plate of each capacitor (labeled C / 2, C / 4, and C / 8) is sampled. The voltage associated with the DAC's feedback code is then another capacitor. It is applied continuously to the plate, thereby for the purpose of comparison (i.e.) (To determine the ADC output value) a binary weighted signal is generated there. .

[0080] The circuit 800 in Figure 8 is an example in which the ADC SH / DAC receives input from four IMC columns. To obtain the power, it is assumed that it will be divided into four segments. Relative sample To prevent large scaling errors and errors, each of the four segments has an equal capacity. It has, and each of the four segments is processed by an ADC for digitization. It is further divided into parts that are processed and parts that are not. The part that is processed is the entire column Corresponds to the binary weighting capacity of the body. The output of each column is sampled on one side of each segment. Only the parts that are processed and then joined on the other side are then joined. It remains uncoupled on the other side (short-circuited at the reference voltage), and then the sample It is discharged before ignition.

[0081] When the segment portions are joined in this way, the column output scaling within the ADC SH / DAC The data is then compiled and aggregated. Subsequently, the SAR is digitized using standard methods, and the final A digital output code is obtained. For example, the scaled and aggregated charge is SH / The signal is sampled at one end of the DAC, and the other end is fed back with a digital control signal. It is driven by this. As a result, the feedback digital control signal is sent to the comparator. This introduces a corresponding negative voltage shift to the supplied signal. When the voltage due to the pulled charge is canceled out (i.e., the comparator voltage is fixed reference) (When reversed), this results in the final digital output code. Separating the DAC from the S / H. Other forms of SAR digitization can also be employed, such as [mention specific method / method].

[0082] Figure 10 shows a binary weighted current division scaler suitable for use in various embodiments. Circuit diagrams of various embodiments of the circuit are shown. MSB column CL b Weighted data representation analysis from The log signal is column CL b+1 The signal weights are effectively weighted twice as much as the column CL. b+1 of The signal is column CL b+2 The signal weights are effectively weighted twice as much as the column CL. b+2 The signal is Column CL b+3 It can be seen that the signal is effectively weighted twice as much as the signal weight. Advantages and limitations

[0083] The above embodiment utilizes an approach that performs scaling and aggregation before the ADC, ADC across all aggregated columns within the context of an in-memory computing embodiment It has the main advantage of being shared. This reduces the energy and area consumption of the ADC. It can be amortized.

[0084] The approach based on setting up and short-circuiting column capacitors requires the addition of auxiliary capacitors. There is a special advantage in that it does not have the following properties. The advantage is that the complexity of the ADC does not increase (a standard ADC can be used).

[0085] Sample to auxiliary capacitor (possibly integrated with ADC SH and DAC) The ring-based approach has an additional scaling stage (after reset and evaluation). Unnecessary, (for example, switches for coupling / disconnecting groups of bit cell capacitors) due to the addition of ), there is an advantage that the complexity of the IMC architecture does not increase.

[0086] Overall, the limitation of analog scaling aggregation is that the signal digitized by the ADC has an increased total dynamic range. The ADC then quantizes the signal to a specific resolution , resulting in quantization error. Quantization error is somewhat reduced compared to scaling and aggregation after ADC, where quantization occurs at each column output (that is, analog residuals cannot be recovered after digitization of each column output, but scaling and aggregation before ADC only has one quantization event). However, scaling and aggregation after ADC have a net advantage in terms of quantization error due to the low energy / area cost of increased digital bits. Quantization error for scaling and aggregation before ADC can be reduced by increasing ADC resolution at the cost of increased ADC energy / area overhead.

[0087] Various embodiments are described primarily in the context of binary-weighted scaling coefficients , but are suitable for use with any analog scaling of column values. That is, in the present disclosure, the description is primarily directed to structures where columns supplied to a shared ADC have binary-weighted scaling coefficients, but it should be understood that any scaling coefficients may be used.

[0088] Furthermore, it should be understood that the scaling coefficients may be configurable. It should be noted that the main advantage of non-binary-weighted scaling coefficients is that alternative numerical formats (i.e., non-binary integers) may be used for the weights of the matrix stored in memory cells. This The modified neural network can handle alternative numerical formats (for example, if the bit position is 2 instead of...) (When representing powers such as 1.5 or 4) the tray between weight and dynamic range. This is beneficial because it allows for the optimization of the management method for dead-end operations.

[0089] Furthermore, by using uniform scaling factors, the total charge signal is increased compared to single-column calculations. This may be done. Doing so may reduce the influence of various charge noise sources.

[0090] Furthermore, the ability to set the scaling factor allows the two features mentioned above to be realized dynamically. For example, even if different in-memory calculations scheduled during execution are optimized Good. Such configurability requires a configurable capacitor setting across the entire column. Yes, this is a capacitive digital-to-analog converter (DAC) coupled to different column outputs. This can be achieved using ), thus enabling the provision of digital configuration control.

[0091] Various embodiments are intended to compensate for the overall capacity mismatch of the column. Specifically When column scaling is determined by the relative ratio of the total capacity of the column, the parasitic capacity Discrepancies in comparison can lead to calculation errors. This is true in various embodiments. As discussed in the details, this can be overcome through one of several practical approaches.

[0092] For example, in some embodiments, careful layout and estimation of parasitic capacity are used. The necessary capacities are matched. In particular, the layout features that affect parasitic capacities are manufactured. Within the substrate or layers of a very large-scale integrated circuit (VLSI), or within the arrangement or periphery of the arrangement, It gets checked.

[0093] Column capacity settings and short circuits; column switches used to connect / disconnect between column capacities. This needs to be considered. As an example, this is a dummy MOSFET switch (statically (Can be kept on or off) and introduces the parasitic characteristics of the actual MOSFET switches in other columns. Either match the properties or adjust the shape of the MOSFET switches to achieve the intended ratio across the entire row. This can be achieved by maintaining rate scaling.

[0094] In the case of sampling, setting, and short-circuiting of auxiliary capacitance, the connection from the column to the auxiliary capacitance (and The layout of the surrounding features is matched, and the layout of the auxiliary capacity itself is also matched. This can be achieved by making them tweak.

[0095] Furthermore, a capacitive DAC is coupled to each column output to introduce linearly adjustable voltage attenuation. This may allow for possible capacity loading and correct for mismatches in parasitic capacity.

[0096] As described herein, some of the various embodiments involve each column or bit line This eliminates the need for the use of individual analog-to-digital converters (ADCs) and allows for multiple parallel connections. IMC Compute configured to obtain a display output of the calculation result for columns or bit lines This covers the architecture, apparatus, methods, and parts thereof of each building. Analog output signals associated with a line or column are transmitted to the IMC Computing Architecture. Rather than converting them into individual digital representations suitable for further processing within the texture, In various embodiments, an analog output signal associated with a bit line or column is used to perform this performs part of further processing, while maintaining the accuracy of the analog output signal (that is, A DC quantization error and other errors are reduced), the number of ADCs required to implement the functions of in-memory computing architecture is reduced.

[0097] The systems, methods, apparatuses, mechanisms, techniques, and portions thereof described herein with reference to various drawings may be subjected to various modifications, and such modifications are contemplated to be within the scope of the present invention. For example, in the various embodiments described herein, a specific order of steps or arrangement of functional elements is shown, but within the context of the various embodiments, various other orders / arrangements of steps or functional elements may be utilized. Further, modifications to the embodiments may be considered individually, and various embodiments may employ multiple modifications simultaneously or sequentially, or employ combined modifications, etc.

[0098] As mentioned above, although specific systems, apparatuses, methodologies, mechanisms, etc. are disclosed, it will be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. Accordingly, the subject matter of the present invention is not to be limited except in the spirit of the present disclosure. Furthermore, in interpreting the present disclosure, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" should be interpreted as referring to elements, components, or steps in a non-exclusive manner, which means the referenced elements, components, or steps coexist with other elements, components, or steps not explicitly mentioned ​To indicate that they can coexist, be used together, or be combined. Furthermore, the references described herein are also part of this application and are not fully described herein. The entire thing is incorporated through reference, as if it were already there.

[0099] Various embodiments incorporating the teachings of the present invention have been shown and described in detail herein, but If you are a proficient programmer, you can easily consider many other various embodiments that still incorporate these teachings. It is possible to consider this. Therefore, although the above applies to various embodiments of the present invention, Other embodiments and further embodiments of the present invention may be provided without departing from their basic scope. It is a good idea to devise a plan.

Claims

1. A device for scaling and aggregating multiple weighted data representation analog signals, Each analog signal is located within the in-memory computing (IMC) array of bit cells. Each includes a voltage associated with a plurality of coupled bit cell outputs, and the device, Multiple signal splitting circuits, where each signal splitting circuit scales according to its respective weighting value. To generate an output signal with weighted values, each weighted data representation is It includes multiple signal division circuits configured to process analog signals, During the measurement phase of the calculation, the output signal of the signal division circuit is the analog signal representing the weighted data. An analog-to-digital converter configured to generate a digital output representing the sum of the numbers. A device that is coupled to the input of an ADC (Automated DC).

2. The apparatus according to claim 1, wherein the signal division circuit includes a voltage division circuit.

3. Each bit cell output is provided through its respective output capacitor. The apparatus according to claim 1, wherein the signal division circuit includes a charge division circuit.

4. Each analog signal corresponds to a plurality of combined bits in the IMC array of the bit cell. This represents the total charge stored in the entire cell output capacitor. Each of the aforementioned plurality of signal division circuits has substantially the same total capacitance, and each output capacitor The denser is stored in the entire set of coupled bit cell output capacitors. In response to a portion of the stored charge moving to the output capacitor, the corresponding scale ring The apparatus according to claim 3, having a capacitance selected to provide a regulated output signal.

5. The claim states that the signal division circuit is integrated with the sample-and-hold circuit in the ADC. The apparatus described in item 2.

6. The analog signal includes N binary-weighted analog signals, and N is greater than 1. It is a large integer, and the device is Total capacity C, C / 2 Ｎ－１ The least significant bit (LSB) signal component with an output capacitor. A split circuit configured to process an LSB-represented analog signal, LSB signal Divider circuit and This is a most significant bit (MSB) signal splitting circuit that has a total capacitance C and an output capacitor of C. This is an MSB signal splitter circuit configured to process an MSB-represented analog signal. The apparatus according to claim 1, including ,

7. An LSB+1 signal splitting circuit comprising an output capacitor having a total capacitance C and a C / N ratio, wherein the The LSB signal splitter circuit is configured to process the LSB+1 representation analog signal, L SB+1 signal splitting circuit, Most significant bit (MSB) signal splitting circuit with total capacitance C and output capacitor C / 2 And, configured to process an MSB-represented analog signal, an MSB signal divider The apparatus according to claim 1, comprising a road.

8. At least some of the column of bit cells are determined by the rest of the column of bit cells The analog signals provided are scaled to the weights associated with the column. The first portion of the column of bit cells is separated from the remaining portion of the column of bit cells. The apparatus according to claim 3, wherein each disconnection switch for that purpose is arranged therein.

9. The remaining portions of the column of bit cells are joined together, thereby weighted It further comprises multiple switches configured to provide an analog signal representing the cumulative result. The apparatus according to claim 8.

10. Analog Scale for Capacitor-Based In-Memory Computing (IMC) A ring and aggregation device, wherein each bit cell in an N×M array of bit cells performs IMC The voltage levels associated with each weighted part of the calculation are assigned to each output capacitor. A bit cell output capacitor that provides the voltage level associated with the same weight and stores it in the sensor. The column "Sa" provides the respective weighted data representation analog signal for each weight. The device is coupled to the device, Multiple signal splitting circuits, where each signal splitting circuit scales according to its respective weighting value. To generate the output signal across each output capacitor with a measured capacitance value, Each weighted data representation of each row of the output capacitors in a set cell represents the analog signal. It includes multiple signal division circuits configured to process, During the measurement phase of the calculation, the output capacitor of the signal division circuit is used in the weighted data table. An analog system configured to generate a digital output from which the sum of the current analog signals is represented. - Coupled to a sample-and-hold circuit associated with the input of a digital converter (ADC) A device that can be used.

11. Each column of the weighted data representation analog signal is the respective batch of the cumulative result of the IMC calculation. The apparatus according to claim 10, which represents bits of Inari weighted data.

12. During the reset phase of the calculation, the data stored in each of the rows of bit cell output capacitors The charge is effectively removed, During the evaluation phase of the calculation, the charge stored in each of the rows of bit cell output capacitors However, it provides a contribution corresponding to the total charge of each of the aforementioned columns, During the measurement stage of the calculation, each of the weighted data representation analog signals is its weighted The cumulative result is scaled according to the bell and thereby processed by the ADC. The apparatus according to claim 11, which provides a weighting portion of an analog signal representing the analog signal.

13. Analog Scale for Capacitor-Based In-Memory Computing (IMC) A ring and aggregation device, wherein each bit cell in an N×M array of bit cells performs IMC The voltage levels associated with each weighted part of the calculation are assigned to each output capacitor. A bit cell output capacitor that provides the voltage level associated with the same weight and stores it in the sensor. The column "Sa" provides the respective weighted data representation analog signal for each weight. The device is coupled to the device, Multiple signal division circuits, each signal division circuit uses a successive approximation register (SAR) analog. Each output capacitor is selectively controlled by a digital converter (ADC). To generate the output signal for the entire system, each weighted data representation analog signal is processed. It includes multiple signal division circuits configured to include, During the reset phase of the calculation, the data stored in each of the rows of bit cell output capacitors The charge is effectively removed, During the evaluation phase of the calculation, the charge stored in each of the rows of bit cell output capacitors However, it provides a contribution corresponding to the total charge of each of the aforementioned columns, During the measurement step of the calculation, a switch in one or more of the row of bit cell output capacitors The mechanism is activated, disconnecting at least a portion of the bit cell output capacitor, and for each column... The remaining portion of the bit cell output capacitor reflects the weighted values ​​of the column. The remaining coupling capacitors in each row, having capacitance, are connected together to the input of the ADC. A device that is combined.

14. A device for scaling and aggregating multiple weighted data representation analog signals, Each weighted data representation analog signal is used in in-memory computing of bit cells ( The electron voltage provided by each column of combined bit cells in the IMC array. Including a current or electric charge, the apparatus is The analog signal provided by the rest of the column of bit cells is associated with the column. The first portion of the column of bit cells is scaled to the weighted weights Each of the disconnection switches within it is for separating the row of the pit cell from the rest of the row. At least some of the columns of the combined bit cells arranged in, The remaining parts of the bit cell column are joined together, thereby representing the cumulative result. A device comprising a switch configured to provide a log signal.

15. Each of the bit cells is an output capacitor for storing the charge indicating the bit cell operation. Includes, Each of the aforementioned bit cell columns is associated with its respective data weighting value, The apparatus described in item 14.

16. Each column is associated with the rest of the bit cell output capacitor, which is proportional to the weight of the column. The apparatus according to claim 15, which can be used.

17. Multiple parasitic capacitors configured to compensate for the weighted parasitic capacitance of the aforementioned disconnection switch Raw offset switch S ＰＯ The apparatus according to claim 15, further comprising:

18. The analog signal includes N binary-weighted analog signals, where N is greater than 1. An integer, and the device outputs each of the N combined bit cells in the IMC array. The apparatus according to claim 15, comprising a denser.

19. The aforementioned weighted data representation analog signal has at least the most significant bit (MSB) Binary weighted data representation of analog signals and binary weighting of the least significant bit (LSB) The apparatus according to claim 15, comprising an analog signal for data representation.

20. The weighted data representation analog signal is at least one additional binary weighted data The apparatus according to claim 19, further comprising a data-represented analog signal.

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