Text-input type hardware relay sequence simulation system

Abstract

This hardware relay sequence circuit simulation system eliminates the need to create specialized ladder diagrams, allowing users to quickly set circuit conditions through intuitive text input and easily simulate circuits. [Solution] The system includes an input processing module with a GUI-based text input interface that allows for intuitive setting of relay conditions. It analyzes the input data and converts it into an internal data structure (JSON format). The simulation engine simultaneously updates the state of all relays, considering the interactions between relays using a parallel evaluation method, accurately reproducing the behavior of an actual hardware relay circuit. The output processing module visualizes the simulation results on the GUI and saves them in JSON format. In addition, it includes auxiliary functions that automatically generate a text circuit diagram from the input data and detect logical errors and input inconsistencies.

Description

Technical Field

[0001] The present invention relates to the design and verification of hardware relay sequence circuits (hereinafter referred to as "circuits"), and particularly to a technology for inputting circuit conditions using a text-based user interface (UI) and simulating relay states by means of a parallel evaluation method. The system of the present invention can be used as a tool for designers and verifiers of switchboards and control panels to perform operation verification of relay circuits without drawing ladder diagrams.

[0002] A "hardware relay sequence circuit" is a circuit configured using actually wired relays and contacts, and is distinguished from control programs based on ladder diagrams in PLC (Programmable Logic Controllers). The simulation system of the present invention aims to reproduce the operation of physical relay circuits, rather than PLC control programs.

[0003] "Parallel evaluation" refers to a processing method in which the state and excitation conditions of each relay are calculated and updated simultaneously for the entire circuit, without depending on the processing order of individual relays. Conventional PLCs process programs one by one from top to bottom via a sequential scanning method, whereas the simulation engine of the present invention acquires the states of all relays in a batch and performs processing in parallel while considering the dependencies between each relay, thereby realizing simulation close to the simultaneous operation of an actual hardware relay sequence circuit.

Background Art

[0004] The design of hardware relay sequence circuits (hereinafter referred to as "circuits") is mainly performed using CAD (Computer-Aided Design). Designers use CAD software to create circuit diagrams, and output the design content to PDF or paper media for confirmation. It is also common to add handwritten notes or modify circuits on paper drawings during the design process and verification.

[0005] However, hardware relay sequence circuits are difficult to simulate as software programs, unlike PLCs (Programmable Logic Controllers). While PLC ladder diagrams can be emulated in dedicated development environments, physical relay circuits lack such environments, forcing designers to perform manual calculations in their minds or on paper drawings to predict circuit operation. Consequently, verifying circuit operation tends to be a highly subjective process, leading to inconsistencies in verification accuracy among designers. Because designers rely on experience and knowledge to perform verification, it becomes difficult to detect design errors, and as circuits become more complex, manual calculations become more cumbersome, increasing the likelihood of errors.

[0006] Due to this situation, many designers conduct actual hardware tests to check for malfunctions and make circuit modifications as needed. However, if a malfunction is discovered during hardware testing, the following rework occurs, leading to a longer design cycle and increased costs. 1) Consideration of countermeasures (analysis of the cause of the malfunction) 2) Circuit design modification (modification of CAD drawings) 3) Modification of the actual circuit (rewiring correction, relay replacement) 4) Retesting (verification after modifications) In particular, when the dependencies of the entire circuit are complex, modifying one relay may affect the operation of other relays, and the problem may not be solved with a single modification, requiring repeated testing and modifications. For this reason, relying on actual hardware testing makes the design inefficient and can lead to longer manufacturing times and increased costs. [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention aims to solve the problems of the prior art in the design and verification of hardware relay sequence circuits and to provide a more efficient and accurate simulation environment. Conventionally, designers had to verify the operation using paper drawings or in their minds, and design while predicting the possibility of malfunctions. Furthermore, there were many problems such as increased time and cost due to rework in actual equipment testing, reliance on individual expertise in verification, and the occurrence of design errors due to the complexity of circuit dependencies. The present invention aims to standardize and streamline the design and verification process of hardware relay sequence circuits by solving the following problems.

[0008] This invention reduces the burden on designers of conventional hardware relay sequence circuits, who typically perform operational verification in their minds or using paper diagrams. It provides an environment where simulations can be easily performed by intuitively inputting conditions. This invention provides a user interface (UI) that allows relay operating conditions to be set solely through text input, without requiring the creation of ladder diagrams or specialized programming knowledge. This creates an environment where anyone can perform simulations in a unified manner, regardless of the designer's experience or intuition.

[0009] Unlike the sequential scanning method of PLCs, this method evaluates the state of all relays in parallel, enabling a simulation that closely resembles the simultaneous operation of an actual hardware relay circuit. Conventional PLC simulations use a sequential scanning method, evaluating the state of relays from top to bottom, and therefore cannot accurately reproduce the operation of parallel relays. This invention adopts a parallel processing method that considers the dependencies of the entire circuit and evaluates and updates all relays simultaneously, enabling a simulation that closely resembles the behavior of an actual hardware relay circuit. As a result, malfunctions and race conditions caused by parallel operation, which were difficult to detect with conventional PLC simulations, can be detected in advance.

[0010] The system outputs configuration data and simulation results in JSON format, enabling automatic circuit analysis and optimization through integration with external AI analysis tools. This invention allows for easy integration with other tools and AI systems by outputting simulation configuration data and results in JSON (JavaScript Object Notation) format. This enables AI analysis of simulation results, allowing for malfunction detection, circuit optimization, and automatic circuit correction suggestions. Furthermore, recording in JSON format facilitates design history management and comparison with past data, enabling reproducible design verification.

[0011] This invention features an automatic input checking function and an auxiliary function that automatically generates a text circuit diagram from the input content, reducing user errors and improving the visibility of the design. The invention analyzes the relay conditions and dependencies entered by the user, automatically detects input errors (e.g., reference to a non-existent device, conflicting logic conditions, incorrect timer settings, etc.), and provides real-time warnings. Furthermore, it automatically generates a circuit diagram in text format based on the input relay circuit settings, allowing the user to visually confirm the input content. This makes it easier to detect design errors in advance and prevents malfunctions before actual testing. [Means for solving the problem]

[0012] The simulation system according to the present invention was developed with the aim of improving efficiency and accuracy in the design and verification of hardware relay sequence circuits. This system combines a text-based user interface (UI) that allows relay circuits to be defined and verified without creating ladder diagrams with a simulation engine that performs parallel evaluations, and comprises the following components.

[0013] 1. Input Processing Module The user inputs information for each relay (device name, relay type, timer setting, excitation conditions) line by line using text boxes or list boxes on the GUI. Here, "excitation conditions" are identifiers that indicate the state of the contacts and coils of each relay, in the format of, for example, "43MYa" or "43AXb," and can be expressed as logical expressions such as AND or OR conditions. The input data is parsed based on a proprietary description grammar specifically for relay circuits and converted into structured data such as JSON format. In addition, an automatic input check function is included, and if formatting errors or logical inconsistencies are detected, a warning is displayed to the user to ensure data integrity. This prevents design errors and improves the reliability of the design process.

[0014] 2. Simulation Engine Based on the input configuration data, the current status of all relays is acquired simultaneously. The excitation conditions (logical conditions and timer settings) of each relay are evaluated in parallel, and the status of all relays is updated simultaneously. Unlike the sequential scan method of conventional PLCs, this parallel evaluation method calculates and updates the status of all relays at the same time, thus more accurately reproducing the simultaneous parallel operation of actual hardware relays. Furthermore, the evaluation process is repeated for a certain period of time (e.g., 10 seconds) until the interactions within the circuit have completely converged. This approach allows for the detection of race conditions and the effects of parallel operation in advance, which are often overlooked in conventional simulation methods.

[0015] 3. Output Processing Module The simulation results are graphically displayed as a time chart showing the state changes of each relay over time. The operating states of each relay's coil (ON / OFF), NO contact (a-contact), and NC contact (b-contact) are also visually displayed on the GUI. Furthermore, the input settings and simulation results are output as a JSON data file, enabling integration with external AI analysis tools and other systems. This JSON data allows for automated analysis for circuit anomaly detection and optimization. Additionally, accumulating simulation results facilitates easy comparison and verification with past operating history. In particular, the ability to visually confirm the coil, NO (a-contact), and NC (b-contact) states on the GUI allows for more intuitive understanding compared to traditional paper diagrams or mental verification.

[0016] 4. Auxiliary functions This feature automatically generates circuit diagrams in text format based on text data entered by the user. For example, a text circuit diagram like the following is generated. ─┬─"1a"─"2a"─┬─[TEST](Control Relay) ├─"3a"─"4a"─┤ └─"5a"────┘ This allows users to intuitively see the circuit configuration resulting from their input. Furthermore, the input check function proactively detects input errors and logical inconsistencies, prompting quick corrections. This feature improves the visibility of the design, enabling more intuitive circuit design and verification.

[0017] 5. Streamlining CAD integration This system employs a method where designers input only the necessary circuit information as text while referring to circuit diagrams (PDF or paper) created with conventional CAD software. This avoids the complex analysis processes required for importing CAD data, enabling a rational design and verification flow in the field. Furthermore, by outputting simulation results as JSON data, future integration with CAD software is also possible. [Effects of the Invention]

[0018] According to the present invention, the following effects can be obtained. 1. Improved operability and reduced learning cost Since professional ladder diagram creation is not required, and a user can quickly set circuit conditions through intuitive text input, no specialized knowledge is required. In particular, even engineers who do not have knowledge of PLC programming or ladder diagram creation, and design beginners can easily perform circuit simulation by using the present system.

[0019] 2. Rapid design verification and flexible modification Since editing via text input is easy, changes and corrections to circuit design can be quickly reflected. Additionally, adding or deleting relays and changing connection conditions can be easily performed, resulting in a higher degree of freedom for design modifications compared to conventional ladder diagram editing. Furthermore, the automatically generated text circuit diagram allows visual confirmation of the consistency of input content, enabling early detection of incorrect inputs.

[0020] 3. Accurate simulation close to an actual device By means of a parallel evaluation method, the states of all relays are updated simultaneously, and a simulation result close to the simultaneous parallel operation of an actual hardware relay circuit can be obtained. This allows competing conditions (race conditions) and logical contradictions, which were difficult to detect with the sequential scanning method of conventional PLC simulation, to be discovered in advance. The high-precision evaluation method of the present system is particularly useful in circuit designs where a plurality of relays mutually influence each other.

[0021] 4. Realization of external linkage and automatic analysis Outputting data in JSON format facilitates linkage with external AI analysis tools, enabling automatic optimization and anomaly detection based on simulation results. Utilizing AI analysis contributes to improving design quality by identifying problems in a shorter time compared to conventional manual circuit review. Furthermore, JSON-format data has high compatibility with other design and analysis tools, making future system expansion and cloud linkage easy to realize.

[0022] 5. Prevention of personal dependence and labor saving measures Since it does not require specialized knowledge, it prevents reliance on individual expertise caused by conventional design methods that depend on ladder diagram creation, and can be used by a wide range of user groups. Accordingly, even new hires and less experienced engineers can efficiently perform design and verification work without relying on the knowledge of veteran engineers. Furthermore, even in manufacturing sites where labor reduction is demanded, design and verification can be completed in a shorter time with fewer personnel compared to conventional design processes.

[0023] 6. Rational linkage with CAD design By adopting a method where only necessary circuit information is input as text while referencing a circuit diagram designed by CAD, the present invention avoids the difficulties associated with conventional CAD data analysis and implements a rational design and verification flow. In conventional methods, format differences or data loss may occur when converting CAD data for simulation software, but the present system avoids such problems and minimizes the workload of designers. In addition, since designers can check simulation results while directly comparing them against the circuit diagram on CAD, this contributes to reducing design errors and shortening design time. MODE FOR CARRYING OUT THE INVENTION

[0024] The present invention relates to a system that simulates hardware relay sequence circuits (hereinafter referred to as "circuits") in switchboards and control panels, and particularly relates to a technology that inputs circuit conditions using a text-based user interface (UI) and simulates the state of relays by means of a parallel evaluation method. The present system is a simulation system that operates on a computer, and is provided with a processing engine that analyzes and updates states in parallel, rather than sequentially evaluating relay states based on circuit conditions input by a user. This makes it possible to reproduce operations close to those of an actual hardware relay circuit, and quickly perform malfunction verification and design improvement. The system of the present invention includes at least the following constituent elements.

[0025] 1. Input processing module Users input the settings for each relay using a text input UI while referring to circuit diagrams (PDF or paper) designed with conventional CAD. The input data is parsed according to a predefined proprietary grammar and converted into internal data (JSON format). It also features an automatic input check function that displays a warning to the user if formatting errors or logical inconsistencies are detected, allowing for prompt correction. This input processing module reduces the burden of manual calculations on traditional paper drawings, enabling rapid circuit input and editing digitally.

[0026] 2. Simulation engine processing This system analyzes the state of all relays simultaneously based on the input circuit conditions and evaluates the excitation conditions (logical conditions and timer settings) of each relay in parallel. This evaluation employs a parallel evaluation method, where the state of all relays is calculated and updated simultaneously, rather than a sequential scan method, thereby reproducing behavior close to that of an actual hardware relay circuit operating simultaneously. The simulation engine continues iterative processing until the state of the entire circuit converges to a stable state with logical consistency. While conventional PLC simulations using sequential evaluation (scan method) sometimes fail to fully reproduce relay interactions, this invention enables highly accurate circuit simulation through parallel evaluation.

[0027] 3. Output and External Integration The simulation results are graphically displayed as a time chart showing the state changes of each relay over time. Furthermore, the operating states of each relay's coil (ON / OFF), NO contact (a-contact), and NC contact (b-contact) are visually displayed on the GUI. In addition, the input settings and simulation results are output as a JSON data file, enabling integration with external AI analysis tools and other systems. This JSON data allows for automated analysis for circuit anomaly detection and optimization. This output function goes beyond simple simulation, facilitating design improvement and error analysis through integration with external systems. In particular, the ability to visually confirm the states of the coil, NO (a-contact), and NC (b-contact) on the GUI allows for more intuitive understanding compared to traditional paper drawings or mental verification.

[0028] 4. Implementation of support functions This system features a function that automatically generates circuit diagrams in text format based on text data entered by the user. This allows users to intuitively confirm the circuit configuration based on their input. Furthermore, an input validation function prevents input errors and logical inconsistencies, ensuring design consistency. This auxiliary function reduces input errors and improves circuit visibility, thereby solving the challenges of traditional manual circuit design. [Examples]

[0029] The system of the present invention operates on a general personal computer (PC), allowing the user to set the conditions of a relay sequence circuit using a GUI and perform simulation using a parallel evaluation method. In this embodiment, the system of the present invention is implemented in Python, and Tkinter is used for the GUI (Graphical User Interface), but the present invention can also be implemented using other programming languages ​​or GUI toolkits (e.g., C++ / Qt, Java / Swing, C# / WPF, etc.). This embodiment includes the following main modules.

[0030] 1. Input Processing Module The user inputs information for each relay using an input form on the GUI, while referring to a drawing (PDF or paper document) of the hardware relay sequence circuit designed with CAD. In this embodiment, instead of the user directly inputting AND or OR conditions, logical conditions are set through a selection UI on the GUI. The entered conditions are internally structured as data and used for logical analysis. The input data is converted into a JSON data structure and used by the simulation engine. In addition, an input validation function detects the following errors and provides feedback to the user on the GUI. • Identifier error (e.g., the device name does not have an appropriate identifier such as a, b, sa, or ra appended to the end) • Reference to a non-existent device • Logical inconsistency (e.g., a contradiction in simultaneously turning on both the a-contact and b-contact of the same device) This input processing structures the data in a way that is suitable for simulation, and this data is then used in subsequent parallel evaluation processes.

[0031] 2. Simulation Engine This implementation introduces a simulation engine that evaluates the state of all relays in parallel based on the input circuit conditions. In this embodiment, Python data structures (dictionaries and lists) are used to manage the state and dependencies of each relay. Overview of the simulation process 1) List the current status of all relays. 2) Evaluate the excitation conditions for each relay. The GUI evaluates logical expressions, including AND OR conditions and timer settings. 3) Update the status of all relays in parallel. 4) Continue the simulation until the overall state stabilizes. This system uses a parallel evaluation method to simultaneously evaluate the state of all relays and simulate the simultaneous operation of hardware.

[0032] 3. Output of simulation results This system outputs simulation results in the following three formats. 1) Display of operating status on the GUI The status of each relay's coil, NO (normally open), and NC (normally closed) contacts are displayed on the GUI, allowing you to check their operating status in real time. 2) Generation of a time chart Based on the simulation results, the state changes of each relay are plotted on a time axis. The time chart visually shows the ON / OFF states of the coil, NO (normally open contact), and NC (normally closed contact). 3) JSON format data file Input data and simulation results are saved in a JSON file, allowing for integration with external systems and AI analysis tools.

[0033] 4. Generating a text-based circuit diagram The text circuit diagrams generated by this system follow the following notation rules. 1) Expression of contact point The type of contact is added after the device name, such as 1a (normally open contact), 2b (normally closed contact), sa (set contact), ra (reset contact), etc. example: ─┬─"1a"─"2sa"──┬─[TEST](Control Relay) ├─"3sa"─"4a"──┤ └─"5ra"─────┘ 2) Representation of coils The relay coil is indicated in square brackets [ ], as in [TEST], followed by the relay type. 3) Expression of logical conditions AND conditions are represented by inserting a ─ between the contacts, and OR conditions are represented by ├ ┤. ─"1a"─"2b"─[TEST](Control Relay) / AND Condition (Series) ├─"3a"─"4a"─┤[TEST](Control Relay) / OR Condition (Parallel) 4) Automatic generation of text circuit diagrams Based on the relay conditions entered via the GUI, a text circuit diagram is automatically generated in the format described above. This allows the user to visually confirm the logical structure of the entire circuit.

[0034] 5. External Integration Function This embodiment provides a function to analyze data output in JSON format in conjunction with an external AI system. Specifically, it performs the following analysis: 1) Circuit malfunction detection 2) Optimization proposals (simplification of logic and reduction of connections) 3) Automatic generation of operation descriptions The system of the present invention enables a reduction in design burden and an improvement in design quality compared to conventional relay sequence circuit design. [Industrial applicability]

[0035] The system of the present invention is applicable to the design and verification of hardware relay sequence circuits in power distribution boards and control panels, and contributes to reducing the burden on designers and improving design accuracy in fields such as verification of control circuits for industrial equipment, power control systems, and manufacturing lines.

[0036] Conventional hardware relay sequence circuits require operational verification through actual hardware testing or manual calculations on paper drawings, resulting in time-consuming and costly corrections for malfunctions. This invention utilizes a text-based interface and a parallel evaluation method to enable simulation before actual hardware testing, thereby reducing design rework.

[0037] This system is software that runs on a PC, is not dependent on specific hardware, and can be easily integrated with existing design environments. Furthermore, by linking the simulation data output in JSON format with AI analysis tools, it becomes possible to automate the optimization and anomaly detection of relay sequence circuits.

[0038] Thus, the system of the present invention is expected to be used as a standard tool in the design process of power distribution boards and control panels, and will also streamline the verification work of hardware relay sequence circuits in fields such as industrial equipment, power control, and manufacturing lines, thereby contributing to reducing the burden on engineers and improving design quality.

Claims

1. A system for simulating hardware relay sequence circuits (hereinafter referred to as "circuits") in distribution boards and control panels, As an input processing method, the user inputs the device name, relay type, timer settings, and excitation conditions using a GUI, and the input data is analyzed and converted into an internal data format (such as JSON format). As a simulation processing means, a means for evaluating the state of all relays in parallel based on input data and updating the state while considering the interactions between relays, As an output processing method, the simulation results are displayed on a GUI and saved as a data file in JSON format. As auxiliary processing means, means for automatically generating a text circuit diagram based on input data, and means for detecting input errors and logical inconsistencies. A hardware relay sequence circuit simulation system characterized by comprising the following features.

2. A hardware relay sequence circuit simulation system according to claim 1, characterized in that the simulation processing means acquires the current state of all relays, analyzes the logic conditions and timer conditions between relays, and updates the state of all relays at the same time using a parallel evaluation method.

3. A hardware relay sequence circuit simulation system according to claim 1 or 2, characterized in that the output processing means can display the simulation results on a GUI as the state of the relay coil, NO (normally open contact), and NC (normally closed contact).

4. A hardware relay sequence circuit simulation system according to any one of claims 1 to 3, characterized in that the auxiliary processing means has a function to analyze the connection relationships of relay contacts and coils based on user input data and to automatically generate a text circuit diagram.

5. A hardware relay sequence circuit simulation system according to any one of claims 1 to 4, characterized in that the output processing means has a function to plot the simulation results on a time axis and output a time chart that visualizes the operating state of each relay.

6. A hardware relay sequence circuit simulation system according to any one of claims 1 to 5, characterized in that the output processing means has a function to perform circuit malfunction detection and optimization suggestions in cooperation with an external AI analysis tool to output simulation results in JSON format.

7. A hardware relay sequence circuit simulation system according to any one of claims 1 to 6, characterized in that the auxiliary processing means has a function to check whether an appropriate identifier (a, b, sa, ra, etc.) is appended to the end of the relay contact name entered by the user, and to warn of incorrect input.

8. A hardware relay sequence circuit simulation system according to any one of claims 1 to 7, characterized in that the simulation processing means includes a function to improve simulation accuracy by analyzing the dependencies between relays and dynamically determining the evaluation order of each relay.

9. A hardware relay sequence circuit simulation system according to any one of claims 1 to 8, characterized in that the simulation processing means has a function to repeatedly execute the simulation a certain number of times and continue evaluation until the state of the entire circuit converges to a stable state.