Semiconductor equipment

Abstract

To provide a semiconductor device with suppressed parasitic capacitance. [Solution] In a semiconductor device, the transistor comprises a first diffusion layer region 11 and a second diffusion layer region 12 provided on a semiconductor substrate spaced apart in the plane direction of the semiconductor substrate, a gate insulating film 13 provided on the semiconductor substrate and at least a portion of which is located in the region between the first diffusion layer region and the second diffusion layer region, a gate electrode 10 located on the side of the semiconductor substrate opposite to the gate insulating film, a first base conductive region 20 provided on the side of the semiconductor substrate opposite to the first diffusion layer region and in the plane direction of the semiconductor substrate, a first connecting conductive region 21 connected to the first base conductive region, a second base conductive region 22 provided on the side of the semiconductor substrate opposite to the second diffusion layer region and in the plane direction of the semiconductor substrate, and a second connecting conductive region 22 connected to the second base conductive region, wherein the height of at least one of the first base conductive region and the second base conductive region is equal to or lower than the height of the gate electrode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device. [Background Art]

[0002] A semiconductor device including a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate is known. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2018-049968 [Summary of Invention] [Problem to be Solved by the Invention]

[0004] An object of one embodiment is to provide a semiconductor device capable of reducing parasitic capacitance. [Means for Solving the Problem]

[0005] The semiconductor device of the embodiment has a semiconductor substrate. The semiconductor device has a first diffusion layer region and a second diffusion layer region provided on the semiconductor substrate spaced apart in the direction of the semiconductor substrate plane. The semiconductor device has a gate insulating film provided on the semiconductor substrate, at least a portion of which is located in the region between the first diffusion layer region and the second diffusion layer region. The semiconductor device has a gate electrode located on the opposite side of the gate insulating film from the semiconductor substrate. The semiconductor device has a first base conductive region provided on the opposite side of the semiconductor substrate from the first diffusion layer region and extending in the direction of the semiconductor substrate plane. The semiconductor device has a first connecting conductive region provided connected to the first base conductive region. The semiconductor device has a second base conductive region provided on the opposite side of the semiconductor substrate from the second diffusion layer region and extending in the direction of the semiconductor substrate plane. The semiconductor device comprises a second connecting conductive region provided connected to the second base conductive region. The height of at least one of the first base conductive region and the second base conductive region is equal to or lower than the height of the gate electrode. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a partial cross-sectional view showing a transistor provided in the semiconductor device. [Figure 3] Figure 3 is a plan view showing an example of a planar layout of the transistor. [Figure 4] Figure 4 is a plan view showing the planar layout of the transistor according to the second embodiment. [Figure 5] Figure 5 is a partial cross-sectional view illustrating the problems in the comparative transistor. [Figure 6] Figure 6 is a plan view illustrating the problems in the comparative transistor. [Figure 7A] Figure 7A is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 7B] Figure 7B is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 7C] Figure 7C is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 7D] Figure 7D is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8A] Figure 8A is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8B] Figure 8B is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8C] Figure 8C is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8D] Figure 8D is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8E] Figure 8E is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8F] Figure 8F is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 8G] Figure 8G is an explanatory diagram showing the process of forming a transistor on a semiconductor substrate. [Figure 9] Figure 9 is a cross-sectional view showing an example of the configuration of a transistor provided in a semiconductor device of the third embodiment. [Figure 10] Figure 10 is an explanatory diagram illustrating the process for manufacturing the planar layout transistor shown in Figure 4. [Figure 11] Figure 11 is an explanatory diagram showing an example of a cross-sectional structure in a transistor with a planar layout as shown in Figure 4. [Modes for carrying out the invention]

[0007] Hereinafter, the semiconductor device according to the first embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Redundant descriptions of these components may be omitted. The terms "parallel", "perpendicular", and "the same" may each include cases of "substantially parallel", "substantially perpendicular", and "substantially the same". The term "connection" is not limited to mechanical connection, and may include electrical connection. That is, the term "connection" is not limited to the case where a plurality of elements are directly connected, and may include the case where a plurality of elements are connected with another element interposed therebetween. The term "facing" means that two members overlap when viewed in a certain direction, and may also include the case where another member exists between the two members.

[0008] First, the X direction, Y direction, and Z direction will be defined. The X direction and the Y direction are directions along the surface of the semiconductor substrate 2 described later (see FIG. 1). The X direction is a direction from the first diffusion layer region (source region) 11 toward the second diffusion layer region (drain region) 12 in the first transistor 5 described later (see FIG. 2). The Y direction is a direction that intersects (for example, is perpendicular to) the X direction. The Z direction is a direction that intersects (for example, is perpendicular to) the X direction and the Y direction. The Z direction is the thickness direction of the semiconductor substrate 2. In the following description, the side where the transistor Tr is located with respect to the semiconductor substrate 2 may be referred to as "upper", and the opposite side may be referred to as "lower". However, these expressions are for convenience and do not define the direction of gravity.

[0009] (First Embodiment) <1. Configuration Example of Semiconductor Device> FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 is, for example, a semiconductor memory device such as a NAND flash memory. The semiconductor device 1 includes, for example, an array chip AC and a circuit chip CC.

[0010] The array chip AC is a chip capable of storing information. The array chip AC includes, for example, a stacked body LB, a plurality of memory pillars MP, a plurality of source lines SL, and a plurality of bit lines BL. The stacked body LB includes a plurality of word lines WL and a plurality of insulating layers IL. The plurality of word lines WL and the plurality of insulating layers IL are alternately stacked one layer at a time in the Z direction. Each of the plurality of source lines SL extends in the X direction, and the plurality of source lines SL are arranged at predetermined intervals in the Y direction. Each of the plurality of bit lines BL extends in the Y direction, and the plurality of bit lines BL are arranged at predetermined intervals in the X direction. Each of the plurality of word lines WL has a layered shape extending in both the X direction and the Y direction, and forms the stacked body LB by being alternately stacked with the insulating layers IL. The periphery of the stacked body LB is also covered with an insulating layer.

[0011] The plurality of memory pillars MP penetrate the stacked body LB and extend in the Z direction. Each memory pillar MP includes, from the center toward the outer peripheral side of the memory pillar MP, an insulating portion, a channel layer, a tunnel insulating film, a charge storage portion, and a block insulating film. One end of each memory pillar MP is connected to the source line SL. The other end of each memory pillar MP is connected to the bit line BL. A memory cell transistor MC is formed at the intersection of each memory pillar MP and each word line WL. The memory cell transistor MC is a storage element capable of storing information by accumulating electric charges.

[0012] The circuit chip CC has a control circuit that controls the operation of the array chip AC. The circuit chip CC includes, for example, a semiconductor substrate 2, a plurality of transistors Tr, and a plurality of wirings L. The plurality of transistors Tr1 are provided on the semiconductor substrate 2. An insulating layer covering each wiring is formed on the semiconductor substrate 2. Each wiring L connects the transistor Tr1 and the array chip AC via a contact formed on the upper surface of the insulating layer.

[0013] <2. Configuration of Semiconductor Substrate and Transistor> Next, the configurations of the semiconductor substrate 2 and the transistor Tr1 will be described in detail. <2.1 Semiconductor Substrates> Figure 2 is a cross-sectional view showing one example configuration of a semiconductor substrate 2 and transistor Tr1. The semiconductor substrate 2 is, for example, a silicon substrate containing single-crystal silicon. One or more element isolation insulating regions, formed of an insulator such as silicon oxide, are provided in a part of the upper layer of the semiconductor substrate 2. A transistor Tr1 is provided in the region of the upper layer of the semiconductor substrate 2 that is surrounded by the element isolation regions.

[0014] Note that the cross-section shown in Figure 2 only shows the upper layer region near the surface of the semiconductor substrate 2, and the element isolation and insulation region is formed from the surface of the semiconductor substrate 2 in the depth direction (-Z direction) to a predetermined depth of the semiconductor substrate 2. In Figure 2, the element isolation and insulation region is omitted, and only the cross-sectional structure of transistor Tr1 formed in the region surrounded by the element isolation and insulation region is shown. Also, in Figure 2, the element isolation and insulation region is omitted, and in Figures 1 and 2, the main part of transistor Tr1 formed in the activation region within the region surrounded by the element isolation region is shown.

[0015] <2.2 Transistors> In the semiconductor device 1 shown in Figure 1, a transistor Tr1 is formed on the surface layer of the semiconductor substrate 2, as shown in the cross-sectional structure in Figure 2. In this example, transistor Tr1 is a field-effect transistor, such as a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor).

[0016] Transistor Tr1 has, for example, a gate electrode 10, a source region (first diffusion layer region) 11, a drain region (second diffusion layer region) 12, a gate insulating film 13, silicide layers 15 and 16, and insulating sidewalls 19. Transistor Tr1 has a first base electrode (first base conductive region) 20 and a first contact electrode (first connection conductive region) 21 on the silicide layer 15. Transistor Tr1 has a second base electrode (second base conductive region) 22 and a second contact electrode (second connection conductive region) 23 on the silicide layer 16.

[0017] Source region 11 is an example of a "first diffusion layer region." Drain region 12 is an example of a "second diffusion layer region." However, drain region 12 may be an example of a "first diffusion layer region," and source region 11 may be an example of a "second diffusion layer region."

[0018] The source region 11 and the drain region 12 are formed by means of ion implantation or other means to a certain depth from the upper surface of the semiconductor substrate 2. The source region 11 and the drain region 12 are formed in a region that is insulated from other regions in a planar view by the aforementioned element isolation region (not shown). The source region 11 and the drain region 12 are arranged with a predetermined distance between them in the X direction, as shown in Figure 2. The source region 11 and the drain region 12 are formed spaced apart in the planar direction (X direction in Figure 2) of the upper surface of the semiconductor substrate 2. In this example, the silicide layer 15 is embedded in the upper part of the source region (first diffusion layer region) 11. In this example, the silicide layer 16 is embedded in the upper part of the drain region (second diffusion layer region) 12.

[0019] As shown in Figure 2, a gate insulating film 13 is formed on the semiconductor substrate 2 above the area between the source region 11 and the drain region 12. A gate electrode 10 is placed on the gate insulating film 13. In this example, the gate electrode 10 has a predetermined width in the X direction and a predetermined thickness (predetermined height) in the Z direction, and is rectangular in plan view. As shown in Figure 2, the gate electrode 10 has insulating side walls 19 on both the left and right sides in the X direction, sandwiching the gate electrode 10 from the left and right. An extension 13A of the insulating film constituting the gate insulating film 13 is interposed between the gate electrode 10 and the insulating side walls 19. The gate insulating film 13 is formed in a concave shape as shown in the cross-section of Figure 2, by combining the portion that contacts the upper surface of the semiconductor substrate 2 and the extension 13A that contacts the side surface of the gate electrode 10. In addition, although not shown in Figure 2, it is preferable that a high dielectric constant material layer is interposed between the gate insulating film 13 and the gate electrode 10. When a high dielectric constant material layer is provided, it may be arranged on the bottom side and the side side of the gate electrode 10 in the cross-section shown in Figure 2.

[0020] The silicide layer 15 is formed on the upper part of the source region 11, and is thinner than the source region 11. The silicide layer 15 includes, for example, a nickel-platinum silicide layer (NiPtSi layer). The silicide layer 15 is formed, for example, by supplying metallic elements such as nickel (Ni), platinum (Pt), or cobalt (Co) to the source region 11 and thermally diffusing these metallic elements towards the semiconductor substrate. The silicide layer 16 is formed on the upper part of the drain region 12, and is thinner than the drain region 12. The silicide layer 16 contains the same material as the material that makes up the silicide layer 15.

[0021] In the structure shown in Figure 2, an insulating layer 25 is provided on the semiconductor substrate 2 around the insulating side wall 19. The silicide layer 15 has a first base electrode (first base conductive region) 20 surrounded by an insulating layer 25. The first base electrode 20 is formed to be in close contact with the upper surface of the silicide layer 15. The thickness (height) of the first base electrode 20 is lower than the thickness (height) of the gate electrode 10. Therefore, the side and top surfaces of the first base electrode 20 are covered by the insulating layer 25. In the example shown in Figure 2, the insulating layer 25 is formed to be thicker than the first base electrode 20, but it is also acceptable for the insulating layer 25 to be thinner than the first base electrode 20.

[0022] The silicide layer 16 has a second base electrode (second base conductive region) 22 surrounded by an insulating layer 25. The second base electrode 22 is formed to be in close contact with the upper surface of the silicide layer 16. The thickness (height) of the second base electrode 22 is lower than the thickness (height) of the gate electrode 10. Therefore, the side and top surfaces of the second base electrode 22 are covered by the insulating layer 25. In the example shown in Figure 2, the insulating layer 25 is formed to be thicker than the second base electrode 22, but it is also acceptable for the insulating layer 25 to be thinner than the second base electrode 22. The thickness (height) of the first base electrode 20 and the second base electrode 22 is preferably equal to or lower than the thickness (height) of the gate electrode 10.

[0023] The side and top surfaces of the first base electrode 20 are coated with a coating layer 26 containing the metal element used to form the silicide layer 15. The side and top surfaces of the second base electrode 22 are coated with a coating layer 27 containing the metal element used to form the silicide layer 16. In detail, an insulating layer 25 is formed to cover the side coating layer 26 and the top coating layer 26 of the first base electrode 20. Furthermore, an insulating layer 25 is formed to cover the side coating layer 27 and the top coating layer 27 of the second base electrode 22.

[0024] The gate electrode 10 is made of a metal such as tungsten, for example, but it may also be a semiconductor layer such as polysilicon or a laminated structure of a semiconductor layer and a metal layer. The insulating sidewall 19 is formed of, for example, a silicon nitride film or a silicon oxide film. The insulating sidewall 19 is located outside the gate electrode 10 when viewed from the center of the transistor Tr1 (center of the gate electrode 10). If a high dielectric constant material layer is provided between the gate electrode 10 and the insulating sidewall 19, the insulating sidewall 19 is located outside the high dielectric constant material layer, and the insulating sidewall 19 is in close contact with the high dielectric constant material layer. In the region close to the source region 11, the bottom of the insulating sidewall 19 covers a part of the source region 11. In the region close to the drain region, the bottom of the insulating sidewall 19 covers a part of the drain region 12. There are no particular restrictions on the height of the insulating sidewall 19 in the Z direction. The insulating sidewall 19 may be formed to a height that covers part or all of the side surface of the gate electrode 10.

[0025] The insulating layer 25 is made of a silicon nitride film or the like. The insulating layer 25 is provided so as to cover the transistor Tr1, the semiconductor substrate 2, etc. In the configuration shown in Figure 2, the insulating layer 25 located around the insulating sidewall 19 is formed to be thicker than the insulating layer 25 covering the first base electrode 20 and the second base electrode 22. A protrusion 25A is formed in the insulating layer 25 in the region close to the insulating sidewall 19, and this protrusion 25A is formed to be the same thickness (height) as the insulating sidewall 19.

[0026] An insulating layer 28 is laminated on top of the insulating layer 25. This insulating layer 28 covers the upper surface of the insulating layer 25 and is formed to be thicker than the insulating layer 25. The insulating layer 28 covers the insulating layer 25 and is also formed to cover the upper surface of the gate electrode 10, the upper surface of the extension 13A of the gate insulating film 13, and the upper surface of the insulating side wall 19. A first contact electrode (first connecting conductive region) 21 is formed on the first base electrode 20. The first contact electrode 21 penetrates the upper part of the insulating layer 25 and the insulating layer 28 in the Z direction and is electrically connected to the first base electrode 20. A second contact electrode (second connecting conductive region) 23 is formed on the second base electrode 22. The second contact electrode 23 penetrates the upper part of the insulating layer 25 and the insulating layer 28 in the Z direction and is electrically connected to the second base electrode 22. The insulating layer 28 is made of a silicon oxide film or the like.

[0027] The first contact electrode 21 has a metal coating layer 30 on its side surface. The coating layer 30 contains a metal such as titanium nitride (TiN). The coating layer 30 covers the side surface of the first contact electrode 21. The coating layer 30 may be made from the same metal used to construct the silicide layer 15. The second contact electrode 23 has a metal coating layer 31 on its side surface. The coating layer 31 contains a metal such as titanium nitride (TiN). The coating layer 31 covers the side surface of the second contact electrode 23. The coating layer 31 may be made from the same metal used to construct the silicide layer 16.

[0028] <2.2 Planar layout of the transistor in the first embodiment> Up to this point, the cross-sectional structure of transistor Tr1 has been explained with reference to Figure 2, but an example of a planar layout of transistor Tr1 is shown in Figure 3. As shown in Figure 3, the transistor Tr1 of the first embodiment has a rectangular silicide layer 15 and a first base electrode 20 connected to the source region 11. The silicide layer 15 and the first base electrode 20 are rectangular in plan view, with a length in the Y direction longer than the length in the X direction. The silicide layer 15 and the first base electrode 20 extend longitudinally in the Y direction. Two first contact electrodes 21 are connected to the first base electrode 20, spaced apart in the Y-axis direction. As shown in Figure 3, the transistor Tr1 of the first embodiment has a rectangular silicide layer 16 and a second base electrode 22 connected to the drain region 12. The silicide layer 16 and the second base electrode 22 are rectangular in plan view, with a length in the Y direction longer than the length in the X direction. The silicide layer 16 and the second base electrode 22 extend longitudinally in the Y direction. Two second contact electrodes 23 are connected to the second base electrode 22, spaced apart in the Y-axis direction.

[0029] As shown in Figure 3, transistor Tr1 has a gate electrode 10 sandwiched between a source region 11 and a drain region 12 in plan view. In this example, the gate electrode 10 has a rectangular shape in plan view, which is longer in the Y direction than in the X direction. One end of the gate electrode 10 in the Y direction in plan view extends through the region between the source region 11 and the drain region 12 to slightly outside that region. At this extended end, a square-shaped connection portion 10A in plan view is formed, whose width in the X direction is greater than that of the gate electrode 10. As previously described, the gate electrode 10, which is provided between the source region 11 and the drain region 12, has insulating side walls 19 on both sides in the X direction. According to the plan view layout shown in Figure 3, these insulating side walls 19 extend around the connection portion 10A on the gate electrode 10.

[0030] The other end of the gate electrode 10 in the Y direction in plan view has an extension 10B that passes through the region between the source region 11 and the drain region 12 and extends slightly outside that region. The aforementioned insulating side wall 19 is formed on the gate electrode 10 so as to surround the extension 10B in plan view. A third contact electrode 33, extending in the Z direction, is connected to the connection portion 10A of the gate electrode 10. Since the cross-section along the line A1-A2 shown in Figure 3 corresponds to Figure 2, the third contact electrode 33 is not depicted in Figure 2.

[0031] As described above, the transistor Tr1 can adjust the amount of current flowing between the drain region 12 and the source region 11 by changing the voltage applied from the third contact electrode 33 to the gate electrode 10. In the transistor Tr with the structure shown in Figure 3, rectangular silicide layers 15 and 16 are used in a plan view to increase the area of ​​the silicide layers 15 and 16. Making the silicide layer 15 rectangular in plan view contributes to reducing the contact resistance and sheet resistance between the silicide layer 15 and the source region 11, and between the silicide layer 15 and the first base electrode 20. Furthermore, making the silicide layer 16 rectangular in plan view contributes to reducing the contact resistance and sheet resistance between the silicide layer 16 and the drain region 12, and between the silicide layer 16 and the second base electrode 22. However, on the other hand, the increased parasitic capacity, which will be explained below, becomes a problem.

[0032] For example, Figure 5 shows a cross-sectional structure of a comparative example transistor Tr, in which a silicide layer 15 is formed on the upper part of the source region 11 and a silicide layer 16 is formed on the upper part of the drain region 12. In the comparative example transistor Tr, when the silicide layer 15 is formed in a rectangular shape in plan view, as shown in Figure 6, a tall first base electrode 35 is formed on top of the silicide layer 15. Also, when the silicide layer 16 is formed in a rectangular shape in plan view, a tall second base electrode 36 is formed on top of the silicide layer 16. The tall first base electrode 35 is an electrode that is taller than the gate electrode 10. The tall second base electrode 36 is an electrode that is taller than the gate electrode 10. In the comparative example structure, a first contact electrode 37 is formed on a first base electrode 35, and a second contact electrode 38 is formed on a second base electrode 36.

[0033] In the comparative example transistor Tr shown in Figures 5 and 6, the first base electrode 35 and the second base electrode 36, which are taller than the gate electrode 10, are positioned in close proximity to the left and right of the gate electrode 10. Therefore, although the comparative example transistor Tr has the advantage of low sheet resistance and contact resistance, it has the problem of large parasitic capacitance between the gate electrode 10 and the first base electrode 35, and between the gate electrode 10 and the second base electrode 36. Figures 5 and 6 highlight, with arrows, the increased parasitic capacitance due to the close proximity of the gate electrode 10 and the first base electrode 35. Figures 5 and 6 also highlight, with arrows, the increased parasitic capacitance due to the close proximity of the gate electrode 10 and the second base electrode 36.

[0034] In contrast, in the transistor Tr1 of the first embodiment described above, as shown in Figure 2, a first base electrode 20 and a second base electrode 22, which are shorter (lower in height) than the gate electrode 10, are arranged on both sides of the gate electrode 10. Therefore, compared to the transistor Tr of the comparative example structure, the transistor Tr1 of the first embodiment can reduce the parasitic capacitance that tends to occur between the gate electrode 10 and the first base electrode 20. Furthermore, it can reduce the parasitic capacitance that tends to occur between the gate electrode 10 and the second base electrode 22. In the transistor Tr1 of the first embodiment shown in Figures 2 and 3, the sheet resistance and contact resistance can be reduced by providing silicide layers 15 and 16, and parasitic capacitance can also be suppressed compared to the comparative example structure. Furthermore, if the heights of the gate electrode 10 and the first base electrode 20 are made equal, or if the heights of the gate electrode 10 and the second base electrode 22 are made equal, the same effect of suppressing parasitic capacitance can be obtained.

[0035] <2.3 Planar layout of transistor according to the second embodiment> Figure 4 shows an example of a planar layout for transistor Tr2 in the second embodiment. In the transistor Tr2 of the second embodiment, components equivalent to those in the transistor Tr1 of the first embodiment are denoted by the same reference numerals, and the description of common components is omitted.

[0036] In transistor Tr2, a silicide layer 15' is provided that is large enough to almost completely cover the source region 11 in a plan view. A first base electrode (first base conductive region) 40 is provided that is larger than this silicide layer 15' in both the X and Y directions in a plan view. In addition, a silicide layer 16' is provided that is large enough to almost completely cover the drain region 12. A second base electrode 41 (second base conductive region) is provided that is larger than this silicide layer 16' in both the X and Y directions in a plan view. The configuration is the same as in the first embodiment, in that the first contact electrode 21 is formed on the first base electrode 40. The configuration is the same as in the first embodiment, in that the second contact electrode 23 is formed on the second base electrode 41. The other structural features are equivalent to those of transistor Tr1 in the first embodiment.

[0037] According to the structure of the second embodiment, compared to the structure of the first embodiment, it has silicide layers 15' and 16' with a larger planar area, so the sheet resistance can be lowered. In terms of reducing parasitic capacitance, the transistor Tr2 of the second embodiment can obtain the same effect as the transistor Tr1 of the first embodiment. Furthermore, according to the structure of the second embodiment, by implementing the manufacturing method described later, a structure can be adopted that prevents edge drop at the boundary region with the element isolation region, as described later. The details of this structure will be described later.

[0038] <Manufacturing method> Figures 7A to 7D and 8A to 8D are explanatory diagrams illustrating an example of the manufacturing process for transistor Tr1, which has the cross-sectional structure shown in Figure 2. As shown in Figure 7A, a dummy gate film 50 with the same shape as the gate electrode is formed in the region for forming the gate electrode on the upper surface of the semiconductor substrate 2, and insulating sidewalls 51 and insulating coatings 52 are formed to cover the sides and top surface of the dummy gate film 50, corresponding to the region for forming the insulating sidewalls 19. A polysilicon film can be used for the dummy gate film 50. A silicon nitride film or a silicon oxide film can be used for the insulating sidewalls 51 and insulating coatings 52.

[0039] After this, ions are implanted to form a source region 11 and a drain region 12 on the upper surface of the semiconductor substrate 2. Next, as shown in Figure 7B, the upper surface of the semiconductor substrate 2 is oxidized to form an upper surface oxide film 53. The upper surface oxide film 53 is formed as a chemical oxide film using ozonated water or the like. This upper surface oxide film 53 is formed thinly on the upper surface of the semiconductor substrate 2, around the insulating sidewall 51. After this, a coating layer 55 made of amorphous silicon or the like is formed to cover the upper surface oxide film 53, the insulating sidewall 51, and the insulating coating 52. Then, the upper surface of the coating layer 55 is polished and flattened using a polishing method such as chemical mechanical polishing (CMP), exposing the upper surface of the insulating coating 52 as shown in Figure 7B.

[0040] Next, as shown in Figure 7C, a resist layer 56 is formed on the coating layer 55 on both sides of the insulating sidewalls 51, 51 in the X direction. Then, a photolithography process is performed to form recesses 55A on both sides of the insulating sidewalls 51, 51 in the X direction. The region where the resist layer 56 is formed corresponds to the region where the silicide layers 15, 16 are formed in the structure shown in Figure 3 in plan view. When etching the coating layer 55 in the photolithography process, the etching is adjusted so that only a portion of the thickness of the coating layer 55 is removed. The recess 55A is made to a depth such that the upper part of the insulating side wall 51 and the insulating coating 52 are exposed within the recess 55A. As a result, the recess 55A is formed as shown in Figure 7C. From the state shown in Figure 7C, the resist layer 56 is removed and the entire surface of the coating layer 55 is etched. As a result, as shown in Figure 7D, a portion of the coating layer 55 remains as a residual layer 58 corresponding to the position where the resist layer 56 was formed. The area surrounding the residual layer 58 is etched completely, exposing the upper oxide film 53.

[0041] Next, insulating layers 25 and 59 are formed to cover the insulating sidewalls 51, 51, insulating coating 52, residual layer 58, etc. The upper parts of the insulating sidewalls 51, 51 and the insulating coating 52 are removed using polishing methods such as chemical mechanical polishing to expose the dummy gate film 50. Then, the dummy gate film 50 is removed by selective removal using an alkaline solution (choline solution, etc.). Since a recess is formed between the insulating side walls 51, 51, the gate insulating film 13 and gate electrode 10 are formed in this recess, resulting in the state shown in Figure 8A. If a high dielectric constant material layer is to be formed on the gate insulating film 13, the gate electrode 10 is formed after the high dielectric constant material layer is formed. Next, an insulating layer 28 is formed to cover the entire surface, and contact holes 60 reaching the residual layer 58 are formed using a method such as dry etching. In the structure shown in Figure 3, the positions where the contact holes 60 are formed are the positions where the first contact electrode 21 and the second contact electrode 23 should be formed.

[0042] Next, using an etching solution such as choline solution or hydrofluoric acid, the residual layer 58 and the upper oxide film 53 beneath it are removed through the contact hole 60 as shown in Figure 8C. This creates a cavity 61 in the area where the residual layer 58 and the upper oxide film 53 were removed, and the contact hole 60 and the cavity 61 are connected. If the structure is as shown in Figure 8C, a metal element for silicide layer formation is deposited through the contact hole 60. Any metal such as Ni, (NiPt), Co, or titanium can be used as the metal for silicide layer formation. Through the above process, a coating layer 63 of the metal element is formed inside the contact hole 60 and the cavity 61, as shown in Figure 8D. After this, a heat treatment for silicide layer formation is performed to diffuse the metal element for silicide layer formation. This heat treatment reacts the metal element with Si, and as shown in Figure 8E, a silicide layer 15 is generated in the upper layer of the source region 11 by diffusing and reacting the metal element, and a silicide layer 16 is generated in the upper layer of the drain region by diffusing and reacting the metal element.

[0043] Next, the coating layer 63 remaining in the contact holes 60 and cavities 61 is removed with an etching solution, so that the inner surfaces of the contact holes 60 and cavities 61 are free of deposits, as shown in Figure 8F. After this, titanium nitride or the like is deposited as a barrier metal on the inner surfaces of the contact holes 60 and cavities 61. This deposition process forms a coating layer 65a on the inner surface of the cavities 61 on the silicide layer 15, and a coating layer 66a on the inner surface of the contact holes 60 above it. In addition, a coating layer 67a is formed on the inner surface of the cavities 61 on the silicide layer 16, and a coating layer 68a is formed on the inner surface of the contact holes 60 above it.

[0044] Next, a first base electrode (first base conductive region) 65 and a first contact electrode (first connecting conductive region) 66 are formed on the silicide layer 15. A second base electrode (second base conductive region) 67 and a second contact electrode (second connecting conductive region) 68 are formed on the silicide layer 16. Through the above process, a transistor Tr3 with a cross-sectional structure equivalent to that shown in Figure 2, as shown in Figure 8G, can be obtained.

[0045] <Third Embodiment> Figure 9 shows the cross-sectional structure of transistor Tr4 according to the third embodiment. In the transistor Tr1 of the first embodiment, a silicide layer 15 was formed on the upper part of the source region 11, and a silicide layer 16 was formed on the upper part of the drain region 12. Furthermore, in the manufacturing method, the residual layer 58 was removed from the state shown in Figure 8B, and the silicide layer 15 and the first base electrode 65 and the silicide layer 16 and the second base electrode 67 were formed.

[0046] Here, without removing the residual layer 58 above the source region 11, the material constituting the residual layer 58 is made of polysilicon, and by ion implantation, the first base electrode can be constructed based on the residual layer 58 while leaving the residual layer 58 intact. Alternatively, without removing the residual layer 58 above the drain region 12, the material constituting the residual layer 58 is made of polysilicon, and by ion implantation, the second base electrode can be constructed based on the residual layer 58. The cross-sectional structure shown in Figure 9 shows a transistor Tr4 of a second embodiment in which a first base electrode 70 based on the residual layer 58 is formed on the source region 11, and a second base electrode 71 based on the residual layer 58 is formed on the drain region 12.

[0047] In the transistor Tr4 with the structure shown in Figure 9, the first base electrode 70 and the second base electrode 71 are formed as pseudo-diffusion regions, which reduces junction leakage with the source region 11 and junction leakage with the drain region 12, thereby realizing a transistor structure that improves the short-channel effect.

[0048] <Fourth Embodiment> Figures 10 and 11 are explanatory diagrams illustrating an example of a method for manufacturing a transistor Tr2 having the planar layout shown in Figure 4. In Figure 10, element isolation regions 80, 80 that demarcate the activation region of the semiconductor substrate 2 are shown on both sides, spaced apart along the X direction. The method for forming the transistor Tr5 with the configuration shown in Figure 11 between the element isolation regions 80, 80 is described below.

[0049] In the upper layer of the semiconductor substrate 2, the source region 11 and the drain region 12 are formed separated in the X direction, sandwiched between element isolation regions 80, 80. Insulating sidewalls 51, 51 similar to the structure shown in Figure 7(A) are formed over the region between the source region 11 and the drain region 12, a dummy gate film 50 is formed between the insulating sidewalls 51, 51, and an insulating coating 52 is formed on top of the dummy gate film 50. In addition, an upper oxide film 53 is formed on the surface of the semiconductor substrate 2 around the insulating sidewalls 51, 51.

[0050] Figure 10 shows a state in which a coating layer 85 is formed on both sides of the insulating sidewalls 51, 51 in the X direction, covering the surface of the semiconductor substrate 2 and the center of the element isolation region 80 in the width direction. The state shown in Figure 10 corresponds to a state similar to Figure 7D, which was previously explained regarding the method of manufacturing a transistor. In the manufacturing methods shown in Figures 7A to 8D, the element isolation region 80 is omitted from the description, but in Figure 10, the element isolation region 80 is depicted. Furthermore, it is shown that the edge of the upper oxide film 53 on the element isolation region 80 side extends to the boundary of the element isolation region 80. It is also shown that the edge of the coating layer 85 on the element isolation region 80 side reaches the element isolation region 80. The coating layer 85 can be formed from amorphous silicon. The thickness of the coating layer 85 should be such that it can cover the bottom side of the insulating side wall 51.

[0051] Subsequently, an insulating layer is formed on the semiconductor substrate 2 in the same manner as shown in Figures 8A, 8B, 8C, and 8D. The coating layer 85 beneath the insulating layer is removed to form a cavity. This cavity is then filled and diffused with silicide layer-forming elements, followed by the formation of a first base electrode layer and a second base electrode layer, and the formation of a first contact electrode and a second contact electrode, resulting in the structure shown in Figure 11.

[0052] In the structure shown in Figure 11, an insulating layer 88 is formed on the semiconductor substrate 2, a silicide layer 90 is formed on the surface of the source region 11, and a first base electrode 91 and a first contact electrode 92 are formed on top of it. A silicide layer 93 is formed on the surface of the drain region 12, and a second base electrode 94 and a second contact electrode 95 are formed on top of it. A coating layer 91a containing elements for forming a silicide layer 90 is formed on the bottom, side, and top surfaces of the first base electrode 91, and a coating layer 92a containing elements for forming a silicide layer 90 is formed on the side surfaces of the first contact electrode 92. A coating layer 94a containing elements for forming a silicide layer 93 is formed on the bottom, side, and top surfaces of the second base electrode 94, and a coating layer 95a containing elements for forming a silicide layer 93 is formed on the side surface of the second contact electrode 95.

[0053] When manufacturing the structure shown in Figure 11, the upper oxide film 53 reaches the edge of the element isolation region 80, as shown in Figure 10, and a coating layer 85 is formed on top of it. In this state, when processing the upper end of the insulating side wall 51 or the insulating coating 52 by ion etching, the edge of the element isolation region 80 is protected, so no damage occurs to the adjacent source region edge and drain region edge. If a recess is created at the edge of the element isolation region 80 by etching or other means, and damage occurs at the edge of the source region or drain region, this can cause junction leakage current to be generated.

[0054] In this case, during ion etching as shown in Figure 10, the boundary between the source region 11 and the element isolation region 80 (the area enclosed by the circle indicated by reference numeral 87 in Figure 10) is protected, so no damage occurs to the edge of the source region. Also, during ion etching, the boundary between the drain region 12 and the element isolation region 80 is protected, so no damage occurs to the edge of the drain region. In the first embodiment, both the first base electrode 20 and the second base electrode 22, which are formed on both sides of the gate electrode 10 in the X direction, are formed thinner than the gate electrode 10. However, the problems in the embodiment can be solved by forming at least one of the first base electrode 20 and the second base electrode 22 thinner than the gate electrode 10. Similarly, the problems in the embodiment can be solved by forming at least one of the first base electrode 40 and the second base electrode 41 thinner than the gate electrode 10 in the second embodiment. Similarly, the problems in the embodiment can be solved by forming at least one of the first base electrode 70 and the second base electrode 71 thinner than the gate electrode 10 in the third embodiment.

[0055] Although several embodiments and structural examples of the present invention have been described above, these embodiments and structural examples are presented as examples only and are not intended to limit the scope of the invention. These embodiments and structural examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and other structural examples are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0056] 1... Semiconductor devices (semiconductor memory devices), 2… Semiconductor substrates, 10… Gate gate, 11…Source region (first diffusion layer region), 12...Drain region (second diffusion layer region), 13…Gate insulating film, 15, 16... Silicide layer, 15', 16'... Silicide layer. 19...Insulating sidewall, 20...first base electrode (first base conductive region), 21...First contact electrode (first connecting conductive region), 22...second base electrode (second base conductive region), 23...Second contact electrode (second connection conductive region), 25, 28...insulating layer, 40...first base electrode (first base conductive region), 41... second base electrode (second base conductive region), 70...first base electrode (first base conductive region), 71... second base electrode (second base conductive region), 80... Element isolation region, 90, 93... Silicide layer, 91...first base electrode (first base conductive region), 92...First contact electrode (first connecting conductive region), 94...second base electrode (second base conductive region), 95…Second contact electrode (second connection conductive region) Tr, Tr1, Tr2, Tr3, Tr4, Tr5... Transistors.

Claims

1. Semiconductor substrate and A first diffusion layer region and a second diffusion layer region are provided on the semiconductor substrate, spaced apart in the plane direction of the semiconductor substrate, A gate insulating film is provided on the semiconductor substrate, and at least a portion of it is located in the region between the first diffusion layer region and the second diffusion layer region, A gate electrode located on the opposite side of the semiconductor substrate from the gate insulating film, A first base conductive region is provided on the side opposite to the semiconductor substrate with respect to the first diffusion layer region, extending in the plane direction of the semiconductor substrate, A first connecting conductive region provided in connection with the first base conductive region, A second base conductive region is provided on the side opposite to the semiconductor substrate with respect to the second diffusion layer region, extending in the plane direction of the semiconductor substrate, A second connecting conductive region provided in connection with the second base conductive region, Equipped with, The height of at least one of the first base conductive region and the second base conductive region is equal to or lower than the height of the gate electrode. Semiconductor equipment.

2. A silicide layer is provided between the first diffusion layer region and the first base conductive region, and between the second diffusion layer region and the second base conductive region. The semiconductor device according to claim 1.

3. The aforementioned gate electrode includes a metal or polysilicon. The semiconductor device according to claim 1.

4. At least one of the first base conductive region and the second base conductive region is formed in a rectangular shape in plan view. The semiconductor device according to claim 1.

5. The gate electrode is formed in a rectangular shape in plan view, At least one of the first base conductive region and the second base conductive region is rectangular in shape along the longitudinal direction of the gate electrode, which is rectangular in plan view. The semiconductor device according to claim 1.

6. The first base conductive region and the second base conductive region are base electrodes that penetrate the insulating layer formed on the semiconductor substrate in the thickness direction, and the first connecting conductive region and the second connecting conductive region are contact electrodes that penetrate the insulating layer formed on the semiconductor substrate in the thickness direction. The semiconductor device according to claim 1.

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