Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device with improved moisture resistance. [Solution] A semiconductor device 100 having an element region CR and a termination region TR surrounding the element region, comprising: a first electrode 11; a semiconductor substrate 20 provided on the first electrode 11; a second electrode 12 provided on the semiconductor substrate 20 in the element region CR; an insulating film 40 provided on the semiconductor substrate 20; control wiring 13 provided on the insulating film 40; a termination electrode 14 facing the semiconductor substrate 20 via the insulating film 40 in the termination region TR; and a protective film 50 provided on the insulating film 40. Between the second electrode 12 and the termination electrode 14, the upper surface of the insulating film 40 facing the protective film 50 has a first upper surface 40a and a second upper surface 40b, the distance between the first electrode 11 and the first electrode 11 in a first direction Z toward the second electrode 12 from the first electrode 11 is shorter than the distance between the first upper surface 40a.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] MOSFET(Metal-Oxide―Semiconductor Field Regarding semiconductor devices such as Effect Transistors, on the upper surface of the semiconductor substrate By forming a groove between the source electrode and the gate wiring, the creepage distance on the upper surface of the semiconductor substrate is increased. Furthermore, structures that inhibit the movement of water are known. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2020 / 105097 [Patent Document 2] Japanese Patent Publication No. 2020-136287 [Patent Document 3] Japanese Patent Publication No. 2024-41497 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device with improved moisture resistance. . [Means for solving the problem]

[0005] The semiconductor device of the embodiment has an element region and a termination region surrounding the element region. A first electrode, a semiconductor substrate provided on the first electrode, and the semiconductor in the element region A second electrode provided on a substrate, an insulating film provided on the semiconductor substrate, and the insulating film Control wiring provided on the edge film, and the semiconductor via the insulating film in the termination region. It has a terminal electrode facing the substrate and a protective film provided on the insulating film. Between the electrode and the terminal electrode, the upper surface of the insulating film facing the protective film is the first upper surface and the distance between the first electrode and the second electrode in the first direction toward the second electrode. It has a second upper surface that is shorter in distance from the first upper surface.

[0006] A semiconductor device of another embodiment has an element region and a termination region surrounding the element region. A first electrode, a semiconductor substrate provided on the first electrode, and in the element region A second electrode provided on a semiconductor substrate, and in the terminal region provided on the semiconductor substrate A cut insulating film, control wiring provided on the insulating film, and in the termination region A terminal electrode facing the semiconductor substrate via an insulating film, and a protection provided on the insulating film The protective film is located at a position further away from the element region than the terminal electrode. The upper surface of the insulating film facing the other has a first upper surface and a second upper surface, and the front of the second upper surface The thickness of the insulating film in the first direction is the thickness of the insulating film in the first direction on the first upper surface. It's even smaller than a baby.

[0007] The manufacturing method of the semiconductor device of the embodiment includes an element region having an upper electrode and surrounding the element region A step of preparing a semiconductor substrate having a termination region, and a step of forming an insulating film on the semiconductor substrate. The process includes forming a terminal electrode on the insulating film in the terminal region, and the upper surface electric Between the electrode and the terminal electrode, the upper surface of the insulating film is partially removed to reduce the thickness of the insulating film. A step of forming a recess having a step smaller than the above, and a step of forming a protective film on the recess of the insulating film. a step of forming; and BRIEF DESCRIPTION OF THE DRAWINGS

[0008] [Figure 1] FIG. 1 is a schematic plan view illustrating the semiconductor device according to the first embodiment. [Figure 2A] FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2B] FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3A] FIG. 4 is an enlarged cross-sectional view of the semiconductor device according to a first modification of the first embodiment. [Figure 3B] FIG. 5 is an enlarged cross-sectional view of the semiconductor device according to a first modification of the first embodiment. [Figure 4] FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 5] FIG. 7 is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 6] FIG. 8 is a cross-sectional view of the semiconductor device according to the fourth embodiment. [Figure 7] FIG. 9 is a cross-sectional view of the semiconductor device according to the fifth embodiment. [Figure 8A] FIG. 10 is a plan view of the semiconductor device according to the sixth embodiment. [Figure 8B] FIG. 11 is a plan view of the semiconductor device according to the sixth embodiment. [Figure 9] FIG. 12 is a plan view of the semiconductor device according to the seventh embodiment. [Figure 10] FIG. 13 is a plan view of the semiconductor device according to the eighth embodiment. [Figure 11] FIG. 14 is a cross-sectional view of the semiconductor device according to the ninth embodiment. [Figure 12] FIG. 15 is an enlarged cross-sectional view of the semiconductor device according to the ninth embodiment. [Figure 13] FIG. 16 is a cross-sectional view of the semiconductor device according to the tenth embodiment. [Figure 14] FIG. 17 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 15] FIG. 18 is a cross-sectional view of a semiconductor device according to a comparative example. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will be described below with reference to the drawings.

[0010] Please note that the drawings are schematic or conceptual, and do not show the relationship between the thickness and width of each part, nor the relationships between parts. The proportions of size and other details may not necessarily be identical to those of reality. Also, the same part may be represented in different ways. Even if they are compatible, the dimensions and proportions of each part may be represented differently in the drawings.

[0011] For example, some cross-sectional views shown in this specification show a laminated structure, The thickness ratio of each layer in a laminated structure is not necessarily the same as in reality. In the cross-sectional view, one of the layers is Even if one layer is depicted as being thicker than the other, in reality, one layer and the other layer The thicknesses may be roughly the same, or one layer may be thinner than the other. The dimensions, such as thickness, shown in the drawings in this specification may differ from those of the actual object.

[0012] The direction from the first electrode 11 to the second electrode 12 is defined as the Z direction (first direction). The direction intersecting the direction is the X direction (second direction), and the direction intersecting the X and Z directions is the Y direction (second direction). (3 directions). Note that the X, Y, and Z directions are shown as orthogonal in this embodiment. However, the relationship is not limited to orthogonal lines; any intersecting relationship is acceptable.

[0013] Also, for the sake of explanation, we will refer to the positive Z direction as "up" and the negative Z direction as "down". Call. However, the directions "up" and "down" refer to the direction of gravity or the direction when the semiconductor device is mounted. It is not limited to the direction. When describing the vertical positional relationship between regions with different positions in the XY plane, , the positions of each of the regions in the Z direction shall be compared.

[0014] Note that in the following description, n + , n, n - and p + , p, p - notations represent the relative levels of the impurity concentration for each conductivity type. That is, n + has a higher n-type impurity concentration than n is relatively high, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + has a relatively higher p-type impurity concentration than p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that n + type, n - type is simply referred to as n-type, p + type, p - type is simply described as p-type in some cases.

[0015] In the present specification and each drawing, the same reference numerals are assigned to the same elements as those described above with respect to the already shown drawings and detailed description thereof is omitted as appropriate.

[0016] (First Embodiment) FIG. 1 is a schematic plan view showing a semiconductor device 100 according to the first embodiment. FIGS. 2A and 2B are cross-sectional views taken along line P1-P2 shown in FIG. 1. FIGS. 3A and 3B are shown in FIGS. 2A and 2B is an enlarged cross-sectional view of region PR1.

[0017] The semiconductor device 100 shown in FIG. 1 is, for example, a MOSFET. The semiconductor device 100 has an element region CR (a region surrounded by a broken line in FIG. 1) in which an element such as a MOSFET is formed and a termination region TR surrounding the element region. The outer edge of the element region CR is, for example, a MOSFET It is located at the outer edge of the second semiconductor region 22 (base region) of the semiconductor device 100.

[0018] For example, a MOSFET is formed in the CR region of the semiconductor substrate 20 (see Figure 2A). A second electrode (top electrode) 12 and control wiring 13 are provided on the semiconductor substrate 20. At least a portion of the control wiring 13 may be located in the termination region TR. The second electrode 12 is, for example... For example, the source electrode. When the semiconductor device is turned on, the current mainly passes through the second electrode 12 to the element region CR. Current flows through it. The control wiring 13 consists of a pad portion 13p and an outer peripheral portion 13s surrounding the second electrode 12. As shown in Figure 2A, the wiring 13w is connected to the outer periphery 13s and provided inside the insulating film 40. This includes applying voltage to the pad portion 13p, thereby changing the potential of the outer circumference 13s and the wiring 13w. Control. An insulating film 40 is provided on the semiconductor substrate 20. Further details will be described later with reference to Figure 2A. A first electrode 11 (drain electrode) is provided on the lower surface of the semiconductor substrate 20.

[0019] In the termination region TR, a termination electrode 14 is provided on the insulating film 40, surrounding the element region CR. The termination electrode 14 is provided, for example, in a continuous ring shape. Element region CR and termination electrode 14 Between these two surfaces, the upper surface of the insulating film 40 is divided into a first upper surface 40a and a second upper surface 40b (in Figure 2A, the rear It has the following. The second upper surface 40b is the bottom surface of the recess CP as described later with reference to Figure 2A. The second upper surface 40b surrounds, for example, the element region CR. In Figure 1, the protective film 50 is not shown. It is.

[0020] Although Figure 1 is shown as a diagram of the first embodiment, the line P1-P2 shown in Figure 1 is the second embodiment. In the subsequent explanation of morphology, when illustrating the cross-section at the position corresponding to the P1-P2 section, the explanation will be as follows: To use for that purpose.

[0021] Figures 2A and 2B are XZ cross-sectional views along the line P1-P2 shown in Figure 1. In the P1-P2 cross-sectional view, the semiconductor device 100 has a MOSFET in the element region CR. An example is shown. Please refer to Figure 2A for explanation.

[0022] The semiconductor device 100 includes a first electrode 11 and a first conductivity type first electrode provided on the first electrode 11. Semiconductor region 21(n ― (Drift region of shape), second guide provided on the first semiconductor region 21 The second semiconductor region 22 of the electric type (base region of the p type), provided on the second semiconductor region 22 Third semiconductor region 23(n + It has a source region of the shape.

[0023] Furthermore, the first semiconductor region 21 is a contact region 21 of the second conductivity type that is in contact with the first electrode 11. c(n + It has a drain region of a certain shape.

[0024] The semiconductor device 100 is provided on the first semiconductor region 21, for example, as shown in Figure 2B. It may also have a fourth semiconductor region 24. The fourth semiconductor region 24 is located in the second semiconductor region 22 It is located closer to the termination electrode 14. Figure 2B shows one fourth semiconductor region 24. Multiple fourth semiconductor regions 24 are provided in the direction from the element region CR to the termination region TR. It may be the fourth semiconductor region 24, for example, a p-type resurf region. Region 24 includes the portion located between the second electrode 12 and the terminal electrode 14 in the X direction. 4. Semiconductor region 24 is the portion located between the control wiring 13 and the termination electrode 14 in the X direction. Includes.

[0025] Furthermore, as shown in Figure 2B, for example, the semiconductor device 100 has a first semiconductor region 21 It has a surface region 21t of the first conductive type located in the positive Z direction (direction toward the surface). The surface region 21t of the first semiconductor region 21 is on the upper surface of the semiconductor substrate 20. It is located further away from the device region CR than the fourth semiconductor region 24. The surface region 21t is the surface region It has a higher impurity concentration of the first conductivity type than the first semiconductor region 21 located below region 21t. The surface region 21t is the first semiconductor region 21 below the second semiconductor region 22 of the device region CR. It is desirable to have an impurity concentration of the first conductivity type that is higher than the above. The surface region 21t is, for example, This is an n-type resurf region. The fourth semiconductor region 24 and the surface region 21t are, for example, in the XY plane. The element region CR is surrounded by the surface region 21t, which in the X direction is the second electrode 12 and the terminal electrode. This includes the portion located between 14 and the surface region 21t. The surface region 21t terminates with the control wiring 13 in the X direction. This includes the portion located between the end electrode 14 and the end electrode.

[0026] Referring again to Figure 2A, in the element region CR, from the second electrode 12 to the first semiconductor region 21 A gate insulating portion 31 is provided within the semiconductor substrate 20 toward the gate insulating portion 31. A gate electrode 32 is provided there. The gate electrode 32 is connected to the second semiconductor via the gate insulating portion 31. It faces the body region 22. The gate insulating portion 31 and the gate electrode 32 are arranged in the X direction, and Y It extends in the direction. The gate insulating portion 31 is thin between the semiconductor substrate 20 and the gate electrode 32. A gate insulating film 31F is formed thickly, and between the second electrode 12 and the gate electrode 32, a thick layer is formed. The gate insulating layer 31L is formed and includes

[0027] An insulating film 40 is provided on the semiconductor substrate 20. The wiring 13w is connected to the control wiring 13. They are connected to each other and provided within the insulating film 40.

[0028] The gate electrode 32 is electrically connected to the wiring 13w in a cross-section not shown in Figure 2A. The wiring 13w is electrically connected to at least a portion of the gate electrode 32 that extends in the Y direction in Figure 1. Connect. For example, at the Y-direction end of the gate electrode 32 extending in the Y direction, gate electrode 3 Wiring 2 and 13W are in contact.

[0029] In the terminal region TR, a terminal electrode 14 is provided on the insulating film 40. The terminal electrode 14 is half It is electrically connected to the conductive substrate 20. The termination electrode 14 is extended through the insulating film 40 to form a semiconductor. It has a connecting electrode 14p that is connected to the substrate 20. The semiconductor substrate 20 has a connecting electrode 14p and It has a gas-connected terminal semiconductor region 25. The terminal semiconductor region 25 is a first conductivity type It contains pure substances, and the impurity concentration of the first conductivity type is higher than that of the first semiconductor region 21.

[0030] The connecting electrode 14p surrounds the element region CR in the XY plane, for example. The termination electrode 14 is insulating. On the film 40, it is stretched in a direction toward the element region CR relative to the connecting electrode 14p.

[0031] Between the element region CR and the termination electrode 14, the upper surface of the insulating film 40 is the first upper surface 40a and It has a second upper surface 40b. Between the element region CR and the termination electrode 14, the insulating film 40 The upper surface is provided with irregularities. The distance in the Z direction between the second upper surface 40b of the insulating film 40 and the first electrode 11. This distance is shorter than the distance between the first upper surface 40a and the first electrode 11. The second upper surface 40b is, for example, a recessed CP It is the bottom surface, and the distance along the Z-direction between it and the semiconductor substrate 20 is shorter than that between it and the first upper surface 40a. It is provided in the position. Although Figure 2A shows three second upper surfaces 40b, this embodiment is shown in Figure This includes the case in 2A where one or more second upper surfaces 40b are provided in the X direction.

[0032] The thickness of the insulating film 40 in the Z direction on the second upper surface 40b is the same as the thickness of the insulating film 40 in the Z direction on the first upper surface 40a. Smaller than the thickness of the insulating film 40. Step in the Z direction between the first upper surface 40a and the second upper surface 40b. This is smaller than the thickness of the insulating film 40 in the Z direction on the first upper surface 40a. The second upper surface 40b is It is located further away from the first electrode 11 in the Z direction than the upper surface of the semiconductor substrate 20. In other words, The distance in the Z direction between the second upper surface 40b and the first electrode 11 is the distance between the upper surface of the semiconductor substrate 20 and the first electrode 1 It is longer than the distance in the Z direction of 1.

[0033] The first upper surface 40a is formed in a flat, planar shape.

[0034] A protective film 50 is provided on the insulating film 40. The protective film 50 is connected to the second electrode 12 and the control wiring 13 It is in contact with the terminal electrode 14. The protective film 50 is in close contact with the first upper surface 40a of the insulating film 40. .

[0035] Next, we will explain some examples of each material.

[0036] The first electrode 11 and the second electrode 12 are made of a metal, such as Al or Cu.

[0037] The pad portion 13p and outer peripheral portion 13s of the control wiring 13 are made of a metal including, for example, Al or Cu. Yes, it exists. Wiring 13W is, for example, conductive polysilicon containing impurities.

[0038] The terminal electrode 14 is made of a metal, such as Al or Cu.

[0039] First semiconductor region 21, second semiconductor region 22, third semiconductor region 23, and fourth semiconductor region in Figure 2B. The semiconductor substrate 20 having region 24 and terminal semiconductor region 25 includes, for example, Si. Conductive semiconductor regions are formed, for example, by injecting N or P and then performing an annealing process. p-type conductive semiconductor regions are formed, for example, by injecting B and performing an annealing process. .

[0040] The gate insulating portion 31 is, for example, an oxide film containing silicon oxide. The gate electrode 32 is, for example It is a conductive polysilicon containing impurities.

[0041] The insulating film 40 contains silicon oxide such as SiO2.

[0042] The protective film 50 is, for example, polyimide. The protective film 50 may also be, for example, epoxy resin.

[0043] Next, the operation of the semiconductor device 100 will be described.

[0044] First, the operation of the element region CR will be described with reference to Figure 2A. For the second electrode 12... With a positive voltage applied to the first electrode 11, a voltage equal to or greater than the threshold voltage is applied to the gate electrode 32. Then, an inversion layer (channel) of the first conductivity type is formed in the second semiconductor region 22. Electrons then... From pole 12, through the inversion layer of the third semiconductor region 23 and the second semiconductor region 22, to the first semiconductor region The current is injected into 21, and the MOSFET turns on.

[0045] Next, when the voltage applied to the gate electrode 32 is made lower than the threshold voltage, the second semiconductor region The inversion layer of the first conductivity type that was formed in region 22 disappeared, and electron injection stopped, resulting in MOS The FET turns off.

[0046] Next, we will explain the off state of MOSFETs and other components formed in the CR element region. When the voltage applied to electrode 32 is less than the threshold voltage, the first electrode 11 is lower than the second electrode 12. The positive voltage applied to the semiconductor substrate 20 promotes depletion and maintains the breakdown voltage. A depletion layer extends from the interface between the semiconductor region 21 and the second semiconductor region 22 into the first semiconductor region 21. Near the upper surface of the semiconductor substrate 20, the depletion layer extends to the termination region TR, causing a concentration of the electric field. It suppresses pressure and maintains pressure resistance.

[0047] Next, the configuration of the comparative example will be described. Figures 14 and 15 show the semiconductor device 1000 related to the comparative example. A cross-sectional view is shown. In Figures 14 and 15, between the control wiring 13 and the termination electrode 14 The upper surface of the insulating film 40 is formed flat. In Figures 14 and 15, the dotted lines represent the extension of the depletion layer. This represents the movement of water and ions contained in the water between the insulating film 40 and the protective film 50. This can happen. For example, the potential of the control wiring 13 is lower than the potential of the termination electrode 14. Therefore As shown in Figure 14, the cation IonP may move toward the control wiring 13.

[0048] Thus, if positive ions are locally present on the upper surface of the insulating film 40 near the control wiring 13, On the upper surface of the semiconductor substrate 20, a depletion layer forms in the portion facing the positive ions through the insulating film 40. The elongation is suppressed. That is, on the upper surface of the semiconductor substrate 20, positive ions are transmitted through the insulating film 40. In areas facing the element, the spatial change in potential becomes steep, potentially leading to a concentration of the electric field. On the upper surface of the substrate 20, chip failure occurs in the portion facing the positive ion through the insulating film 40. There is a risk of it occurring.

[0049] On the other hand, Figure 15 shows that on the upper surface of the insulating film 40, anions are locally located near the terminal electrode 14. This indicates the presence of anions on the upper surface of the semiconductor substrate 20 via the insulating film 40. In the area opposite to it, the depletion layer elongation is promoted. On the other hand, the terminal electrode 14 is at the edge of the chip. The first electrode 11 is connected via the semiconductor substrate 20, and the terminal electrode 14 is, for example, a drain electrode. It has a potential equal to the position. The terminal electrode 1 is on the upper surface of the semiconductor substrate 20 via the insulating film 40. In the portion opposite to 4, a charge is induced by the potential of the terminal electrode 14. In the portion of the upper surface facing the terminal electrode 14 via the insulating film 40, the induced charge This suppresses the elongation of the depletion layer. Therefore, anions terminate on the upper surface of the insulating film 40. Because it is locally present in the vicinity of electrode 14, the depletion layer stops below terminal electrode 14. The electric field that should be dispersed is paired with anions on the upper surface of the semiconductor substrate 20 via the insulating film 40. There is a risk of concentration in the area facing the object. On the upper surface of the semiconductor substrate 20, through the insulating film 40, shadow Breakdown may occur in the region opposite the ion.

[0050] Furthermore, differences in the thermal expansion coefficients of each material at high temperatures, as well as swelling due to humidity, can cause, for example, terminal regions. Delamination may occur between the insulating film 40 and the protective film 50 of the region TR. High moisture may be present at the delamination interface. Moisture accumulates due to the temperature, and mobile ions in the moisture affect the electric field on the surface of the semiconductor substrate 20. This could lead to a deterioration in pressure resistance and an increase in leaks.

[0051] According to the semiconductor device 100 of this embodiment, the adhesion between the insulating film 40 and the protective film 50 is improved. This improves the reliability of semiconductor devices. A recess is formed at the interface between the insulating film 40 and the protective film 50. By forming a convex shape, the creepage distance at the interface between the insulating film 40 and the protective film 50 can be increased. By forming irregularities at the interface between the insulating film 40 and the protective film 50, the density between the insulating film 40 and the protective film 50 is increased. The adhesion strength can be improved. The adhesion strength between the insulating film 40 and the protective film 50 is improved, and the insulating film 40 and This suppresses the movement of moisture and ions contained in the protective film 50, thereby lowering the breakdown voltage of the semiconductor device. The following can be suppressed. When the humidity of the environment is high, moisture and water can get between the insulating film 40 and the protective film 50. Even when ions are present in the air, this suppresses the decrease in pressure resistance and improves moisture resistance. It is possible.

[0052] According to the semiconductor device 100 of this embodiment, the adhesion between the insulating film 40 and the protective film 50 is improved. Furthermore, the movement of moisture and ions contained in moisture between the insulating film 40 and the protective film 50 is suppressed. This makes it possible to suppress voltage degradation or increased leakage under high temperature, high humidity, and high voltage conditions.

[0053] According to the semiconductor device 100 of this embodiment, along the interface between the insulating film 40 and the protective film 50 By increasing the creepage distance from the terminal electrode 14 to the second electrode 12 or control wiring 13, It suppresses the movement of water and ions contained in water. Also, the increased creepage distance provides insulation. The adhesion between film 40 and protective film 50 is improved, which suppresses peeling, and furthermore, moisture and It can suppress the movement of ions contained in water.

[0054] Furthermore, by selecting a material for the protective film 50 that has the property of absorbing water and swelling, Furthermore, adhesion can be improved. Materials that have the property of absorbing water and swelling include, for example, poly It is a liimide film. The protective film 50 swells to reliably fill the recess CP on the upper surface of the insulating film 40. It is possible.

[0055] In the semiconductor device 100 according to this embodiment, the creepage distance at the interface between the insulating film 40 and the protective film 50 is By making it longer, the movement of water and the ions contained in water can be suppressed. (Control wiring) The movement of ions caused by the potential difference between 13 and the terminal electrode 14 is suppressed, and the semiconductor substrate 20 This suppresses the concentration of the electric field inside and prevents a decrease in withstand voltage.

[0056] According to the semiconductor device 100 of this embodiment, between the first upper surface 40a and the second upper surface 40b The step in the Z direction is smaller than the thickness of the insulating film 40 in the Z direction on the first upper surface 40a. The distance in the Z direction between the upper surface 40b and the first electrode 11 is equal to the distance between the upper surface of the semiconductor substrate 20 and the first electrode 11. It is longer than the distance in the direction. Compared to the semiconductor device 110 shown in Figure 13 later, this embodiment In this configuration, the upper surface of the semiconductor substrate 20 can be formed to be flatter.

[0057] When the second electrode 12 is at a lower potential than the first electrode 11, the insulating film 40 and the protective film 50 At the interface, water and ions move toward the second electrode 12 (or terminal electrode 14). The insulating film 40 has a first upper surface 40a and a second upper surface 40b, Along the interface between 40 and the protective film 50, the terminal electrode 14 leads to the second electrode 12 and the control wiring 13. The creepage distance increases. Therefore, it is possible to suppress the movement of water and the ions contained in water. Yes, it is possible. In other words, according to the semiconductor device 100 of this embodiment, the terminal electrode 14 and the terminal electrode An electrode to which a potential lower than electrode 14 can be applied (the second electrode 12 in Figure 7 and the control shown in Figure 2A, which will be described later) The movement of moisture and ions contained in the moisture between the wiring 13) and the other components can be suppressed.

[0058] In the example shown in Figure 2A, the recessed area CP is, for example, CDE (Chemical Dry). Formed by Etching or RIE (Reactive Ion Etching) As shown in Figure 1, the recessed portion CP has, for example, a side surface aligned with the Z direction.

[0059] Next, regarding the uneven shape of the upper surface of the insulating film 40, Figure 3A and Refer to B for further explanation. According to at least one of the modifications described below, the recess CP is filled. The anchoring effect of the embedded protective film 50 further improves the adhesion between the insulating film 40 and the protective film 50. This is possible. Due to the structure of the recessed CP, the insulating film 40 and the protective film 50 peel off in the Z direction. It can prevent them from letting go.

[0060] The protective film 50 that fills the recessed CP is positioned in the positive Z direction near the bottom surface of the recessed CP. The width in the X direction is wider than the area to be placed, and if the protective film 50 peels off in the positive Z direction It exhibits an anchoring effect when attempting to do so. Furthermore, if the protective film 50 is made of a material that swells... In this case, an even greater anchoring effect can be expected.

[0061] Furthermore, as shown in Figure 2B, the semiconductor device 100 has a fourth semiconductor region 24 and a surface region 21t. The reduction in breakdown voltage can be further suppressed when the fourth semiconductor region 24 and the surface region By region 21t, the concentration of the electric field in the termination region TR of the semiconductor substrate 20 can be reduced. Yes, it is possible. Between the insulating film 40 and the protective film 50, the fourth semiconductor region 24 and the surface region 21t Even when charges such as ions are present, the electric field concentration in the terminal region TR of the semiconductor substrate 20 is maintained. It can be reduced.

[0062] The fourth semiconductor region 24 has a second electrode 12 (or control wiring 13) and a termination electrode in the X direction. It includes the portion located between 14 and the fourth semiconductor region 24. The fourth semiconductor region 24 has a lower potential than the terminal electrode 14. The ions attracted to the second electrode 12 (or control wiring 13) cause the semiconductor substrate 20 to... Reduces the concentration of the region. For example, the fourth semiconductor region 24 reduces the depletion layer extension in the terminal region TR. This promotes the attraction of positive ions to the second electrode 12 (or control wiring 13). This suppresses the concentration of the electric field (see Figure 14). By suppressing the concentration of the electric field, in this embodiment, half This further suppresses the decrease in the withstand voltage of the conductor device.

[0063] The surface region 21t is in the X direction and the second electrode 12 (or control wiring 13) of the insulating film 40 This includes the portion located between the terminal electrodes 14, and is at a potential higher than the second electrode 12 (or control wiring 13). This reduces the concentration of the electric field in the semiconductor substrate 20 due to ions attracted to the high-frequency terminal electrode 14. For example, this can occur when negative ions are attracted to the terminal electrode 14, causing the electric field to concentrate. This suppresses chip damage (see Figure 15).

[0064] According to the semiconductor device 100 of this embodiment, between the element region CR and the termination electrode 14 The upper surface of the insulating film 40 is provided with irregularities, forming a first upper surface 40a and a second upper surface 40b. The process of processing the semiconductor substrate 20 is not required. First upper surface 40a and second upper surface 40b This is provided, for example, by etching the insulating film 40. Therefore, the semiconductor substrate 20 is etched Compared to the case where irregularities are formed by grinding, for example, the fourth semiconductor region 24 and the surface shown in Figure 2B The influence on the impurity concentration distribution in region 21t can be reduced. For example, it can be formed as a diffusion layer. By making the impurity concentration distribution in the fourth semiconductor region 24 and the surface region 21t more uniform, This can suppress the concentration of the electric field caused by the non-uniformity of the impurity concentration distribution.

[0065] For example, as a comparative example, the fourth semiconductor region 24 and the surface region 21t in Figure 2B are considered to be a diffusion layer. Let's consider the case where the semiconductor substrate 20 is excavated after it has been formed. Excavation of the semiconductor substrate 20 This causes the shape of the diffusion layer to change compared to its original shape and impurity concentration profile.

[0066] As another comparative example, after drilling the semiconductor substrate 20, the fourth semiconductor region in Figure 2B Consider the case where region 24 and surface region 21t are formed as a diffusion layer. Injecting impurities from the top surface of the semiconductor substrate 20 affects the diffusion layer profile. Sometimes.

[0067] (First embodiment, first modified example) Figure 3A is an enlarged cross-sectional view illustrating a first modified example of the first embodiment. Insulating film 40 and protective film The portion between 50 where the first upper surface 40a and the second upper surface 40b are formed (region PR1 in Figure 2A) It is shown in an enlarged view.

[0068] The second upper surface 40b is the bottom surface of the recess CP. The recess CP extends in the Z direction from the upper surface of the insulating film 40. It is concave in the negative direction, and the second upper surface 40b is the bottom surface, and the first upper surface 40a and the second upper surface of the insulating film 40 It has a side surface 40w between it and the upper surface 40b.

[0069] The recessed portion CP has a part whose width in the X direction widens in the negative Z direction toward the bottom surface. In the example shown in Figure 3A, the X-direction of the recess CP is greater in the side surface 40w than near the first upper surface 40a. It has a portion with a large width in that direction.

[0070] The recessed area CP shown in Figure 3A is formed, for example, by wet etching. Any isotropic etching is acceptable, not just etched etching. For example, even dry etching can be CDE This allows for the formation of a recessed area (CP).

[0071] The structure of the recessed CP in this modified example allows the insulating film 40 and the protective film 50 to be anchored by an anchoring effect. This can further improve the adhesion.

[0072] (Second modified example of the first embodiment) Figure 3B is an enlarged cross-sectional view illustrating a second modified example of the first embodiment. Insulating film 40 and protective film The portion between 50 where the first upper surface 40a and the second upper surface 40b are formed (region PR1 in Figure 2A) This is shown in a magnified view. Some explanations of parts common to Figure 3A are omitted.

[0073] The structure of the recessed CP in this modified example also provides an anchoring effect between the insulating film 40 and the protective film 50. This can further improve the adhesion.

[0074] An example of a manufacturing method for a recessed CP having the shape shown in Figure 3B is described below. For example, RIE, etc. The process involves etching to excavate the insulating film 40 and form a recess CP, and the side wall of the recess CP The process involves forming a side wall insulating layer and selectively removing the insulating film 40 located at the bottom of the recessed CP. The process includes the following: The insulating film 40 and the sidewall insulating layer are different types of insulators. The insulating film 40 is For example, it includes silicon oxide. The sidewall insulating layer includes, for example, polysilicon or silicon nitride. For example, the etching rate for wet etching differs between the insulating film 40 and the sidewall insulating layer. The chemicals used for wet etching are, for example, BHF (Buffered Hydrogen). It contains fluoride (buffered hydrofluoric acid). The insulating film 40 is, for example, more than the side wall insulating layer. It also has a high etching rate for BHF.

[0075] (Second Embodiment) Figure 4 shows a cross-sectional view of the semiconductor device 200 according to the second embodiment. I will omit the explanation of the part that goes through.

[0076] In this embodiment, the gate electrode 32 in the element region CR is a so-called planar gate. Yes, that is, a gate electrode 32 is provided on the semiconductor substrate 20 via a gate insulating portion 31. The gate insulating portion 31 is formed thinly between the semiconductor substrate 20 and the gate electrode 32. The gate insulating film 31F is formed thickly between the second electrode 12 and the gate electrode 32. The gate insulating layer 31L includes the gate electrode 32 and the second electrode 1. Insulate point 2.

[0077] The gate electrode 32 is connected to the second semiconductor region 22 of the second conductivity type via the gate insulating film 31F. It faces the part. By applying a voltage above the threshold voltage to the gate electrode 32, the second semiconductor region If an inversion layer is formed in the portion of 22 facing the gate insulating film 31F, the semiconductor device 200 It will turn on.

[0078] The gate electrode 32 extends in the Y direction. The gate electrode 32 has a cross-section not shown in Figure 4. It is connected to the 13W wiring.

[0079] According to the semiconductor device 200 of this embodiment, even in a planar gate semiconductor device By suppressing the movement of water and ions contained in water in the terminal region TR, the breakdown voltage of the semiconductor device is reduced. The decrease can be suppressed. Along the interface between the insulating film 40 and the protective film 50, the terminal electrode 14 By increasing the creepage distance from the second electrode 12 or control wiring 13, moisture and moisture-containing This suppresses the movement of ions. Also, as the creepage distance increases, the insulating film 40 and the protective film 50 improves adhesion and suppresses peeling, and furthermore, moisture and moisture-containing It can suppress the movement of ions.

[0080] (Third embodiment) Figure 5 shows a cross-sectional view of the semiconductor device 300 according to the third embodiment. I will omit the explanation of the part that goes through.

[0081] In this embodiment, in the element region CR and the termination region TR, from the upper surface of the semiconductor substrate 20 The device region has a deep semiconductor region 26 of a second conductivity type extending within the first semiconductor region 21. In region CR, the deep semiconductor region 26 is located between the gate electrodes 32 in the XY plane. It is kicked and extends in the Y direction. In the element region CR, the deep semiconductor region 26 is, for example, It is in contact with the second semiconductor region 22. In the device region CR, the deep semiconductor region 26 is For example, it is in contact with the third semiconductor region 23. The deep semiconductor region 26 is in contact with the device region CR. It is then electrically connected to the second electrode 12.

[0082] The distance between the deep semiconductor region 26 and the first electrode 11 is the distance between the second semiconductor region 22 and the first electrode 1 It is shorter than the distance to 1.

[0083] The deep semiconductor region 26 is also provided in the termination region TR, for example in the device region CR. They are arranged at equal intervals in the X direction together with the provided deep semiconductor region 26. However, multiple The deep semiconductor regions 26 do not necessarily need to be equally spaced, and adjacent regions in the device region CR are not necessarily The spacing between adjacent deep semiconductor regions 26 and the adjacent deep semiconductor regions TR in the termination region TR The spacing between the conductor regions 26 may be different from that of the other.

[0084] According to the semiconductor device 300 of this embodiment, the deep semiconductor region 26 and the first semiconductor region The depletion layer extends from the interface with region 21, further suppressing the decrease in the breakdown voltage of the semiconductor device. This can be done. Alternatively, the impurity concentration of the first semiconductor region 21 can be controlled while maintaining the breakdown voltage of the semiconductor device. Increasing this value can reduce the on-resistance.

[0085] (Fourth Embodiment) Figure 6 shows a cross-sectional view of the semiconductor device 400 according to the fourth embodiment. I will omit the explanation of the part that goes through.

[0086] In this embodiment, between the deep semiconductor region 26, there is a fourth semiconductor region 24 and a first semiconductor region It has a surface region 21t. It extends beyond the deep semiconductor region 26 that is in contact with the second electrode 12. A fourth semiconductor region 24 is located between a plurality of deep semiconductor regions 26 provided near the end electrode 14. It is located there. The fourth semiconductor region 24 contains impurities of the same conductivity type as the deep semiconductor region 26. The impurity concentration in the fourth semiconductor region 24 is lower than that in the deep semiconductor region 26. i. The fourth semiconductor region 24 and the deep semiconductor region 26 have, for example, a p-type conductivity.

[0087] It is located closer to the termination electrode 14 than the deep semiconductor region 26 connected to the second electrode 12. The surface region 21t of the first semiconductor region 21 is located between multiple deep semiconductor regions 26. The surface region 21t is the first semiconductor region located closer to the first electrode 11 than the surface region 21t. It has a higher impurity concentration than region 21. Surface region 21t is, for example, from the fourth semiconductor region 24. It is also provided near the terminal electrode 14. The surface region 21t is located near the second electrode 12 in the X direction. This includes the portion located between the terminal electrode 14 and the terminal electrode 14.

[0088] Deep semiconductor region 26 Fourth semiconductor region 24 Deep semiconductor region 26 Figure 6 shows deep The diagram shows two fourth semiconductor regions 24 divided into semiconductor region 26, but the fourth semiconductor region There may be three or more 24s. Deep semiconductor region 26 Deep semiconductor region 26 Figure Figure 6 shows two surface regions 21t divided into a deep semiconductor region 26, but the surface There may be three or more regions 21t. That is, deep semiconductor region 26, fourth half The number and layout of the conductor regions 24 and surface regions 21t are not limited to the structure illustrated in Figure 6. i. Depending on the semiconductor device design, the deep semiconductor region 26, the fourth semiconductor region 24, and the surface The number and layout of the 21t regions can be selected as needed.

[0089] According to the semiconductor device 400 of this embodiment, provided between the deep semiconductor regions 26 The fourth semiconductor region 24 and the surface region 21t create an ion between the insulating film 40 and the protective film 50. To reduce the impact on the depletion layer in the semiconductor substrate 20 when ions are present, and to reduce the impact on the semiconductor device This can suppress the decrease in pressure resistance.

[0090] The fourth semiconductor region 24 has a second electrode 12 (or control wiring 13) and a termination electrode in the X direction. The second electrode 12 (or control electrode) includes a portion located between it and the terminal electrode 14, and has a lower potential than the terminal electrode 14. This reduces the concentration of the electric field on the semiconductor substrate 20 caused by ions attracted to the wiring 13). For example, the concentration of the electric field due to the attraction of positive ions to the second electrode 12 (or control wiring 13) The central (see Figure 14) is suppressed. By suppressing the concentration of the electric field, the semiconductor device in this embodiment is controlled. This can further suppress the decrease in pressure resistance.

[0091] The surface region 21t is located in the X direction between the second electrode 12 (or control wiring 13) and the terminal electrode 14 The terminal electric current includes the portion located between the two, and has a potential higher than the second electrode 12 (or control wiring 13). This reduces the concentration of the electric field in the semiconductor substrate 20 caused by ions attracted to pole 14. Damage to the tip can occur when negative ions are attracted to the end electrode 14, causing the electric field to concentrate. (See Figure 15) is suppressed.

[0092] (Fifth embodiment) Figure 7 shows a cross-sectional view of the semiconductor device 500 according to the fifth embodiment. I will omit the explanation of the part that goes through.

[0093] In the above explanation, the control wiring 13 is located in a layout between the second electrode 12 and the terminal electrode 14. Although I have explained this, it is not necessarily limited to this. However, unlike the layout shown in Figure 1, the second electrode 12 is located in a terminal region T that is further away from the control wiring 13. This is an example where it is located near R. In other words, the control wiring 13 does not necessarily surround the second electrode 12. Not necessarily. For example, the control wiring 13 does not need to have an outer peripheral portion 13s surrounding the second electrode 12. There are none, and the control wiring 13 and wiring 13w are located between the second electrodes 12 in the XY plane. For example, the second electrode 12 may be divided into two or more parts in the XY plane, and the divided second electrode A layout in which the control wiring 13 is located between the poles 12 may also be adopted.

[0094] In the semiconductor device 500 according to this embodiment, between the second electrode 12 and the terminal electrode 14 Due to the potential difference, charges such as ions can move between the insulating film 40 and the protective film 50. In other words, In the first to fourth embodiments described above, the cations are attracted to the control wiring 13 This is not necessarily the case; it could also be the second electrode 12.

[0095] (Sixth Embodiment) Figures 8A and 8B show the semiconductor device according to the sixth embodiment, specifically the semiconductor device according to the first embodiment. This is an enlarged schematic plan view of the part of the body device 100 corresponding to area RA shown in Figure 1. Figures 8A to 10 show embodiments of the shape of the XY plane of the second plane 20b, and the first to fifth This can be combined with other embodiments as appropriate. The protective film 50 is not shown in the illustration.

[0096] The following will be explained with reference to Figure 8A. The insulating film 40 located between the control wiring 13 and the termination electrode 14 The upper surfaces consist of a first upper surface 40a and a second upper surface 40b (the second upper surface 40b is the area enclosed by the dotted line). This includes the portion located in the negative direction in the X direction relative to the second electrode 12, the second upper surface 40b The (recessed portion CP) extends along the Y direction. It is located in the positive Y direction relative to the second electrode 12. In this portion, the second upper surface 40b (recess CP) extends along the X direction.

[0097] The portion of the second upper surface 40b (recess CP) extending in the X direction and the portion extending in the Y direction are continuous. The portion of the second upper surface 40b (recess CP) extending in the X direction and the portion extending in the Y direction are semiconductor equipment. They intersect at the corner of position 600. As shown in Figure 8A, for example, the second upper surface is provided in three rows. 40b (recessed CP) is located at the corners of the semiconductor device 600, at the three intersections, They intersect. Furthermore, the second upper surface 40b (recess CP) is provided in one or more rows and extends in the X direction. The portion that extends in the Y direction and the portion that extends in the Y direction must be continuous. The X direction of the second upper surface 40b (recess CP) The number of columns in the part extending in the direction of the y-axis is, for example, equal to the number of columns in the part extending in the direction of the y-axis, but not necessarily equal. This is not always the case, and can be appropriately selected depending on the structure of the semiconductor device. For example, in Figure 8B As shown, for every row of parts extending in the X direction, there are two or more consecutive rows of parts extending in the Y direction. It is not necessary for the intersection of the part extending in the X direction and the part extending in the Y direction to be L-shaped. It may include a T-shape.

[0098] According to the semiconductor device 600 of this embodiment, the adhesion between the insulating film 40 and the protective film 50 Further improvement is achieved, and peeling can be suppressed. The portion of the second upper surface 40b (recess CP) extending in the X direction. The portion extending in the Y direction is continuous, and the insulating film 40 is maintained in both the X and Y directions. This can enhance the effect of suppressing the peeling of the protective film 50.

[0099] For example, in the portion of the second upper surface 40b (recess CP) that extends in the X direction, along the X direction Adhesion force (The void created by the delamination of the insulating film 40 and the protective film 50 propagates along the X direction) The adhesion force in the case of peeling (due to the separation of the insulating film 40 and the protective film 50) and the adhesion force along the Y direction (due to the peeling of the insulating film 40 and the protective film 50) The adhesion force when the resulting void propagates along the Y direction can be different. For example, The adhesion force along the X direction and the adhesion force along the Y direction are determined by the number of rows of the second upper surface 40b (recessed CP). It also depends on the circumstances. In other words, the adhesion force along the X direction and the adhesion force along the Y direction may differ. Therefore, delamination may occur along the direction of weaker adhesion.

[0100] Similarly, in the portion of the second upper surface 40b (recess CP) extending in the Y direction, along the X direction The adhesion force may differ from the adhesion force along the Y direction, and peeling may occur along the direction of weaker adhesion. It is possible that it will happen.

[0101] In this embodiment, the portion of the second upper surface 40b (recess CP) extending in the X direction and the portion extending in the Y direction The continuous sections reduce the difference in adhesion force between the X and Y directions, and the X and Y directions The effect of suppressing delamination in both directions can be enhanced. For example, if the terminal region TR is in the X direction And when provided with equal lengths in the Y direction, the second upper surface 40b (recess CP) extends in the X direction. The number of parts extending in the Y direction may be equal to the number of parts extending in the Y direction.

[0102] The adhesion force is relatively smaller in the direction along the extending direction of the second upper surface 40b (recess CP). Let's assume a case. For example, the portion of the second upper surface 40b (recess CP) that extends in the X direction, It is possible that the adhesion force will try to peel off along the X direction, where the adhesion force is relatively weak. On the other hand, 2. In the portion of the upper surface 40b (recess CP) that extends in the X direction and the portion that extends in the Y direction which is continuous with the upper surface 40b (recess CP) The adhesion force along the X direction is relatively large. Therefore, peeling along the X direction can be suppressed. Conversely, in the portion extending in the Y direction, the adhesion force in the Y direction becomes relatively smaller, but in the Y direction In the portion extending in the X direction and the portion continuing in the X direction, the adhesion force along the Y direction is relatively It is large. Therefore, peeling along the Y direction can be suppressed.

[0103] (Seventh Embodiment) Figure 9 shows a cross-sectional view of the semiconductor device 700 according to the seventh embodiment. I will omit the explanation of the part that goes through.

[0104] Figure 9 shows a semiconductor device according to the seventh embodiment, specifically a semiconductor device according to the first embodiment 1. This is an enlarged schematic plan view of the portion corresponding to area RA shown in Figure 1 for 00. Protective film 50 The illustration is omitted.

[0105] In this embodiment, between the second upper surfaces 40b that extend along the X direction and are arranged in multiple rows in the Y direction, It has a connecting region 40m that extends along the direction and connects multiple second upper surfaces 40b. Extending along the X direction, between the second upper surface 40b which is arranged in multiple rows in the X direction, there are multiple second It has a connecting region 40m that connects the two upper surfaces 40b. The connecting region 40m is, for example, the second upper surface 40 It is a plane that is smoothly continuous with b.

[0106] The connection region 40m is located in the Z direction, closer to the second upper surface 40b than to the first upper surface 40a. The connection area 40m is provided, for example, in the same position as the second upper surface 40b in the Z direction. The connection area 40m has a width equivalent to, for example, the second upper surface 40b. In other words, , the length (width) in the Y direction of the second upper surface 40b extending in the X direction, and the connection region 40 extending in the X direction The length (width) of m in the Y direction is the same. Or, the X direction of the second upper surface 40b extending in the Y direction. The length (width) of this section is equivalent to the length (width) in the X direction of the 40m connecting area extending in the Y direction. For example, the connection region 40m is formed by the process of removing the insulating film 40 in order to form the second upper surface 40b. They may be formed in the same process.

[0107] The following example refers to the case where three or more rows are formed on the second upper surface 40b, as shown in Figure 9. To explain, the second upper surface 40b is the innermost second upper surface 40b (closest to the control wiring 13) and the The second upper surface 40b on the outer circumference (closest to the terminal electrode 14), the second upper surface 40b on the innermost circumference, and the outermost circumference. It has one or more intermediate second upper surfaces 40b located between the second upper surfaces 40b.

[0108] The connecting region 40m is the first part that connects the innermost second upper surface 40b and the intermediate second upper surface 40b. The second part 40 connects the outermost second upper surface 40b and the intermediate second upper surface 40b. It has m2 and, for example, between adjacent first parts 40m1 in the Y direction, the second part 40 m2 is located, and in the Y direction, the first part 40m1 is between the adjacent second part 40m2. It is located there.

[0109] When two rows of the second upper surface 40b are formed, the second upper surface 40b is the innermost second upper surface 40 b (closest to control wiring 13) and the outermost second upper surface 40b (closest to termination electrode 14) The connection region 40m has the innermost second upper surface 40b and the outermost second upper surface 40b and are connected. Therefore, it is not necessarily the case that there is one or more intermediate second upper surfaces 40b. I don't know.

[0110] According to the semiconductor device 700 of this embodiment, the adhesion between the insulating film 40 and the protective film 50 Further improvement is achieved, and peeling can be suppressed. The portion of the second upper surface 40b (recess CP) extending in the X direction. The portion extending in the Y direction is continuous, suppressing peeling in both the X and Y directions. The effect can be further enhanced.

[0111] In this embodiment, since there is a connection region 40m, for example, adjacent second upper surfaces 40b A connecting region 40m extending in the Y direction is provided between the portions extending in the X direction. In cases where the adhesion force becomes relatively weaker (or stronger) in the direction in which surface 40b extends, However, the second upper surface 40b has a mixture of portions that extend in the X direction and portions that extend in the Y direction, This further enhances the effect of suppressing peeling in both the forward and Y directions.

[0112] Furthermore, in this embodiment, the second upper surface 40b formed in multiple rows is, for example, the innermost second upper surface 40b and the intermediate second upper surface 40b are connected to the connection region 40m (first part 40m1 in Figure 9) The connection is further strengthened. Or the outermost second upper surface 40b and the intermediate second upper surface 40b are connected in region 4. It is connected by 0m (the second part, 40m2, in Figure 9). Therefore, it extends in parallel. Between the second upper surfaces 40b, the material of the protective film 50 is movable when the protective film 50 is embedded. The second upper surface 40b of multiple rows is well embedded with the protective film 50 with minimal material bias. This makes it possible to further improve the adhesion between the insulating film 40 and the protective film 50.

[0113] Furthermore, according to this embodiment, moisture and moisture at the interface between the insulating film 40 and the protective film 50 This further suppresses the movement of ions and further suppresses the decrease in the breakdown voltage of semiconductor devices. Compared to the structure shown in Figure 8A, in this embodiment, for example, the second upper surface 40b extends in the X direction. A connecting region 40m extending in the Y direction is located between the parts. Therefore, the second upper surface 40b It attempts to move in the X direction along the first upper surface 40a located between the portions extending in the X direction. The creepage distance of water and the ions contained in water is increased by the connection region 40m. Connection region 4 Due to 0m, water and ions contained in the water move in the direction in which the second upper surface 40b extends. This can suppress the localized concentration of water and ions contained in it. Furthermore, by suppressing electric field concentration within the semiconductor substrate 20, the breakdown voltage of the semiconductor device is reduced. It can be further suppressed.

[0114] (Eighth embodiment) Figure 10 shows a cross-sectional view of the semiconductor device 800 according to the eighth embodiment. I will omit the explanation of the common parts.

[0115] Figure 10 shows a semiconductor device according to the first embodiment, which is part of the eighth embodiment. This is an enlarged schematic plan view of the portion corresponding to area RA shown in Figure 1 for 100. Protective film 5 The illustration of 0 has been omitted.

[0116] In this embodiment, the connection region 40m consists of the innermost second upper surface 40b and one or more intermediate second The upper surface 40b and the outermost second upper surface 40b are connected. The connection area 40m is the innermost second The second upper surface 40b and the first part 40m1 connecting the intermediate second upper surface 40b, and the outermost second upper It has a surface 40b and a second portion 40m2 connecting the intermediate second upper surface 40b. Section 40m1 and the second section 40m2 are located on the same straight line along the X or Y direction. The first section 40m1 and the second section 40m2, which extend in the direction, are a straight line along the X direction and each has a small length However, some overlap. The second upper surface 40b is arranged in a grid pattern.

[0117] According to the semiconductor device 800 of this embodiment, the adhesion between the insulating film 40 and the protective film 50 Further improvement is achieved, and peeling can be suppressed. The portion of the second upper surface 40b (recess CP) extending in the X direction. The portion extending in the Y direction is continuous, suppressing peeling in both the X and Y directions. The effect can be further enhanced.

[0118] (Ninth Embodiment) Figure 11 shows a cross-sectional view of a semiconductor device 900 according to the ninth embodiment. I will omit the explanation of the common parts.

[0119] In this embodiment, the semiconductor device 900 has a terminal region TR that is greater than the terminal electrode 14. The insulating film 40 has a first upper surface 40a and a second upper surface 40b on its upper surface, away from the region CR. .

[0120] In this embodiment as well, on the upper surface of the insulating film 40 between the element region CR and the termination electrode 14 The first upper surface 40a and the second upper surface 40b may also be provided. It may have the shape of the recessed CP shown as a modified example or a second modified example.

[0121] According to the semiconductor device 900 of this embodiment, the outside of the semiconductor device, for example, the package side This suppresses the intrusion of moisture from the surface, thereby suppressing the concentration of electric fields within the semiconductor substrate 20, and the semiconductor device. This can suppress the decrease in pressure resistance.

[0122] In the termination region TR, on the upper surface of the insulating film 40 which is further away from the element region CR than the termination electrode 14, In this case, having a first upper surface 40a and a second upper surface 40b allows moisture and water from the sides of the package to be absorbed. The ions contained in the film creep between the insulating film 40 and the protective film 50 until they reach the terminal electrode 14. By increasing the distance, the intrusion of moisture and ions contained in moisture is suppressed. Water and ions contained in the water move beyond the terminal electrode 14 towards the element region CR. This suppresses moisture and ions contained in the moisture from reaching the terminal electrode 14 and exceeding the terminal electrode 14. By suppressing movement, the second electrode 12 or control wiring 13 and the terminal electrode 14 The potential difference inhibits the movement of water and the ions contained in it. Ions contained in moisture or water are suppressed from moving and locally concentrating, and the semiconductor substrate 20 can reduce electric field concentration therein.

[0123] (Modification of the Seventh Embodiment) FIG. 12 is an enlarged cross-sectional view illustrating a semiconductor device 901 according to a modification of the seventh embodiment. An enlarged view shows a portion where a first upper surface 40a and a second upper surface 40b are formed between an insulating film 40 and a protective film 50 (see FIG. 11, a region PR2 indicated by a broken line).

[0124] In this modification, a void (air layer) AG exists between the second upper surface 40b, which is the bottom surface of the recess CP, and the protective film 50. Here, the air layer AG is not limited to a gas having the same composition as the atmosphere, and may contain any substance in a gaseous state.

[0125] According to this modification, moisture is trapped in the air layer AG between the second upper surface 40b and the protective film 50, thereby further suppressing movement of moisture and ions contained in moisture along the upper surface of the insulating film 40 . This can suppress local concentration of moisture and ions contained in moisture around the second electrode 12, the control wiring 13, and the termination electrode 14, thereby suppressing electric field concentration in the semiconductor substrate 20 and thus suppressing a decrease in the breakdown voltage of the semiconductor device.

[0126] The concave-convex structure formed by the first upper surface 40a and the second upper surface 40b increases the creepage distance for movement of moisture and ions contained in moisture, thereby suppressing intrusion of moisture and ions contained in moisture. In addition, since moisture and ions contained in moisture are trapped in the air layer AG, intrusion of moisture and ions contained in moisture can be further suppressed.

[0127] ​​Further, moisture trapped by the air layer and ions contained in the moisture are located from the termination electrode 14 also at a position away from the element region CR, so the influence of the trapped moisture and ions contained in the moisture on the expansion of the depletion layer can be reduced. That is, in this modification, the influence of the trapped moisture and ions contained in the moisture on the expansion of the depletion layer can be reduced. That is, in this modification, by trapping moisture and ions contained in moisture in a region where the influence on the breakdown voltage of the semiconductor device is relatively small (a position farther from the element region CR than the termination electrode 14), by trapping moisture and ions contained in moisture, the electrical characteristics of a region where the influence on the breakdown voltage of the semiconductor device is relatively large (a position closer to the element region CR than the termination electrode 14) can be further stabilized.

[0128] According to the semiconductor devices 900 and 901 according to the present embodiment, the unevenness on the upper surface of the insulating film 40 that is farther from the element region CR than the termination electrode 14 suppresses the intrusion of moisture and ions contained in moisture from the side surface of the semiconductor package, suppresses a decrease in the breakdown voltage of the semiconductor device, and improves reliability. suppresses the intrusion of moisture and ions contained in moisture from the side surface of the semiconductor package, suppresses a decrease in the breakdown voltage of the semiconductor device, and improves reliability. can be improved.

[0129] (Tenth Embodiment) FIG. 13 is a cross-sectional view of a semiconductor device 110 according to the tenth embodiment. Descriptions of parts common to the semiconductor device 100 will be omitted.

[0130] In the present embodiment, a groove GT is formed on the upper surface of the semiconductor substrate 20 in the termination region TR, and an insulating film 40 is formed on the bottom surface and side walls of the groove GT. In the present embodiment, a groove GT is formed on the upper surface of the semiconductor substrate 20 in the termination region TR. An insulating film 40 is formed in the groove GT. In the present embodiment, a groove GT is formed on the upper surface of the semiconductor substrate 20 in the termination region TR, and an insulating film 40 is formed on the bottom surface and side walls of the groove GT. In the present embodiment, a groove GT is formed on the upper surface of the semiconductor substrate 20 in the termination region TR. A groove GT is formed on the upper surface of the semiconductor substrate 20. An insulating film 40 is formed in the groove GT.

[0131] The distance in the Z direction between the second upper surface 40b of the insulating film 40 and the first electrode 11 is shorter than the distance in the Z direction between the first upper surface 40a of the insulating film 40 and the first electrode 11. the distance in the Z direction between the first upper surface 40a and the first electrode 11.

[0132] The semiconductor device 110 according to this embodiment also has a second electrode 12 (or control wiring 13) and By increasing the creepage distance of the insulating film 40 between the terminal electrodes 14, moisture and moisture contained in the film can be filtered out. This suppresses ion movement and prevents a decrease in the breakdown voltage of the semiconductor device. Second electrode 12 (or control wiring 13) may have a lower potential applied to it than the terminal electrode 14, Due to the difference in position, water and the ions contained in the water may move. In this embodiment, the first upper By providing surface 40a and the second upper surface 40b, the movement of water and ions contained in water is suppressed. This can reduce the impact on the depletion layer of the semiconductor substrate 20.

[0133] According to the semiconductor device of at least one embodiment described above, the upper surface of the insulating film 40 By providing the first upper surface 40a and the second upper surface 40b, the concentration of the electric field in the semiconductor substrate 20 This can suppress the decrease in the breakdown voltage of semiconductor devices. According to one embodiment of a semiconductor device, moisture and ions contained in the moisture are present inside the semiconductor device. This can suppress the decrease in withstand voltage when a condensation occurs, thereby improving the moisture resistance of semiconductor devices.

[0134] The embodiments have been described above with reference to specific examples. However, the embodiments are based on these specific examples. This is not limited to specific examples. In other words, a person skilled in the art may make appropriate design changes to these specific examples. As long as the obtained invention possesses the characteristics of the embodiment, it is also included within the scope of the embodiment. Each specific example includes its elements, their arrangement, materials, conditions, shape, size, etc. It is not limited to this and can be changed as appropriate.

[0135] Furthermore, each element of the aforementioned embodiments is combined to the extent technically possible. and combinations of these are also included within the scope of the embodiments as long as they include the features of the embodiments In addition, within the scope of the idea of the embodiments, those skilled in the art can conceive various modifications and amendments, and it is understood that these modifications and amendments also belong to the scope of the embodiments It is understood that these modifications and amendments also belong to the scope of the embodiments.

[0136] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms , and various omissions, substitutions and alterations can be made without departing from the gist of the invention. These embodiments and their modifications are included in the gist and scope of the invention and are also included in the scope of the invention defined in the claims and equivalents thereof .

[0137] (Supplementary Note 1) A semiconductor device comprising: an element region; and a termination region surrounding the element region, a first electrode; a semiconductor substrate provided on the first electrode; a second electrode provided on the semiconductor substrate in the element region; an insulating film provided on the semiconductor substrate; a control wiring provided on the insulating film; a termination electrode facing the semiconductor substrate via the insulating film in the termination region; a protective film provided on the insulating film; wherein: between the second electrode and the termination electrode, an upper surface of the insulating film facing the protective film comprises a first upper surface, and a second upper surface whose distance to the first electrode in a first direction from the first electrode toward the second electrode is shorter than that of the first upper surface. Semiconductor equipment.

[0138] (Note 2) The thickness of the insulating film in the first direction on the second upper surface is the thickness of the insulating film in the first upper surface Smaller than the thickness of the insulating film in the first direction, The semiconductor device described in Appendix 1.

[0139] (Note 3) The step difference in the first direction between the first upper surface and the second upper surface is the first upper surface Smaller than the thickness of the insulating film in the first direction, The semiconductor device described in Appendix 1.

[0140] (Note 4) The distance between the second upper surface and the first electrode in the first direction is the distance between the upper surface of the semiconductor substrate and the A distance longer than the distance of one electrode in the first direction, The semiconductor device described in Appendix 1.

[0141] (Note 5) The second upper surface is the bottom surface of the recess provided in the insulating film. A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0142] (Note 6) The recess has a portion that widens in the direction opposite to the first direction. Semiconductor device as described in Appendix 5.

[0143] (Note 7) The protective film comprises polyimide, A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0144] (Note 8) The termination electrode is electrically connected to the drift region of the semiconductor substrate. A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0145] (Note 9) From the element region toward the termination region, the second electrode, the control wiring, and the insulating film are located. The second upper surface and the terminal electrode are arranged in this order. The semiconductor device described in Appendix 1.

[0146] (Note 10) In the element region, the first electrode is the drain electrode and the second electrode is the source electrode, M OSFET formed A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0147] (Note 11) The aforementioned semiconductor substrate is The first semiconductor region of the first conductivity type, A second semiconductor of a second conductivity type is provided on the first semiconductor region in the aforementioned element region. Domain and, In the element region, provided on the second semiconductor region, and electrically connected to the second electrode The third semiconductor region of the first conductivity type to be connected, It is provided on the first semiconductor region, intersecting in the first direction and extending from the element region to the terminal In the second direction toward the edge region, it is located closer to the termination electrode than the second semiconductor region. The fourth semiconductor region of the second conductivity type, Having, A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0148] (Note 12) The fourth semiconductor region is located between the second electrode and the second upper surface in the second direction. Including the part in which it is located, The semiconductor device described in Appendix 11.

[0149] (Note 13) The first semiconductor region is, The terminal region has a surface region provided on the insulating film side, The impurity concentration of the first conductivity type in the surface region is the surface of the first semiconductor region. The impurity concentration of the first conductivity type is higher than that of the lower part of the region. The surface region is located between the fourth semiconductor region and the termination electrode in the second direction. Including the part in which it is located, Semiconductor device as described in Appendix 12.

[0150] (Note 14) The aforementioned semiconductor substrate is The first semiconductor region of the first conductivity type, A second semiconductor of a second conductivity type is provided on the first semiconductor region in the aforementioned element region. Domain and, In the element region, provided on the second semiconductor region, and electrically connected to the second electrode The third semiconductor region of the first conductivity type to be connected, Extending from the upper surface of the semiconductor substrate in a direction opposite to the first direction, and from the second semiconductor region Furthermore, a deep semiconductor region of the second conductivity type, where the distance between it and the first electrode is shorter, Having, A semiconductor device as described in any one of the items 1 to 4 of the appendix.

[0151] (Note 15) A planar gate type MOSFET is formed in the aforementioned element region. The semiconductor device described in Appendix 15.

[0152] (Note 16) A semiconductor device having an element region and a termination region surrounding the element region, First electrode and, A semiconductor substrate provided on the first electrode, In the element region, a second electrode is provided on the semiconductor substrate, In the terminal region, an insulating film is provided on the semiconductor substrate, Control wiring provided on the insulating film, In the termination region, the termination electrode facing the semiconductor substrate via the insulating film, A protective film provided on the insulating film, It has, At a position further away from the element region than the terminal electrode, the protective film is facing the The upper surface of the insulating film has a first upper surface and a second upper surface, and the front of the second upper surface in the first direction The thickness of the insulating film is smaller than the thickness of the insulating film in the first direction on the first upper surface. , Semiconductor equipment.

[0153] (Note 17) A gap is provided between the second upper surface and the protective film. The semiconductor device described in Appendix 16.

[0154] (Note 18) A semiconductor substrate is prepared having an element region with an upper electrode and a termination region surrounding the element region. The process and The steps include forming an insulating film on the semiconductor substrate, A step of forming a terminal electrode on the insulating film in the terminal region, Between the upper electrode and the terminal electrode, the upper surface of the insulating film is partially removed. A step of forming a recess having a step smaller than the thickness of the insulating film, A step of forming a protective film on the recess of the insulating film, A method for manufacturing a semiconductor device equipped with [the specified features].

[0155] (Note 19) The process further comprises forming control wiring on the insulating film after forming the insulating film, The recess is located between the control wiring and the termination electrode. The method for manufacturing a semiconductor device as described in Appendix 18.

[0156] (Note 20) In the process of excavating the upper surface of the first insulating film to form a recess, the first insulating film is deposited on the side wall of the recess. This includes the process of forming different types of insulating layers. The method for manufacturing a semiconductor device as described in Appendix 18. [Explanation of Symbols]

[0157] CR element area TR...Terminal area 11...1st electrode 12...Second electrode 13. Control Wiring 13p... Pad section 13s...Outer periphery 13W...Wiring 14...Terminal electrode 21. First Semiconductor Region (Drift Region) 21t...Surface area 21c... Contact area (drain area) 22. Second Semiconductor Region (Base Region) 23. Third Semiconductor Region (Source Region) 24. Fourth Semiconductor Area 25. Terminal Semiconductor Region 26. Deep Semiconductor Domain 31...Gate insulation 32.. Government 40... insulating film 40a...1st top surface 40b...2nd top surface CP... recessed 50...Protective film

Claims

1. A semiconductor device having an element region and a termination region surrounding the element region, First electrode and A semiconductor substrate provided on the first electrode, In the element region, a second electrode is provided on the semiconductor substrate, An insulating film provided on the semiconductor substrate, Control wiring provided on the insulating film, In the termination region, the termination electrode facing the semiconductor substrate via the insulating film, A protective film provided on the insulating film, It has, Between the second electrode and the terminal electrode, the upper surface of the insulating film facing the protective film is , the first upper surface and the first electrode in the first direction toward the second electrode A second upper surface having a distance shorter between it and the first upper surface, Semiconductor equipment.

2. The thickness of the insulating film in the first direction on the second upper surface is the thickness of the insulating film in the first upper surface Smaller than the thickness of the insulating film in the first direction, The semiconductor device according to claim 1.

3. The second upper surface is the bottom surface of the recess provided in the insulating film, The recess has a portion that widens in the direction opposite to the first direction. The semiconductor device according to claim 2.

4. From the element region toward the termination region, the second electrode, the control wiring, and the insulating film are located. The second upper surface and the terminal electrode are arranged in this order. The semiconductor device according to claim 1.

5. The aforementioned semiconductor substrate is The first semiconductor region of the first conductivity type, A second semiconductor of a second conductivity type is provided on the first semiconductor region in the element region. Domain and, In the element region, provided on the second semiconductor region, and electrically connected to the second electrode The third semiconductor region of the first conductivity type to be connected, It is provided on the first semiconductor region, intersecting in the first direction and extending from the element region to the terminal In the second direction toward the edge region, it is located closer to the termination electrode than the second semiconductor region. The fourth semiconductor region of the second conductivity type, Having, The semiconductor device according to any one of claims 1 to 4.

6. The first semiconductor region is, The terminal region has a surface region provided in contact with the insulating film, The impurity concentration of the first conductivity type in the surface region is the surface of the first semiconductor region. The impurity concentration of the first conductivity type is higher than that of the lower part of the region. The surface region is located between the fourth semiconductor region and the termination electrode in the second direction. Including the part in which it is located, The semiconductor device according to claim 5.

7. A semiconductor device having an element region and a termination region surrounding the element region, First electrode and A semiconductor substrate provided on the first electrode, In the element region, a second electrode is provided on the semiconductor substrate, In the terminal region, an insulating film is provided on the semiconductor substrate, Control wiring provided on the insulating film, In the termination region, the termination electrode facing the semiconductor substrate via the insulating film, A protective film provided on the insulating film, It has, At a position further away from the element region than the terminal electrode, the protective film is facing the The upper surface of the insulating film has a first upper surface and a second upper surface, and the second upper surface is from the first electrode The thickness of the insulating film in the first direction toward the second electrode is the thickness of the first upper surface toward the first direction toward the second electrode. Smaller than the thickness of the insulating film in the direction Semiconductor equipment.

8. A gap is provided between the second upper surface and the protective film. The semiconductor device according to claim 7.

9. A semiconductor substrate is prepared having an element region with an upper electrode and a termination region surrounding the element region. The process and The steps include forming an insulating film on the semiconductor substrate, A step of forming a terminal electrode on the insulating film in the terminal region, Between the upper electrode and the terminal electrode, the upper surface of the insulating film is partially removed. A step of forming a recess having a step smaller than the thickness of the insulating film, A step of forming a protective film on the recess of the insulating film, A method for manufacturing a semiconductor device equipped with [the specified features].

10. In the step of excavating the upper surface of the preceding insulating film to form the recess, the preceding The process includes forming an insulating layer of a different type than the insulating film, The method for manufacturing a semiconductor device according to claim 9.

Images