Multi-gang multilayer ceramic capacitor

Abstract

We provide multi-gang multilayer ceramic capacitors that reduce costs, improve yield, and enhance production efficiency. [Solution] In the multi-layer ceramic capacitor 10, the laminate 12 has multiple capacitor sections arranged inside a single element, and includes a first internal electrode layer connected to a first external electrode 30a and having a first counter electrode section and a first lead section, and a second internal electrode layer connected to a second external electrode 30b and having a second counter electrode section and a second lead section, wherein the first lead section has first exposed sections 29a1 to 29a9 exposed on the second main surface 12d, and the second lead section has second exposed sections 29b1 to 29b9 exposed on the second main surface. The first exposed section located closest to the first side surface 12a is curved convexly toward the first side surface when viewed from the second main surface, and the second exposed section located closest to the second side surface 12b is curved convexly toward the second side surface when viewed from the second main surface.

Description

[Technical Field]

[0001] This invention relates to a multi-gang multilayer ceramic capacitor. [Background technology]

[0002] As the performance of APUs (Accelerated Processing Units) used in smartphones and other devices improves, impedance design to ensure power supply stability during high-speed operation has become increasingly difficult. The most common solution is to prepare multiple two-terminal capacitors with their internal electrode layers exposed on both end faces, select these capacitors appropriately according to their different frequency characteristics, and arrange them in parallel on the power line to reduce impedance over a wide bandwidth. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-179928 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, this method raises concerns about increased costs due to the increased number of components and decreased yield.

[0005] Therefore, the primary objective of this invention is to provide a multi-gang multilayer ceramic capacitor that can reduce costs, improve yield, and enhance production efficiency. [Means for solving the problem]

[0006] The multilayer ceramic capacitor according to this invention comprises a laminate having a first side surface and a second side surface opposite to each other in the stacking direction, a first main surface and a second main surface opposite to each other in the height direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in the length direction perpendicular to both the stacking direction and the height direction; a first external electrode extending in the stacking direction on the second main surface; and a second external electrode extending in the stacking direction on the second main surface. The laminate has a plurality of capacitor sections, each consisting of a plurality of dielectric layers and a plurality of internal electrode layers, arranged at predetermined intervals in the length direction and the stacking direction within a single element. The internal electrode layer includes a first internal electrode layer connected to the first external electrode and a second internal electrode layer connected to the second external electrode. The first internal electrode layer includes a first opposing electrode section and a section protruding toward the first external electrode. The multilayer ceramic capacitor has a first lead portion, and the second internal electrode layer has a second opposing electrode portion and a second lead portion protruding toward the second external electrode, the first lead portion has a first exposed portion exposed on the second main surface, the second lead portion has a second exposed portion exposed on the second main surface, the first exposed portion located closest to the first side surface is curved convexly toward the first side surface when viewed from the second main surface, the first exposed portion located closest to the second side surface is curved convexly toward the second side surface when viewed from the second main surface, the second exposed portion located closest to the first side surface is curved convexly toward the first side surface when viewed from the second main surface, and the second exposed portion located closest to the second side surface is curved convexly toward the second side surface when viewed from the second main surface.

[0007] In the multi-gang multilayer ceramic capacitor according to this invention, the laminate has multiple capacitor sections, each consisting of multiple dielectric layers and multiple internal electrode layers, arranged at predetermined intervals in the longitudinal and lamination directions within a single element. The internal electrode layers include a first internal electrode layer connected to a first external electrode and a second internal electrode layer connected to a second external electrode. The first internal electrode layer has a first opposing electrode portion and a first lead portion protruding toward the first external electrode, and the second internal electrode layer has a second opposing electrode portion and a second lead portion protruding toward the second external electrode. This makes it possible to shorten the current path, thereby lowering the ESL (Equivalent Series Inductance) compared to a conventional two-terminal capacitor where the internal electrode layers are exposed on both end faces. Furthermore, this multi-gang multilayer ceramic capacitor alone can replace multiple two-terminal capacitors. In addition, by adjusting the number of capacitor sections arranged inside the laminate in the multi-gang multilayer ceramic capacitor according to the arrangement of the land electrodes, the arrangement of land electrodes for a conventional two-terminal capacitor can be used as is without redesigning it.

[0008] Furthermore, in this multi-layer ceramic capacitor, the first internal electrode layer has a first opposing electrode portion and a first lead portion protruding toward the first external electrode, the second internal electrode layer has a second opposing electrode portion and a second lead portion protruding toward the second external electrode, the first lead portion has a first exposed portion exposed on the second main surface, the second lead portion has a second exposed portion exposed on the second main surface, and the first exposed portion located closest to the first side surface is, when viewed from the second main surface, toward the first side surface The first exposed portion, which is closest to the second side surface, is curved in a convex shape toward the second side surface when viewed from the second main surface, and the second exposed portion, which is closest to the first side surface, is curved in a convex shape toward the first side surface when viewed from the second main surface, and the second exposed portion, which is closest to the second side surface, is curved in a convex shape toward the second side surface when viewed from the second main surface, thus improving the adhesion between the dielectric layer and the internal electrode layer and suppressing peeling of structural defects. Effects of the Invention

[0009] According to the present invention, it is possible to provide a multiple-unit multilayer ceramic capacitor that achieves cost reduction and yield improvement, and can improve production efficiency.

[0010] The above object, other objects, features and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings. Brief Description of the Drawings

[0011] [Figure 1] Fig. 1 is an external perspective view showing a multiple-unit multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 2] Fig. 2 is a bottom view showing an example of the multiple-unit multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] Fig. 3 is a left side view showing an example of the multiple-unit multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] Fig. 4 is a schematic cross-sectional view along line IV-IV in Fig. 1. [Figure 5] Fig. 5 is a schematic cross-sectional view along line V-V in Fig. 1. [Figure 6] Fig. 6 is a schematic cross-sectional view along line VI-VI in Fig. 3. [Figure 7] Fig. 7 is a schematic cross-sectional view along line VII-VII in Fig. 3. [Figure 8] Fig. 8 is a transparent perspective view showing the arrangement of internal electrode layers inside a multilayer body of the multiple-unit multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 9] Fig. 9 is a transparent perspective view showing the arrangement of exposed portions of internal electrode layers inside a multilayer body of the multiple-unit multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 10] (a) is an enlarged view of a portion A in Fig. 9, and (b) is an enlarged view of a portion B in Fig. 9. [Figure 11]This is an exploded perspective view of the laminated body of a multi-gang type multilayer ceramic capacitor according to an embodiment of the present invention. [Modes for carrying out the invention]

[0012] 1. Multi-gang multilayer ceramic capacitor Next, an example of a multi-gang multilayer ceramic capacitor 10 according to an embodiment of this invention will be described.

[0013] Figure 1 is an external perspective view showing a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a bottom view showing an example of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. Figure 3 is a left side view showing an example of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. Figure 4 is a schematic cross-sectional view along line IV-IV in Figure 1. Figure 5 is a schematic cross-sectional view along line VV in Figure 1. Figure 6 is a schematic cross-sectional view along line VI-VI in Figure 3. Figure 7 is a schematic cross-sectional view along line VII-VII in Figure 3. Figure 8 is a transparent perspective view showing the arrangement of the internal electrode layers inside the laminate of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. Figure 9 is a transparent perspective view showing the arrangement of the exposed portions of the internal electrode layers inside the laminate of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. Figure 10(a) is an enlarged view of part A in Figure 9, and Figure 10(b) is an enlarged view of part B in Figure 9.

[0014] As shown in Figures 1 and 2, the multi-gang multilayer ceramic capacitor 10 includes, for example, a laminate 12 and an external electrode 30.

[0015] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The internal electrode layers 16 have a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0016] The laminate 12 has a first side surface 12a and a second side surface 12b facing the stacking direction x, a first main surface 12c and a second main surface 12d facing the height direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing the length direction z perpendicular to the stacking direction x and the height direction y. The second main surface 12d is the surface on the mounting side.

[0017] The laminate 12 has capacitor sections 18, each consisting of multiple dielectric layers 14 and multiple internal electrode layers 16, arranged within a single element. Multiple capacitor sections 18 are arranged inside the laminate 12 at predetermined intervals in the longitudinal direction z and the stacking direction x. In this embodiment, the capacitor section 18 includes a first capacitor section 181 to a ninth capacitor section 189 and nine capacitor sections in total.

[0018] Furthermore, when the capacitor units 18 arranged inside the laminated body 12 are arranged in a predetermined interval of N units in the length direction z and M units in the stacking direction x, it is preferable that they be arranged to satisfy either 1 ≤ N ≤ 12 and 2 ≤ M ≤ 12, or 2 ≤ N ≤ 12 and 1 ≤ M ≤ 12.

[0019] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first side surface 12a and the second side surface 12b, the first main surface 12c and the second main surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them.

[0020] The dimension t in the height direction y of the laminate 12 is preferably 1.00 mm or less.

[0021] As shown in Figure 4, the laminate 12 has, in the stacking direction x, a plurality of capacitor portions 18, a first outer layer portion 20a located between the first side surface 12a and the capacitor portion 18 (181-183) closest to the first side surface 12a, a second outer layer portion 20b located between the second side surface 12b and the capacitor portion 18 (187-189) closest to the second side surface 12b, and an intermediate layer 21 located between the capacitor portions 18. The intermediate layer 21 has a thickness of 10 times or more the dielectric layer 14 of the capacitor portion 18. In this embodiment, the intermediate layer 21 has a first intermediate layer 21a located between capacitor portions 181-183 and capacitor portions 184-186, and a second intermediate layer 21b located between capacitor portions 184-186 and capacitor portions 187-189.

[0022] Furthermore, as shown in Figure 4, the laminate 12 has, in the longitudinal direction z, a first end gap 22a located between the capacitor portion 18 (181, 184, 187) and the first end face 12e, a second end gap 22b located between the capacitor portion 18 (183, 186, 189) and the second end face 12f, and an intermediate gap 23 located between the capacitor portions 18. In this embodiment, the intermediate gap 23 has a first intermediate gap 23a located between the capacitor portions 181, 184, 187 and the capacitor portions 182, 185, 188, and a second intermediate gap 23b located between the capacitor portions 182, 185, 188 and the capacitor portions 183, 186, 189.

[0023] Furthermore, as shown in Figures 5 to 7, the laminate 12 has an upper region 24a located between the capacitor portion 18 and the first main surface 12c in the height direction y, and a lower region 24b located between the capacitor portion 18 and the second main surface 12d.

[0024] As shown in Figures 4 and 10, the first outer layer 20a is located on the first side surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first side surface 12a and the capacitor portion 18 (181-183) closest to the first side surface 12a. The second outer layer 20b is located on the second side surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second side surface 12b and the capacitor portion 18 (187-189) closest to the second side surface 12b.

[0025] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0026] The thickness of the dielectric layer 14 is preferably 0.3 μm or more and 1.0 μm or less. Furthermore, the number of dielectric layers 14 stacked to constitute one capacitor portion 18 is preferably 4 or more and 1000 or less.

[0027] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b.

[0028] As shown in Figures 4 and 6, the first internal electrode layer 16a includes a plurality of first internal electrode layers 16a1 to 16a3 constituting the first capacitor section 181 to the third capacitor section 183, a plurality of first internal electrode layers 16a4 to 16a6 constituting the fourth capacitor section 184 to the sixth capacitor section 186, and a plurality of first internal electrode layers 16a7 to 16a9 constituting the seventh capacitor section 187 to the ninth capacitor section 189. The first internal electrode layers 16a1 to 16a3 are arranged on the same dielectric layer 14, the first internal electrode layers 16a4 to 16a6 are arranged on the same dielectric layer 14, and the first internal electrode layers 16a7 to 16a9 are arranged on the same dielectric layer 14. Furthermore, the first internal electrode layer 16a is led out to the second main surface 12d.

[0029] The first internal electrode layer 16a will be described in detail, using the first internal electrode layer 16a1 as an example. As shown in Figure 6, the first internal electrode layer 16a1 has a first opposing electrode portion 26a1 facing the second internal electrode layer 16b1, and a first leading portion 28a1 extending from the first opposing electrode portion 26a1 and leading out to the second main surface 12d. The first leading portion 28a1 is exposed to the second main surface 12d of the laminate 12. The shape of the first opposing electrode portion 26a1 and the shape of the first leading portion 28a1 are not particularly limited, but they are preferably rectangular. However, the corners of the first opposing electrode portion 26a1 may be rounded. Furthermore, the first internal electrode layers 16a2 to 16a9 have the same configuration as the first internal electrode layer 16a1.

[0030] As shown in Figures 4 and 7, the second internal electrode layer 16b includes a plurality of second internal electrode layers 16b1 to 16b3 constituting the first capacitor section 181 to the third capacitor section 183, a plurality of second internal electrode layers 16b4 to 16b6 constituting the fourth capacitor section 184 to the sixth capacitor section 186, and a plurality of second internal electrode layers 16b7 to 16b9 constituting the seventh capacitor section 187 to the ninth capacitor section 189. The second internal electrode layers 16b1 to 16b3 are arranged on the same dielectric layer 14, the second internal electrode layers 16b4 to 16b6 are arranged on the same dielectric layer 14, and the second internal electrode layers 16b7 to 16b9 are arranged on the same dielectric layer 14. Furthermore, the second internal electrode layer 16b is led out to the second main surface 12d.

[0031] The second internal electrode layer 16b will be described in detail, using the second internal electrode layer 16b1 as an example. As shown in Figure 7, the second internal electrode layer 16b1 has a second opposing electrode portion 26b1 that faces the first internal electrode layer 16a1, and a second leading portion 28b1 that extends from the second opposing electrode portion 26b1 and is drawn out to the second main surface 12d. The second leading portion 28b1 is exposed to the second main surface 12d of the laminate 12. The shape of the second opposing electrode portion 26b1 and the shape of the second leading portion 28b1 are not particularly limited, but they are preferably rectangular. However, the corners of the second opposing electrode portion 26b1 may be rounded. Furthermore, the second internal electrode layers 16b2 to 16b9 have the same configuration as the second internal electrode layer 16b1.

[0032] The first extension portions 28a1 to 28a9 have first exposed portions 29a1 to 29a9 that are exposed to the second main surface 12d. The second extension portions 28b1 to 28b9 have second exposed portions 29b1 to 29b9 that are exposed to the second main surface 12d.

[0033] The first exposed portions 29a1 to 29a3, which are located closest to the first side surface 12a, are curved in a convex shape toward the first side surface 12a when viewed from the second main surface 12d, as shown in Figure 9. The first exposed portions 29a7 to 29a9, which are located closest to the second side surface 12b, are curved in a convex shape toward the second side surface 12b when viewed from the second main surface 12d, as shown in Figure 9. The above-described configuration improves the adhesion between the dielectric layer 14 and the internal electrode layer 16, thereby suppressing the peeling of structural defects.

[0034] The second exposed portions 29b1 to 29b3, which are located closest to the first side surface 12a, are curved in a convex shape toward the first side surface 12a when viewed from the second main surface 12d, as shown in Figure 9. The second exposed portions 29b7 to 29b9, which are located closest to the second side surface 12b, are curved in a convex shape toward the second side surface 12b when viewed from the second main surface 12d, as shown in Figure 9. With the above configuration, the adhesion between the dielectric layer 14 and the internal electrode layer 16 can be improved, and peeling of structural defects can be suppressed.

[0035] As shown in Figure 10(a), the distance w between the central part of the first exposed portion 29a1, which is closest to the first side surface 12a, and the first side surface 12a is... 11 w is the distance between the end of the first exposed portion 29a1 closest to the first side surface 12a and the first side surface 12a. 12 It is smaller than that. The same applies to the first exposed parts 29a2 and 29a3. As shown in Figure 10(b), the distance w between the central part of the first exposed portion 29a7, which is closest to the second side surface 12b, and the second side surface 12b is... 13 w is the distance between the end of the first exposed portion 29a7 closest to the second side surface 12b and the second side surface 12b. 14 It is smaller than that. The same applies to the first exposed parts 29a8 and 29a9. With the above configuration, the adhesion between the dielectric layer 14 and the internal electrode layer 16 can be further improved, and peeling of structural defects can be suppressed.

[0036] As shown in Figure 10(a), the distance w between the central part of the second exposed portion 29b1, which is closest to the first side surface 12a, and the first side surface 12a is... 21 w is the distance between the end of the second exposed portion 29b1 closest to the first side surface 12a and the first side surface 12a. 22 It is smaller than that. The same applies to the second exposed parts 29b2 and 29b3. As shown in Figure 10(b), the distance w between the central part of the second exposed portion 29b7, which is closest to the second side surface 12b, and the second side surface 12b is 23 The distance W is the distance between the end of the second exposed portion 29b7 closest to the second side surface 12b and the second side surface 12b. 24 It is smaller than that. The same applies to the first exposed parts 29b8 and 29b9. With the above configuration, the adhesion between the dielectric layer 14 and the internal electrode layer 16 can be further improved, and peeling of structural defects can be suppressed.

[0037] As shown in Figures 10(a) and (b), the first exposed portions 29a1 to 29a3, which are closest to the first side surface 12a, and the first exposed portions 29a7 to 29a9, which are closest to the second side surface 12b, are exposed in a convex shape in opposite directions. As shown in Figures 10(a) and (b), the second exposed portions 29b1 to 29b3 located closest to the first side surface 12a and the second exposed portions 29b7 to 29b9 closest to the second side surface 12b are exposed in a convex shape in opposite directions.

[0038] As shown in Figure 10, in the length l1 of the first exposed portions 29a1 to 29a9 exposed from the second main surface 12d in the longitudinal direction z, the ratio of the maximum length l1 to the minimum length is preferably 1.0 or more and 1.5 or less. In Figure 10, the first exposed portions 29a1 and 29a7 are shown as an example. As shown in Figure 10, in the length l2 of the second exposed portions 29b1 to 29b9 exposed from the second main surface 12d in the longitudinal direction z, the ratio of the maximum length l2 to the minimum length is preferably 1.0 or more and 1.5 or less. In Figure 10, the second exposed portions 29b1 and 29b7 are shown as an example. The above configuration ensures contact between the external electrode 30 and the internal electrode layer 16, thereby improving impedance characteristics. Furthermore, the above configuration prevents the internal electrode layer 16 from being exposed to the external electrode 30, thus ensuring moisture resistance reliability.

[0039] The thickness of the first extension portions 28a1 to 28a9 and the second extension portions 28b1 to 28b9 is preferably 0.2 μm or more and 1.0 μm or less. With the above configuration, contact between the external electrode 30 and the internal electrode layer 16 can be ensured, and the impedance characteristics can be further improved.

[0040] As shown in Figure 9, the dimension w3 of the laminate 12 in the stacking direction x in the region where the first exposed portions 29a1 to 29a9 are located along the stacking direction x is greater than the dimension w4 of the laminate 12 in the stacking direction x in the region where neither the first exposed portions 29a1 to 29a9 nor the second exposed portions b1 to 29b9 are located along the stacking direction x. The same applies to the second exposed portions 29b1 to 29b9. With the above configuration, the surface of the laminate 12 becomes wavy, and when the multi-gang multilayer ceramic capacitor 10 is molded with molding resin, the wavy structure provides an anchoring effect, improving the adhesion force of the molding resin to the multi-gang multilayer ceramic capacitor 10.

[0041] In the first capacitor section 181, the first counter electrode section 26a1 of the first internal electrode layer 16a1 and the second counter electrode section 26b1 of the second internal electrode layer 16b1 face each other. In this embodiment, capacitance is formed and the characteristics of a capacitor are exhibited when the first counter electrode section 26a1 of the first internal electrode layer 16a1 and the second counter electrode section 26b1 of the second internal electrode layer 16b1 face each other via the dielectric layer 14. Furthermore, the second to ninth capacitor sections 182 to 189 have the same configuration as the first capacitor section 181, thereby exhibiting the characteristics of each capacitor.

[0042] By including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0043] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0044] The number of first internal electrode layers 16a stacked to constitute one capacitor section 18 is not particularly limited, but is preferably, for example, 1 to 250. Similarly, the number of second internal electrode layers 16b stacked to constitute one capacitor section 18 is not particularly limited, but is preferably, for example, 1 to 250. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b stacked to constitute one capacitor section 18 is preferably 2 to 500.

[0045] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.3 μm to 1.0 μm. The thickness of the second internal electrode layer 16b is also not particularly limited, but is preferably, for example, 0.3 μm to 1.0 μm.

[0046] By having the internal electrode layer 16 extended to the second main surface 12d side (mounting side), the current path can be shortened, and the ESL (equivalent series inductance) can be lowered compared to a two-terminal capacitor in which the internal electrode layer is exposed on both end faces, which is a common configuration. Furthermore, by using a multi-gang type multilayer ceramic capacitor 10 in which multiple capacitor sections are arranged on the laminate 12, multiple two-terminal capacitors can be replaced.

[0047] (external electrode) The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0048] The first external electrode 30a includes a plurality of first external electrodes 30a1 to 30a3. The plurality of first external electrodes 30a1 to 30a3 are arranged on the second main surface 12d at predetermined intervals along the length direction z. Furthermore, each of the plurality of first external electrodes 30a1 to 30a3 is arranged to extend in the stacking direction x.

[0049] The first external electrode 30a1 is electrically connected to the first exposed portions 29a1, 29a4, and 29a7 of the first internal electrode layers 16a1, 16a4, and 16a7. The first external electrode 30a1 is also positioned to cover the first exposed portions 29a1, 29a4, and 29a7 of the first internal electrode layers 16a1, 16a4, and 16a7 that are exposed on the second main surface 12d. The first external electrode 30a1 may also have a first folded portion 31a1 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0050] The first external electrode 30a2 is electrically connected to the first exposed portions 29a2, 29a5, and 29a8 of the first internal electrode layers 16a2, 16a5, and 16a8. The first external electrode 30a2 is also positioned to cover the first exposed portions 29a2, 29a5, and 29a8 of the first internal electrode layers 16a2, 16a5, and 16a8 that are exposed on the second main surface 12d. The first external electrode 30a2 may also have a first folded portion 31a2 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0051] The first external electrode 30a3 is electrically connected to the first exposed portions 29a3, 29a6, and 29a9 of the first internal electrode layers 16a3, 16a6, and 16a9. The first external electrode 30a3 is also positioned to cover the first exposed portions 29a3, 29a6, and 29a9 of the first internal electrode layers 16a3, 16a6, and 16a9 that are exposed on the second main surface 12d. The first external electrode 30a3 may also have a first folded portion 31a3 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0052] The second external electrode 30b includes a plurality of second external electrodes 30b1 to 30b3. The plurality of second external electrodes 30b1 to 30b3 are arranged on the second main surface 12d at predetermined intervals along the length direction z. Furthermore, each of the plurality of second external electrodes 30b1 to 30b3 is arranged to extend in the stacking direction x.

[0053] The second external electrode 30b1 is electrically connected to the second exposed portions 29b1, 29b4, and 29b7 of the second internal electrode layers 16b1, 16b4, and 16b7. The second external electrode 30b1 is also positioned to cover the second exposed portions 29b1, 29b4, and 29b7 of the second internal electrode layers 16b1, 16b4, and 16b7 that are exposed on the second main surface 12d. The second external electrode 30b1 may also have a second folded portion 31b1 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0054] The second external electrode 30b2 is electrically connected to the second exposed portions 29b2, 29b5, and 29b8 of the second internal electrode layers 16b2, 16b5, and 16b8. The second external electrode 30b2 is also positioned to cover the second exposed portions 29b2, 29b5, and 29b8 of the second internal electrode layers 16b2, 16b5, and 16b8 that are exposed on the second main surface 12d. The second external electrode 30b2 may also have a second folded portion 31b2 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0055] The second external electrode 30b3 is electrically connected to the second exposed portions 29b3, 29b6, and 29b9 of the second internal electrode layers 16b3, 16b6, and 16b9. The second external electrode 30b2 is positioned to cover the second exposed portions 29b3, 29b6, and 29b9 of the second internal electrode layers 16b3, 16b6, and 16b9 that are exposed on the second main surface 12d. The second external electrode 30b3 may also have a second folded portion 31b3 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0056] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0057] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0058] The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0059] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. More specifically, the first external electrodes 30a1 to 30a3 have first base electrode layers 32a1 to 32a3 and first plating layers 34a1 to 34a3. Furthermore, the second external electrode 30b has a second underlay electrode layer 32b and a second plating layer 34b. More specifically, the second external electrodes 30b1 to 30b3 have second underlay electrode layers 32b1 to 32b3 and second plating layers 34b1 to 34b3.

[0060] The first underlay electrode layers 32a1 to 32a3 are arranged on the surface of the second main surface 12d of the laminate 12 and are formed to extend from the second main surface 12d and cover a portion of the first side surface 12a and a portion of the second side surface 12b.

[0061] The second base electrode layers 32b1 to 32b3 are arranged on the surface of the second main surface 12d of the laminate 12 and are formed to extend from the second main surface 12d and cover a portion of the first side surface 12a and a portion of the second side surface 12b.

[0062] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0063] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0064] In the first underlay electrode layers 32a1 to 32a3 located on the second main surface 12d, the thickness in the height direction y connecting the first main surface 12c and the second main surface 12d is preferably 10 μm or more and 30 μm or less. In the second base electrode layers 32b1 to 32b3 located on the second main surface 12d, the thickness in the height direction y connecting the first main surface 12c and the second main surface 12d is preferably 10 μm or more and 30 μm or less.

[0065] Furthermore, the thickness in the stacking direction x connecting the first side surface 12a and the second side surface 12b at the center of the first folded portion 31a1 to 31a3 of the first underlay electrode layer 32a1 to 32a3, which is located in the height direction y connecting the first main surface 12c and the second main surface 12d, is preferably, for example, 1 μm or more and 20 μm or less. Furthermore, the thickness in the stacking direction x connecting the first side surface 12a and the second side surface 12b at the center of the second folded portion 31b1 to 31b3 of the second underlay electrode layer 32b1 to 32b3, which is located in the height direction y connecting the first main surface 12c and the second main surface 12d, is preferably, for example, 1 μm or more and 20 μm or less.

[0066] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0067] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multi-gang multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multi-gang multilayer ceramic capacitor 10.

[0068] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0069] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0070] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0071] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0072] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0073] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0074] The thickest part of the conductive resin layer is preferably, for example, 3 μm to 20 μm.

[0075] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0076] The plating layer 34 is positioned to cover the underlying electrode layer 32. The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0077] The first plating layer 34a is positioned to cover the first underlay electrode layer 32a. More specifically, the first plating layers 34a1 to 34a3 are positioned to cover the first underlay electrode layers 32a1 to 32a3, respectively. The second plating layer 34b is positioned to cover the second underlay electrode layer 32b. More specifically, the second plating layers 34b1 to 34b3 are positioned to cover the second underlay electrode layers 32b1 to 32b3, respectively.

[0078] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0079] The plating layer 34 may be formed by multiple layers. In this case, it is preferable that the plating layer 34 has a two-layer structure consisting of a lower plating layer made of Ni plating formed on the underlay electrode layer 32 and an upper plating layer made of Sn plating formed on the lower plating layer. In other words, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. The second plating layer 34b comprises a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0080] The lower plating layer made of Ni is used to prevent the base electrode layer 32 from being corroded by the solder when mounting the multi-gang multilayer ceramic capacitor 10, and the upper plating layer made of Sn is used to improve the wettability of the solder when mounting the multi-gang multilayer ceramic capacitor 10, making it easier to mount. The thickness of each plating layer is preferably 1 μm or more and 10 μm or less.

[0081] The length z dimension of the multi-gang multilayer ceramic capacitor 10 is denoted as dimension L. Dimension L is preferably 0.8 mm or more and 14.4 mm or less. Dimension L may also be 0.2 mm or more and 20.0 mm or less. The dimension T is the height y dimension of the multi-gang multilayer ceramic capacitor 10. The T dimension is preferably 0.5 mm or more and 0.8 mm or less. The T dimension may also be 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x of the multi-gang multilayer ceramic capacitor 10 is defined as the W dimension. The W dimension is preferably 0.4 mm or more and 7.8 mm or less. The W dimension may also be 0.2 mm or more and 20.0 mm or less.

[0082] In the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the internal electrode layer 16 is arranged to be exposed only on the second main surface 12d, which is the mounting surface. This shortens the current path, allowing for a lower ESL (equivalent series inductance) compared to a typical two-terminal capacitor where the internal electrode layer is exposed on both end surfaces.

[0083] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the laminate 12 has a capacitor section 18 consisting of multiple dielectric layers 14 and multiple internal electrode layers 16 arranged within a single element. Multiple capacitor sections 18 are arranged inside the laminate 12 at predetermined intervals in the longitudinal direction z and the stacking direction x. As a result, multiple two-terminal capacitors can be replaced by this multi-gang multilayer ceramic capacitor 10 alone.

[0084] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, by adjusting the number of capacitor sections 18 arranged inside the laminate 12 in the multi-gang multilayer ceramic capacitor 10 according to the arrangement of land electrodes, the arrangement of land electrodes for a normal two-terminal capacitor can be used as is without redesigning it.

[0085] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the first exposed portions 29a1 to 29a3, which are closest to the first side surface 12a, are curved convexly toward the first side surface 12a when viewed from the second main surface 12d, and the first exposed portions 29a7 to 29a9, which are closest to the second side surface 12b, are curved convexly toward the second side surface 12b when viewed from the second main surface 12d. Also, the second exposed portions 29b1 to 29b3, which are closest to the first side surface 12a, are curved convexly toward the first side surface 12a when viewed from the second main surface 12d, and the second exposed portions 29b7 to 29b9, which are closest to the second side surface 12b, are curved convexly toward the second side surface 12b when viewed from the second main surface 12d. This improves the adhesion between the dielectric layer 14 and the internal electrode layer 16, thereby suppressing the peeling of structural defects.

[0086] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of a multi-gang multilayer ceramic capacitor. The following describes the manufacturing method of the multi-gang multilayer ceramic capacitor 10.

[0087] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and solvent may be known substances.

[0088] Next, a conductive paste for internal electrodes is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer and a dielectric sheet with the pattern for the second internal electrode layer.

[0089] Here, multiple capacitor sections are formed by alternately stacking dielectric sheets on which a first internal electrode layer and a second internal electrode layer are printed, in order to obtain the desired structure.

[0090] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer portion 20a on the first side surface 12a. Then, the multiple capacitor portions 18 formed by the above process are stacked on top of the first outer layer portion 20a. Next, an intermediate layer 21 is formed by stacking a predetermined number of dielectric sheets without printed internal electrode layer patterns on top of the multiple capacitor portions 18. Then, multiple other capacitor portions 18 formed by the above process are stacked on top of the intermediate layer 21. Here, the layers containing the capacitor portions 18 and the intermediate layer 21 are repeated a predetermined number of times. Finally, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the multiple capacitor portions 18 to form the second outer layer portion 20b on the second side surface 12b. This completes the production of the laminated sheet.

[0091] Next, the laminated sheets are pressed in the lamination direction by means of hydrostatic pressure pressing or other means to produce a laminated block of a multi-gang type multilayer ceramic capacitor. At this time, the first exposed portion located closest to the first side surface 12a is formed to curve convexly toward the first side surface 12a when viewed from the second main surface 12d, and the first exposed portion located closest to the second side surface 12b is formed to curve convexly toward the second side surface 12b when viewed from the second main surface 12d. Furthermore, the second exposed portion located closest to the first side surface 12a is formed to curve convexly toward the first side surface 12a when viewed from the second main surface 12d, and the second exposed portion located closest to the second side surface 12b is formed to curve convexly toward the second side surface 12b when viewed from the second main surface 12d.

[0092] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0093] The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0094] (base electrode layer) Next, a first base electrode layer 32a for a plurality of first external electrodes 30a and a second base electrode layer 32b for a plurality of second external electrodes 30b are formed on the second main surface 12d of the laminate 12 obtained by firing.

[0095] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0096] Here, various methods can be used to form the baking layer. For example, a method can be used in which the orientation of the laminate 12 is aligned with a camera or magnet so that the second main surface 12d is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the second main surface 12d, but also on a part of the first side surface 12a and a part of the second side surface 12b.

[0097] Furthermore, it can also be formed using a roller transfer method. When forming the base electrode layer 32 not only on the second main surface 12d but also on a portion of the first side surface 12a and a portion of the second side surface 12b using the roller transfer method, it is possible to form the base electrode layer 32 on a portion of the first side surface 12a and a portion of the second side surface 12b by increasing the pressing pressure during roller transfer.

[0098] (Conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0099] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0100] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, for example, by extruding the conductive resin paste through a slit.

[0101] (thin film layer) Furthermore, when forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0102] Finally, a plating layer 34 is formed. The plating layer 34 is formed on the surface of the under electrode layer 32. More specifically, a Ni plating layer is formed on the under electrode layer 32 as the lower plating layer and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0103] As described above, the multi-gang type multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0104] 3. Experimental Examples Next, in order to confirm the effect of the multi-gang ceramic capacitor according to the present invention described above, experimental samples were prepared according to the manufacturing method described above, with varying lengths of the internal electrode layer and the side surface of the laminate, as well as with varying thicknesses and lengths of the lead-out sections. Experiments were then conducted to check for structural defects and impedance characteristics.

[0105] (1) Specifications of the multi-gang multilayer ceramic capacitor fabricated as a sample for the experimental example A multi-gang multilayer ceramic capacitor was fabricated using the manufacturing method according to the above embodiment. • Number of capacitor units in a multi-gang multilayer ceramic capacitor (N×M): 2×2 • Length dimension of multi-gang multilayer ceramic capacitor: 2.25 mm • Dimensions in the stacking direction of multi-gang ceramic capacitors: 1.25 mm • Height dimension of multi-gang ceramic capacitor: 0.45mm • Dielectric layer thickness: 0.50 μm • Thickness of the internal electrode layer: 0.50 μm • Number of layers: 400

[0106] (2) Experiments to confirm the effect on the adhesion between the dielectric layer and the internal electrode layer (2-1) Methods for quality assurance For each prepared sample, we checked whether or not structural defects had occurred. A digital microscope manufactured by Keyence Corporation (VHX-5000, VHX-8000) was used for the check.

[0107] (2-2) Conditions for determining a defect Each sample consisted of 100 pieces. If even one structural defect was found in any of the 100 pieces, it was judged to be defective.

[0108] (2-3) Specifications of the samples used in the experiment In Sample No. 1, w is the distance between the first side surface 12a and the central part of the first exposed portion 29a1 located closest to the first side surface 12a 11 and w is the distance between the first side surface 12a and the end of the first exposed portion 29a1 located closest to the first side surface 12a 12 , the relationship satisfies w 11 <w 12 , and for Sample No. 2, w 11 ≧w 12 was satisfied. The thickness of the lead-out portion of each sample was fixed at 0.5 µm. The ratio of the maximum length to the minimum length in the length direction of the lead-out portion of each sample was fixed at 1.2. When w3 is defined as the dimension of the laminated body 12 in the lamination direction x in a region where the first exposed portion 29a1 is located along the lamination direction x, and w4 is defined as the dimension of the laminated body 12 in the lamination direction x in a region where the first exposed portion 29a1 is not located along the lamination direction x, the relationship w3 > w4 is satisfied.

[0109] For Sample No. 3, the relationship between w3, which is the dimension of the laminated body 12 in the lamination direction x in a region where the first exposed portion 29a1 is located along the lamination direction x, and w4, which is the dimension of the laminated body 12 in the lamination direction x in a region where the first exposed portion 29a1 is not located along the lamination direction x, satisfies w3 > w4, and for Sample No. 4, the relationship w3 ≦ w4 is satisfied. The thickness of the lead-out portion of each sample was fixed at 0.5 µm. The ratio of the maximum length to the minimum length in the length direction of the lead-out portion of each sample was fixed at 1.2. w is the distance between the first side surface 12a and the central part of the first exposed portion 29a1 located closest to the first side surface 12a 11 and w is the distance between the first side surface 12a and the end of the first exposed portion 29a1 located closest to the first side surface 12a 12 , then w 11 <w 12 was satisfied.

[0110] (2-4) Results Table 1 shows the results of confirming structural defects with respect to differences in the length between the internal electrode layer and the side surface of the laminated body. Table 2 shows the results of examining structural defects in relation to the difference in dimensions in the lamination direction between the laminate in the region where the exposed portion is located and the laminate in the region where the exposed portion is not located.

[0111] [Table 1]

[0112] [Table 2]

[0113] According to Table 1, in sample number 1, the distance w between the central part of the first exposed portion 29a1, which is closest to the first side surface 12a, and the first side surface 12a is... 11 The distance w between the end of the first exposed portion 29a1 closest to the first side surface 12a and the first side surface 12a. 12 The relationship is, w 11 <w 12 Therefore, the adhesion between the dielectric layer and the internal electrode layer was good, and no structural defects were observed. On the other hand, in sample number 2, the distance w between the central part of the first exposed portion 29a1, which is closest to the first side surface 12a, and the first side surface 12a is... 11 The distance w between the end of the first exposed portion 29a1 closest to the first side surface 12a and the first side surface 12a. 12 The relationship is, w 11 ≧w 12 Therefore, a structural defect was confirmed due to poor adhesion between the dielectric layer and the internal electrode layer.

[0114] Furthermore, according to Table 2, in sample number 3, the relationship between the dimension w3 of the laminate 12 in the lamination direction x in the region where the first exposed portion 29a1 is located along the lamination direction x and the dimension w4 of the laminate 12 in the lamination direction x in the region where the first exposed portion 29a1 is not located along the lamination direction x is w3 > w4. Therefore, the adhesion between the dielectric layer and the internal electrode layer is good, and no structural defects were observed. On the other hand, in sample number 4, the relationship between the dimension w3 of the laminate 12 in the laminate direction x in the region where the first exposed portion 29a1 is located along the laminate direction x and the dimension w4 of the laminate 12 in the laminate direction x in the region where the first exposed portion 29a1 is not located along the laminate direction x is w3 ≤ w4. Therefore, a structural defect was confirmed because the adhesion between the dielectric layer and the internal electrode layer was poor.

[0115] (3) Experiment to confirm the effect of contact between the external electrode and the internal electrode layer on impedance characteristics (3-1) Methods for quality assurance Each sample was mounted on a circuit board. A network analyzer (E5080A) manufactured by Keyence Corporation was used for verification.

[0116] (3-2) Criteria for determining defects A good performance was determined if the impedance of the individual capacitor unit at 100MHz and 1GHz was equivalent to or less than that of a multilayer ceramic capacitor of the same size and capacitance per unit. On the other hand, if the impedance of the capacitor unit alone at 100MHz and 1GHz was greater than that of a multilayer ceramic capacitor of the same size and capacitance per unit, it was determined to be defective. Each sample size was set to 10.

[0117] (3-3) Specifications of the samples used in the experiment Samples No. 5 through No. 7 were prepared with internal electrode layer extension thicknesses of 0.1 μm, 0.2 μm, and 1.0 μm, respectively. The distance w between the central part of the first exposed portion 29a1, which is closest to the first side surface 12a, and the first side surface 12a. 11 The distance w between the end of the first exposed portion 29a1 closest to the first side surface 12a and the first side surface 12a. 12 When that happens, w 11 <w 12 That's what I decided. When the dimension w3 of the laminate 12 in the stacking direction x of the region where the first exposed portion 29a1 is located along the stacking direction x is denoted as w3, and the dimension w4 of the laminate 12 in the stacking direction x of the region where the first exposed portion 29a1 is not located along the stacking direction x is denoted as w3 > w4, we assumed that w3 > w4. The ratio of the maximum length to the minimum length in the longitudinal direction of the drawer portion of each sample was fixed at 1.2.

[0118] Samples No. 8 through No. 11 were prepared with ratios of the maximum length to the minimum length l1 of the exposed portion of the internal electrode layer to 1.0, 1.5, 1.7, and 1.9, respectively. The distance w between the central part of the first exposed portion 29a1, which is closest to the first side surface 12a, and the first side surface 12a. 11 The distance w between the end of the first exposed portion 29a1 closest to the first side surface 12a and the first side surface 12a. 12 When that happens, w 11 <w 12 That's what I decided. When the dimension w3 of the laminate 12 in the stacking direction x of the region where the first exposed portion 29a1 is located along the stacking direction x is denoted as w3, and the dimension w4 of the laminate 12 in the stacking direction x of the region where the first exposed portion 29a1 is not located along the stacking direction x is denoted as w3 > w4, we assumed that w3 > w4. The thickness of the drawer section was fixed at 0.5 μm.

[0119] (3-5) Results Table 3 shows the measured impedance characteristics with respect to changes in the thickness of the internal electrode layer lead-out. Table 4 shows the measured impedance characteristics with respect to changes in the ratio of the maximum length l1 of the internal electrode layer lead-out to the minimum length.

[0120] [Table 3]

[0121] [Table 4]

[0122] According to Table 3, in sample number 5, the thickness of the lead-out portion of the internal electrode layer was 0.1 μm, so contact between the external electrode and the internal electrode layer could not be ensured, resulting in an impedance characteristic that was greater than that of equivalent multilayer ceramic capacitors of the same size and capacitance per unit in the capacitor section. On the other hand, in samples 6 and 7, the thickness of the lead-out portion of the internal electrode layer was 0.2 μm and 1.0 μm, respectively. As a result, contact between the external electrode and the internal electrode layer was ensured, and the impedance characteristics were equivalent to or better than those of multilayer ceramic capacitors of the same size and capacitance per capacitor unit.

[0123] Furthermore, according to Table 4, in samples 8 and 9, the ratio of the maximum length to the minimum length of the internal electrode layer lead-out portion l1 was 1.0 and 1.5, respectively. As a result, contact between the external electrode and the internal electrode layer was ensured, and the impedance characteristics were equivalent to or better than those of multilayer ceramic capacitors of the same size and capacitance per capacitor unit. On the other hand, in samples 10 and 11, the ratio of the maximum length to the minimum length of the internal electrode layer lead-out portion l1 was 1.7 and 1.9, respectively. This resulted in large variations in the lead-out portion length l1, and contact between the external electrode and the internal electrode layer could not be ensured. Consequently, the impedance characteristics were greater than those of equivalent multilayer ceramic capacitors of the same size and capacitance per unit in the capacitor section.

[0124] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, and these modifications are included in the present invention. [Explanation of symbols]

[0125] 10 Multi-gang multilayer ceramic capacitors 12-layer structure 12a First side 12b Second Aspect 12c First main face 12d Second principal surface 12e First end face 12f Second end face 14 Dielectric layer 16 Internal electrode layer 16a, 16a1~16a9 First internal electrode layer 16b, 16b1~16b9 Second internal electrode layer 18 Capacitor section 181-189 First capacitor section to ninth capacitor section 20a First outer layer 20b Second outer layer 21 Middle Class 21a First intermediate layer 21b Second Mesopotamia 22a First end gap 22b Second end gap 23. Mid-term gap 23a First Intermediate Gap 23b Second Intermediate Gap 24a Upper area 24b Lower area 26a1~26a9 First counter electrode portion 26b1~26b9 Second counter electrode section 28a1~28a9 First drawer section 28b1~28b9 Second drawer section 29a1~29a9 First exposed area 29b1~29b9 Second exposed area 30 External electrode 30a, 30a1~30a3 First external electrodes 30b Second external electrode 31a1~31a3 First folded section 31b1~31b3 Second fold 32 Base electrode layer 32a, 32a1~32a3 First underlay electrode layer 32b, 32b1~32b3 Second base electrode layer 34 Plating layer 34a, 34a1~34a3 First plating layer 34b, 34b1~34b3 Second plating layer x stacking direction y: Height direction z-length direction

Claims

1. A laminate having a first side surface and a second side surface that are opposite to each other in the stacking direction, a first main surface and a second main surface that are opposite to each other in the height direction perpendicular to the stacking direction, and a first end surface and a second end surface that are opposite to each other in the length direction perpendicular to both the stacking direction and the height direction, A first external electrode extending in the stacking direction on the second main surface, A second external electrode extending in the stacking direction on the second main surface, Equipped with, The laminated body is Multiple capacitor sections, each consisting of multiple dielectric layers and multiple internal electrode layers, are arranged within a single element at predetermined intervals in the longitudinal and stacking directions. The internal electrode layer is A first internal electrode layer connected to the first external electrode, A second internal electrode layer connected to the second external electrode, Includes, The first internal electrode layer is The first opposing electrode portion and The first lead portion protruding toward the first external electrode, It has, The above-mentioned second internal electrode layer is The second opposing electrode portion, The second lead portion protruding toward the second external electrode, It has, The first extension portion has a first exposed portion that is exposed to the second main surface, The second extension portion has a second exposed portion that is exposed on the second main surface, The first exposed portion, which is closest to the first side surface, is curved convexly toward the first side surface when viewed from the second main surface. The first exposed portion, which is closest to the second side surface, is curved convexly toward the second side surface when viewed from the second main surface. The second exposed portion, which is closest to the first side surface, is curved convexly toward the first side surface when viewed from the second main surface. A multi-gang multilayer ceramic capacitor in which the second exposed portion, located closest to the second side surface, is curved convexly toward the second side surface when viewed from the second main surface.

2. A laminate having a first side surface and a second side surface that are opposite to each other in the stacking direction, a first main surface and a second main surface that are opposite to each other in the height direction perpendicular to the stacking direction, and a first end surface and a second end surface that are opposite to each other in the length direction perpendicular to both the stacking direction and the height direction, A first external electrode extending in the stacking direction on the second main surface, A second external electrode extending in the stacking direction on the second main surface, Equipped with, The laminated body is Multiple capacitor sections, each consisting of multiple dielectric layers and multiple internal electrode layers, are arranged within a single element at predetermined intervals in the longitudinal and stacking directions. The internal electrode layer is A first internal electrode layer connected to the first external electrode, A second internal electrode layer connected to the second external electrode, Includes, The first internal electrode layer is The first opposing electrode portion and The first lead portion protruding toward the first external electrode, It has, The above-mentioned second internal electrode layer is The second opposing electrode portion, The second lead portion protruding toward the second external electrode, It has, The distance between the central portion of the first exposed portion that is closest to the first side surface and the first side surface is smaller than the distance between the end of the first exposed portion that is closest to the first side surface and the first side surface. The distance between the central portion of the first exposed portion that is closest to the second side surface and the second side surface is smaller than the distance between the end of the first exposed portion that is closest to the second side surface and the second side surface. The distance between the central part of the second exposed portion that is closest to the first side surface and the first side surface is smaller than the distance between the end of the second exposed portion that is closest to the first side surface and the first side surface. A multi-gang multilayer ceramic capacitor in which the distance between the central part of the second exposed portion closest to the second side surface and the second side surface is smaller than the distance between the edge of the second exposed portion closest to the second side surface and the second side surface.

3. The first exposed portion located closest to the first side surface and the first exposed portion located closest to the second side surface are convex in opposite directions to each other. The multi-gang multilayer ceramic capacitor according to claim 1 or claim 2, wherein the second exposed portion located closest to the first side surface and the second exposed portion located closest to the second side surface are convex in opposite directions to each other.

4. The ratio of the maximum length to the minimum length in the longitudinal direction of the first exposed portion is 1.0 or more and 1.5 or less. The multi-gang type multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the ratio of the maximum length to the minimum length in the longitudinal direction of the second exposed portion is 1.0 or more and 1.5 or less.

5. The multi-gang type multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the thickness of the first lead portion and the second lead portion is 0.2 μm or more and 1.0 μm or less.

6. The dimension of the laminate in the stacking direction in the region where the first exposed portion is located is larger than the dimension of the laminate in the stacking direction in the region where the first exposed portion is not located. The multi-gang multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the dimension of the laminate in the stacking direction in the region where the second exposed portion is located is larger than the dimension of the laminate in the stacking direction in the region where the second exposed portion is not located.

7. The laminate has multiple capacitor units arranged at predetermined intervals, with N units in the longitudinal direction and M units in the stacking direction. 1 ≤ N ≤ 12 and 2 ≤ M ≤ 12, or 2 ≤ N ≤ 12 and 1 ≤ M ≤ 12 A multi-gang multilayer ceramic capacitor according to any one of claims 1 to 6, satisfying any of the conditions.

8. The multi-gang type multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the height dimension of the laminate is 1.00 mm or less.

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