Multi-gang multilayer ceramic capacitor

Abstract

This invention provides a multi-gang multilayer ceramic capacitor that can improve production efficiency by reducing costs and increasing yield. [Solution] In the multi-layer ceramic capacitor 10, the laminate 12 has multiple capacitor sections 18, each consisting of multiple dielectric layers and multiple internal electrode layers 16, arranged at predetermined intervals in the length direction Z and the stacking direction X within a single element. The internal electrode layers include a first internal electrode layer 16a connected to a first external electrode 30a and a second internal electrode layer 16b connected to a second external electrode 30b. The first internal electrode layer has a first opposing electrode portion and a first lead portion protruding toward the first external electrode, and the second internal electrode layer has a second opposing electrode portion and a second lead portion protruding toward the second external electrode. The maximum height dimension of the laminate is greater than the height dimension at a position halfway along the stacking direction.

Description

[Technical Field]

[0001] The present invention relates to a multi-type multilayer ceramic capacitor. [Background Art]

[0002] Along with the performance improvement of APUs (Accelerated Processing Units) used in smartphones and the like, impedance design for ensuring power supply stability during high-speed operation has become increasingly difficult. The most common countermeasure is to prepare a plurality of two-terminal capacitors having a normal configuration in which internal electrode layers are exposed on both end face sides, appropriately select these two-terminal capacitors in accordance with different frequency characteristics, and arrange them in parallel on a power supply line, thereby reducing impedance over a wide band. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 2019-179928 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] However, in this method, there are concerns about problems caused by increased cost and decreased yield due to an increase in the number of mounted components.

[0005] Therefore, a main object of the present invention is to provide a multi-type multilayer ceramic capacitor that can achieve cost reduction, yield improvement, and improvement in production efficiency. [Means for Solving the Problem]

[0006] The multi-layer ceramic capacitor according to this invention comprises a laminate having a first side surface and a second side surface opposite to each other in the stacking direction, a first main surface and a second main surface opposite to each other in the height direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in the length direction perpendicular to both the stacking direction and the height direction; a first external electrode extending in the stacking direction on the second main surface; and a second external electrode extending in the stacking direction on the second main surface, wherein the laminate has a capacitor section consisting of a plurality of dielectric layers and a plurality of internal electrode layers within a single element along its length. This is a multi-gang type multilayer ceramic capacitor, in which multiple units are arranged at predetermined intervals in the direction and stacking direction, and the internal electrode layer includes a first internal electrode layer connected to a first external electrode and a second internal electrode layer connected to a second external electrode, the first internal electrode layer having a first opposing electrode portion and a first lead portion protruding toward the first external electrode, and the second internal electrode layer having a second opposing electrode portion and a second lead portion protruding toward the second external electrode, and the maximum height dimension of the stack is greater than the height dimension at a position halfway along the stacking direction.

[0007] In the multi-gang multilayer ceramic capacitor according to this invention, the laminate has multiple capacitor sections, each consisting of multiple dielectric layers and multiple internal electrode layers, arranged at predetermined intervals in the longitudinal and lamination directions within a single element. The internal electrode layers include a first internal electrode layer connected to a first external electrode and a second internal electrode layer connected to a second external electrode. The first internal electrode layer has a first opposing electrode portion and a first lead portion protruding toward the first external electrode, and the second internal electrode layer has a second opposing electrode portion and a second lead portion protruding toward the second external electrode. This makes it possible to shorten the current path, thereby lowering the ESL (Equivalent Series Inductance) compared to a conventional two-terminal capacitor where the internal electrode layers are exposed on both end faces. Furthermore, this multi-gang multilayer ceramic capacitor alone can replace multiple two-terminal capacitors. In addition, by adjusting the number of capacitor sections arranged inside the laminate in the multi-gang multilayer ceramic capacitor according to the arrangement of the land electrodes, the arrangement of land electrodes for a conventional two-terminal capacitor can be used as is without redesigning it.

[0008] Furthermore, in the multi-gang multilayer ceramic capacitor according to this invention, the maximum height dimension of the laminate is greater than the height dimension at the halfway point in the lamination direction. Therefore, two sides of the second main surface are convex, which improves the stability of the mounting position. Moreover, with this configuration, when resin sealing with molding resin, there is a gap on the lower surface side of the laminate. This makes it easier for the molding resin to flow into the gap on the lower surface of the laminate, improving the adhesion force between the molding resin and the multi-gang multilayer ceramic capacitor. [Effects of the Invention]

[0009] This invention provides a multi-gang multilayer ceramic capacitor that can reduce costs, improve yield, and enhance production efficiency.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 2] This is a bottom view showing an example of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] This is a left side view showing an example of a multi-gang multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view of the line IV-IV shown in Figure 1. [Figure 5] This is a schematic cross-sectional view of the line VV shown in Figure 1. [Figure 6] This is a schematic cross-sectional view of the line VI-VI shown in Figure 3. [Figure 7] This is a schematic cross-sectional view of the line VII-VII shown in Figure 3. [Figure 8] This is a transparent perspective view showing the arrangement of the internal electrode layers inside the laminate of a multi-layer ceramic capacitor according to an embodiment of this invention. [Figure 9] This is a transparent perspective view showing the arrangement of exposed portions of the internal electrode layers inside the laminate of a multi-gang type multilayer ceramic capacitor according to an embodiment of this invention. [Figure 10] This is an exploded perspective view of the laminated body of a multi-gang type multilayer ceramic capacitor according to an embodiment of the present invention. [Modes for carrying out the invention]

[0012] 1. Multi-gang multilayer ceramic capacitor Next, an example of a multi-gang multilayer ceramic capacitor 10 according to an embodiment of this invention will be described.

[0013] FIG. 1 is an external perspective view showing a multiple laminated ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a bottom view showing an example of the multiple laminated ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a left side view showing an example of the multiple laminated ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a schematic cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a transparent perspective view showing an arrangement state of internal electrode layers inside a laminated body of the multiple laminated ceramic capacitor according to an embodiment of the present invention. FIG. 9 is a transparent perspective view showing an arrangement state of exposed portions of internal electrode layers inside a laminated body of the multiple laminated ceramic capacitor according to an embodiment of the present invention.

[0014] As shown in FIGS. 1 and 2, the multiple laminated ceramic capacitor 10 includes, for example, a laminated body 12 and external electrodes 30.

[0015] The laminated body 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. The internal electrode layers 16 include a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0016] The laminated body 12 has a first side surface 12a and a second side surface 12b opposed to each other in a lamination direction x, a first main surface 12c and a second main surface 12d opposed to each other in a height direction y orthogonal to the lamination direction x, and a first end surface 12e and a second end surface 12f opposed to each other in a length direction z orthogonal to both the lamination direction x and the height direction y. Note that the second main surface 12d is a surface on a mounting surface side.

[0017] In the multilayer body 12, a capacitor unit 18 composed of a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 is disposed within a single element. A plurality of said capacitor units 18 are arranged inside the multilayer body 12 at predetermined intervals in the length direction z and the lamination direction x. In the present embodiment, the capacitor units 18 include nine capacitor units, from the first capacitor unit 181 to the ninth capacitor unit 189.

[0018] It should be noted that, when assuming that a plurality of capacitor units 18 disposed inside the multilayer body 12 are arranged at predetermined intervals, with N capacitor units in the length direction z and M capacitor units in the lamination direction x, the capacitor units are preferably arranged so as to satisfy any one of the conditions: 1≦N≦12 and 2≦M≦12, or 2≦N≦12 and 1≦M≦12.

[0019] The multilayer body 12 has a rectangular parallelepiped shape, and it is preferable that corners and ridge portions of the multilayer body 12 are rounded. A corner is a portion where three surfaces of the multilayer body 12 intersect, and a ridge portion is a portion where two surfaces of the multilayer body 12 intersect. Further, unevenness or the like may be formed on part or all of the first side surface 12a and the second side surface 12b, the first main surface 12c and the second main surface 12d, and the first end surface 12e and the second end surface 12f.

[0020] The dimension t of the multilayer body 12 in the height direction y is preferably 1.00 mm or less.

[0021] As shown in Figure 4, the laminate 12 has, in the stacking direction x, a plurality of capacitor portions 18, a first outer layer portion 20a located between the first side surface 12a and the capacitor portion 18 (181-183) closest to the first side surface 12a, a second outer layer portion 20b located between the second side surface 12b and the capacitor portion 18 (187-189) closest to the second side surface 12b, and an intermediate layer 21 located between the capacitor portions 18. The intermediate layer 21 has a thickness of 10 times or more the dielectric layer 14 of the capacitor portion 18. In this embodiment, the intermediate layer 21 has a first intermediate layer 21a located between capacitor portions 181-183 and capacitor portions 184-186, and a second intermediate layer 21b located between capacitor portions 184-186 and capacitor portions 187-189.

[0022] Furthermore, as shown in Figure 4, the laminate 12 has, in the longitudinal direction z, a first end gap 22a located between the capacitor portion 18 (181, 184, 187) and the first end face 12e, a second end gap 22b located between the capacitor portion 18 (183, 186, 189) and the second end face 12f, and an intermediate gap 23 located between the capacitor portions 18. In this embodiment, the intermediate gap 23 has a first intermediate gap 23a located between the capacitor portions 181, 184, 187 and the capacitor portions 182, 185, 188, and a second intermediate gap 23b located between the capacitor portions 182, 185, 188 and the capacitor portions 183, 186, 189.

[0023] Furthermore, as shown in Figures 5 to 7, the laminate 12 has an upper region 24a located between the capacitor portion 18 and the first main surface 12c in the height direction y, and a lower region 24b located between the capacitor portion 18 and the second main surface 12d.

[0024] As shown in Figures 4 and 10, the first outer layer 20a is located on the first side surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first side surface 12a and the capacitor portion 18 (181-183) closest to the first side surface 12a. The second outer layer 20b is located on the second side surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second side surface 12b and the capacitor portion 18 (187-189) closest to the second side surface 12b.

[0025] The maximum height dimension y of the laminate 12 is greater than the height dimension y at the halfway point of the lamination direction x. This configuration allows for stable orientation of the multi-gang multilayer ceramic capacitor 10 during mounting. Furthermore, when molding resin is applied after mounting the multi-gang multilayer ceramic capacitor 10 to the mounting substrate, the molding resin can easily flow into the gap between the second main surface 12d of the laminate 12 and the mounting substrate, thereby improving the adhesion force of the molding resin to the multi-gang multilayer ceramic capacitor 10.

[0026] Preferably, the first main surface 12c has a projection 15a1 that extends from the first end face 12e to the second end face 12f, projecting in the height direction y along the edge on the side surface 12a. Furthermore, it is preferable that the first main surface 12c has a projection 15a2 that extends from the first end face 12e to the second end face 12f, projecting in the height direction y along the edge on the side surface 12b. As a result, the first main surface 12c appears concave when viewed from the second end face 12f. Similarly, it is preferable that the second main surface 12d has a projection 15b1 that extends from the first end face 12e to the second end face 12f, projecting in the height direction y along the edge on the side surface 12a. It is also preferable that the second main surface 12d has a projection 15b2 that extends from the first end face 12e to the second end face 12f, projecting in the height direction y along the edge on the side surface 12b. As a result, the second main surface 12d is concave when viewed from the second end face 12f. Thus, by having at least the second main surface 12d have protrusions 15b1 and 15b2, the orientation of the multi-gang multilayer ceramic capacitor 10 during mounting can be made more stable. Furthermore, when the molding resin is molded after the multi-gang multilayer ceramic capacitor 10 is mounted on the mounting substrate, the molding resin can easily flow into the gap between the second main surface 12d of the laminate 12 and the mounting substrate, thereby improving the adhesion force of the molding resin to the multi-gang multilayer ceramic capacitor 10.

[0027] Preferably, when viewed from the first end face 12e, the first main surface 12c has a distance d1 of 2 μm or more between the line m connecting the maximum point of the projection 15a1 provided on the edge of the first side surface 12a and the maximum point of the projection 15a2 provided on the edge of the second side surface 12b, and a point at half the distance in the stacking direction x. Similarly, when viewed from the first end face 12e, the second main surface 12d preferably has a distance of 2 μm or more between the line connecting the maximum point of the projection 15b1 provided on the edge of the first side surface 12a and the maximum point of the projection 15b2 provided on the edge of the second side surface 12b and the point at 1 / 2 of the stacking direction x. Thus, by having at least the second main surface 12d have protrusions 15b1 and 15b2, the orientation of the multi-gang multilayer ceramic capacitor 10 during mounting can be further stabilized. In addition, when the molding resin is molded after the multi-gang multilayer ceramic capacitor 10 is mounted on the mounting substrate, the molding resin can easily flow into the gap between the second main surface 12d of the laminate 12 and the mounting substrate, further improving the adhesion force of the molding resin to the multi-gang multilayer ceramic capacitor 10.

[0028] The maximum dimension of the laminate 12 in the longitudinal direction z is greater than the dimension of the longitudinal direction z at a position halfway along the lamination direction x. With this configuration, the contact area between the mold resin and the laminate 12 is increased during resin encapsulation with the mold resin, thereby improving the adhesion force of the mold resin to the multi-gang multilayer ceramic capacitor 10.

[0029] The first end face 12e has a projection 15c1 that extends from the first main surface 12c to the second main surface 12d, projecting in the longitudinal direction z along the edge on the side surface 12a. Furthermore, the first end face 12e has a projection 15c2 that extends from the first main surface 12c to the second main surface 12d, projecting in the longitudinal direction z along the edge on the side surface 12b. As a result, the first end face 12e is concave when viewed from the second main surface 12d. Similarly, the second end face 12f has a projection 15d1 that extends from the first main surface 12c to the second main surface 12d, projecting in the longitudinal direction z along the edge on the side surface 12a. The second end face 12f also has a projection 15d2 that extends from the first main surface 12c to the second main surface 12d, projecting in the longitudinal direction z along the edge on the side surface 12b. As a result, the second end face 12f is concave when viewed from the second main surface 12d. With the above configuration, the contact area between the mold resin and the laminate 12 is increased during resin encapsulation with the mold resin, thereby further improving the adhesion force of the mold resin to the multi-gang multilayer ceramic capacitor 10.

[0030] Preferably, when viewed from the second main surface 12d, the distance d2 of the line n connecting the maximum point of the projection 15c1 provided on the edge of the first side surface 12a and the maximum point of the projection 15c2 provided on the edge of the second side surface 12b, and the point at 1 / 2 of the stacking direction x, is 2 μm or more. Similarly, when viewed from the second main surface 12d, it is preferable that the distance between the line connecting the maximum point of the projection 15d1 provided on the edge of the first side surface 12a and the maximum point of the projection 15d2 provided on the edge of the second side surface 12b and the point at 1 / 2 of the stacking direction x is 2 μm or more. With the above configuration, the contact area between the mold resin and the laminate 12 is increased during resin encapsulation with the mold resin, thereby further improving the adhesion force of the mold resin to the multi-gang multilayer ceramic capacitor 10.

[0031] The radius of curvature R of the protrusions 15a1 to 15d2 of the laminate 12 shown in Figures 4 and 5 is preferably 10 μm to 200 μm. This suppresses cracking and chipping of the laminate 12, thereby improving the reliability of the multi-gang multilayer ceramic capacitor 10.

[0032] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0033] The thickness of the dielectric layer 14 is preferably 0.3 μm or more and 1.0 μm or less. Furthermore, the number of dielectric layers 14 stacked to constitute one capacitor portion 18 is preferably 4 or more and 1000 or less.

[0034] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b.

[0035] As shown in Figures 4 and 6, the first internal electrode layer 16a includes a plurality of first internal electrode layers 16a1 to 16a3 constituting the first capacitor section 181 to the third capacitor section 183, a plurality of first internal electrode layers 16a4 to 16a6 constituting the fourth capacitor section 184 to the sixth capacitor section 186, and a plurality of first internal electrode layers 16a7 to 16a9 constituting the seventh capacitor section 187 to the ninth capacitor section 189. The first internal electrode layers 16a1 to 16a3 are arranged on the same dielectric layer 14, the first internal electrode layers 16a4 to 16a6 are arranged on the same dielectric layer 14, and the first internal electrode layers 16a7 to 16a9 are arranged on the same dielectric layer 14. Furthermore, the first internal electrode layer 16a is led out to the second main surface 12d.

[0036] The first internal electrode layer 16a will be described in detail, using the first internal electrode layer 16a1 as an example. As shown in Figure 6, the first internal electrode layer 16a1 has a first opposing electrode portion 26a1 facing the second internal electrode layer 16b1, and a first leading portion 28a1 extending from the first opposing electrode portion 26a1 and leading out to the second main surface 12d. The first leading portion 28a1 has a first exposed portion 29a1 exposed to the second main surface 12d of the laminate 12. The shape of the first opposing electrode portion 26a1 and the shape of the first leading portion 28a1 are not particularly limited, but are preferably rectangular. However, the corners of the first opposing electrode portion 26a1 may be rounded. Furthermore, the first internal electrode layers 16a2 to 16a9 have the same configuration as the first internal electrode layer 16a1.

[0037] As shown in Figures 4 and 7, the second internal electrode layer 16b includes a plurality of second internal electrode layers 16b1 to 16b3 constituting the first capacitor section 181 to the third capacitor section 183, a plurality of second internal electrode layers 16b4 to 16b6 constituting the fourth capacitor section 184 to the sixth capacitor section 186, and a plurality of second internal electrode layers 16b7 to 16b9 constituting the seventh capacitor section 187 to the ninth capacitor section 189. The second internal electrode layers 16b1 to 16b3 are arranged on the same dielectric layer 14, the second internal electrode layers 16b4 to 16b6 are arranged on the same dielectric layer 14, and the second internal electrode layers 16b7 to 16b9 are arranged on the same dielectric layer 14. Furthermore, the second internal electrode layer 16b is led out to the second main surface 12d.

[0038] The second internal electrode layer 16b will be described in detail, using the second internal electrode layer 16b1 as an example. As shown in Figure 7, the second internal electrode layer 16b1 has a second opposing electrode portion 26b1 facing the first internal electrode layer 16a1, and a second leading portion 28b1 extending from the second opposing electrode portion 26b1 and leading out to the second main surface 12d. The second leading portion 28b1 has a second exposed portion 29b1 that is exposed to the second main surface 12d of the laminate 12. The shape of the second opposing electrode portion 26b1 and the shape of the second leading portion 28b1 are not particularly limited, but are preferably rectangular. However, the corners of the second opposing electrode portion 26b1 may be rounded. Furthermore, the second internal electrode layers 16b2 to 16b9 have the same configuration as the second internal electrode layer 16b1.

[0039] In the first capacitor section 181, the first counter electrode section 26a1 of the first internal electrode layer 16a1 and the second counter electrode section 26b1 of the second internal electrode layer 16b1 face each other. In this embodiment, capacitance is formed and the characteristics of a capacitor are exhibited when the first counter electrode section 26a1 of the first internal electrode layer 16a1 and the second counter electrode section 26b1 of the second internal electrode layer 16b1 face each other via the dielectric layer 14. Furthermore, the second to ninth capacitor sections 182 to 189 have the same configuration as the first capacitor section 181, thereby exhibiting the characteristics of each capacitor.

[0040] By including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0041] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0042] The number of first internal electrode layers 16a stacked to constitute one capacitor section 18 is not particularly limited, but is preferably, for example, 1 to 250. Similarly, the number of second internal electrode layers 16b stacked to constitute one capacitor section 18 is not particularly limited, but is preferably, for example, 1 to 250. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b stacked to constitute one capacitor section 18 is preferably 2 to 500.

[0043] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.3 μm to 1.0 μm. The thickness of the second internal electrode layer 16b is also not particularly limited, but is preferably, for example, 0.3 μm to 1.0 μm.

[0044] By having the internal electrode layer 16 extended to the second main surface 12d side (mounting side), the current path can be shortened, and the ESL (equivalent series inductance) can be lowered compared to a two-terminal capacitor in which the internal electrode layer is exposed on both end faces, which is a common configuration. Furthermore, by using a multi-gang type multilayer ceramic capacitor 10 in which multiple capacitor sections are arranged on the laminate 12, multiple two-terminal capacitors can be replaced.

[0045] (external electrode) The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0046] The first external electrode 30a includes a plurality of first external electrodes 30a1 to 30a3. The plurality of first external electrodes 30a1 to 30a3 are arranged on the second main surface 12d at predetermined intervals along the length direction z. Furthermore, each of the plurality of first external electrodes 30a1 to 30a3 is arranged to extend in the stacking direction x.

[0047] The first external electrode 30a1 is electrically connected to the first exposed portions 29a1, 29a4, and 29a7 of the first internal electrode layers 16a1, 16a4, and 16a7. The first external electrode 30a1 is also positioned to cover the first exposed portions 29a1, 29a4, and 29a7 of the first internal electrode layers 16a1, 16a4, and 16a7 that are exposed on the second main surface 12d. The first external electrode 30a1 may also have a first folded portion 31a1 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0048] The first external electrode 30a2 is electrically connected to the first exposed portions 29a2, 29a5, and 29a8 of the first internal electrode layers 16a2, 16a5, and 16a8. The first external electrode 30a2 is also positioned to cover the first exposed portions 29a2, 29a5, and 29a8 of the first internal electrode layers 16a2, 16a5, and 16a8 that are exposed on the second main surface 12d. The first external electrode 30a2 may also have a first folded portion 31a2 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0049] The first external electrode 30a3 is electrically connected to the first exposed portions 29a3, 29a6, and 29a9 of the first internal electrode layers 16a3, 16a6, and 16a9. The first external electrode 30a3 is also positioned to cover the first exposed portions 29a3, 29a6, and 29a9 of the first internal electrode layers 16a3, 16a6, and 16a9 that are exposed on the second main surface 12d. The first external electrode 30a3 may also have a first folded portion 31a3 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0050] The second external electrode 30b includes a plurality of second external electrodes 30b1 to 30b3. The plurality of second external electrodes 30b1 to 30b3 are arranged on the second main surface 12d at predetermined intervals along the length direction z. Furthermore, each of the plurality of second external electrodes 30b1 to 30b3 is arranged to extend in the stacking direction x.

[0051] The second external electrode 30b1 is electrically connected to the second exposed portions 29b1, 29b4, and 29b7 of the second internal electrode layers 16b1, 16b4, and 16b7. The second external electrode 30b1 is also positioned to cover the second exposed portions 29b1, 29b4, and 29b7 of the second internal electrode layers 16b1, 16b4, and 16b7 that are exposed on the second main surface 12d. The second external electrode 30b1 may also have a second folded portion 31b1 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0052] The second external electrode 30b2 is electrically connected to the second exposed portions 29b2, 29b5, and 29b8 of the second internal electrode layers 16b2, 16b5, and 16b8. The second external electrode 30b2 is also positioned to cover the second exposed portions 29b2, 29b5, and 29b8 of the second internal electrode layers 16b2, 16b5, and 16b8 that are exposed on the second main surface 12d. The second external electrode 30b2 may also have a second folded portion 31b2 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0053] The second external electrode 30b3 is electrically connected to the second exposed portions 29b3, 29b6, and 29b9 of the second internal electrode layers 16b3, 16b6, and 16b9. The second external electrode 30b2 is positioned to cover the second exposed portions 29b3, 29b6, and 29b9 of the second internal electrode layers 16b3, 16b6, and 16b9 that are exposed on the second main surface 12d. The second external electrode 30b3 may also have a second folded portion 31b3 that is positioned on a part of the first side surface 12a and a part of the second side surface 12b.

[0054] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0055] The base electrode layer 32 has a first base electrode layer 32a and a second base electrode layer 32b.

[0056] The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0057] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. More specifically, the first external electrodes 30a1 to 30a3 have first base electrode layers 32a1 to 32a3 and first plating layers 34a1 to 34a3. Furthermore, the second external electrode 30b has a second underlay electrode layer 32b and a second plating layer 34b. More specifically, the second external electrodes 30b1 to 30b3 have second underlay electrode layers 32b1 to 32b3 and second plating layers 34b1 to 34b3.

[0058] The first underlay electrode layers 32a1 to 32a3 are arranged on the surface of the second main surface 12d of the laminate 12 and are formed to extend from the second main surface 12d and cover a portion of the first side surface 12a and a portion of the second side surface 12b.

[0059] The second base electrode layers 32b1 to 32b3 are arranged on the surface of the second main surface 12d of the laminate 12 and are formed to extend from the second main surface 12d and cover a portion of the first side surface 12a and a portion of the second side surface 12b.

[0060] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0061] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0062] In the first underlay electrode layers 32a1 to 32a3 located on the second main surface 12d, the thickness in the height direction y connecting the first main surface 12c and the second main surface 12d is preferably 10 μm or more and 30 μm or less. In the second base electrode layers 32b1 to 32b3 located on the second main surface 12d, the thickness in the height direction y connecting the first main surface 12c and the second main surface 12d is preferably 10 μm or more and 30 μm or less.

[0063] Furthermore, the thickness in the stacking direction x connecting the first side surface 12a and the second side surface 12b at the center of the first folded portion 31a1 to 31a3 of the first underlay electrode layer 32a1 to 32a3, which is located in the height direction y connecting the first main surface 12c and the second main surface 12d, is preferably, for example, 1 μm or more and 20 μm or less. Furthermore, the thickness in the stacking direction x connecting the first side surface 12a and the second side surface 12b at the center of the second folded portion 31b1 to 31b3 of the second underlay electrode layer 32b1 to 32b3, which is located in the height direction y connecting the first main surface 12c and the second main surface 12d, is preferably, for example, 1 μm or more and 20 μm or less.

[0064] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0065] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multi-gang multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multi-gang multilayer ceramic capacitor 10.

[0066] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0067] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0068] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0069] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0070] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0071] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0072] The thickest part of the conductive resin layer is preferably, for example, 3 μm to 20 μm.

[0073] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0074] The plating layer 34 is positioned to cover the underlying electrode layer 32. The plating layer 34 has a first plating layer 34a and a second plating layer 34b.

[0075] The first plating layer 34a is positioned to cover the first underlay electrode layer 32a. More specifically, the first plating layers 34a1 to 34a3 are positioned to cover the first underlay electrode layers 32a1 to 32a3, respectively. The second plating layer 34b is positioned to cover the second underlay electrode layer 32b. More specifically, the second plating layers 34b1 to 34b3 are positioned to cover the second underlay electrode layers 32b1 to 32b3, respectively.

[0076] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0077] The plating layer 34 may be formed by multiple layers. In this case, it is preferable that the plating layer 34 has a two-layer structure consisting of a lower plating layer made of Ni plating formed on the underlay electrode layer 32 and an upper plating layer made of Sn plating formed on the lower plating layer. In other words, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. The second plating layer 34b comprises a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0078] The lower plating layer made of Ni is used to prevent the base electrode layer 32 from being corroded by the solder when mounting the multi-gang multilayer ceramic capacitor 10, and the upper plating layer made of Sn is used to improve the wettability of the solder when mounting the multi-gang multilayer ceramic capacitor 10, making it easier to mount. The thickness of each plating layer is preferably 1 μm or more and 10 μm or less.

[0079] The length z dimension of the multi-gang multilayer ceramic capacitor 10 is denoted as dimension L. Dimension L is preferably 0.8 mm or more and 14.4 mm or less. Dimension L may also be 0.2 mm or more and 20.0 mm or less. The dimension T is the height y dimension of the multi-gang multilayer ceramic capacitor 10. The T dimension is preferably 0.5 mm or more and 0.8 mm or less. The T dimension may also be 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x of the multi-gang multilayer ceramic capacitor 10 is defined as the W dimension. The W dimension is preferably 0.4 mm or more and 7.8 mm or less. The W dimension may also be 0.2 mm or more and 20.0 mm or less.

[0080] In the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the internal electrode layer 16 is arranged to be exposed only on the second main surface 12d, which is the mounting surface. This shortens the current path, allowing for a lower ESL (equivalent series inductance) compared to a typical two-terminal capacitor where the internal electrode layer is exposed on both end surfaces.

[0081] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the laminate 12 has a capacitor section 18 consisting of multiple dielectric layers 14 and multiple internal electrode layers 16 arranged within a single element. Multiple capacitor sections 18 are arranged inside the laminate 12 at predetermined intervals in the longitudinal direction z and the stacking direction x. As a result, multiple two-terminal capacitors can be replaced by this multi-gang multilayer ceramic capacitor 10 alone.

[0082] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, by adjusting the number of capacitor sections 18 arranged inside the laminate 12 in the multi-gang multilayer ceramic capacitor 10 according to the arrangement of land electrodes, the arrangement of land electrodes for a normal two-terminal capacitor can be used as is without redesigning it.

[0083] Furthermore, in the multi-gang multilayer ceramic capacitor 10 shown in Figure 1, the maximum dimension of the laminate 12 in the longitudinal direction z is larger than the dimension of the longitudinal direction z at a position halfway along the lamination direction x. Therefore, when resin sealing is performed with the molding resin, the contact area between the molding resin and the laminate 12 increases, thereby improving the adhesion force of the molding resin to the multi-gang multilayer ceramic capacitor 10.

[0084] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of a multi-gang multilayer ceramic capacitor. The following describes the manufacturing method of the multi-gang multilayer ceramic capacitor 10.

[0085] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and solvent may be known substances.

[0086] Next, a conductive paste for internal electrodes is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer and a dielectric sheet with the pattern for the second internal electrode layer.

[0087] Here, multiple capacitor sections are formed by alternately stacking dielectric sheets on which a first internal electrode layer and a second internal electrode layer are printed, in order to obtain the desired structure.

[0088] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer portion 20a on the first side surface 12a. Then, the multiple capacitor portions 18 formed by the above process are stacked on top of the first outer layer portion 20a. Next, an intermediate layer 21 is formed by stacking a predetermined number of dielectric sheets without printed internal electrode layer patterns on top of the multiple capacitor portions 18. Then, multiple other capacitor portions 18 formed by the above process are stacked on top of the intermediate layer 21. Here, the layers containing the capacitor portions 18 and the intermediate layer 21 are repeated a predetermined number of times. Finally, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the multiple capacitor portions 18 to form the second outer layer portion 20b on the second side surface 12b. This completes the production of the laminated sheet.

[0089] Next, the laminated sheets are pressed in the stacking direction using means such as hydrostatic pressing to produce a laminated block of a multi-gang multilayer ceramic capacitor. Furthermore, by incorporating a large amount of resin into the dielectric sheet used to form the first outer layer 20a and the second outer layer 20b, the laminated sheet can be made more stretchable by hydrostatic pressing, thereby enabling the formation of protrusions 15a1 to 15d2.

[0090] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0091] The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0092] (base electrode layer) Next, a first base electrode layer 32a for a plurality of first external electrodes 30a and a second base electrode layer 32b for a plurality of second external electrodes 30b are formed on the second main surface 12d of the laminate 12 obtained by firing.

[0093] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0094] Here, various methods can be used to form the baking layer. For example, a method can be used in which the orientation of the laminate 12 is aligned with a camera or magnet so that the second main surface 12d is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the second main surface 12d, but also on a part of the first side surface 12a and a part of the second side surface 12b.

[0095] Furthermore, it can also be formed using a roller transfer method. When forming the base electrode layer 32 not only on the second main surface 12d but also on a portion of the first side surface 12a and a portion of the second side surface 12b using the roller transfer method, it is possible to form the base electrode layer 32 on a portion of the first side surface 12a and a portion of the second side surface 12b by increasing the pressing pressure during roller transfer.

[0096] (Conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0097] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0098] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, for example, by extruding the conductive resin paste through a slit.

[0099] (thin film layer) Furthermore, when forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0100] Finally, a plating layer 34 is formed. The plating layer 34 is formed on the surface of the under electrode layer 32. More specifically, a Ni plating layer is formed on the under electrode layer 32 as the lower plating layer and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0101] As described above, the multi-gang type multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0102] 3. Experimental Examples Next, in order to confirm the effect of the multi-gang multilayer ceramic capacitor according to the present invention as described above, experimental samples were prepared by changing the distance d1 between the line m connecting the two protrusions at the ends of each sample and the central part of each sample, and by changing the R amount of the protrusions, according to the manufacturing method described above. Experiments were then conducted to check for the occurrence of chipping or cracking and the presence or absence of molding resin leakage.

[0103] (1) Specifications of the multi-gang multilayer ceramic capacitor fabricated as a sample for the experimental example A multi-gang multilayer ceramic capacitor was fabricated using the manufacturing method according to the above embodiment. • Number of capacitor units in a multi-gang multilayer ceramic capacitor (N×M): 2×2 • Length dimension of multi-gang multilayer ceramic capacitor: 2.25 mm • Dimensions in the stacking direction of multi-gang ceramic capacitors: 1.25 mm • Height dimension of multi-gang ceramic capacitor: 0.45mm • Dielectric layer thickness: 0.50 μm • Thickness of the internal electrode layer: 0.50 μm • Number of layers: 400

[0104] (2) Experiments to confirm the effect of chipping and cracking on moisture resistance reliability (2-1) Methods for quality assurance After the humidity load test, the presence or absence of chipping or cracking in samples that had deteriorated due to IR (irradiation emission) was checked. A Keyence digital microscope (VHX-8000) was used for the check.

[0105] (2-2) Humidity load test conditions The humidity load test was confirmed as follows: Specifically, a humidity resistance load test was conducted in which the voltage was kept below 4V for 144 hours under conditions of 125°C and 95% RH relative humidity. The test chambers used were ESPEC Corporation's heating chambers (EHS-221M, EHS-222M). Each sample was prepared with 100 pieces. If even one sample out of 100 exhibited a deterioration in moisture resistance due to chipping or cracking, it was judged as defective. Deterioration of moisture resistance was determined by the presence or absence of IR degradation.

[0106] (2-3) Specifications of the samples used in the experiment For samples numbered 1 through 3, samples were prepared with the distance d1 between the line m connecting the two protrusions at the ends of each sample and the central part of each sample set to 0 μm, 2 μm, and 10 μm, respectively. The R-value for each sample was fixed at 20 μm.

[0107] Samples numbered 4 through 6 were prepared with radius R values ​​of 1 μm, 10 μm, and 200 μm, respectively. The distance d1 between the line m connecting the two protrusions at the ends of each sample and the center of each sample was fixed at 5 μm.

[0108] (2-4) Results Table 1 shows the results of checking whether or not moisture resistance reliability deteriorates due to chipping or cracking in response to changes in the distance d1 between the line m connecting the two protrusions at the ends of each sample and the central part of each sample. Table 2 shows the results of checking whether or not moisture resistance reliability deteriorates due to chipping or cracking in response to changes in the R value of the protrusions.

[0109] [Table 1]

[0110] [Table 2]

[0111] According to Table 1, in sample number 1, the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample is 0 μm, thus confirming a deterioration in moisture resistance reliability due to chipping or cracking. On the other hand, in samples No. 2 and No. 3, the distance d1 between the line m connecting the two protrusions at the ends of the samples and the center of each sample was 2 μm and 10 μm, respectively, so no deterioration in moisture resistance reliability due to chipping or cracking was observed.

[0112] Furthermore, according to Table 2, in sample number 4, the radius of the protrusion was 1 μm, resulting in chipping and cracking, and a deterioration in moisture resistance reliability was confirmed. On the other hand, in samples 5 and 6, the radius of the protrusions was 10 μm and 200 μm, respectively, so no chipping or cracking occurred, and no deterioration in moisture resistance reliability was observed.

[0113] (3) Experiments on implementation feasibility (3-1) Methods for quality assurance Each sample was mounted on a substrate and sealed with molding resin. Next, the molded samples were polished to confirm that the molding resin had penetrated between the substrate and the sample. A Keyence digital microscope (VHX-8000) was used for this confirmation.

[0114] (3-2) Criteria for determining defects If no molding resin was present between the substrate and the sample, it was determined to be defective. Each sample was prepared in 100 units.

[0115] (3-3) Specifications of the samples used in the experiment For samples 7 through 9, samples were prepared by setting the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample to 0 μm, 2 μm, and 10 μm, respectively. Then, each sample was sealed with resin. The R quantity was fixed at 20 μm.

[0116] (3-5) Results Table 3 shows the results of confirming whether or not molding resin seeped between the substrate and the sample, based on the change in the distance d1 between the line m connecting the two protrusions at the ends of each sample and the central part of each sample.

[0117] [Table 3]

[0118] According to Table 3, in sample number 7, when the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample is 0 μm, it was confirmed that the molding resin did not penetrate and the improvement in adhesion strength was not achieved. On the other hand, in samples 8 and 9, when the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample was 2 μm and 10 μm, it was confirmed that the molding resin had entered between the substrate and the sample, and that the adhesion strength between the substrate and the sample could be improved.

[0119] The following effects were confirmed from the results of the above experiment. When the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample was 2 μm and 10 μm, it was confirmed that the deterioration of moisture resistance reliability due to chipping and cracking was suppressed. Furthermore, improved reliability due to suppression of chipping and cracking was confirmed even when the radius of the protrusion was 10 μm and 200 μm. Furthermore, it was confirmed that when the distance d1 between the line m connecting the two protrusions at the ends of the sample and the center of each sample is 2 μm and 10 μm, the molding resin can more easily fill the gap between the sample and the substrate during sealing with the molding resin, potentially improving the adhesion strength.

[0120] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, and these modifications are included in the present invention. [Explanation of symbols]

[0121] 10 Multi-gang multilayer ceramic capacitors 12-layer structure 12a First side 12b Second Aspect 12c First main face 12d Second principal surface 12e First end face 12f Second end face 14 Dielectric layer 15a1, 15a2, 15b1, 15b2, 15c1, 15c2, 15d1, 15d2 protrusion 16 Internal electrode layer 16a, 16a1~16a9 First internal electrode layer 16b, 16b1~16b9 Second internal electrode layer 18 Capacitor section 181-189 First capacitor section to ninth capacitor section 20a First outer layer 20b Second outer layer 21 Middle Class 21a First intermediate layer 21b Second Mesopotamia 22a First end gap 22b Second end gap 23. Mid-term gap 23a First Intermediate Gap 23b Second Intermediate Gap 24a Upper area 24b Lower area 26a1~26a9 First counter electrode portion 26b1~26b9 Second counter electrode section 28a1~28a9 First drawer section 28b1~28b9 Second drawer section 29a1~29a9 First exposed area 29b1~29b9 Second exposed area 30 External electrode 30a, 30a1~30a3 First external electrodes 30b, 30b1~30b3 Second external electrodes 31a1~31a3 First folded section 31b1~31b3 Second fold 32 Base electrode layer 32a, 32a1~32a3 First underlay electrode layer 32b, 32b1~32b3 Second base electrode layer 34 Plating layer 34a, 34a1~34a3 First plating layer 34b, 34b1~34b3 Second plating layer x stacking direction y: Height direction z-length direction

Claims

1. A laminate having a first side surface and a second side surface that are opposite to each other in the stacking direction, a first main surface and a second main surface that are opposite to each other in the height direction perpendicular to the stacking direction, and a first end surface and a second end surface that are opposite to each other in the length direction perpendicular to both the stacking direction and the height direction, A first external electrode extending in the stacking direction on the second main surface, A second external electrode extending in the stacking direction on the second main surface, Equipped with, The laminated body is Multiple capacitor sections, each consisting of multiple dielectric layers and multiple internal electrode layers, are arranged within a single element at predetermined intervals in the longitudinal and stacking directions. The internal electrode layer is A first internal electrode layer connected to the first external electrode, A second internal electrode layer connected to the second external electrode, Includes, The first internal electrode layer is The first opposing electrode portion and The first lead portion protruding toward the first external electrode, It has, The above-mentioned second internal electrode layer is The second opposing electrode portion, The second lead portion protruding toward the second external electrode, It has, A multi-gang ceramic capacitor wherein the maximum dimension in the height direction of the laminate is greater than the dimension in the height direction at a position halfway along the stacking direction.

2. The first main surface is provided with a projection that protrudes in the height direction along the edge of the first side surface, and a projection that protrudes in the height direction along the edge of the second side surface, and the first main surface is concave when viewed from the second end surface. The multi-gang ceramic capacitor according to claim 1, wherein the second main surface is provided with a projection that protrudes in the height direction along the edge of the first side surface, and a projection that protrudes in the height direction along the edge of the second side surface, and the second main surface is concave when viewed from the second end surface.

3. The first main surface, when viewed from the second end face, has a distance of 2 μm or more between the line connecting the maximum point of the projection along the first side surface and the maximum point of the projection along the second side surface, and the point at the halfway point in the stacking direction. The multilayer ceramic capacitor according to claim 1 or 2, wherein, when viewed from the second end face, the distance between the line connecting the maximum point of the projection provided along the first side surface and the maximum point of the projection provided along the second side surface and the tent at the 1 / 2 position in the stacking direction is 2 μm or more.

4. The multi-gang ceramic capacitor according to any one of claims 1 to 3, wherein the maximum dimension of the laminate in the longitudinal direction is greater than the dimension in the longitudinal direction at a position halfway along the lamination direction.

5. The first end face is provided with a projection that protrudes in the longitudinal direction along the edge of the first side surface, and a projection that protrudes in the longitudinal direction along the edge of the second side surface, and the first end face is concave when viewed from the second main surface. The multi-gang ceramic capacitor according to any one of claims 1 to 4, wherein the second end face is provided with a projection that protrudes in the longitudinal direction along the edge of the first side surface, and a projection that protrudes in the longitudinal direction along the edge of the second side surface, and the second end face is concave when viewed from the second main surface.

6. The first end face, when viewed from the second main surface, has a distance of 2 μm or more between the line connecting the maximum point of the projection provided on the edge of the first side surface and the maximum point of the projection provided on the edge of the second side surface and the point at the halfway point in the stacking direction. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, when viewed from the second main surface, the distance between the line connecting the maximum point of the projection provided on the edge of the first side surface and the maximum point of the projection provided on the edge of the second side surface and the point at the halfway point in the stacking direction is 2 μm or more.

7. The multi-gang type multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the radius of curvature R of the corner of the laminate is 10 μm or more and 200 μm or less.

8. The laminate has multiple capacitor units arranged at predetermined intervals, with N units in the longitudinal direction and M units in the stacking direction. 1 ≤ N ≤ 12 and 2 ≤ M ≤ 12, or 2 ≤ N ≤ 12 and 1 ≤ M ≤ 12 A multi-gang multilayer ceramic capacitor according to any one of claims 1 to 7, satisfying any of the conditions.

9. The multi-gang type multilayer ceramic capacitor according to any one of claims 1 to 8, wherein the height dimension of the laminate is 1.00 mm or less.

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