Wiring laminate, wiring board, circuit board, and method for manufacturing a wiring laminate

Abstract

This invention provides a novel wiring laminate that is advantageous in suppressing the thinning of the wiring layer due to etching of the seed layer. [Solution] The wiring laminate 2 comprises a seed layer 10 and a wiring layer 20. The wiring layer 20 is in contact with the seed layer 10 and is positioned on top of the seed layer 10. The wiring layer 20 contains copper. The seed layer 10 has a continuous phase containing silver.

Description

[Technical Field]

[0001] The present invention relates to a wiring laminate, a wiring board, a circuit board, and a method for manufacturing a wiring laminate. [Background Art]

[0002] Conventionally, wiring boards provided with a copper seed layer are known.

[0003] For example, Patent Document 1 describes a method for manufacturing a printed wiring board, and this printed wiring board is manufactured using a semi-additive process. Electroless copper plating is applied to the surface of an insulating plate to form a copper-containing seed layer. Next, after a plating resist is applied, electrolytic copper plating is performed on portions where a conductor pattern is to be formed through exposure and development processes. Thereafter, the resist is peeled off, and the seed layer remaining at the bottom between the formed conductor patterns is dissolved and removed by etching. In this way, a printed wiring board is formed. The printed wiring board has fine wiring with line / space of 50 μm / 50 μm or less.

[0004] For etching the seed layer, an etching solution is used in which the etching rate of the electroless copper plating forming the seed layer is at least twice the etching rate of the electrolytic copper plating. In the etching solution, the removal time for electroless copper plating on spaces in fine wiring with line / space of 50 μm / 50 μm or less is at most three times the removal time for electroless copper plating on spaces larger than 50 μm. [Prior Art Documents] [Non-Patent Literature]

[0005] [Patent Document 1] Japanese Unexamined Patent Publication No. 2005-005341 [Summary of the Invention] [Problem to be Solved by the Invention]

[0006] According to the printed circuit board manufacturing method described in Patent Document 1, the reduction in wiring width is suppressed because an etching solution that selectively etches electroless copper plating more selectively than electrolytic copper plating is used. On the other hand, even in such a manufacturing method, a reduction in wiring width can occur when the seed layer formed by electroless copper plating is removed by etching.

[0007] In view of these circumstances, the present invention provides a novel wiring laminate that is advantageous for suppressing the thinning of the wiring layer due to etching of the seed layer. [Means for solving the problem]

[0008] The present invention Seed layer, A wiring layer containing copper is provided, which is in contact with the seed layer and positioned on the seed layer. The seed layer has a continuous phase containing silver. A wiring laminate is provided.

[0009] Furthermore, the present invention is The above wiring stack comprises, We provide a wiring board.

[0010] Furthermore, the present invention is The above-mentioned wiring board is provided, We provide circuit boards.

[0011] Furthermore, the present invention is Forming a seed layer having a continuous phase containing silver by sputtering, A wiring layer having a predetermined wiring pattern and containing copper is formed on the seed layer by plating, This includes etching a portion of the seed layer that is not covered by the wiring layer, A method for manufacturing a wiring laminate is provided. [Effects of the Invention]

[0012] The above-described wiring laminate is advantageous in that it suppresses the thinning of the wiring layer due to etching of the seed layer. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a schematic diagram showing an example of a wiring board. [Figure 2] Figure 2 is a cross-sectional view of a wiring board with the line II-II shown in Figure 1 as the cutting line. [Figure 3] Figure 3 is a schematic diagram illustrating an example of a method for manufacturing a wiring board. [Figure 4] Figure 4 is a schematic diagram showing an example of a circuit board. [Modes for carrying out the invention]

[0014] Embodiments of the present invention will be described below with reference to the drawings. The following description is illustrative and does not limit the present invention to the following embodiments.

[0015] Figure 1 is a schematic diagram showing an example of a wiring board. Figure 2 is a cross-sectional view of the wiring board with the line II-II shown in Figure 1 as the cutting line. As shown in Figures 1 and 2, the wiring board 1a comprises a seed layer 10 and a wiring layer 20. The wiring layer 20 is in contact with the seed layer 10 and is placed on top of the seed layer 10. In the wiring board 1a, a wiring laminate 2 comprising the seed layer 10 and the wiring layer 20 is formed. The wiring layer 20 contains copper. The seed layer 10 has a continuous phase containing silver. The seed layer 10 does not have a dispersed phase containing silver, for example. The seed layer 10 may have only a continuous phase, or it may have a dispersed phase.

[0016] For example, when the wiring laminate 2 is manufactured by a semi-additive method, an etching solution suitable for the seed layer 10 having a silver-containing continuous phase can be used as the etching solution for etching the seed layer 10. This can suppress the thinning of the copper-containing wiring layer 20 caused by the etching of the seed layer 10. When the seed layer is a copper seed layer, even if an etching solution that selectively etches electroless copper plating over electrolytic copper plating is used as in the technique described in Patent Document 1, the influence of the seed layer etching can extend to a certain extent to the copper wiring layer. On the other hand, when the wiring laminate 2 is manufactured by a semi-additive method, an etching solution suitable for the seed layer 10 having a silver-containing continuous phase is used, so the influence of the etching of the seed layer 10 on the wiring layer 20 is considered to be smaller.

[0017] In the semi-additive method, in consideration of the thinning of the wiring layer caused by the etching of the seed layer, it is also conceivable to adjust the width of the wiring layer to be larger in advance during photolithography for forming the wiring layer. However, in this case, the thinning of the wiring layer does not occur uniformly over the entire in-plane area of the wiring board during the etching of the seed layer, which may cause variation in the width of the wiring layer. On the other hand, when the wiring laminate 2 is manufactured by a semi-additive method, an etching solution suitable for the seed layer 10 having a silver-containing continuous phase is used, so there is no need to adjust the width of the wiring layer to be larger in advance.

[0018] The thickness of the seed layer 10 is not limited to a specific value. The thickness of the seed layer 10 is, for example, 50 nm or more and 300 nm or less. When the thickness of the seed layer 10 is 50 nm or more, the wiring layer 20 is likely to be uniformly formed on the seed layer 10. When the thickness of the seed layer 10 is 300 nm or less, the time required for etching the seed layer 10 tends to be shortened when manufacturing the wiring laminate 2 by the semi-additive method, and the thinning of the wiring layer 20 caused by the etching of the seed layer 10 can be further suppressed.

[0019] The thickness of the seed layer 10 is preferably 50 nm to 250 nm, more preferably 50 nm to 200 nm, and even more preferably 100 nm to 200 nm.

[0020] The seed layer 10 is not limited to a specific layer as long as it has a continuous phase containing silver. The seed layer 10 is, for example, a sputtered layer. In this case, the seed layer 10 is likely to have the desired thickness. The seed layer 10 may also be a film formed by vacuum deposition, ion plating, chemical vapor deposition, or other dry processes.

[0021] The seed layer 10 may contain, for example, a silver alloy. In this case, the seed layer 10 is likely to have additional properties such as environmental resistance. The seed layer 10 may also contain pure silver.

[0022] If the seed layer 10 contains a silver alloy, the silver alloy may contain, for example, palladium and copper. In this case, the seed layer 10 is likely to have resistance to ion migration, etching, corrosion, or heat. The silver content in the silver alloy is not limited to a specific value. The silver content is, for example, 95% by mass or more.

[0023] The wiring layer 20 is, for example, a plating layer. The wiring layer 20 can be formed, for example, by electroplating. The thickness of the wiring layer 20 is not limited to a specific value. The thickness of the wiring layer 20 is, for example, 1.5 μm or more and 10 μm or less. The copper content in the wiring layer 20 is, for example, 90% or more.

[0024] As shown in Figures 1 and 2, the wiring layer 20 forms a pattern with a predetermined line-and-space (L / S) ratio. This L / S ratio is not limited to a specific value. For example, this L / S ratio is 5 μm / 5 μm or less. In other words, L, which corresponds to the width of the wiring layer 20, is 5 μm or less, and S, which corresponds to the spacing between adjacent wiring layers, is 5 μm or less. Even when the L / S ratio of the pattern formed by the wiring layer 20 is adjusted to be this small when manufacturing the wiring laminate 2 by the semi-additive method, the thinning of the wiring layer 20 due to etching of the seed layer 10 is easily suppressed.

[0025] In the pattern formed by the wiring layer 20, L / S may be 4 μm / 4 μm or less, or 3 μm / 3 μm or less. For example, L / S may be 0.5 μm / 0.5 μm or more.

[0026] As shown in Figures 1 and 2, the wiring laminate 2 is supported by, for example, a substrate 5. The substrate 5 is not limited to a specific substrate. The substrate 5 may be a rigid substrate or a flexible substrate. Examples of materials for base material 5 include polyimide, polyamide-imide, polyamide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, acrylonitrile-butadiene-styrene (ABS) resin, polymer alloys of ABS and polycarbonate, acrylic resins such as poly(meth)acrylate, polytetrafluoroethylene, polyvinylidene fluoride, polyvinyl chloride, polyvinylidene chloride, polyvinyl alcohol, polycarbonate, polyethylene, polypropylene, polyurethane, liquid crystal polymer (LCP), polyetheretherketone (PEEK), polyphenylene sulfide (PPS), polyphenylene sulfone (PPSU), epoxy resin, cellulose nanofiber, silicon, silicon carbide, gallium nitride, sapphire, ceramics, glass, diamond-like carbon (DLC), alumina, stainless steel foil, copper foil, and iron foil.

[0027] The substrate 5 may be a silicon wafer. The resistivity of the silicon wafer is, for example, 1 to 100 Ω·cm. The surface of the silicon wafer may be mirror-finished.

[0028] The thickness of the substrate 5 is not limited to a specific value. The substrate 5 may be, for example, 1 to 1000 μm, and may also be 5 to 550 μm, 10 to 550 μm, 50 to 550 μm, 100 to 550 μm, 200 to 550 μm, 300 to 550 μm, 400 to 550 μm, or 500 to 550 μm.

[0029] As shown in Figure 2, the wiring board 1a includes, for example, an intermediate layer 30 between the substrate 5 and the seed layer 10 in the thickness direction of the seed layer 10. The intermediate layer 30 is a layer for improving the adhesion between the substrate 5 and the seed layer 10. The intermediate layer 30 includes, for example, at least one selected from the group consisting of Ni, Ti, and Cr. Preferably, the intermediate layer 30 includes at least one selected from the group consisting of Ti and Cr.

[0030] The thickness of the intermediate layer 30 is not limited to a specific value. The thickness of the intermediate layer 30 may be, for example, 5 to 40 nm, or it may be 10 to 30 nm.

[0031] The intermediate layer 30 is, for example, a sputtering layer. The intermediate layer 30 may also be a film formed by vacuum deposition, ion plating, chemical vapor deposition, or other dry processes.

[0032] The wiring board 1a may, if necessary, include vias, lands, pads, etc., containing conductive material.

[0033] An example of a manufacturing method for the wiring board 1a is shown. Figure 3 is a schematic diagram illustrating an example of a manufacturing method for the wiring board 1a. The wiring laminate 2 may be manufactured, for example, by a semi-additive method, and may be manufactured by a method including (I), (II), and (III) below. (I) A seed layer 10 having a continuous phase containing silver is formed by a dry process. (II) A wiring layer 20 having a predetermined wiring pattern and containing copper is formed on the seed layer 10 by plating. (III) Etch a portion of the seed layer 10 that is not covered by the wiring layer 20.

[0034] As shown in Figure 3, for example, an intermediate layer 30 is formed on the substrate 5. The intermediate layer 30 is formed, for example, by sputtering. The intermediate layer 30 may also be formed by vacuum deposition, ion plating, chemical vapor deposition, or other dry processes.

[0035] Next, a seed layer 10 is formed on the intermediate layer 30. The seed layer 10 is formed, for example, by sputtering. The seed layer 10 may also be formed by vacuum deposition, ion plating, chemical vapor deposition, or other dry processes.

[0036] Next, a resist 40 is formed on the seed layer 10. The resist 40 can be formed using a known photosensitive resin used for forming resists in a semi-additive method. Next, the resist 40 is exposed using a photomask to expose the areas corresponding to a predetermined wiring pattern on which the wiring layer 20 is to be formed. Next, the exposed areas of the resist 40 are removed with a predetermined solvent to form an opening 40h corresponding to the wiring pattern. The opening 40h exposes a portion of the surface of the seed layer 10.

[0037] Next, a wiring layer 20 is formed on the surface of the seed layer 10 exposed at the opening 40h by plating. The plating is, for example, electroplating.

[0038] Next, the resist 40 is removed. The removal of the resist 40 may be carried out by a wet process using an organic solvent or the like, or by a dry process using plasma and ozone or the like.

[0039] Next, a portion of the seed layer 10 not covered by the wiring layer 20 is etched. An etching solution suitable for the seed layer 10, which has a continuous phase containing silver, is selected as the etching solution. The etching solution is not limited to a specific one, as long as it can etch the seed layer 10. An example of an etching solution is the ADEKA etching solution (ADEKA ELUMICA SVE series). Next, a portion of the intermediate layer 30 not covered by the wiring layer 20 is also removed using an etching solution suitable for etching the intermediate layer 30. In this way, the wiring board 1a is obtained.

[0040] A circuit board equipped with a wiring board 1a can be provided. Figure 4 is a schematic diagram showing an example of a circuit board. As shown in Figure 4, the circuit board 3a is equipped with a wiring board 1a.

[0041] A predetermined electronic device 4 is mounted on the circuit board 3a, and the electronic device 4 is electrically connected to the wiring layer 20. Thus, the circuit board 3a comprises an electrical circuit including the wiring layer 20 and the electronic device 4. [Examples]

[0042] The present invention will be described in more detail below with reference to examples. However, the present invention is not limited to the following examples.

[0043] <Example 1> A chromium layer and a seed layer were formed on one main surface of a silicon wafer substrate by continuous sputtering. The chromium layer had a thickness of 20 nm, and the seed layer had a thickness of 200 nm. The chromium layer was positioned between the main surface of the silicon wafer and the seed layer in its thickness direction. An APC alloy containing silver, palladium, and copper was used as a target for forming the seed layer. Therefore, the seed layer was formed as an APC alloy film. The silver content in the APC alloy was 90% by mass or more. Next, a photosensitive resin AZ Mir900 Photoresist manufactured by Merck was placed on top of the seed layer to form a resist layer. Next, the resist layer was exposed using a photomask to form photosensitive areas of a predetermined pattern, and the photosensitive areas were removed using a developer to form openings corresponding to the predetermined pattern. A portion of the surface of the seed layer was exposed by the openings. Next, a copper plating layer was formed as a wiring layer on the exposed portion of the seed layer surface by electroplating. The thickness of the wiring layer was 2 μm, and the resist layer was removed to obtain an evaluation sample according to the example. In this evaluation sample, the wiring layer formed a pattern with an L / S ratio of 2 μm / 2 μm.

[0044] The seed layer of the evaluation sample according to the example was brought into contact with an etching solution manufactured by ADEKA Corporation (ADEKA ELUMICA SVE series) to etch the seed layer. The etching time was set to a time equivalent to 100% of the standard time corresponding to a seed layer with a thickness of 200 nm. The standard time was determined as follows. APC alloy films of different thicknesses, formed under the same conditions as the seed layer formation in the above evaluation sample, were etched using the above etching solution, and the shortest etching time required to completely remove each APC alloy film was measured. Based on these measurement results, a calibration curve was created showing the relationship between the shortest etching time required to completely remove the APC alloy film and the thickness of the APC alloy film. In this calibration curve, the shortest etching time required to completely remove the APC alloy film corresponding to a thickness of 200 nm was defined as the standard time.

[0045] Using a Keyence laser microscope, the width of each wiring layer (wiring width) was measured at four locations before and after etching of the seed layer, and the arithmetic mean was calculated. In this measurement, the laser microscope was focused on the outermost surface of the wiring layer in the evaluation sample. The reduction in wiring width was calculated according to the following formula (1). The results are shown in Table 1. Reduction in wiring width [μm] = Arithmetic mean of wiring width before etching [μm] - Arithmetic mean of wiring width after etching [μm] Equation (1)

[0046] <Example 2> In etching the seed layer of the evaluation sample according to the example, the reduction in wiring width was calculated in the same manner as in Example 1, except that the etching time was changed to a time equivalent to 120% of the standard time corresponding to a seed layer with a thickness of 200 nm. The results are shown in Table 1.

[0047] <Comparative Example 1> A chromium layer and a seed layer were formed on one main surface of a silicon wafer substrate by continuous sputtering. The chromium layer had a thickness of 20 nm, and the seed layer had a thickness of 100 nm. The chromium layer was positioned between the main surface of the silicon wafer and the seed layer in its thickness direction. Cu was used as the target for forming the seed layer. Therefore, the seed layer was formed as a Cu film. Next, a photosensitive resin AZ Mir900 Photoresist manufactured by Merck was placed on top of the seed layer to form a resist layer. Next, the resist layer was exposed using a photomask to form photosensitive areas of a predetermined pattern, and the photosensitive areas were removed using a developer to form openings corresponding to the predetermined pattern. A portion of the surface of the seed layer was exposed by the openings. Next, a copper plating layer was formed as a wiring layer on the exposed portion of the seed layer surface by electroplating. The wiring layer had a thickness of 2 μm, and the resist layer was removed to obtain an evaluation sample related to the comparative example. In this evaluation sample, the wiring layer formed a pattern with an L / S ratio of 2 μm / 2 μm.

[0048] The seed layer of the evaluation sample for the comparative example was etched by contacting it with an etching solution manufactured by ADEKA Corporation (ADEKA ELUMIA CSE series). The etching time was set to 100% of the standard time corresponding to a seed layer with a thickness of 100 nm. The standard time was determined as follows. Etching was performed using the above etching solution on Cu films of different thicknesses formed under the same conditions as the seed layer formation in the above evaluation sample, and the shortest etching time required to completely remove each Cu film was measured. Based on these measurement results, a calibration curve was created showing the relationship between the shortest etching time required to completely remove the Cu film and the thickness of the Cu film. In this calibration curve, the shortest etching time required to completely remove a Cu film with a thickness of 100 nm was defined as the standard time.

[0049] Using a Keyence laser microscope, the width of each wiring layer (wiring width) before and after etching of the seed layer was measured at four locations, and the arithmetic mean was calculated. In this measurement, the laser microscope was focused on the outermost surface of the wiring layer in the evaluation sample. Based on these measurement results, the reduction in wiring width was calculated according to equation (1) above. The results are shown in Table 1.

[0050] <Comparative Examples 2 and 3> In etching the seed layer of the evaluation sample according to the example, the reduction in wiring width was calculated in the same manner as in Comparative Example 1, except that the etching time was changed to a time equivalent to 120% or 150% of the standard time corresponding to a seed layer with a thickness of 100 nm. The results are shown in Table 1.

[0051] As shown in Table 1, the reduction in wiring width was 0.05 μm or more in each comparative example, whereas in each example, the wiring width remained almost unchanged before and after etching, resulting in a reduction of 0. A comparison between the example and the comparative example suggests that the presence of a continuous phase containing silver in the seed layer can suppress the narrowing of the wiring layer due to etching of the seed layer.

[0052] [Table 1]

[0053] The first aspect of the present invention is, Seed layer, A wiring layer containing copper is provided, which is in contact with the seed layer and positioned on the seed layer. The seed layer has a continuous phase containing silver. A wiring laminate is provided.

[0054] A second aspect of the present invention is, in the first aspect, The seed layer has a thickness of 50 nm to 300 nm. A wiring laminate is provided.

[0055] A third aspect of the present invention is that, in the first or second aspect, The aforementioned seed layer is a sputtering layer. A wiring laminate is provided.

[0056] A fourth aspect of the present invention is that in any one of the first to third aspects, The aforementioned seed layer contains a silver alloy, A wiring laminate is provided.

[0057] The fifth aspect of the present invention is, in the fourth aspect, The aforementioned silver alloy contains palladium and copper. A wiring laminate is provided.

[0058] The sixth aspect of the present invention is that in any one of the first to fifth aspects, The aforementioned wiring layer forms a pattern having line-and-space (L / S) dimensions of 5 μm / 5 μm or less. A wiring laminate is provided.

[0059] The seventh aspect of the present invention is, A wiring stack comprising one of the first to sixth sides, We provide a wiring board.

[0060] The eighth aspect of the present invention is, Equipped with a wiring board on the seventh side, We provide circuit boards.

[0061] The ninth aspect of the present invention is, Forming a seed layer having a continuous phase containing silver by a dry process, A wiring layer having a predetermined wiring pattern and containing copper is formed on the seed layer by plating, This includes etching a portion of the seed layer that is not covered by the wiring layer, A method for manufacturing a wiring laminate is provided. [Explanation of symbols]

[0062] 1a Wiring board 2 Wiring Stack 3a Circuit board 10 Seed Layer 20 wiring layer

Claims

1. Seed layer, A wiring layer containing copper is provided, which is in contact with the seed layer and positioned on the seed layer. The seed layer has a continuous phase containing silver. Wiring stack.

2. The seed layer has a thickness of 50 nm to 300 nm. The wiring laminate according to claim 1.

3. The aforementioned seed layer is a sputtering layer. The wiring laminate according to claim 1.

4. The aforementioned seed layer contains a silver alloy, The wiring laminate according to claim 1.

5. The aforementioned silver alloy contains palladium and copper. The wiring laminate according to claim 4.

6. The aforementioned wiring layer forms a pattern having line-and-space (L / S) dimensions of 5 μm / 5 μm or less. The wiring laminate according to claim 1.

7. A wiring laminate comprising the wiring laminate according to any one of claims 1 to 6, wiring board.

8. A wiring board as described in claim 7, Circuit board.

9. Forming a seed layer having a continuous phase containing silver by a dry process, A wiring layer having a predetermined wiring pattern and containing copper is formed on the seed layer by plating, This includes etching a portion of the seed layer that is not covered by the wiring layer, A method for manufacturing a wiring array.

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