Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device capable of suppressing the occurrence of wormholes within a semiconductor substrate when forming contact plugs. [Solution] The semiconductor substrate has an upper surface, and the interlayer insulating film is formed on the upper surface and has an opening, and a first insulating film and a second insulating film are provided. A first trench and a second trench are formed on the upper surface. In a plan view, each of the first trench and the second trench extends along a first direction so as to cross the opening. In a plan view, the first trench and the second trench are spaced apart from each other along a second direction perpendicular to the first direction. The first insulating film is formed in the first trench. The second insulating film is formed in the second trench. In a plan view, a recess is formed on the upper surface that overlaps with the opening and is located between the first insulating film and the second insulating film.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. BACKGROUND ART

[0002] For example, in the semiconductor device disclosed in Japanese Patent Laid-Open No.2024-46511 (Patent Document 1), a trench gate type vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed. PRIOR ART DOCUMENT PATENT DOCUMENT

[0003] Patent Document 1 Japanese Patent Laid-Open No.2024-46511 SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0004] In a semiconductor device having a trench gate type MOSFET, a trench is formed on an upper surface of a semiconductor substrate, and an insulating film is formed in the trench. When an attempt is made to form a contact hole reaching a source layer or a back gate layer by self-alignment, a recess is formed by etching the upper surface of the semiconductor substrate positioned between two mutually adjacent insulating films. This etching may cause wormholes to occur in the semiconductor substrate when forming a contact plug. Other problems and novel features will become apparent from the description of the present specification and the accompanying drawings. MEANS FOR SOLVING THE PROBLEM

[0005] The semiconductor substrate has an upper surface, and the interlayer insulating film formed on the upper surface and having an opening, comprises a first insulating film and a second insulating film. A first trench and a second trench are formed on the upper surface. In a plan view, each of the first and second trenches extends along a first direction so as to cross the opening. In a plan view, the first and second trenches are spaced apart from each other along a second direction perpendicular to the first direction. The first insulating film is formed in the first trench. The second insulating film is formed in the second trench. In a plan view, a recess is formed on the upper surface that overlaps with the opening and is located between the first and second insulating films. In a cross-sectional view passing between the first and second insulating films and perpendicular to the second direction, the side surface of the recess and the inner wall surface of the opening form a single plane. [Effects of the Invention]

[0006] The semiconductor device of this disclosure can suppress the occurrence of wormholes within the semiconductor substrate when forming contact plugs. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of semiconductor device DEV1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 in line II-II of Figure 1. [Figure 3] This is a cross-sectional view of semiconductor device DEV1 in line III-III of Figure 1. [Figure 4] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 5] This is a cross-sectional view of the semiconductor substrate SUB prepared by preparation step S1. [Figure 6A] This is a first cross-sectional view illustrating the preparation process S1. [Figure 6B] This is a second cross-sectional view illustrating the preparation process S1. [Figure 6C] This is a third cross-sectional view illustrating the preparation process S1. [Figure 6D] This is a fourth cross-sectional view illustrating the preparation process S1. [Figure 6E] It is a fifth cross-sectional view illustrating preparation step S1. [Figure 6F] It is a sixth cross-sectional view illustrating preparation step S1. [Figure 6G] It is a seventh cross-sectional view illustrating preparation step S1. [Figure 6H] It is an eighth cross-sectional view illustrating preparation step S1. [Figure 7] It is a cross-sectional view illustrating interlayer insulating film forming step S2. [Figure 8] It is a cross-sectional view illustrating ion implantation step S3. [Figure 9] It is a cross-sectional view illustrating interlayer insulating film forming step S4. [Figure 10] It is a cross-sectional view illustrating etching step S5. [Figure 11] It is a first cross-sectional view illustrating etching step S6. [Figure 12] It is a partially enlarged view of FIG. 11. [Figure 13] It is a second cross-sectional view illustrating etching step S6. [Figure 14] It is a cross-sectional view illustrating thermal oxidation step S7. [Figure 15] It is a cross-sectional view illustrating ion implantation step S8. [Figure 16] It is a first cross-sectional view illustrating sidewall spacer forming step S9. [Figure 17] It is a second cross-sectional view illustrating sidewall spacer forming step S9. [Figure 18] It is a cross-sectional view illustrating etching step S10. [Figure 19] It is a cross-sectional view illustrating ion implantation step S11. [Figure 20] It is a first cross-sectional view illustrating barrier metal forming step S12. [Figure 21] It is a second cross-sectional view illustrating barrier metal forming step S12. [Figure 22] It is a cross-sectional view illustrating etching step S6 in a method for manufacturing semiconductor device DEV3. [Figure 23] This is a cross-sectional view illustrating the barrier metal formation step S12 in the manufacturing method of semiconductor device DEV3. [Figure 24] This is a cross-sectional view of semiconductor device DEV2. [Figure 25] This is a manufacturing process diagram for the semiconductor device DEV2. [Figure 26] This is a cross-sectional view illustrating the ion implantation step S14 in the manufacturing method of semiconductor device DEV2. [Figure 27] This is a cross-sectional view illustrating the etching process S6 in the manufacturing method of the semiconductor device DEV2. [Figure 28] This is a first cross-sectional view illustrating the polysilicon layer formation step S15 in the manufacturing method of semiconductor device DEV2. [Figure 29] This is a second cross-sectional view illustrating the polysilicon layer formation step S15 in the manufacturing method of semiconductor device DEV2. [Modes for carrying out the invention]

[0008] Embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of Semiconductor Device DEV1> As shown in Figures 1, 2, and 3, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has a bottom surface F1 and an upper surface F2 located on the opposite side of the bottom surface F1. The semiconductor substrate SUB is made of, for example, single-crystal silicon. The conductivity type of the semiconductor substrate SUB is a first conductivity type. The first conductivity type is, for example, n-type. Note that the barrier metal BM and contact plug CP are not shown in Figure 1.

[0011] Multiple trenches TR are formed within the semiconductor substrate SUB and on its upper surface F2. Each of the multiple trenches TR extends along a first direction DR1 in a plan view. In a cross-sectional view perpendicular to the first direction DR1, each of the multiple trenches TR extends from the upper surface F2 toward the lower surface F1. The multiple trenches TR are arranged with a gap between adjacent pairs of trenches TR along a second direction DR2 perpendicular to the first direction DR1 in a plan view.

[0012] As shown in Figures 1, 2, and 3, the semiconductor device DEV1 further has a plurality of insulating films IF. Each of the plurality of insulating films IF is formed inside each of the plurality of trenches TR. Each of the plurality of insulating films IF is made of, for example, silicon oxide. Each of the plurality of insulating films IF has a lower surface F3 that is in contact with the bottom surface of the trench TR and an upper surface F4 located on the opposite side of the lower surface F3. In a cross-sectional view perpendicular to the first direction DR1, the width of the insulating film IF in the second direction DR2 increases toward the upper surface F4. In other words, in a cross-sectional view perpendicular to the first direction DR1, the shape of the insulating film IF is tapered.

[0013] As shown in Figure 2, the semiconductor device DEV1 further has a plurality of gate electrodes GE. The semiconductor device DEV1 may also further have a plurality of shield gates SG. Each of the plurality of gate electrodes GE is formed inside each of the plurality of trenches TR such that, in a cross-sectional view perpendicular to the first direction DR1, it is surrounded by each of the plurality of insulating films IF. Each of the plurality of shield gates SG is formed inside each of the plurality of trenches TR such that, in a cross-sectional view perpendicular to the first direction DR1, it is surrounded by each of the plurality of insulating films IF. Each of the plurality of shield gates SG is located below each of the plurality of gate electrodes GE. In other words, the distance between each of the plurality of shield gates SG and the bottom surface of each of the plurality of trenches TR is smaller than the distance between each of the plurality of gate electrodes GE and the bottom surface of each of the trenches TR. Each of the plurality of gate electrodes GE and each of the plurality of shield gates SG is formed of, for example, polycrystalline silicon.

[0014] As shown in Figures 1, 2, and 3, the semiconductor device DEV1 further has an interlayer insulating film ILD. The interlayer insulating film ILD is formed on the upper surface F2. An opening OP is formed within the interlayer insulating film ILD. The opening OP penetrates the interlayer insulating film ILD. The interlayer insulating film ILD has a first layer ILD1, a second layer ILD2 formed on the first layer ILD1, and a third layer ILD3 formed on the second layer ILD2. The first layer ILD1 and the third layer ILD3 are formed of, for example, silicon oxide. The second layer ILD2 is formed of, for example, silicon nitride. Multiple trenches TR cross the opening OP along a first direction DR1 in a plan view.

[0015] A recess RCS is formed on the upper surface F2 of the semiconductor substrate SUB, which overlaps the opening OP in a plan view and is located between two adjacent insulating films IF (multiple trenches TR). In a cross-sectional view perpendicular to the first direction DR1, the bottom surface of the recess RCS is located below the upper surface F2 of the semiconductor substrate SUB, which overlaps with the interlayer insulating film ILD in a plan view. Also, the bottom surface of the recess RCS is located below the upper surface F4 of the insulating film IF. In a cross-sectional view perpendicular to the first direction DR1, one of the two adjacent insulating films IF (insulating film IFa) forms one side of the recess RCS, and the other of the two adjacent insulating films IF (insulating film IFb) forms the other side of the recess RCS.

[0016] In a cross-sectional view passing between two adjacent insulating films IF and perpendicular to the second direction DR2, the side surface of the recessed RCS and the inner wall surface of the opening OP form a single plane. From another perspective, in a cross-sectional view passing between two adjacent insulating films IF and perpendicular to the second direction DR2, the side surface of the recessed RCS is flush with the inner wall surface of the opening OP, and no undercut is formed at the boundary between the side surface of the recessed RCS and the inner wall surface of the opening OP.

[0017] As shown in Figure 2, the semiconductor substrate SUB has a plurality of source layers SL and a plurality of body layers BDL. Each of the plurality of source layers SL is formed within the semiconductor substrate SUB and on the upper surface F2. Each of the plurality of body layers BDL is formed within the semiconductor substrate SUB so as to be located below each of the plurality of source layers SL and in contact with each of the plurality of source layers SL. In a cross-sectional view perpendicular to the first direction DR1, each of the plurality of body layers BDL faces each of the plurality of gate electrodes GE with a portion of each of the plurality of insulating films IF interposed between them. The conductivity type of the plurality of source layers SL is a first conductivity type. The conductivity type of the plurality of body layers BDL is a second conductivity type opposite to the first conductivity type. The second conductivity type is, for example, p-type. As shown in Figure 3, the semiconductor substrate SUB further has a well layer WEL. The well layer WEL is formed within the semiconductor substrate SUB and on the upper surface F2. In a plan view, the interlayer insulating film ILD overlaps the well layer WEL. Furthermore, the well layer WEL may extend to a position where it protrudes into the opening OP in a plan view. The conductivity type of the well layer WEL is the second conductivity type.

[0018] As shown in Figures 1, 2, and 3, the semiconductor device DEV1 has sidewall spacers SW1, SW2, and SW3. Sidewall spacer SW1 is formed on the bottom surface of the recess RCS so as to be in contact with the insulating film IFa. Sidewall spacer SW2 is formed on the bottom surface of the recess RCS so as to be in contact with the insulating film IFb. Sidewall spacers SW1 and SW2 are separated from each other in the second direction DR2. Sidewall spacer SW3 is formed on the bottom surface of the recess RCS so as to be in contact with one plane formed by the side surface of the recess RCS and the opening OP. Sidewall spacers SW1, SW2, and SW3 are made of, for example, silicon oxide.

[0019] As shown in Figures 1, 2, and 3, a contact hole CH is formed on the bottom surface of the recess RCS located between sidewall spacers SW1 and SW2. In a cross-sectional view perpendicular to the first direction DR1, the contact hole CH extends toward the bottom surface F1 of the semiconductor substrate SUB. More specifically, the contact hole CH penetrates each of the multiple source layers SL and reaches each of the multiple body layers BDL. The semiconductor substrate SUB also has multiple back gate layers BGL. Each of the multiple back gate layers BGL is formed within the semiconductor substrate SUB and on the bottom surface of the contact hole CH. Each of the multiple back gate layers BGL is surrounded by, for example, a body layer BDL in a cross-sectional view perpendicular to the first direction DR1. The bottom surface of each of the multiple back gate layers BGL may be located below the bottom surface of each of the multiple body layers BDL. The conductivity type of the back gate layers BGL is second conductivity type.

[0020] As shown in Figures 2 and 3, the semiconductor device DEV1 further includes a barrier metal BM. The barrier metal BM is formed on the bottom surface of the contact hole CH, on the inner wall surface of the contact hole CH, on the sidewall spacer SW1, on the sidewall spacer SW2, on the sidewall spacer SW3, on the insulating film IF (top surface F4), and on the interlayer insulating film ILD (third layer ILD3). The barrier metal BM is, for example, a laminated film of a titanium film and a titanium nitride film. Although not shown, the barrier metal BM formed on the inner wall surface and the bottom surface of the contact hole CH reacts with the semiconductor substrate SUB at the interface between the barrier metal BM and the semiconductor substrate SUB to form a silicide.

[0021] As shown in Figures 2 and 3, the semiconductor device DEV1 further includes a contact plug CP. The contact plug CP is formed on the barrier metal BM between the sidewall spacers SW1 and SW2 and within the contact hole CH. The contact plug CP is made of, for example, tungsten. The contact plug CP is electrically connected to the source layer SL and the back gate layer BGL.

[0022] <Manufacturing method for semiconductor device DEV1> As shown in Figure 4, the method for manufacturing the semiconductor device DEV1 includes a preparation step S1, an interlayer insulating film formation step S2, an ion implantation step S3, an interlayer insulating film formation step S4, an etching step S5, an etching step S6, a thermal oxidation step S7, and an ion implantation step S8. The method for manufacturing the semiconductor device DEV1 further includes a sidewall spacer formation step S9, an etching step S10, an ion implantation step S11, a barrier metal formation step S12, and a contact plug formation step S13.

[0023] As shown in Figure 5, in preparation step S1, a semiconductor substrate SUB is prepared. In the semiconductor substrate SUB prepared in preparation step S1, a plurality of trenches TR are formed on the upper surface F2, and inside each of the plurality of trenches TR, a plurality of insulating films IF, a plurality of gate electrodes GE, and a plurality of shield gates SG are formed. In preparation step S1, first, as shown in Figure 6A, a plurality of trenches TR are formed on the upper surface F2 of the semiconductor substrate SUB. In the formation of the plurality of trenches TR, firstly, a hard mask is formed on the upper surface F2 of the semiconductor substrate SUB. Secondly, anisotropic dry etching is performed on the semiconductor substrate SUB through the openings of the hard mask, thereby forming a plurality of trenches TR on the upper surface F2.

[0024] In preparation step S1, each of the multiple insulating film IFs, each of the multiple shield gate SGs, and each of the multiple gate electrodes GEs are then formed inside each of the multiple trenches TR. In the formation of the multiple insulating film IFs, the multiple shield gate SGs, and the multiple gate electrodes GEs, firstly, as shown in Figure 6B, the constituent material of the insulating film IFs is formed on the bottom surface, the inner wall surface, and the top surface F2 of each of the multiple trenches TR. Secondly, as shown in Figure 6C, the constituent material of the shield gate SGs is formed on the constituent material of the insulating film IFs, for example by CVD (Chemical Vapor Deposition). The constituent material of the shield gate SGs is formed inside each of the multiple trenches TR and outside each of the multiple trenches TR.

[0025] Thirdly, as shown in Figure 6D, a portion of the constituent material of the shield gate SG formed on the outside of each of the multiple trenches TR and a portion of the constituent material of the shield gate SG formed inside each of the multiple trenches TR are removed by methods such as CMP (Chemical Mechanical Polishing) or etch-back, thereby forming multiple shield gates SG. Fourthly, as shown in Figure 6E, the constituent material of the insulating film IF is formed on each of the multiple shield gates SG, on the inner wall surface and the upper surface F2 of each of the multiple trenches TR, for example by CVD. Fourthly, as shown in Figure 6F, the constituent material of the gate electrode GE is formed on the constituent material of the insulating film IF, for example by CVD. The constituent material of the gate electrode GE is formed inside each of the multiple trenches TR and on the outside of each of the multiple trenches TR.

[0026] Fifth, as shown in Figure 6G, the constituent material of the gate electrode GE formed on the outside of each of the multiple trenches TR and a portion of the constituent material of the gate electrode GE formed inside each of the multiple trenches TR are removed by, for example, the CMP method and the etch-back method to form multiple gate electrode GEs. Sixth, as shown in Figure 6H, the constituent material of the insulating film IF is formed inside each of the multiple trenches TR and on the upper surface F2 by, for example, the CVD method. Seventh, the constituent material of the insulating film IF formed on the outside of each of the multiple trenches TR is removed by, for example, etching. As a result, a semiconductor substrate SUB having the structure shown in Figure 5 is prepared.

[0027] As shown in Figure 7, in the interlayer insulating film formation step S2, for example, by the ISSG (In Situ Steam Generation) oxidation method, the first layer ILD1 of the interlayer insulating film ILD is formed on the upper surface F2 so as to cover multiple insulating films IF. As shown in Figure 8, in the ion implantation step S3, a well layer WEL is formed by ion implantation using the resist pattern formed on the first layer ILD1 as a mask. As shown in Figure 9, in the interlayer insulating film formation step S4, for example, by the CVD method, the second layer ILD2 and the third layer ILD3 of the interlayer insulating film ILD are formed sequentially.

[0028] As shown in Figure 10, in etching step S5, the third layer ILD3 is removed by dry etching, and then the second layer ILD2 and the first layer ILD1 are removed by wet etching, forming an opening OP. Dry etching of the third layer ILD3 is performed through the opening in the resist pattern formed on the third layer ILD3. Wet etching of the second layer ILD2 and the first layer ILD1 is performed through the opening OP formed in the third layer ILD3.

[0029] As shown in Figure 11, in etching step S6, anisotropic dry etching is performed, forming a recess RCS between two adjacent insulating films IF (insulating film IFa, insulating film IFb). In a cross-sectional view perpendicular to the first direction DR1, each of the multiple insulating films IF is tapered. Therefore, as shown in Figure 12, in a cross-sectional view perpendicular to the first direction DR1, a portion of the semiconductor substrate SUB remains partially in the space between the recess RCS and insulating film IFa, and between the recess RCS and insulating film IFb. Furthermore, since the etching performed in etching step S6 is anisotropic dry etching, as shown in Figure 13, in a cross-sectional view passing between insulating films IFa and insulating film IFb and perpendicular to the second direction DR2, the inner wall surface of the opening OP and the side surface of the recess RCS form a single plane.

[0030] As shown in Figure 14, in the thermal oxidation step S7, the portions of the semiconductor substrate SUB located at the bottom of the recess RCS, between the recess RCS and the insulating film IFa, and between the recess RCS and the insulating film IFb are thermally oxidized to form a thermal oxide film TOX. As shown in Figure 15, in the ion implantation step S8, ion implantation is performed through the thermal oxide film TOX to form multiple source layers SL and multiple body layers BDL within the semiconductor substrate SUB. Each of the multiple source layers SL is formed to be in contact with the thermal oxide film TOX, and each of the multiple body layers BDL is located below each of the multiple source layers SL and is formed to be in contact with each of the multiple source layers.

[0031] As shown in Figure 16, in the sidewall spacer formation step S9, sidewall spacer SW1 is formed on the bottom surface of the recessed RCS so as to be in contact with the insulating film IFa, and sidewall spacer SW2 is formed on the bottom surface of the recessed RCS so as to be in contact with the insulating film IFb. In the sidewall spacer formation step S9, firstly, the constituent material such as sidewall spacer SW1 is formed, for example by CVD, so as to cover the thermal oxide film TOX, the insulating film IF, and the interlayer insulating film ILD. Secondly, the constituent material such as sidewall spacer SW1 and the thermal oxide film TOX are etched back until the insulating film IF and the interlayer insulating film ILD are exposed. This forms sidewall spacer SW1 and sidewall spacer SW2. In addition, as shown in Figure 17, in the sidewall spacer formation step S9, in addition to sidewall spacer SW1 and sidewall spacer SW2, sidewall spacer SW3 is also formed on the recessed RCS so as to be in contact with one plane formed by the side surface of the recessed RCS and the inner wall surface of the opening OP.

[0032] As shown in Figure 18, in etching step S10, anisotropic dry etching is performed on the semiconductor substrate SUB through the space between sidewall spacers SW1 and SW2, and a contact hole CH is formed on the bottom surface of the recess RCS located between sidewall spacers SW1 and SW2. As shown in Figure 19, in ion implantation step S11, ion implantation is performed through the space between sidewall spacers SW1 and SW2, thereby forming a back gate layer BGL in the semiconductor substrate SUB that is in contact with the top surface F2 and surrounded by the body layer BDL.

[0033] As shown in Figures 20 and 21, in the barrier metal formation step S12, barrier metal BM is formed on the sidewall spacers SW1, SW2, SW3, the inner wall surface of the contact hole CH, the bottom surface of the contact hole CH, the insulating film IF, and the interlayer insulating film ILD, for example by sputtering. After the formation of the barrier metal BM, heat treatment is performed, causing the semiconductor substrate SUB and the barrier metal BM to react at the interface between the barrier metal BM and the semiconductor substrate SUB, thereby forming silicide.

[0034] In the contact plug formation step S13, a contact plug CP is formed between the sidewall spacers SW1 and SW2 and within the contact hole CH. In the contact plug formation step S13, firstly, the constituent material of the contact plug CP is formed on the barrier metal BM, for example by CVD. Secondly, etch-back is performed on the constituent material of the contact plug CP until the barrier metal BM located on each of the multiple insulating films IF is exposed. The constituent material of the contact plug CP may remain on the barrier metal BM covering the sidewall spacer SW3. As a result, the structure of the semiconductor device DEV1 shown in Figures 1 to 3 is formed.

[0035] <Effects of Semiconductor Device DEV1> In the comparative example semiconductor device DEV3, isotropic dry etching is performed in etching step S6, rather than anisotropic dry etching. As a result, as shown in Figure 22, an undercut UDC is formed in the portion of the semiconductor substrate SUB located at the boundary between the side surface of the recess RCS and the inner wall surface of the opening OP, in a cross-sectional view that passes between the insulating film IFa and the insulating film IFb and is perpendicular to the second direction DR2. As shown in Figure 23, the surface of the undercut UDC may not be sufficiently covered by sputtering performed in barrier metal formation step S12. As a result, a phenomenon may occur in which the deposition gas of CVD performed in contact plug formation step S13 erodes the semiconductor substrate SUB, i.e., a wormhole occurs.

[0036] On the other hand, in semiconductor device DEV1, anisotropic dry etching is performed in etching step S6. As a result, in a cross-sectional view that passes between insulating film IFa and insulating film IFb and is perpendicular to the second direction DR2, no undercut UDC is formed on the semiconductor substrate SUB located at the boundary between the side surface of the recess RCS and the inner wall surface of the opening OP, and the side surface of the recess RCS and the inner wall surface of the opening OP form a single plane. Consequently, in contact plug formation step S13, the semiconductor substrate SUB is not exposed to the deposition gas of CVD, and the generation of wormholes is suppressed.

[0037] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0038] <Configuration of Semiconductor Device DEV2> Figure 24 shows a cross-section of semiconductor device DEV2 at the position corresponding to II-II in Figure 1. As shown in Figure 24, semiconductor device DEV2 does not have sidewall spacers SW1 and SW2. In semiconductor device DEV2, the semiconductor substrate SUB has a plurality of source layers SL1 and a plurality of source layers SL2. In a cross-sectional view perpendicular to the first direction DR1, each of the plurality of source layers SL1 is located between one side of the recess RCS and the insulating film IFa, and each of the plurality of source layers SL2 is located between the other side of the recess RCS and the insulating film IFb. In semiconductor device DEV2, each of the plurality of body layers BDL is located below each of the plurality of source layers SL1 and each of the plurality of source layers SL2, and is formed in the semiconductor substrate SUB so as to be in contact with each of the plurality of source layers SL1 and each of the plurality of source layers SL2, and forms the bottom surface of the recess RCS.

[0039] The semiconductor device DEV2 has a plurality of polysilicon layers PS1 and a plurality of polysilicon layers PS2. Each of the plurality of polysilicon layers PS1 is formed on the bottom surface of the recess RCS so as to cover each of the plurality of source layers SL1. Each of the plurality of polysilicon layers PS2 is formed on the bottom surface of the recess RCS so as to cover each of the plurality of source layers SL2. In a cross-sectional view perpendicular to the first direction DR1, there is a gap between adjacent polysilicon layers PS1 and polysilicon layers PS2. Each of the plurality of polysilicon layers PS1 and each of the plurality of polysilicon layers PS2 is made of polycrystalline silicon. The conductivity type of the plurality of polysilicon layers PS1 and the plurality of polysilicon layers PS2 is the first conductivity type. That is, the conductivity type of the plurality of polysilicon layers PS1 is the same as the conductivity type of the plurality of source layers SL1, and the conductivity type of the plurality of polysilicon layers PS2 is the same as the conductivity type of the plurality of source layers SL2. In semiconductor device DEV2, the contact hole CH is formed on the bottom surface of the recess RCS located between adjacent polysilicon layers PS1 and PS2.

[0040] <Manufacturing method for semiconductor device DEV2> As shown in Figure 25, the method for manufacturing the semiconductor device DEV2 does not include the thermal oxidation step S7, the ion implantation step S8, the sidewall spacer formation step S9, and the etching step S10. The method for manufacturing the semiconductor device DEV2 further includes the ion implantation step S14 and the polysilicon layer formation step S15. The ion implantation step S14 is performed after the etching step S5 and before the etching step S6. The polysilicon layer formation step S15 is performed after the etching step S6. After the polysilicon layer formation step S15, the ion implantation step S11, the barrier metal formation step S12, and the contact plug formation step S13 are performed sequentially.

[0041] As shown in Figure 26, in the ion implantation step S14, ion implantation is performed to form multiple source layers SL located on the upper surface F2 and multiple body layers BDL located below each of the multiple source layers SL and in contact with each of the multiple source layers SL within the semiconductor substrate SUB. Similar to the manufacturing method of semiconductor device DEV1, in the manufacturing method of semiconductor device DEV2, anisotropic dry etching is performed in the etching step S6 to form the recess RCS. As shown in Figure 27, in the manufacturing method of semiconductor device DEV2, anisotropic dry etching in etching step S6 forms, in a cross-sectional view perpendicular to the first direction DR1, a source layer SL1 located between one side of the recess RCS and the insulating film IFa and a source layer SL2 located between the other side of the recess RCS and the insulating film IFb from each of the multiple source layers SL.

[0042] As shown in Figure 28, in the polysilicon layer formation step S15, multiple polysilicon layers PS1 and multiple polysilicon layers PS2 are formed. In the polysilicon layer formation step S15, firstly, a constituent material such as a polysilicon layer PS1 is formed on each of the multiple insulating film IFs so as to cover the bottom and sides of the recessed RCS, for example by CVD. Secondly, by performing etch-back (anisotropic dry etching) on ​​the constituent material such as the polysilicon layer PS1, the constituent material such as the polysilicon layer PS1 covering each of the multiple insulating film IFs is removed, and multiple polysilicon layers PS1 and multiple polysilicon layers PS2 are formed from the constituent material such as the polysilicon layer PS1 covering the bottom and sides of the recessed RCS.

[0043] As shown in Figure 29, as anisotropic etching continues, etching progresses from the bottom surface of the recess RCS located between adjacent polysilicon layers PS1 and PS2 to the semiconductor substrate SUB (body layer BDL), forming contact holes CH. Subsequently, the ion implantation process S11, the barrier metal formation process S12, and the contact plug formation process S13 are carried out sequentially to form the structure of the semiconductor device DEV2 shown in Figure 24.

[0044] <Effects of Semiconductor Device DEV2> In semiconductor device DEV2, anisotropic dry etching is performed in etching process S6, so that an undercut UDC is not formed on the semiconductor substrate SUB located at the boundary between the side surface of the recess RCS and the inner wall surface of the opening OP in a cross-sectional view that passes between the insulating film IFa and the insulating film IFb and is perpendicular to the second direction DR2, thereby suppressing the generation of wormholes.

[0045] If multiple polysilicon layers PS1 and PS2 are not formed, the reaction between the barrier metal BM and multiple source layers SL1 and SL2 can cause the multiple source layers SL1 and SL2 to be completely silicided. In semiconductor device DEV2, multiple polysilicon layers PS1 and PS2 are formed, so the disappearance of multiple source layers SL1 and SL2 due to silicide can be suppressed. In addition, in semiconductor device DEV2, the etching process S16 to form the contact holes CH also etches the multiple polysilicon layers PS1 and PS2, so the contact holes CH are widened compared to semiconductor device DEV1. As a result, in semiconductor device DEV2, the coverage of the barrier metal BM is improved and the stress near the contact holes CH is relieved. From another perspective, semiconductor device DEV2 allows for a smaller chip size.

[0046] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0047] BDL Body layer, BGL Back gate layer, BM Barrier metal, CH Contact hole, CP Contact plug, DEV1, DEV2, DEV3 Semiconductor device, DR1 First direction, DR2 Second direction, F1 Bottom surface, F2 Top surface, F3 Bottom surface, F4 Top surface, GE Grid gate, IF, IFA, IFb Insulating film, ILD Interlayer insulating film, ILD1 First layer, ILD2 Second layer, ILD3 Third layer, OP Opening, PS1, PS2 Polysilicon layer, RCS Recess, S1 Preparation process, S2 Interlayer insulating film formation process, S3 Ion implantation process, S4 Interlayer insulating film formation process, S5, S6 Etching process, S7 Thermal oxidation process, S8 Ion implantation process, S9 Sidewall spacer formation process, S10 Etching process, S11 Ion implantation process, S12 Barrier metal formation process, S13 Contact plug formation process, S14 Ion implantation process, S15 Polysilicon layer formation process: SG shield gate, SL, SL1, SL2 source layer, SUB semiconductor substrate, SW1, SW2, SW3 sidewall spacer, TOX thermal oxide film, TR trench, UDC undercut, WEL well layer.

Claims

1. A semiconductor substrate having an upper surface, An interlayer insulating film formed on the upper surface and having an opening, The first insulating film and It comprises a second insulating film, A first trench and a second trench are formed on the upper surface. Each of the first trench and the second trench extends along a first direction so as to cross the opening in a plan view. The first trench and the second trench are arranged in a plan view, with a gap between them, along a second direction perpendicular to the first direction. The first insulating film is formed in the first trench, The second insulating film is formed in the second trench, A recess is formed on the upper surface that overlaps with the opening in a plan view and is located between the first insulating film and the second insulating film. A semiconductor device wherein, in a cross-sectional view passing between the first insulating film and the second insulating film and perpendicular to the second direction, the side surface of the recess and the inner wall surface of the opening form a single plane.

2. First sidewall spacer and A second sidewall spacer is provided, In a cross-sectional view perpendicular to the first direction, the first insulating film forms one side surface of the recess. In a cross-sectional view perpendicular to the first direction, the second insulating film forms the other side surface of the recess. The first sidewall spacer is formed on the bottom surface of the recess so as to be in contact with the first insulating film, The semiconductor device according to claim 1, wherein the second sidewall spacer is in contact with the second insulating film and is formed on the bottom surface of the recess such that there is a gap between the first sidewall spacer and the second sidewall spacer in the second direction.

3. A source layer formed within the semiconductor substrate and on the bottom surface of the recess, The semiconductor substrate further comprises a body layer formed in contact with the source layer and located below the source layer, A contact hole is formed in the bottom surface of the recess located between the first sidewall spacer and the second sidewall spacer, so as to penetrate the source layer and reach the body layer. The semiconductor device according to claim 2, further comprising a back gate layer formed within the semiconductor substrate and on the bottom surface of the contact hole.

4. The semiconductor device according to claim 3, further comprising a third sidewall spacer formed on the bottom surface of the recess so as to be in contact with the aforementioned one plane.

5. The semiconductor device according to claim 4, further comprising a barrier metal formed on the first insulating film, the second insulating film, the bottom surface of the recess, the inner wall surface of the contact hole, the bottom surface of the contact hole, the first sidewall spacer, the second sidewall spacer, the third sidewall spacer, and the interlayer insulating film.

6. Equipped with additional contact plugs, The semiconductor device according to claim 5, wherein the contact plug is formed between the first sidewall spacer and the second sidewall spacer and within the contact hole.

7. A first gate electrode is formed in the first trench so as to be surrounded by the first insulating film in a cross-sectional view perpendicular to the first direction and facing the body layer with a portion of the first insulating film interposed between them, The semiconductor device according to claim 6, further comprising: a second gate electrode surrounded by the second insulating film in a cross-sectional view perpendicular to the first direction and formed in the second trench such that a portion of the second insulating film is interposed and faces the body layer.

8. The first polysilicon layer and The second polysilicon layer, A first source layer is located between one side surface of the recess and the first insulating film, A second source layer is located between the other side surface of the recess and the second insulating film, The semiconductor substrate further comprises a body layer that is in contact with the first source layer and the second source layer and is formed in the semiconductor substrate so as to form the bottom surface of the recess, The first polysilicon layer covers the first source layer, The second polysilicon layer covers the second source layer with a gap between it and the first polysilicon layer. The conductivity type of the first source layer, the conductivity type of the second source layer, the conductivity type of the first polysilicon layer, and the conductivity type of the second polysilicon layer are all first conductivity types. The semiconductor device according to claim 1, wherein the conductivity type of the body layer is a second conductivity type opposite to the first conductivity type.

9. A step of preparing a semiconductor substrate having an upper surface in which a first trench and a second trench are formed, wherein a first insulating film is formed in the first trench and a second insulating film is formed in the second trench, The process includes forming an interlayer insulating film having an opening on the upper surface, Each of the first trench and the second trench extends along a first direction so as to cross the opening in a plan view. The first trench and the second trench are arranged in a plan view, with a gap between them, along a second direction perpendicular to the first direction. The process further includes forming a recess on the upper surface that overlaps with the opening in a plan view and is located between the first insulating film and the second insulating film, A method for manufacturing a semiconductor device, wherein, in a cross-sectional view passing between the first insulating film and the second insulating film and perpendicular to the second direction, the side surface of the recess and the inner wall surface of the opening form a single plane.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the recess is formed by performing anisotropic dry etching on the semiconductor substrate through the opening.

11. A step of forming a thermal oxide film by performing thermal oxidation on the portion of the semiconductor substrate located between the recess and the first insulating film, between the recess and the second insulating film, and on the bottom surface of the recess, A step of forming a source layer in the semiconductor substrate so as to be in contact with the thermal oxide film by implanting ions into the semiconductor substrate through the thermal oxide film, The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming a body layer in the semiconductor substrate so as to be located below the source layer and in contact with the source layer by implanting ions into the semiconductor substrate through the thermal oxide film.

12. The process further includes forming a first sidewall spacer and a second sidewall spacer on the bottom surface of the recess, The first sidewall spacer is formed to be in contact with the first insulating film, The method for manufacturing a semiconductor device according to claim 11, wherein the second sidewall spacer is in contact with the second insulating film and is formed such that there is a gap between the first sidewall spacer and the second sidewall spacer in the second direction.

13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the first sidewall spacer and the second sidewall spacer, a third sidewall spacer is further formed on the bottom surface of the recess so as to be in contact with the one plane.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of forming a contact hole in the bottom surface of the recess located between the first sidewall spacer and the second sidewall spacer, which penetrates the source layer and reaches the body layer.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of forming a barrier metal on the first insulating film, the second insulating film, the bottom surface of the recess, the inner wall surface of the contact hole, the bottom surface of the contact hole, the first sidewall spacer, the second sidewall spacer, and the third sidewall spacer.

16. The process further comprises forming a contact plug, The method for manufacturing a semiconductor device according to claim 15, wherein the contact plug is formed between the first sidewall spacer and the second sidewall spacer and within the contact hole.

17. Prior to the step of forming the recess, the step of forming a source layer in the semiconductor substrate so as to be located on the upper surface, The process further comprises the step of forming a body layer in the semiconductor substrate so as to be located below the source layer and in contact with the source layer, prior to the step of forming the recess, In the step of forming the recess, the recess is formed so as to penetrate the source layer, thereby forming a first source layer in contact with the first insulating film and a second source layer in contact with the second insulating film from the source layer. The steps include forming a polysilicon layer on the first insulating film, on the second insulating film, on the first source layer, on the second source layer and on the bottom surface of the recess, after the step of forming the recess, The process further comprises, after the step of forming the polysilicon layer, an anisotropic dry etching of the polysilicon layer such that a first polysilicon layer covering the first source layer and a second polysilicon layer covering the second source layer of the polysilicon layer remain intact. The conductivity type of the source layer and the conductivity type of the polysilicon layer are first conductivity types. The method for manufacturing a semiconductor device according to claim 10, wherein the conductivity type of the body layer is a second conductivity type opposite to the first conductivity type.

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